SIEMENS C16x-Family of c167 High-Performance CMOS 16-Bit Microcontrollers Preliminary C167 16-Bit Microcontroller High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20-MHz CPU Clock 500 ns Multiplication (16 x 16 bits), 1 us Division (32 / 16 bit) Enhanced Boolean Bit Manipulation Facilities ‘Additional Instructions to Support HLL and Operating Systems. Register-Based Design with Multiple Variable Register Banks ‘Single-Cycle Context Switching Support Up to 16 MBytes Linear Address Space for Code and Data 2 KBytes On-Chip RAM 8 KBytes On-Chip ROM Programmable Extemal Bus Characteristics for Different Address Ranges 8Bit or 16-Bit External Data Bus Multiplexed or Demultiplexed Extemal Address/Data Buses Five Programmable Chip-Select Signals Hold and Hold-Acknowledge Bus Arbitration Support 1024 Bytes On-Chip Special Function Register Area. Idle and Power Down Modes Channel Intorrupt-Driven Single-Cycie Data Transfer Facilities via Penpheral Event Controller (PEC) 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 50 ns 16-Channel 10-bit A/D Converter with 9.7 jis Conversion Time Two 16-Channel Capture/Compare Units 4-Channel PWM Unit (up to 78 KHz) ‘Two Mult-Funetional General Purpose Timer Units with 5 Timers ‘Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous) Programmable Watchdog Timer Up to 111 General Purpose 1/0 Lines Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards ‘On-Chip Bootstrap Loader 144-Pin MQFP Package (EIAJ) Semiconductor Group 1 06.94SIEMENS Gi? Introduction The C167 is a new derivative of the Siemens SAB 80166 family of full featured single-chip CMOS. rmicrocontroliers It combines high CPU performance (up to 10 millon instructions per second) with high peripheral functionality and enhanced 1O-capabilties, war of rt | m2 <— K—> "e's | mix —+| Por rst =| > Feet Yer I K—> i8'sh | we | C167 ter a | > fost | mai | K—> ae >, Pot 6 i >> "5H | a wR — | pons ay, bon eet > Fhe Logie Symbol Ordering Information Type Ordering Code Package Function — — SAB-CI67-LM |067120-Ce06 | P.MOFP.1441 | 16-61 mirocontaor with BKB ste ROM and 2 KByte RAM Temperature range 010 + 70°C Sar-CHe7 LM |087120-C510 | PMOFPIAKT —/16t mevocontoer wth 8 KByte ROM and KByte RAM | “Temperature range = 40 + 88 6 Semiconductor Group 2SIEMENS c167 Pin Configuration (top view) rire mee ies os neji rat racjeaes eine ireice rakes Riecns Bone fans saint Baja ine oes | ele aja a0 reejeogoxon ‘Serniconductor Group 3SIEMENS cee Pin Definitions and Functions Symbol [pin input @) [Function Number Output (O) Pe0- 1. WO Pot 6 i an Sb bidreclonal WO pot WS bitwise rer la Fromrammabi for nput or aula via recon is. Fora ph configured as input, the output driver is put into high Impedance state. Port 6 outputs can be configured as push’ pull or open drain drivers, The following Port 6 pins also serve for alternate functions: 1 ° P60 C85. Chip Select 0 Output 5 6 P64 — CSE_— Chip Select 4 Output 6 ' P65 HOLD External Master Hold Request Input 7 ° P66 HULDA Hold Acknowledge Output __ie ° P67 BREO BusRequest Output Pa0- |9- V0 Por 8 is an &-bit bidirectional VO port. is bitwise Pe7|16 programmable for input or output via direction bits. For a pin configured as input, the output driver is put into. high- impedance state. Port 8 outputs can be configured as push’ pull or open dain drivers. The following Port @ pins also serve for alternate functions: 9 |vo P80 CCTBIO CAPCOM2: CC16 Cap.-n/Comp.Out ie |v P87 CO23I0_ CAPCOM: CC23 Cap.-InComp.Out Pro- [1a [v0 [Por 7 is an &-bit bidirectional VO por. It is bitwise p77 |26 programmable for input or output via direction bits. For a pin Contigured as input, the output driver is put into high- |impedance state. Pon 7 outputs can be configured as pushy pul or open drain avers. ‘The following Por 7 pins also serve for alternate functions: 1 jo P70 POUTO PWM Channe! 0 Output 2 0 P73 POUT3 PWM Channe! 3 Output 23 HO P74 CG28I0._ CAPCOM: CC28 Cap.-In/Comp.Out 2 Wo P77 GO3tIO_CAPCOM2: C631 Cap-In’Comp.Out ‘Semiconductor Group 4SIEMENS ee Pin Definitions and Functions (cont'd) Symbol [Pin [input (l) | Function Number Output (0) Ps0- 27-36 |1 Port 5 is a 16-bit inputonly port with Schmitt-Trigger P5158 |39-44 |) characteristics. The pins of Port 5 also serve as the (up to 18) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x), or they serve as timer inputs: 39 P5.10 TBEUD —GPT2 Timer T6 Ext. Up/Down Ctrl. Input 40 P5.11 TSEUD —GPT2 Timer TS Ext. Up/Down Ctrl. Input a 512 TIN GPT2 Timer T Gount Input 1 1 fl a2 1 P5139 TSIN | GPT2 Timer T5 Count Input 1 1 43 5.14 TAEUD PTI Timer Ta Ext. Up/Down Cirl.nput 44 5.18 T2EUD GPT Timer T2 Ext Up/Down Cir.Input P20- | 47-54 [vO Port 2 is @ 16-bit bidirectional VO por. It is bitwise 21s | 57-64 programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. Port 2 outputs can be configured as push’ pull or open drain drivers. ‘The following Port 2 pins also serve for altemate funetions: a7 vo P20 CCOIO CAPCOM: CCO Cap -IniComp. Out 54 io P27 CCTIO. CAPCOM: CC7 Cap.-In/Comp. Out 87 vo P2.8 — CC8IO CAPCOM: CCB Cap.-in/Comp. Out, 1 EXOIN Fast External Interrupt 0 Input 64 vo P2.15 CC1SIO_ CAPCOM: CO15 Cap.-In’Comp.Out, i EX7IN Fast External Interrupt 7 Input 1 T7IN__CAPCOM2 Timer T? Count Input Semiconductor Group 5SIEMENS uy Pin Definitions and Functions (cont) Symbol [Pin [input ()__ | Function Number | Output (0) P30- | 65-70, [VO Port 3is a 15-bit (P3.14 is missing) bidirectional VO port. itis P3.13, 73-80, |VO bit-wise programmable for input or ouput via direction bits pats jet vo For a pin configured as input, the output driver is put into high impedance state. Port 3 outputs can be configured as push’ pull or open drain drivers, ‘The following Port 3 pins also serve for alternate functions: 6 it |P30 TON CAPCOM Timer TO Count Input 6 0 P31 TBQUT —GPT2 Timer T6 Toggle Latch Output eit P32 CAPIN GPT? Register CAPREL Capture Input 6 0 P33 T3OUT —GPT1 Timer T3 Toggle Latch Output eit P34 T3EUD GPT Timer T3 Ext Up/Down Gir.nput 7 I P35 TAIN. GPT Timer T4 input for CountiGate/ReloadiCapture 7” it P36 TSIN GPT! Timer T3 CountiGate Input m4 it P97 TRIN. _GPT1 Timer T2 Input for Count’Gate/ReloadiCapture 7 |vo P38 MRST SSC Master-Flec./‘Siave-Transmit VO \7%e | wo P39 MTSR_ SSC Master-TransmilSlave-Rec, O/ 7 'o P310 TxD0 ASCO Clock/Data Output (Asyn./Syn.) 78 vo P3At RxDO ASCO Data Input (Asyn.) or I/O (Syn.) 70 312 BHE —_ Ext. Memory High Byte Enable Signal ° WRH Ext, Memory High Byte Write Strobe 8 © 0 P9139 SCLK SSC Master Clock Outp /Slave Cl. Inp a P3185 CLKOUT System Clock Output (=CPU Clock) Pa0- [@5-92 vO Port 4 is an 8-bit bidirectional WO port. it is bitwise paz | programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. Incase of an external bus configuration, Port 4 can be used 10 ‘output the segment address lines: a jo P40 AIG Least Significant Segment Addr. Line |92 ° Paz A23 Most Significant Segment Addr. Line a fas fo Extemal Memory Read Strobe. AD is activated for every external instuction or data ead access, wa fas fo Extemal Memory Write Stiobe, In Whi-mode this pin is Wat activated for every external data write access. in WRL-mode this pin is activated for low byte data write accesses on a 16- bit bus, and for every data write access on an 8:bit bus. See WRCFG in register SYSCON for mode selection. Semiconductor Group 6SIEMENS eed Pin Definitions and Functions (cont) Symbol |Pin [Input (I) | Function Number | Output (0) READY | 97 1 Ready Input. When the Ready function is enabled, a high level at this pin during an external memory access will force the insertion of memory cycle lime waitstates until the pin returns to a low level. ALE | 98 ° ‘Address Latch Enable Output, Can be used for latching the | address info external memory or an address latch in the multiplexed bus modes. EA 99 External Access Enable pin, A low level at this pin during and after Reset forces the C167 to begin instruction execution out of external memory. A high level forces execution out of the _intermal ROM. ROMless versions must have this pin tied to 0 PORTO: vo "/ PORTO consisis of the two &-bit bidirectional /O ports POL. POLO | 100 and POH, It is bitwise programmable for input or output via Po7, | 107 direction bits. For a pin configured as input, the output driver POH.O- | 108, is put into high-impedance state. Por? [114-117 In case of an external bus configuration, PORTO serves as the address (A) and address/data (AD) bus in multiplexed bus. modes and as the data (D) bus in demultiplexed bus modes. Demuttiplexed bus modes: Data Path Width: bit 16-bit POLO -POL7: D0-D7 Do-07 POH.O-POH7: 0 Ds -D15 Multiploxed bus modes: Data Path Width: -bit revit POLO -POL7: AD0-AD? ADO AD7 POH.O-POH7: —A8- AIS. ADB - ADI5, PORT! vo PORT! consists of the two 8-bit bidirectional /O ports P1L PILO- | 118— and P1H. It is bit-wise programmable for input or output via paz, | 125 direction bits. For a pin configured as input, the output driver PIHO- | 128— is put into high-impedance state. PORT is used as the 16-bit Pin? | 135 address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. ‘The following PORT! pins also serve for alternate functions: 132 | PiH4 — CC24I0 CAPCOM2: CC24 Capture Input 133 | PIHS — CC25I0 CAPCOM2; CO25 Capture Input 134 PIH6 — CC26IO_ CAPCOM2: CC26 Capture Input 135 | PIH7 — CC27IO_CAPCOM2: CC27 Capture Input ‘Semiconductor Group 7SIEMENS C167 Pin Definitions and Functions (contd) ‘Symbol | Pin Input () Function Number | Output (0) XTALT | 138 ' XTAL1: — Input to the oscillator amplifier and input to the intemal clock generator xraz |137 0 XTAL2: Output of the oscillator amplifier circut To clock the device from an extemal source, drive XTALI, while leaving XTAL2 unconnected. Minimum and maximum | highfow and riserfall times specified in the AC Characteristics must be observed RSTN 140 Reset input with Schmitt Trigger characteristics, A low level at this pin for a specified duration while the oscillator is running resets the C167. An internal pulup resistor permits power-on reset using only a capacitor connected to Vss. RSTOUT 141 (0 Internal Reset Indication Output. This pin is set toa low level when the partis executing either a hardware-, a sottware- ora watchdog timer reset. RSTOUT remains iow until the EINIT (end of initialization) instruction is executed Ni tae 'Non-Maskable Interrupt Input. A high to iow transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRON (power down) instruction is executed, the NMI pin must be low in order to force the C167 to go into power down mode. If NMI is high, when PWRDN is executed, the ‘art wil continue to run in normal made. If not used, pin NMI should be pulled high extemal. Vase (87 [- Reference voltage for the A/D converter. Vawo [98 | oference ground for the A/D converter. Ver a4 Flash programming voltage. This pin accepts the programming voltage for flash versions of the C167. Note: This pin is not connected (NC) on non-flash versions. Veo [7.48 | Digital Supply Votage: 56,72, +5 V during normal operation and idle mode. 82.93, | 22.5 .V during power down mode 108, 426, 196, 144 Ves 18,45, | Digital Ground. 55,71, 83,94, 110, 127, [139,143 ‘Semiconductor Group 8SIEMENS c167 Functional Description The architecture of the C167 combines advantages of both RISC and CISC processors and of ‘advanced peripheral subsystems in a very well-balanced way. The following biock diagram gives an ‘overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C167. Note: All ime specifications refer to a CPU clock of 20 MHz (see definition in the AC Characteristics section). Figure 3 Block Diagram Semiconductor Group 9SIEMENS ciey Memory Organization The memory space of the C167 is configured in a Yon Neumann architecture which means that code memory, data memary, registers and /O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. The C167 contains 8 KBytes of on-chip mask programmable ROM for code or constant data. The OM can be mapped to either segment 0 or segment 1 2 KBytes of on-chip RAM are provided as a storage for user defined variables, for the system stack, {general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (RO to R15) andlor bytewide (RLO, RHO, .., RL7, RH?) so-called General Purpose Registers (GPRs) 1024 bytes (2 * $12 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling {and monitoring functions of the different on-chip units. 212 SFRs are currently implemented Unused SFR addresses are reserved for future members of the C167 family In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 MBytes of extemal RAM andior ROM can be connected to the microcontroller. External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no extemal memory is required, or to one of four different extemal memary access modes, which are as follows: 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed ~ 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed — 16-/18-/20-/24 bit Addresses, 8-bit Data, Multiplexed ~ 16-/18-/20i24-bit Addresses, 8-bit Data, Demultiplexed In the demutiploxed bus modes, addresses are output on PORT and data is inpuvoutput on PORTO. in the multiplexed bus modes both addresses and data use PORTO for input/output Important timing characteristics of the extemal bus interlace (Memory Cycle Time, Memory Tri= State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of afferent types of memories. In addition, diferent address ranges may be accessed with different bus characteristics. Up to 5 extemal CS signals can be generated in order to save external glue logic. Access to very slow memories is supported via a particular Ready’ function. A HOLDIHLDA protocol is available for bus arbitration. For applications which require less than 16 MBytes of external memory space, this address space can be restricted to 1 MByto, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no address lines at al. It outputs all 8 address lines, it an address space af 16 MBytes is used. Semiconductor Group 10SIEMENS ce Central Processing Unit (CPU) ‘The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide Unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C167's instructions can be executed in just one machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All muttiple-cycie instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 x 16 bit multiplication in § cycles and a $2-/16 bit division in 10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. 0 ; : KT ries —_ a RAM ee as] STK a Teta] [Er Tnsicpie—] [Bt-WaskGer| | General 3 aly Purpose et He eytes y ic) row [Borer sni i tama) T nS I Euscon 1 | RO auscon 21a = BUSCON SADDEST auscon «1 apDRSE« Date Page Pr Pin Figure 4 CPU Block Diagram ‘Semiconductor Group "SIEMENS cee The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time, The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overiap others, A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicily compared against the stack pointer value upon each stack access for the detection of a stack overtlow or undertiow. ‘The high performance offered by the hardware implementation of the CPU can efficiently be utlized by a programmer via the highly efficient C167 instruction set which includes the following instruction. classes: — Arithmetic Instructions = Logical Instructions = Boolean Bit Manipulation Instructions Compare and Loop Contro! Instructions ~ Shift and Rotate Instructions = Prioitize Instruction Data Movement Instructions. — System Stack Instructions ‘Jump and Cal instructions ~ Retum Instructions = System Control Instructions — Miscellaneous Instructions ‘The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specity the required operands Semiconductor Group 2SIEMENS Clee Interrupt System With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal program execution), the C167 is capable of reacting very fast to the occurence of non-deterministic, events, The architacture of the C167 supports several mechanisms for fast and flexible response to service ‘requests that can be generated from various sources internal or external o the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC) {In contrast to a standard interrupt service where the current program execulion is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. & PEC service implies a single byle or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicty decremented for each PEC service except when performing in the continuous transfer mode, When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of biocks of data, oF for transferring A/D converted results to a memory table, The C167 has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. ‘A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possibie interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priorty levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location, Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling ledge or both edges). Software interrupts are supported by means of the “TRAP instruction in combination with an individual trap (interrupt) number ‘The following table shows all of the possible C167 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Note: The four last nodes in the table (X-Peripheral nodes) are prepared to accept interrupt requests from integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by selting the respective XPni bit Semiconductor Group 13SIEMENS ae Source of Interrupt or |Request Enable Interrupt. [Vector Trap PEC Service Request Flag Flag Vector _| Location | Number CAPCOM Regisiero —|GCoIR_—([GooIE ——(|CCOINT | 000040, | 10, CAPCOM Register GCIIR | GCHE | GCIINT” 000084, [114 CAPCOM Register? |CC2IR_—~|CC2IE «| CC2INT 000048, | 124 CAPCOM RegisiorS |CCSIR_[COSIE_—|GOSINT | 090040, | 19, CAPCOMResister4 |CCAIR—|CCAIE—GCAINT | 000050, | 144 Ccsie 5 CAPCOM cosIR, CsINT [000054 | 15, CAPCOM Register6 CBIR ——|CCBIE «| CCBINT | 0010058,, "184 CAPCOM Register? /GC7IR_——CC7IE—«|CO7INT[00008G, 174 CAPCOM Registers |CO8IR CCIE «| CCBINT | 0010060, | 18, CAPCOM Register9CC9IR_——|CC8IE | CCRINT [19.4 CAPCOM Register 10 CCIOIR_—|CCIOIE | CC1OINT Ay CAPCOM Register 11 [CC1IR —|CCIIE | CC1TINT [18,4 - CAPCOM Register 12 |Co12IR_—|CC12IE_—«|CCIZINT | 000070, | 10, CAPCOM Register 13 |CCI3IR_—[CCI3IE_|CCISINT 000074, | 1, CAPCOM Regisier 14 |GC14IA—[GCI4IE —CCIAINT | 000078, | TE CAPCOM Register 15 /CCTSIR | CCISIE —_CCISINT | 00007G, | 1Fy CAPCOM Register 16 —|CCI6IA | CCIBIE | COIGINT |0000C0, 30, CAPCOM Register 17 [CCI7IR.-——CCITIE—|CCITINT | 00100C4,, | 31, CAPCOM Register 18 |CC18IR_~——| rr 3 y Request pst | sf caPcow Timer Ty GPT2 Timer 18 coal } Ovar/Uncetiow 4 aA‘ Rood Peg. TEL scans | +) 12 outputs on caPcOME Figure 5 ‘CAPCOM Unit Block Diagram ‘Semiconductor Group 18SIEMENS cee PWM Module The Pulse Width Modulation Module can generate up to four PWM output signals using edge- aligned or center-aligned PWN. In addition the PWM module can generate PWM burst signals and single shot outputs. The frequency range of the PWM signals covers 4.8 Hz to 78.1 KHz (referred toa CPU clock of 20 MHz). The level of the output signals is selectable and the PWM module can generate interrupt requests, General Purpose Timer (GPT) Unit ‘The GPT unit represents a very flexible muttifunctional timer/counter structure which may be used {for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. ‘The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2, Each timer in each module may operate independently in a number of diferent modes, ‘or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of madule GPT! can be configured individually for one of three basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events, Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timeris controlled by the ‘gate’ level on an extemal input pin. For these purposes, each timer has ‘one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 400 ns (@ 20:MHz CPU clock). The count direction (upidown) for each timer is programmable by software or may additionally be altered dynamically by an extemal signal on a port pin (TxEUD) to facilitate e. g. position tracking, Timers TS and T4 have output toggle latches (TKOTL) which change their state on each timer over: flow/undertlow. The state o! these latches may be output on port pins (TxOUT} e. q. for time out monitoring of external hardware components, or may be used internally to clack timers T2 and T4 {or measuring long time periods with high resolution. In addition to their basic operating modes. timers T2 and T4 may be configured as reload or capture registers for timer TS. When used as capture or reload registers, timers T2 and Té are stopped. The contents of timer TS is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition ofits toggle latch T3OTL. When both 72 and T4 are configured to altemately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention, With its maximum resolution of 200 ns (@ 20 MHz). the GPT2 module provides precise event Control and time measurement. It includes two timers (T5, T6) and a capture/reload ragister (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via {a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a Port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (TEOTL) of timer T6, which changes its state on each timer overfiow/underfiow Semiconductor Group 19SIEMENS cee The stale of ths latch may be used to clock timer TS, or it may be output on a port pin (T6OUT). The overfiows/undertiows of timer T6 can additionally be used to clock the CAPCOM timers TO or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to ‘be measured or pulse multiplication to be performed without software overhead. 2eu0 (JJ ——-——, Inrapt co[ er timer 2} + regue OP Cok Tras} }! 2 c 20 +} uote cent a ou co Ply Toggle 7 ‘Mois oftson} ++) 200 oun rap | + — Request + [Rocos VA ° TaN >| Mode + on cont PY Clock sts} h erp! oer ner + ere 1 — Fo Figure 6 Block Diagram of GPT ‘Semiconductor Group 20SIEMENS Gl rsevo a PU Cock GPO Clock n=. b+] uw = if 198 | vsce [sorta timer 18 ie | cw] Ob sued fT cP Request Cr APE ren CT} woe [of CPU Clock, Contra +f +| | 2.8 i to caPcoM yet — 5 Figure 7 Block Diagram of GPT2 Semiconductor Group aSIEMENS c167 AID Converter For analog signal measurement, a 10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external citcuity. ‘Overrun error detection/protection is provided for the conversion result register (ADDAT): either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is camplete, or the next conversion is suspended in such a case until the previous result has been read, For applications wich require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins, ‘The A/D converter of the C167 supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted 10.2 digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. In he ‘Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and Converted. In addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence. This is called Channel Injection Mode, ‘The Peripheral Event Controller (PEC) may be used to automaticaly store the conversion results, into a table in memory for later evaluation, without requiring the overhead of enteting and exiting interrupt routines for each data transfer Parallel Ports The C167 provides up to 111 VO lines which are organized into eight inpuvoutput ports and one input por. All port lines are bit-addressable, and all inou¥output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The /O ports are true bidirectional ports Which are switched to high impedance state when configured as inputs. The output drivers of five WO ports can be configured (pin by pin) for pushipull operation or open-drain operation via control registers. During the internal reset, al port pins are configured as inputs. Al por lines have programmable alternate input or output functions associated with them. PORTO and PORT! may be used as address and data lines when accessing external memory, while Port 4 oututs the additional segment address bits A23/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 2, Port 8 and Port 7 are associated with the capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM module, Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. Port includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Por 5 is used for the analog input channels to the Ai D converter or timer control signals. Allport ines that are not used for these altemate functions may bbe used as general purpose /0 lines. ‘Semiconductor Group 22SIEMENS cer Serial Channels Serial communication with other microcontrollers, processors, terminals or extemal peripheral components is provided by two serial interfaces with different functionality, an Asynchronous! ‘Synchronous Serial Channel (ASCO) and a High-Speed Synchronous Serial Channel (SSC). ‘They are upward compatible with the serial ports of the Siemens SAB 8051x micracontroller family and support full-duplex asynchronous communication up to 625 Kbaud and half-duplex synchronous communication up to § Mbaud (2.5 Mbaud on the ASCO) @ 20-MHz system clock. ‘Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning. For transmission, reception, and erroncous reception 3 separate interrupt vectors are provided for ‘each serial channel In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bils, For multiprocessor communication, a mechanism to distinguish adores from data bytes has been included (8-bit data + wake up bit mode). In synchronous mode, the ASCO transmits oF receives byles (8 bits) synchronously to a shift clock \which is generated by the ASCO. The SSC transmits or receives characters of 2...16 bits length synchronously te a shift clock which can be generated by the SSC (master mode) or by an extemal master (slave mode). The SSC can stat shifting with the LSB or with the MSB, while the ASCO always shifts the LSB first ‘A loop back option is available for testing purposes. ‘A number of optional hardware error detection capabilties has been included to increase the rellabiliy of data transfers. A parity bil can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, ifthe last character received has not been read out of the receive buffer register atthe time the reception of a new character is complete. Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controlier from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overtiows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set lo a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time itis serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 25 us and 420 ms can be monitored (@ 20 MHz). The default Watchdog Timer interval after resel is 6.55 ms (@ 20 MHz) ‘Semiconductor Group 23SIEMENS Instruction Set Summary ‘The table below lists the instructions of the C167 in a condensed way. ‘The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the °C16x Family Instruction Set Manual”. ‘This document also provides a detailed description of each instruction. c167 Instruction Set Summary ‘Mnemonic |Description Bytes ADDe) ‘Add word (byte) operands aia ADDCIB) [Add word (byte) operands with Carry aia SUB) ‘Subtract word (byte) operands 2/4 SUBC(B) ‘Subtract word (byte) operands with Cary 27a MUL) __|(Un)Signed multiply direct GPR by direct GPR (16-16-bit) [2 vu) (Un)Signed divide register MDL by direct GPR (16-16-i) [2 DIL) (Un)Sianed long divide reg. MD by direct GPR (92/16-bi) | 2 CPLIB) Complement direct word (byte) GPR 2 NEG) Negate direct word (byte) GPR 2 AND(B) Bitwise AND, (wordibyte operands) fz) ORB) - Bitwise OR, (word/byte operands) ara XOR(6) __[Bitwise XOR, (woreibyte operands) 2a BCR Clear direct bit 2 BSET [Set direct bit 2 BMOVIN) __|Move (negated) direct bit to direct bit 4 BAND, BOR, BXOR ‘ANDIORIXOR dlect bit with direct bit 4 BCMP ‘Compare direct bit to direct bit a BFLOAIL Bitwise modify masked highliow byte of bitaddressable | 4 direct word memory with immediate data MP (B) ‘Compare word (byte) operands aia oMppie ‘Compare word data fo GPR and decrement GPR by 1/2 2/4 OMPlive ‘Compare word data fo GPR and increment GPR by 22/4 PRIOR | Determine number of shift cycles to normalize direct 2 word GPR and store result in direct word GPR SHL/SHR | Shittietvright diact word GPR ROL/ ROR [Rotate letvright direct word GPR ASHR ‘ithmetic sgn bit) shit ght direct word GPR ‘Semiconductor Group 24SIEMENS C167 Instruction Set Summary (contd) Mnemonic Description Bytes Movie) ‘Move word (byte) data aia MOvBS ‘Move byte operand to word operand with sign extension 2/4 Movez Move byte operand to ward operand. with zero extension [2/4 MPA, JMPI, JMPR. Jump absolutelindirect/elative if condition is met 4 IMPS Jump absolute to a code segment JNB Jump relative i direct bits (not) set ec ‘Jump relative and clear bitif direct bit is set - NBS Jump relative and set bit if direct bit is not set (CALLA, CALI, CALLR CALLS Call absolute subroutine in any code segment 4 4 4 Call absolutesindirectirelative subroutine if condition is met | 4 4 4 PCALL Push direct word register onto system stack and call absolute subroutine - TRAP Call interrupt service routine via immediate trap number | 2 PUSH, POP, Pushipop direct word register ontoitrom system stack 2 SoxT Push direct word register onto system stack and update 4 register with word operand RET Return from intra-segment subroutine 2 RETS [Return irom inter segment subrout 2 RETP | Return from intra-segment subroutine and pop direct 2 word register from system stack RETI Feturn from interrupt service subroutine 2 srt Software Reset - 4 IDLE Enter idle Mode a “is PRADA ” Enter Power Down Node ~ 7 {supposes Ni-pin being ow) sRVWOT [Service Watchdog Timer 4 DIsWwoT Disable Watchdog Timer - a EINT | Signty End-otIitialization on RSTOUT-pin 4 ATOMIC [Begin ATOMIC sequence - 2 exIR Begin EXTended Register sequence “2 EXTPIR) Bagin EXTended Page (and Register) sequence 214 EXTS(R) Bogin EXTended Segment (and Register) sequence aia NOP Nulloperation _ 2 ‘Semiconductor Group 25.SIEMENS tal Special Function Registers Overview “The following table lists all SFR which are implemented in the C167 in alphabetical order. Bit-addressable SFAs are marked with the letter "b" in column "Name", SFRs within the Extended ‘SFR-Space (ESFAs) are marked with the lotter"E” in column “Physical Address”. ‘An SFR can be specified va ils individual mnemonic name. Depending on the selected addressing ‘mode, an SFR can be accessed via its physical address (using the Data Page Pointers), of via its short 8-bit address (without using the Data Page Pointers), ‘Special Function Registers Overview Description Reset Value ‘AID Converter End of Conversion Interrupt (0000, Contro! Register AID Converter Control Register (0000,, appaT —|FEAQ, |50, __| A/D Converter Result Register 0000) ADDAT2 —FOAO, E|50, | A/D Converter 2 Result Register (000044 ADDRSEL1 | FE18,, | 0Cy ADDRSEL2 FETA, [00,, ress Select Register 1 (0000, ross Select Register 2 0000, ADDRSEL3 |FEIC, OE _| Address Select Register 3 (0000, ADDRSEL4 FETE, |0F, | Address Select Register¢ | 0000 ADEIC by ‘ND Converter Overrun Error Interrupt Control | 0000, Register BUSCONO b. Bus Configuration Register On BUSCONI b |[Bus Configuration Register t BUSCON2 b ‘Bus Configuration Register 2 BUSCONS b FFI8, 8, | Bus Configuration Register 3 BUSCONA b|FF1A, | 80,, Bus Configuration Register 4 CAPREL coo [CAPCOM Regier 0 ecole CAPCOM Regt rerupt Conte Regier [0000 co FESQ, ‘CAPCOM Register 1 - 0000, - coe b rr? CAPCOM Regt nterupi Gon Regier 0000, cca CAPCOM Regste2 0000, Comb FF7C, BE, | CAPCOM Registor 2 ion Contol Region 0000, ‘Serniconductor Group 26SIEMENS Special Function Registers Overview (cont'd) 167 Name [Physical [e-68 | Description Reset Address | Address Value ces FEBG, [43 |CAPCOMRegisier3 (0000, CO3Ie —B FF7E, [BF, CAPCOM Register 3 Interrupt Control Register | 0000, cc SNe cored |sa7teeel CAPCOM Ese Tea, CHIC FFB, |CO, | CAPCOM Register 4 Interrupt Control Register | 0000) ces FEBA, | 45y CAPCOMRegister 5 CCEIC —BLFFAQ, C1, CAPCOM Register 5 interrupt Control Register ccs FEGC, |46, CAPCOM Register 6 0000, CCBIG BD LFFE4, C2, CAPCOM Register 6 Interrupt Control Register 0000, cor FEBE, [47% | CAPCOM Register 7 (00004, CCTIC _B/FFBG, C3, | CAPCOM Register 7 Interrupt Control Register | 0000, ccs FEO, 48, CAPCOM Register 8 (00004, CCBIC FFE, C4, | CAPCOM Register 8 Interrupt Control Register| 0000,, coo FE92, [49, | CAPCOM Register 9 ~ [0000 CORIC —B/FFEA, C5, | CAPCOM Register 9 Interrupt Control Register | 0000, ecto FE94, [48 | CAPCOM Register 10 - 0000,, CCIOIC —_B/FFEC, 06, CAPCOM Register 10 Interrupt Control Register [0000 cot FE96,, 4B, [CAPCOMRegster 1 0000, CHIC b/FFEE, C7, [CAPCOM Register 11 Interupt Control Register |0000, core FE98, [40 [CAPCOM Register 12 0000}, CII FIO, (CB, | CAPCOM Register 12 Interrupt Control Register | 0000), cers FEO, [4D [CAPCOM Register 13, ~ 0000, CCI3IC b/FF92, C9, [CAPCOM Register 13 Interrupt Control Register | 0000), cca FESC, aE, | CAPCOM Register 14 (00004 CCIAIGb FFB4, CA, | CAPCOM Register 14 Interrupt Contro! Register | 0000, ccs, FEQE, 4Fy | CAPCOM Register 15, (0000), CCISIC —b FF26, CB, | CAPCOM Register 15 Interrupt Control Register | 0000), ccis FE60, 90, __ [CAPCOM Register 16, 0000 CCIBIC F160, E 80, | CAPCOM Register 16 Interrupt Control Register | 00004, cci7 FE62, Sty [CAPCOM Register 17 0000, Semiconductor Group orSIEMENS ly ‘Special Function Registers Overview (cont'd) Name Physical |8-Bit | Description Reset Address | Address [Value F162, E)B1y __, GAPGOM Register 17 Interrupt Control Register 0000, FECA, | 32, SAPCOM Register 18 0000), F164,, E82, [CAPCOM Register 18 Interrupt Contiol Register [0000 FE65, | 33, CAPCOM Register 19 0000), F166), E83, | CAPCOM Register 19 interrupt Control Register | 0000, EGS, "| CAPCOM Register 20 - 0000, F168, E84, CAPCOM Register 20 Interrupt Control Register | 0000, Ay CAPCOM Register 21 ©0000, CAPCOM Register 21 Interrupt Control Register | 0000) — CAPCOM Register 22 [o000,, ‘CAPCOM Register 22 Interrupt Control Register | 0000. CAPCOM Register 23 | 000044 CAPCOM Rgister 28 interrupt Control Register| 0000}. CAPCOM Register 24 0000). CAPCOM Register 24 Interrupt Control Register | 0000, “CAPCOM Register 26 0000, CAPCOM Register 25 interrupt Control Register 0000), CAPCOM Register 26, 0000, CAPCOM Register 26 Interrupt Control Register | 0000,, CAPCOM Register 27 (0000), cearic CAPCOM Register 27 Interrupt Control Register | 0000, cc28 | CAPCOM Register 28 (0000), ce2sic CAPCOM Register 28 Interrupt Control Register | 0000), 29 CAPCOM Register 29, (0000, ecze1c “CAPCOM Register 29 Intemupt Control Reaister 0000, cso CAPCOM Register 30, 0000, cesoic ‘CAPCOM Register 30 interrupt Control Register | 0000,, cost ‘CAPCOM Register 31 a cose b CAPCOM Register 31 Intertupt Control Register | 0000, Semiconductor Group 28SIEMENS ey Special Function Registers Overview (cont) Name [Physical [-Bi Description a () fatrese_Aderess Value emo b/FFEE, AS, [EAPCOM Mode Conse Ragitar —_—_—|00004 cout _b’FFS4, AA, CAPCOM Mode ContolRegstor+ —— 0, cCM2, bIFFS6, | AB, | CAPCOM Mode Control Register 2 0000, - Cows bIFFSG, AC, CAPCOM Mode ContolRepsier3 ~~ 00 COM4 BFPO, | ty CAPCOM Mode Control Register 4 00004 CMS Db FF244 92 "| CAPCOM Mode Control Register 5 0000, come b Fa5, CAPCOM Mode Control Regstors 0000), cow _b FF, CAPCOMMode Con Register? ~~~ 0D, cp FEO, {PU Conon Pointer Register F000, cic _b FFoA, GPTECAPREL Ierupt Conti Regier 0000, csp FEO, CPU Code Segment oie Reis (aan) | 0000, oPOL_b FI00 € 80, Cento Register oO, oPOH b FI02y € 81, recon Gone Register ———SS_«4(O DPIL _B/FI0% £/e2, PIL Ovecton Corto! Regs Too. DPW b F106,, Efe, PIMDvecton Conta Regsier ——SS«( oro b FFc2, Ely : 000 Ps. £3, 0000) ope 5, Port Drecton Conti Ragster 00,4 Ps hy | Pa Diecton Contl Regier 004 DP? ES, Port 7 Direction Control Register [004 ore By, Part Dieton Cont Regier 00, pee 20, CPU Data Page Pits O Register (bi) 0000, PPI O14, “CPU Data Page Pointer 1 Register (10 bits) 0001, pez Joe, CPUs Page Porter Regster (bis) 0002, Pra 3, CPU Data Page Poinior Seite (10 bis) | 00004 ERIGON b|FICO, €]EO, External tpt Contol Regier WoC b/FFOE, |e7, CPU Muy Onde ContolRegitor WoH | FE0C,,|06, "CPU Mutiny Ode Regier High Word wo. 7, CBU Muy Die ‘Semiconductor Group 29SIEMENS Special Function Registers Overview (cont) C167 Name Physical 6-Bit | Description Reset Address | Address Value O02 B'FIC2, E/Ety | Port 2 Open Drain Control Register (0000, (0005, F105,_e|E5, [Pon 3 Open Oran Cone Regier 00, ODPE—BIFICE, E/E% Port 6 Open Drain Control Register 00,4 ODP7 —_bIF1D2, E/E, | Port 7 Open Drain Gontiol Register 00, opps —_bIFID6, E EB, | Port & Open Drain Control Register 004 ONES FFIE, |8Fy | Constant Value 1's Register (read only) FFFF Pow, b FFOO, | 80, Port 0 Low Register (Lower half of PORTO) 00,4 POH BIFFOQ, aly Port 0 High Register (Upper half of PORTO) | 00), Pita Fou | 2q_ Pet 1 Low Roper (Loworhat of PORTS) {0D PIH | FFO6, 63, | Port High Register (Upper half of PORT!) | 00 PaReEin Fe cora cage | a2 ogc 0000, P3 DIFFCA, [E2, [Port 3 Register (00004 Pa b FFCa, |E4 | Port 4 Register (@ bits) 00, Ps bIFFA, [Diy [Port S Register (ead only) XXXXy Ps DIFFCC,, |E6y Port 6 Register (8 bis) — 0, 7 b/FFDO, | EB, Port 7 Register (8 bits) 004, PB BIFFD4, EA, | Port ® Register (@ bits) 004 60, | PEC Channel 0 Control Register (00004, 61x __| PEC Channel 1 Control Register 0000, 62, | PEC Ghannol 2 Control Register 0000), 63, PEG Channel 3 Gontrol Register 2000) 64,, | PEC Channel 4 Controi Register 0000, 65, | PEC Channel § Control Register 0000, 66, [PEC Channel 6 Gontol Register [00004 67 | PEC Channel 7 Control Register 0000, 1Cy___ | PWM Module Period Register 0 00004, 1D, | PWM Module Period Register 1 2000) 1E, PWM Module Period Register 2 [00004 1Fy__ | PWM Module Period Register 3 00004 ‘Semiconductor GroupSIEMENS Special Function Registers Overview (cont) C167 Name Physical &-Bit |Description Roset Address , Address Value FEW BL FFIOy 188 (CBU Program Sizus Word 000, PTO | PWM Module Up/Down Counter 0 0000 Prt PWN Module Up/Down Counter 1 0000 pre PWM Module Up/Down Counter 2 0000, PTs PWM Module Up/Down Counter 8 “90004, Pwo FES, | 18, PWM Module Pulse Width Register 0 0000), wi FES2, [194 | PWM Module Pulse Width Register 1 00004, Pwe FES4, | 1A, __| PWM Module Pulse Width Register 2 0000, Pw FE36,, | 18, | PWM Module Pulse Width Register 3 0000, PWMCONOb FFI0, | 98, PWM Module Control Register 0 0000, PWMCON1b FF32,, [99 | PWM Module Control Register 1 0000, PWMIC bFI7E, E[BFj, | PWM Module Interrupt Control Register (0000%, POH —_b F108, E84, | Systom Startup Configuration Register (Ra. only) | XXy 30BG —-FEG4,, [5A, | Serial Channel 0 Baud Rate Generator Reload | 0000, Register SOCON b FFBO, [D8 | Serial Channel 0 Control Register (0000,, SOEIC —b FF70, |[B8, | Serial Channel 0 Error Interrupt Control Register | 0000), SORBUF —FEB2, 59, Serial Channel 0 Receive Butfer Register XX (read only) SORIC —B FF6E, 87, Serial Channel 0 Raceive Interrupt Control 00005, Register SOTBIC b F19C, E/CE, Serial Channel 0 Transmit Butfer Interrupt Control | 0000, Register SOTBUF FEB, [58 | Serial Channel 0 Tranemit Buller Register 00, (write only) SOTIC —B|FFEC, |b, Serial Channel 0 Transmit Interrupt Control | 0000, | Register SP TFE12, | 094 CPU System Stack Pointer Register FOO, SSCBR FOB, E/5A, | SSC Baudrate Register 0000, SSCCON b FFB2, |09, | SSC Control Register 0000, SSCEIC b FF76, [BBy | SSC Error interupt Control Register 0000, Semiconductor Group 31SIEMENS ‘Special Function Registers Overview (contd) c167 Name Physical [8-8it |Description Reset Address | Address Value SSCRB | FOB, E)59, | SSC Receive Butfer (read only) XXX, SSCRIC BA, __ | SSC Receive Interrupt Control Register 0000, s8cTB E]58, | SSC Transmit Buffer (write only) 0000, SSCTIC b|FF72, |B9, SSC Transmit interrupt Gontrol Register 0000, STKOV|FE14, [0A, _| CPU Stack Overtlow Pointer Register FA00, STKUN | FE16, [08 CPU Stack Undertlow Pointer Register C00 SYSCON b) 9 __| CPU System Configuration Register 0x10") CAPCOM Timer 0 Register 0000), ‘CAPCOM Timer 0 and Timer 1 Control Register | 0000}, CAPCOM Timer interrupt Control Register | 0000, ‘CAPCOM Timer 0 Reload Register (0000, 29, | CAPCOM Timer 1 Register 0000, CAPCOM Timer 1 interrupt Control Register | 0000, ~ [CAPCOM Timer t Reload Register | 0000, | GPTT Timer 2 Register (0000 GPT1 Timer 2 Control Register 00004, GPT1 Timer 2 Interrupt Control Register (0000, GPT! Timer 3 Register 0000 | GPT1 Timer Gontroi Register 0000 GPT1 Timer 3 interrupt Control Register 0000 GPTI Timer 4 Rogister (0000, ‘GPT1 Timer 4 Control Ragister 0000, GPT Timer 4 Interupt Control Register 0000, 29, __| GPT2 Timer 5 Register (00004. ‘A3,__| GPT2 Timer § Gontrol Register 0000 T5IC_bBIFF65, [B3, _GPT2 Timer interrupt Control Register (0000 16 FE%8, [24 | GPT2 Timer 6 Register 0000, T6CON _b/FFA, |A4, | GPT2 Timer 6 Control Register | 0000, T6IC _bB|FF6B, B4, _| GPT2 Timer 6 Interrupt Contol Registor 0000, Semiconductor Group 32SIEMENS ‘Special Function Registers Overview (cont'd) c167 Name Physical |6-Bit | Description “Reset Address | Address | Value 7 F050, E28, CAPCOM Timer 7 Register 0000,, T78CON _b FF20, ‘CAPCOM Timer 7 and 8 Control Register 0000,, Tic b FI7A, E "CAPCOM Timer 7 Interrupt Control Register 0000, TIREL F054, E ___ CAPCOM Timer 7 Reload Register 0000,, Te F052 E|29, CAPCOM Timer 8 Register (0000, Tae BIFITO, E ‘CAPCOM Timer 8 Interrupt Control Register| 0000, TREL TFO56, E| ‘CAPCOM Timer 8 Reload Register 0000, TER bl FFAG), ‘Trap Flag Register 0000}, wor FEAE, ‘Watchdog Timer Register (read only) 0000, WOTCON |FFAE, Watchdog Timer Control Register 0000, XPOIG | F186), X-Peripheral 0 Interrupt Control Register ‘0000, XPHC Bb IFI6E, ~__X-Peripheral Interrupt Control Register (0000, xP2IC IF 196, "-X-Peripheral 2 Interrupt Control Register 0000,, XPIC Bb FISE, X-Peripheral 3 Interrupt Control Register 0000), ZEROS b FFIC, “Constant Value 0's Register (read only) 10000}, *) The system configuration is selected during reset Note: The Interrupt Control Registers XPnIC are prepared to contvol interrupt requests trom integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit, Sorniconductor Group 33SIEMENS cia Absolute Maximum Ratings Ambient temperature under bias (7) SAB-C167.LM.... soon 0t0+70°C SAF-C167-LM 40 to + 85°C Storage temperature (7) = 6510+ 150°C Voltage on Vz. pins with respect to ground (Vx) -0510+85V \Voltage on any pin with respect to ground (Vse) 05 t0 Veo 4 05V Input current on any pin during overload condition = 1010+ 10 mA Absolute sum ofall input currents during overload condition, . 1100 mA Power dissipation 15W Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Thisis a stress rating only and functional operation of the device at these or any other conditions above thase indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may atfect device reliability. During overload conditions (Vs, > Ver OF Vy Vas) the voltage on pins with respect to ground (Vs) must not exceed the values defined by tho ‘Absolute Maximum Ratings. Parameter interpretation The parameters listed in the following partly represent the characteristics of the C167 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column *Symbo CC (Controller Characteristics} ‘The logic of the C167 will provide signals with the respective timing characteristics. SR (System Requirement): The extemal system must provide signals with the respective timing characteristics to the C167. DC Characteristics Voc=5V10% Vos=0V; — fopy=20MHz. T,=0t0+70'C for SAB-C167-LM T, = 4010.4 85°C for SAF-C167-1M Parameter Symbol | Limit Values __| Unit. [Test Condition min. ma Input low voltage My, SR/-05 [02Vee |v |- on Input high voltage (all except ASTIN and XTAL1) Input high vottage RSTIN input high voltage XTALI Semiconductor Group wnSIEMENS cr67 Parameter 7 ‘Symbol | Limit Values | Unit [Test Condition min. [max. . Output low voltage Va. 6G|- 045 V [t= 24mA (PORTO, PORT!, Port 4, ALE, RO, WR, BHE, CLKOUT, RSTOUT) I Outputiow watage Vo. 66|= 045 /V day = 16mA {allother outputs) Ouiput high voltage Vou 60109 Vex | V | oy=—800 uA (PORTO, PORT, Port, ALE. AD, 24 Tau== 24 mA WA, BHE, CLKOUT, RSTOUT) Output high voltage * Vous CC 0.9 Veo = v Joy = — 250 pA - {allother outputs) 24 V fox ==1.6mA Input leakage current (Port §) 2) | fox, OC |— +200 mA |0V< Vy < Veo Input leakage current all other) | fazs_ OC — £500 [AA [OV = Vn< Vor FSTIN puliuo resistor |Rasr CC] 50 150 ka [= Read/Write inactive current a tem 2 = | 150 VA | Vour= 2.4 ReadiWite active curont [lag #7 ~1800 |= WA | Veur= Vora ALE inactive current 9 Ing. 9 i- 150, WA | Vour = Vous ALE active current 8 Jaen | 2000 - WA | Vour = 2.4 V Port 6 inactive current °) foo 8 |= 150 WA | Vour=2.4¥ Port 6 active current * ja WA | Your = Vox imax PORTO configuration current * 10 HA | Vou = Viren E WA | Vin= Vin XTALT input current a cc|- +20 WA [OV < Vin < Veo Pin capacitance 9 - Go CC} 10 pF MHz (digital inputs/outputs) Ta = 25°C Power supply current a 304 MA — Reset active 8 x/eru Jepy (M2) Idle mode supply current — dg CCl = [20+ mA | fepyin [MHz] 7) 3Xferu Power-down mode supply current | Jey CC] — 100 HA [Voo=5.5V% Semiconductor Group 35SIEMENS C167 Notes 1) This specication isnot va or outputs which are switched fo open drain mode. n his case the respective ‘output wi foal and the votage results from the extemal cicuty ‘This specication does not apply to the analog input (Port 5.x) which is curerily converted “The maximum current may be crawn while the respective signal line remains inactive. “The minimum curent must be drawn in order to crive the respective signal ine active. “This specication only vald during Rese, or during Hold- oF Adap-mode. Por 6 pins are onty allected, i they are used for CS output and the open drain tuncton isnot enabled. Not 100% tested, quarantead by design characterization. 7) The supply curtentis@ function ofthe operating frequency. This dependency i ilusrated inthe figure below. ‘These parameters ae tostad at 20 MHZ CPU clock with al OUpLIS open. All inputs (nelusing pins conigured as inputs) at OV 10.0.1 Vor atVgg ~ 011 V0 Voc. Ver = OV, all uspUS (including pins contgured as outputs) disconnected, ima 200: 150: 100 50 Figure 8 ‘Supplylidie Current as a Function of Operating Frequency ‘Semiconductor Group 36SIEMENS er AID Converter Characteristics Vec=5V=10%; Vsg=0V Ty=Oto+70'C for SAB-C167LM Ty=~ 4010 4 85'C for SAF-C167-LM 4OVE Vener € Veo + 0.1 V; Vas -O.1 VS Vaone © Vas + 0.2 ¥ Parameter ‘Symbol | Limit Values [Unit |Test Condition ‘min. [max Analog input voltage range Van SR[Vacw [Varner [V | ‘Sample time ts 00|~ 2 iso ae ‘Conversion time te Cl Wt a aTeL Total unadjusted error TUE Gol— #2 uss |* Internal resistance of reference | Ryser SR] — oe 1250 | k62 | foc in ins) © voltage source 0.25 internal resistance of analog RasacSR]— 15/500 [ka [iin ins] 77 source -025 ADC input capacitance Can CC} 50 pF |” Notes +) Vay may exceed Vagno OF Vaper up 10 the absolute maxmum ratings. However, the conversion resu in these cases willbe X000, or XSF Fy, respecively uring the sample tme the input capactiance Cj can be chargeaiaischarged by the external source. The Intornal resistance of the analog source must allow the capacitors to reach ther fal voltage tevel within. ‘Ate the end o the sample timers, changes ofthe analog input voltage nave no effect onthe conversion resi. ‘Values for the sample cock ig¢ depend on pragramming and can be taken trom the fabie below. “This parameter includes the sample time , the ime for determining the digital fesult and the ime to load the result register wih the conversion result ‘Values for tie conversion clock i¢¢ depend on programming and ean be taken trom the table below: “This parameter depends on the ADC contol logic. Is nota real maximum value, but rather a faum. “TUE is tested at Vance = 5.0 V. Vacno = 0, Voc = 4.8 V. It's quarartoed by design characterization frat ‘ther volages within he delined volage range. © During the conversion the ADC's capacitance must be repeatedly charged or discharged. The intemal Fesistance of he reference vollage source must alow the capacitors to reach their respective vollage lovel ‘wan rec. The maximum intemal resistance results from Ine programmes conversion tng, 7) Not 100% tested, quarantood by design characterization. 2 9 * 9 ADCON.15I18 [Conversion Clock fee [ADCON.13112 | Sample Clock ec cy ToL x32 oo ‘ee or Reserved, donot use or tec X2 0 TOL x 128 10 tee x4 i ToL «ea 1 cox ‘Semiconductor Group aSIEMENS ce Testing Wavetorms nav TIS, | Tas Pons < A2v-081 0.2%.-0.0° 0.48 AC inputs during testing are driven al 2.4 V for a logic ‘t” and 0.4 V for a logic ‘0 ‘Timing measurements are made at ¥,min for a logic “1” and V, max for a logic Figure 9 Input Output Waveforms Yous “O.1¥ ha 10.14 For timing purposes a port pin is n0 longer floating when a 100 mV change trom load voltage occurs, butbeginsto float whena 100 mV change fromtheloaded Vi./Vay leveloocurs oul, = 20 mA, Figure 10 Float Waveforms Semiconductor Group 38SIEMENS cee [AC Characteristics External Clock Drive XTAL1 Voc=5V 110%: Vas= OV Th=010+70'C tor SAB-C167-LM T= = A010 +85 © for SAF-CI67-LM Parameter ‘Symbol | Max. CPU Glock | Variable CPU Glock] Unit 0 MHz UZTCL = 1 t0 20 Miz min. [max | min, max. Oscillator period Tet sR|25 25 25 500 ts sale = 6 : ns 1 sale = 6 7 ns 6 sAl- 5 = 5 ns 4 sh[- 5 = 5 8 Figure 11 External Clock Drive XTAL1 Memory Cycle Variables crores ‘The timing tables below use three variables which are derived from the BUSCONs registers and represent the special characteristics of the programmed memory cycle. The folowing table describes, how these variables are to be computed, Description ‘Symbol Values ALE Extension he TGL x Memory Cycle Time Waitstates [ic 2TCL x (18 - Wa \ vA WAL, WAH ; Figure 12-3 External Memory Cycle: Multiplexed Bus, No ReadiWrite Delay, Normal ALE ‘Semiconductor Group 44SIEMENS et A23-A16. —— Read Cycle fly et ress fata in SSS ous Cran 3 Write Cycle ‘ iz —— hi, eh oa wR \ f WRU, WAH — oly iy Figure 12-4 External Memory Cycle: Multiplexed Bus, No ReadiWrite Delay, Extended ALE ‘Semiconductor Group 45SIEMENS Gl AC Characteristics (contd) Demuttiptexed Bus =5VE10% —Vgp= OV 010+ 70°C for SAB-C167-LM = 40 to + 85°C for SAF-C167-LM G. (lor PORTO, PORT!. Port 4, ALE, AD, WA, BHE, CLKOUT) = 100 pF C {for Port 6, CS} = 100 pF ALE cycte time = 4 TOL + 214+ 1c + fe (100s at 20-Mez CPU clock without waitstates) Parameter ‘Symbol | Max. CPU Clock | Variable CPU Clock | Unit ' = 20MHz 4V2TCL = 1 to 20 MHz min. [max. min, max ALE high time 6 OC/18+m | TEL—10+%|- ns ‘Address setuptoALE CC t0¥m | TOL= 18 +%4|— ns ALE faling edgetoB, 4 CCltS+ To.-10 |= ns WR (with AW-delay) +h ALE falling edge 10D, [fe CC) 10444 |= =10 = ns WA (no RW-delay) +t fe 06/4040 |— zroL-10 | ns tte RD. WA low time ty OC 654i |= sreL-10 |= ns (10 RW-delay) tte AD to valé data in hy SR) Brie 2to.—25 [ns (with RW-delay) lees AD to vali data in he SR Bor |= STCL-25 ns {no RW-delay) tHe [ALE low to valid data in SRI 50 = sTcL—25 [ns | ttle tint te Address to validdata inf) SR,~ 65 7 4TOL-35. | ns + 2ta tte + 2h tte Data hoid atter FD hy SRO = ° = ns fising edge Data float after RD rising 1. SR) — 5h 2TCL-15 ns. edge (wvth RW. delay) tte Data float after RB rising |, SR/— ase, [= ToL-10 [ns edge (no RW-delay) te Data vail to WF te OC) 4 arer~ 15 | ns tle Data hold atter WA liu CC[1S 4% |- TCL=10 +1, ~ ns ALE tising edge atter AD, |p CG |— 104% [— 10 = ns we +e i Semiconductor Group 46SIEMENS er Parameter Symbol] WMax.CPU Clock | Variable CPUCIock | Unit 20MHz WRTCL = 110.20 MHZ max. min. max. ‘Address hold after RD, [is = o 7 8 wa tte ALE fling edge 10S =m |-8-m(1-m as CS iow to Valid Data In 48 - sTCL-30 | ns Het 2 tlo+ 2 Whois ater AD.WA ly CC/O+n | To-15 = ns te ALE falling edge toRACS, ta CC/20+% |- Ta-5 |= ns. WreS (wih RW-delay) te : ALE fang ode 10 RACS, ig CCS +m — =5 = m8 WIS (no AW-deay) lem RECS 10 Vaid Data in (re SA 2041 = aTcL=30 [ne (wth RW-dely) - te FACS 10 Valid Dataln ry) SA ae arci=30 [ns (0 FW-seiay) tte RAS, WES LowTime ty CC AO+t aTeL-10 ns (oth FiWdeay) ] +e FACS, WICS tow Time fy CC/ESv% | sroL-10 |= 18 (ro PWdelay) tte Data vaidtoWCS |p OO]a5+1 | areL-15 = cs He Data hold after RCS [im SR/O = ° 5 ns Data oat ater RECS [uy SR)— Bem 2TCL-20 [ns (win Relay) + Data oat ater REGS (ty SA! ben TeL-20 [ns (no RW.celay) + Address hold ater fy OCH 4% | a1 . 78 FACS, Wrcs | +e DataholdatterWiS | CC 104% — ToL 15 \ns — Eafe l ‘Semiconductor Group ceSIEMENS ew A23-A16 hs ee yet te tos BU Read Cycle as Cian SD D7-D0 Write Cycle ti BUS = 5 WAL, WAH ——_t—4t L EuuEEUEEEEEEEEEENEESSSSSESSSSSSSESESESEEEEEEESEEEEEST Figure 13-1 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Serniconductor Group 48SIEMENS ced a a Ae 4 \ 4 \ be Aye, . A23-A16 —_—__ 9 O— Aga Raess HK are ay ae —n— Bead Gucle boty ai (015-08) €_batain > 07-00 0 Ram wa BUS (015-08) 7-b0 Figure 13-2 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE ‘Semiconductor Group 49A23-A16 (015-08), vr-p0 7] t = ts FO \ 4 RaCse —— | | Write Gyete ona | bus Z (015-08) Data Oat | | Dr-bo | wa, ee es Wa, WAH f Figure 13-3 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group 50SIEMENS cee OME ——__, Eas) BHE ibs nea Se (015-08) < taain D> 07-00 Write Cycle ee be = te +i — — fee ef Wes \ fo —. Figure 19-4 External Memory Cycl : Demultiplexed Bus, No ReadWrite Delay, Extended ALE ‘Semiconductor Group 51SIEMENS C167 ‘AC Characteristics (cont'd) ‘CLKOUT and READY Voc=5V 210% Vos = OV Te=0to+70°G tor SAB-C167-LM Ty=~ 4010+ 85°C forSAF-CI671M G, (lor PORTO, PORT!, Port 4, ALE, AD, WR, BAE, CLKOUT) = 100 pF G. tor Por 6, CS) = 100 pF Parameter _ ‘Symbol | Max. CPU Clock Variable CPU Clock Unit 20 MHz 4I2TCL = 1 10 20 MHz min. [max [min, max. CLKOUT cycle time tou CC |50 50 2ToL etc. ns. CLKOUT high time ‘mm OC |20 E Te-8|- ns CLKOUT low time ty CC) 15 J TCL-10 | ns CLKOUT rise time te _OC|- 5 5 5 ns GLKOUT fal time yy |= 5 = 5 ns GLKOUT sing edge to jiu CClO+n ~10em [Orn 10m [ne ALE falling edge Synchronous READY fim SA) 18 = 6 7 ns setup time to GLKOUT Synctvonous READY | 1,, SR/5 = 5 = ns hold time after OLKOUT Asynchronous READY | ty) SA 65 = aroL+ 16 |- ns tow ume Asynchronous READY ta S115 - 15, - ns setup ime " ‘Agynchronous READY SRlo = ° = "8 hold time ‘sync. READY hold tme [tw SATO 0 ° ToL-25 [ns ater AD, WA high £2, +46 +2 + (Demultipiexed Bus)?” a 2 Notes These timings are gwen for tast purposes ony, sn order to assure recagaition ata specie clock edge. 7) Demultplexed bus i the worst case. For mumpiexed bus 2TCL are tobe aed to the maximum values. This ‘adds oven more ime for deactwaing READY ‘The 2iq reer to the next foiowing bus eve ‘Semiconductor GroupSIEMENS cacy READY + unning cycle warstate_j MUX/Tristate 5 bs ououT \ NN YN NZ | sr t tu Command XEX x RO, WA ¢ bes | ite by i ite} Syn t READY. , Figure 14 CLKOUT and READY Notes ° oycle as programmed, including MCTC watstates (Example shows 0 MCTC WS). The leading edge of the respective command depends on RW-dolay. «+ HERBY sampiea HIGH at ns sampling point generates a READY controlled watstate READY sampled LOW al ths sampling port terminates the curently running bus cycle EADY may be deactwated in response to the trating (rising) edge of the cortesponding command (0 ot WR * ifthe Asynchronaus READY signal does rot util the ineicated setup and hokd nes wih respect to CLKOUT (eg. because CLKOUTs not enatled), t must full n order 19 be salely synchronized. THs is quarantoed, 1" READY ic removed in response to the command (soe Note“) Multiplexed bus modes have @ MUX waitstate added ater ats eyelo, and an addtional MTTC wattslate may be inserted nere, For a multiplexed bus with MTTC wattslate Ins delay 's 2 CLKOUT cycles, fr a demutipiexed bus without MITC waitslate tis delay is zero. "The next external bus cycle may start here, ‘Semiconductor Group 53SIEMENS C167 AC Characteristies (cont) External Bus Arbitration Veo=5V+109%; Voss OV Tr= 010+ 70°C. for SAB-CI67-1M Th=~40t0 + 85°C for SAF-C167-LM G. (lor PORTO, PORT!, Pon 4, ALE, (lor Port 6, 6S) = 100 pF WR, BHE, CLKOUT) « 100 pF Parameter Symbol | Max. CPU Clock Variable CPU Clock [Unit = 20 MHz 112TCL = 1 to 20 MHz _ min. [max. | min. ‘max. FOLD input setup time [z,, SR] 20 = 20 = nS to CLOUT CLOUT to HLDA hgh J, CCl 20 = 15 or BREQ low delay CLKOUT to HULDA low [iu Co] — 20 = ns or BREG hugh delay CSkreiease cc) ~ 20 S 20. ns CExanve 28 5 2 95 Other signalsrelease [tue CC] - 20 = 20 5 Other signals dive i OC 25 6 25 98 ‘Semiconductor Group 54SIEMENS cist L/ Yj AUDA oy YY Yn Sy fe 9 conten) thy serals YY > 7 0 Figure 15 External Bus Arbi 1, Releasing the Bus, Semiconductor Group 55SIEMENS ote om” (On 6.x) Other ., Signals Figure 16 External Bus Arbitration, (Regaining the Bus) Notes Tins 1s the tat chance for BREG to trigger the insicated regain-sequence_ Even # BREQ is actwatod oarier he regam-sequence « tiated by HOLD going Nh Please note that HOLD may also be deactivated without the C167 requesting the BUS. 2) The next C167 diven bus cycle may stat net. ‘Semiconductor up 58SIEMENS Package Outline Plastic Package, P-MOFP-144-1 (SMD) (Plastic Metric Quad Flat Package) | {S10.2-0)0) 445 410-2810 Nex Figure 17 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information’ ‘SMD = Surface Mounted Device Semiconductor Group 87 C167 Dimensions in mm