1 Introduction To Boundary-Scan

Medalist i3070 In-circuit Test System
Boundary-Scan Testing
1
Introduction to Boundary-Scan
Overview 1-2
Boundary-Scan Background and Applications 1-3
The Boundary-Scan Device 1-11
Operation Modes and Instructions 1-19
Hold States 1-22
Test Functions 1-31
Tap Controller State Diagram 1-44
1-1
1 Introduction to Boundary-Scan
Overview
The Agilent Boundary- Scan Software supports the testing of digital devices
that comply with IEEE Standard 1149.1. Test developers can effectively
and efficiently test digital devices while significantly reducing test
development time. Fault coverage and diagnosis can improve when
boundary- scan is implemented.
This chapter gives you an overview and background information about
boundary- scan and the IEEE Standard 1149.1. It covers the following:
• A description of a boundary- scan device.
• A description of the Test Access Port (TAP) Controller.
• A description of the Instruction Register and Data Registers.
• A description of the Boundary- Scan tests and hold states.
• A description of the Boundary- Scan instructions.
• A description of the TAP Controller State Diagram and its importance
to boundary- scan testing.
• A simple test program showing the vectors that the Boundary- Scan
Software generates for your board test.
Parts of this chapter are derived and/or reprinted from IEEE Std.
1149.1- 2001, IEEE Standard Test Access Port and Boundary- Scan
Architecture, Copyright © 2001 by the Institute of Electrical and
Electronics Engineers, Inc. Information is reprinted with the permission of
the IEEE. In the event of any discrepancy between this document and the
original IEEE Standard, the IEEE Standard takes precedence.
1-2 Boundary-Scan Testing

Introduction to Boundary-Scan 1
Boundary-Scan Background and Applications

Boundary- Scan has many practical applications. This section introduces
the applications and describes how they can be implemented, as well as
how they meet your board test needs.
• What is Boundary- Scan?
• Why Boundary- Scan?
• How Can Boundary- Scan Solve These Problems?
• The Manufacturing Fault Spectrum
What is Boundary-Scan?
Boundary- Scan is a test technique that involves devices designed with
shift registers placed between each device pin and the internal logic as
shown in Figure 1- 1. Each shift register is called a cell. These cells allow
you to control and observe what happens at each input and output pin.
When these cells are connected together, they form a data register chain,
called the Boundary Register.
Figure 1-1 A boundary-scan device
There are other registers within a boundary- scan device.

• An Instruction Register decodes instruction bits that allow the device to
perform various functions.
• A Bypass Register provides a one- bit path that minimizes the distance
between the scan input and the scan output.
Boundary-Scan Testing 1-3

• An Identification Register, called the IDCODE Register, identifies the

device and manufacturer.
• Other designer- specified data registers typically perform internal test
functions.
Boundary- scan devices have a dedicated port, called the Test Access Port
(TAP), that routes input signals to a controller, called the TAP Controller,
and the register cells. The TAP Controller is a 16- state machine that
controls the Boundary Register. Figure 1- 2 is a simplified block diagram of
a boundary- scan device.
The signals shown in the illustration are the TAP inputs used to control
the boundary- scan device. They include:
• Test Data In (TDI): The serial input for test data and instruction bits.
• Test Data Out (TDO): The serial output for test data.
• Test Clock (TCK): An independent clock used to drive the device.
• Test Mode Select (TMS): This provides the logic levels needed to change
the TAP Controller from state to state.
Figure 1-2 Simplified block diagram of a boundary-scan device
Test Data Registers
G1
MUX
TDO
ModeN
Mode1
Mode2
Mode3
Select
TDI
Instruction Register
Reset*
Clock-DR
Shift-DR Reset*
Update-DR Clock-IR
Shift-IR
TAP Controller Update-IR
TMS
TCK
(16-State Select
TRST* Machine)
* Active-Low Signal

Boundary- scan devices can perform many test functions. Three of these,
EXTEST, SAMPLE/PRELOAD, and BYPASS, are mandatory for every
boundary- scan device. Four other test functions, INTEST, RUNBIST,
IDCODE, CLAMP, HIGHZ, and USERCODE, are described by the IEEE
standard, but are optional. Manufacturers can also add test functions
whose implementation is guided by the IEEE standard.
Why Boundary-Scan?
At the end of a circuit board manufacturing assembly line, the circuit
board circuit board should meet its specifications. For that to happen, the
following must be true:
• A: All components work according to their specifications.
• B: All components were mounted in the right position.
• C: All component's pins were properly soldered to the circuit board.
• D: All components function together to meet the specifications.
To achieve this, you could apply different test strategies:
• Incoming inspection to verify (A), followed by in- circuit test to verify
(B) and (C), followed by functional test to verify (D).
• Assuring good components from vendors by quality audits (A).
Production in- circuit test to verify (B) and (C), followed by system test
(D).
• Statistical incoming inspection to verify (A), followed by functional test
to verify (B) and (C) where in- circuit test performs diagnosis, and
finally system test to verify (D).
• No incoming inspection, but combinational (both in- circuit and
functional) test to verify (A), (B), and (C). D is assured through a worst
case design philosophy.
These are just a few of the primary test strategies; many others are
possible. There are, however, some concerns about these test strategies for
the future:
• Tests for complex ICs and ASICs are time consuming to develop and
can delay time to market.
• Limited node access can restrict the in- circuit test option.
Functional cluster test or full, edge- connector functional test can be a
solution to this, but complex designs and a pressure to reduce time to
market can make this option less attractive because functional test
development is normally a process that takes a long time. One way to
alleviate this problem is to implement concurrent engineering, which
involves developing the test while developing the circuit board.

Another method that can be used to solve the complexity and node access
problems is Design For Testability (DFT), which involves designing test
components into the device. Boundary- Scan is one DFT strategy that is
gaining momentum and shows promise for solving these test problems.
Boundary- Scan addresses mainly (B) and (C) of the test objectives for
digital devices; it can also address (A). Boundary- Scan does not address
analog test problems.
How Can Boundary-Scan Solve These Problems?

IEEE Standard 1149.1 is open- ended and provides many alternatives for
addressing a variety of design needs. This open- ended standard, together
with the fact that boundary- scan can be implemented on a circuit board
in many ways, provides the flexibility needed to address device test
problems.
Implementation can range from a circuit board with only one
boundary- scan component, to a board with all digital devices having
boundary- scan. Configuration concerns include how boundary- scan devices
are connected to the rest of the devices on the circuit board, as well as
how they are connected to other boundary- scan devices. Both of these
concerns affect test strategy.
New tools must be flexible so they address the implementation and
configuration concerns. The following scenarios examine a few
implementations that are likely to occur in the board test environment.
They also describe how boundary- scan contributes to better testing for
each implementation.
• Scenario 1
• Scenario 2
Scenario 1
Implementation: Few boundary- scan components on the board.
(Figure 1- 3 shows an example with only one boundary- scan component.)
Configuration: Boundary- scan components not connected to one another.
Strategy: The best test strategy for this case is to use a bed- of- nails
approach and to place test probes on all nodes.
Agilent uses traditional in- circuit test methods including unpowered shorts
tests and conventional tests for non- boundary scan digital devices.
Boundary- scan devices are tested using a function known as EXTEST. (For
a description of boundary- scan functions, see Test Functions.)

The benefit of Boundary- Scan in this case is that its automatic test
generation significantly simplifies test development for the boundary- scan
components, which helps reduce time to market. Boundary- Scan also
provides more accurate fault diagnostics than traditional in- circuit testing
because diagnosis is performed on input pins, as well as output pins.
Figure 1-3 Few boundary-scan components, not connected to each other
Boundary-Scan Component Conventional Components
Note that in all figures, the signal flow is from left to right. All IC pins
NOTE
on the left are inputs, and all pins on the right are outputs; except pins
connected to the TAP Controller, which are all inputs.

Scenario 2
Implementation: Several boundary- scan components on the board, which
also has many conventional components.
Configuration: Some of the boundary- scan components are connected to
each other. Figure 1- 4 shows an example.
Strategy: A test strategy could be:
• A test fixture with probes on all nodes, except on internal nodes with
only boundary- scan components connected to them.
• Traditional in- circuit test complemented by boundary- scan interconnect
test (for nodes without boundary- scan). You will still need to access
some of the traditional components, but you can use the cells in the
Boundary Register as Silicon Nails. Silicon Nails use the output cells of
one boundary- scan device as drivers, and the input cells of another
boundary- scan device as receivers. Silicon Nails provide more control
and observability than you could get from conventional functional test
methods. This implementation also uses the boundary- scan EXTEST
function.
Figure 1- 4 shows that, in this case, all internal test probes can be
removed. The main test strategy is to use the boundary- scan interconnect
test to find most of the manufacturing faults. The benefit in this
configuration is that significantly fewer test probes are needed, and the
automatic generation of test vectors for the boundary- scan devices
decreases test development time. EXTEST is the primary function used for
this implementation.

Figure 1-4 Several boundary-scan components, many nodes connected to only boundary-scan components
Probes can be removed from these nodes
In the implementations described in Scenario 2, EXTEST could be

complemented with IDCODE test, Built- in Self- test, and other IEEE test
functions supported by the specific component. However, you should
recognize that EXTEST is the most important boundary- scan test used to
find manufacturing faults in the board test environment.
A significant advantage of a boundary- scan device's design is that board
test developers can develop a board- level test without regard for the
device's internal logic. The test developer need only know the device's
pinout and assigned signals, and the tests that can be performed on the
device. This feature proves beneficial when you consider the impact that
last- minute changes to devices such as ASICs would have on a board test
without boundary- scan. It also allows the test developer to begin
developing the board- level test much earlier in the design cycle.

The Manufacturing Fault Spectrum

Before we continue with describing how boundary- scan works, let's review
the primary faults that we are trying to find with board test. Data
collected by the Colorado Surface Mount Center at Agilent shows the
distribution of the most common failures. Figure 1- 5 shows that the most
common failure is opens, followed by missing or wrong components, then
faulty analog devices, dead ICs, shorts, and fixture problems.
Figure 1-5 The manufacturing fault spectrum
Bonding faults Internal errors Open pin
37%
22%
19%
14%
7%
Short
1%
Opens
Missing, wrong
Faulty Analog
Dead ICs
Shorts
Fixture
Wrong component
Dead component

The Boundary-Scan Device

This section describes the boundary- scan device elements and the TAP
signals employed by the TAP controller.
• Boundary- Scan Device Elements
• Instruction Register
• Data Registers
• TAP Signals
Boundary-Scan Device Elements

• Test Access Port (TAP)
A general- purpose port that routes the control signals into a
boundary- scan device (TCK, TMS, TRST) and provides the serial input
and output pins (TDI, TDO) for the boundary- scan logic.
• TAP Controller
A 16- state machine, programmed by the Test Mode Select (TMS) and
Test Clock (TCK) inputs, that controls the flow of data bits to the
Instruction Register and the data registers. The TAP Controller can be
thought of as the control center of a boundary- scan device.
See TAP Signals for a description of the control signals used by the
TAP Controller.
• Instruction Register
This decodes the instruction to be performed by the test data registers.
It also selects the test data register to be accessed.
• Data Registers
These include the Boundary Register and the Bypass Register, which
every boundary- scan device must have. Optional data registers that can
be included are the Identification Register and designer- specified data
registers.

Figure 1-6 Boundary-Scan Device
In the device illustrations throughout this book, the register cells look
NOTE
alike; however, you should be aware that IEEE Standard 1149.1
describes many possible cell designs. Refer to the IEEE Standard for
more information and examples.

Instruction Register
The Instruction Register lets you define the test to be performed, or the
test data register to be accessed, or both. Each Instruction Register cell
comprises a shift- register flip- flop and a parallel output latch. The shift
registers hold the instruction bits moving through the Instruction Register.
The latches hold the current instruction.
Many mandatory and optional instructions are defined by IEEE Standard
1149.1. Design- specific instructions can also be added to a device. The
minimum size of the Instruction Register is two cells. The size of the
register dictates the size of the instruction codes that can be used: code
size must match the length of the register.
The two least significant register cells must load a fixed binary "01"
pattern during a controller state called CAPTURE- IR. The instruction
shifted into the register is latched onto the outputs at the completion of
the shifting process; this must occur during the UPDATE- IR state only.
This requirement ensures that the instruction changes only at the end of
the Instruction Register (IR) scanning sequence. The values latched onto
the Instruction Register outputs define the test to be applied, the test data
register to be accessed, or both.
When a reset is applied by the TAP Controller, or after the controller
enters the TEST- LOGIC- RESET state, the IDCODE instruction must be
latched onto the Instruction Register outputs. If the device does not have
an ID (identification) Register, then the BYPASS instruction must be
loaded onto the outputs. Table 1- 1 shows the behavior of the Instruction
Register during each TAP Controller state.
Table 1-1 A Sample Instruction Register Cell (source: IEEE Standard 1149.1)
TAP Controller State Shift-Register Flip-Flop Parallel Output Latch

TEST-LOGIC-RESET Undefined Set to give the IDCODE
CAPTURE-IR Load "01" into LSBs Retain last state
SHIFT-IR Shifts the instruction Retain last state
EXIT1-IR Retain last state Retain last state
UPDATE-IR Retain last state Load (latch) data from
All other states Undefined Retain last state

Sample Instruction Register Cell

Figure 1- 7 shows an example of a single Instruction Register cell and
those components of the cell that you will be most concerned with in
developing your tests.
The pins labeled Data and Instruction Bit are the parallel inputs and
outputs. The pins labeled From Last Cell and To Next Cell are the serial
inputs and outputs of the Instruction Register's shift- register flip- flops. All
other pins route control signals from the TAP Controller into the cell.
Figure 1-7 A sample instruction register cell
Latch Flip-Flop
(Parallel Output)
Shift-IR G1 Shift-Register 1D
Instruction Bit
Flip-Flop C1
Data 1
1D R
From Last Cell 1 C1
or TD1 To Next Cell
or TD0
Clock-IR
Update-IR
TRST* &
Reset*
Internal Logic
Output cells
Input cells
BP
TDI TDO
IR
TCK TAP
Controller TMS
Source: IEEE Standard 1149.1

Data Registers
Several different data registers can be built into boundary- scan
components. The most important is the Boundary Register, which has a
boundary- scan cell adjacent to each input and output pin. This register is
used to control and observe activities on the device's input and output
pins. The Boundary Register is a mandatory feature of IEEE 1149.1.
Another mandatory register is the Bypass Register. This register consists
of only one boundary- scan cell. The Bypass Register shortens the scan
chain to a single cell when testing other boundary- scan components on
the board.
One other data register, the Identification Register, described by IEEE
Standard 1149.1 is optional. This register contains device identification
information. The register services two functions: the IDCODE and
USERCODE functions.
The standard also allows device manufacturers to implement other
registers. These registers are typically used to perform
manufacturer- specified instructions for built- in self tests and similar
functions.
Sample Data Register Cell

Figure 1- 8 shows an example of a single data register cell and those
components of the cell that you will be most concerned with in developing
your tests. The cell design shown is flexible enough to permit the cell to
be used as an input or output. The Internal Logic and Output Pin boxes
illustrate an output configuration. Note the capture (CAP) and update
(UPD) flip- flops; these components are important to the functionality of
the data register cells during any test function.
You should note that for bidirectional pins, you can use one of two
approaches. First, you can use two data register cells: one as an input and
one as an output. Second, you can use a single, reversible cell to perform
both functions.
In Figure 1- 8, the pins labeled Input Pin and Internal Logic are the
parallel inputs from the device pins. (In an output configuration these are
the parallel outputs to the device pins.) The pins labeled Shift In and Shift
Out are the serial inputs and outputs of the Boundary Register. All other
pins route control signals from the TAP Controller into the cell.
Note that this drawing shows one Boundary Register cell extracted from
the chain and placed in an inset at the lower left of the drawing. From
this inset, you can see how the primary input signals relate to the cell
drawing and to the Boundary Register of the sample device. A similarly
inset at the lower right shows the primary output signals.

Figure 1-8 A sample data register cell
Shift out MUX

Mode
Input Pin 1 Internal Logic

Internal Logic 1 Output Pin
MUX
Shift-DR Shift-Register Latch
Flip-Flop Flip-Flop
1 CAP UPD
1
Shift in Clock-DR Update-DR

(Capture and Shift)
Output cells
Shift Out
Internal Logic
Input cells
Internal Output Pin
Shift Out Logic
Input Pin Internal Shift In

Logic
BP
Shift In TDI IR TDO
TCK TAP Controller TMS


TAP Signals
The TAP signals employed by the TAP Controller include:
• Test Data In (TDI)
• Test Data Out (TDO)
• Test Clock (TCK)
• Test Mode Select (TMS)
• Test Reset (TRST) (optional)
Figure 1- 9 illustrates how the control signals (TMS, TCK, TRST) are routed
into the TAP Controller and what the outputs from the TAP Controller can
be. These outputs control the Instruction Register and the data registers.
The mode signals produced from the instruction decode section of the
Instruction Register tell the data registers what test function to perform.
Test Data In (TDI)

TDI provides serial inputs for test instructions shifted into the Instruction
Register and for data shifted through the Boundary Register or other data
registers. Values are clocked into the selected register on a rising edge of
TCK.
Test Data Out (TDO)

TDO is the serial output for test instructions and data from the Boundary
Register or other data registers. The contents of the selected register
(instruction or data) are shifted out on the falling edge of TCK.
Test Clock (TCK)

The Test Clock input provides the clock for the test logic. TCK is a
dedicated input that allows the serial test data path to be used
independent of component- specific system clocks. It also permits shifting
of test data concurrently with normal component operation.
Test Mode Select (TMS)

The logic level of TMS, along with a rising edge applied to TCK, causes the
movement from one state to another through the TAP Controller. This, in
turn, allows movement of data and TAP instructions through the state
machine.
Only test signals are permitted to pass through the core logic (for INTEST,
RUNBIST, and other self- tests) in this mode. This isolates the device from
the rest of the board.

While in test mode, you can execute:

• EXTEST to check the physical connections of the boundary- scan device.
• INTEST to test the internal logic of the device.
• RUNBIST to test the internal logic of the device.
• Manufacturer- defined functions that emulate or extend these tests.
Test Reset (TRST)

This optional input provides asynchronous initialization of the TAP
Controller, which in turn causes asynchronous initialization of other test
logic included in the design. The reset places the device in the normal
operating mode and makes the Boundary Register inactive.
Figure 1-9 Block diagram of a boundary-scan device
Test Data Registers

Boundary Register
Device Inputs Internal Logic Device Outputs
Device Identification Register

Design-Specific Data Registers MUX
Bypass Register
G1
ModeN
Mode1
Mode2
Mode3
Select
MUX 1D TDO
1 EN
1 C1
TDI
Instruction Decode
Instruction Bits
Shift Register
Reset* Instruction Register

Clock-DR
Shift-DR
Reset*
Update-DR
Clock-IR
Shift-IR
TAP Update-IR
TMS Controller
Select
TCK
(16-State TCK*
TRST* Shift
Machine)
* Active-Low Signal

Operation Modes and Instructions

Boundary- scan devices can be operated in one of two basic modes: normal
mode, where the device performs its primary function; and test mode,
where the device is isolated to perform test functions.
Some test functions are performed during normal operation mode. Testing
the device in normal mode allows you to see how well the device operates.
Testing the device in test mode primarily allows you to verify that all
physical elements are intact.
Within each of these modes, a device can perform several functions,
depending on the current instruction. The following sections describe the
modes and the functions a device can perform with a given instruction.
• Normal Operation Mode
• Test Operation Mode
Normal Operation Mode

When the device is operating (normal mode) the Boundary Register is
transparent. Signals can pass through the boundary- scan cells freely and
the device operates as it would without test cells. In this mode, test data
is captured in the Boundary Register cells, then shifted through the
Boundary Register out to TDO.
While in normal mode, SAMPLE/PRELOAD, BYPASS, IDCODE, USERCODE
and possibly a manufacturer- supplied function can be executed.
• SAMPLE must be executed in normal mode because, as the name
implies, the test takes a sample of the data present in the device at a
specified time. The sample is subsequently shifted out for examination.
• PRELOAD sets the output register cells to a specified data pattern prior
to the selection of another boundary- scan operation.
(SAMPLE/PRELOAD is one instruction that performs two functions.)
• BYPASS selects the one- bit register path so that data can be shifted
through the device more quickly during scan operations.
• IDCODE and USERCODE verify device and manufacturer identification
and device application. These functions are explained in more detail in
the following section.
Figure 1- 10 illustrates the status of the Boundary Register cells during
normal operation mode. The red line shows how signal flows during
normal operation mode. The yellow lines show how a sample is captured.
The green line shows the path for shifting the captured sample data out.

Figure 1-10 Cell status during normal operation mode
Test Operation Mode

During test operation mode, a single Boundary Register cell routes input
and output signals so the device's core logic essentially ignores the inputs
and outputs. Only test signals are permitted to pass through the core logic
(for INTEST, RUNBIST, and other self- tests) in this mode. This effectively
isolates the device from the rest of the board.
While in test mode, you can execute EXTEST, INTEST, RUNBIST, and
manufacturer- defined functions that emulate or extend these tests.
• EXTEST checks the physical connections of the boundary- scan device.
• INTEST and RUNBIST test the internal logic of the device.
• Manufacturer- defined tests might require you to preset the cells in the
Boundary Register (PRELOAD) so the states will be known when the
test mode is entered. Check to see if your devices or board topology
have such a requirement before writing your test.
Figure 1- 11 illustrates the status of the Boundary Register cells during
test operation mode. The black lines show how data is routed during test
mode. The red lines show how data is shifted out of the cell; this is the
path taken during EXTEST. The green lines show the path for updating
data; this is the path taken during INTEST.

Figure 1-11 Cell status during test operation mode

Hold States
In some circuit topologies, it may be necessary to hold one or more nodes
to fixed states during boundary- scan testing, so that downstream circuitry
(typically non- boundary- scan devices) is not excited, thus preventing
damage to the circuitry. Boundary- scan hold states are nodes on a board
that are held to a logic of 1 or 0 by a boundary- scan driver on the node,
when the IC containing the driver is in EXTEST.
An example is shown in Figure 1- 12. The boundary- scan memory
controller IC is connected to another boundary- scan IC and to
non- boundary- scan RAM ICs. Each RAM IC has a select pin, but because
their data lines are connected, only one RAM IC should be selected at any
time. This means nodes Sel- 1 and Sel- 2 should not both be high at the
same time. If one Select pin is controlled at 0 during boundary- scan
testing, the RAM outputs will never be in conflict.
Figure 1-12 Boundary-scan ICs connected to non-boundary-scan ICs
U4 TDO
RAM
TDI U2
Memory Sel-1 Select

Controller Data
RAM
Address
U1
U3
Select
Sel-2
Test Types and Hold States

There are seven boundary- scan test types. The following sections explain
how Hold States operate within each test type.
• Connect Tests
• Interconnect Tests
• Buswire Test
• Powered Shorts Tests
• Disable Tests
• Silicon Nails Tests
• Custom Tests

Connect Tests
Figure 1-13 Connect test hold state
(In Bypass) (In Extest) (In Bypass)

TDI U1 U3 TDO
A D
U2
B E
C F
The ITL node block syntax would look like Example 1- 1:
Example 1-1 Connect test hold state syntax

node
node "A" test "U2.1"
node "B" test "U2.2"
node "C" test "U2.3"
node "D" test "U2.4"
node "E" test "U2.5"
node "F" test "U2.6"
end nodes
Connect test held low

If needed, it is possible to control node X to a low state, as shown in
Figure 1- 14.
Figure 1-14 Connect test with node X held low
(In Bypass) (In Extest) (In Extest)

TDI U1 U3 TDO
A D
U2
B E X
C F
Hold 0
The ITL node block syntax would be modified as shown in Example 1- 2:

Example 1-2 Connect test with node X held low

nodes
silicon node "X" hold low "3.12"
! Not on the DUT
end nodes
If node X has a connection (not noted in the ITL) to a driver in U1 (in

NOTE
BYPASS mode) there could be a driver contention problem when the
test is executed. If node X has a connection to a non-boundary-scan
device driver, it must be disabled. To prevent this type of problem, it is
important to examine the topology of the nodes that are to be held.
Connect test held high
Figure 1-15 Connect test with node F held high
(In Bypass) (In Extest) (In Extest)

TDI U1 U3 TDO
A D
U2
B E X
C F
Hold 1 Hold 0
The ITL node block syntax would be modified as shown in Example 1- 3.
Example 1-3 Connect test with node F held high

nodes
silicon node "F" hold high "U2.6" ! On the DUT
silicon node "X" hold low "U3.12" ! Not on the DUT
end nodes

The example shows a hold node (F) on the DUT. The node will be held
high rather than be tested in both states. There may be interactions
between node F and other nodes. For example, the control cell needed to
enable F may also enable node E. If E is output only, there is no conflict
of purpose. If node E is bidirectional, then the driver cannot be turned off
or control the node. Under this condition, you cannot test the input
capability of node E; only the output capability can be tested. This is a
sufficient check for solder opens on E, but you lose the ability to check
whether the receiver is operational.
Interconnect Tests
Interconnect tests test for shorts and opens on boundary- scan nodes and
pins.
Figure 1- 16 shows nodes A through F with sufficient Boundary- Scan
resources; they can be tested. Node G lacks a receiver and cannot be
tested.
Figure 1-16 Interconnect test hold state
(In Extest) (In Extest) (In Extest)

TDI TDO
A D
U1 U2 U3
B E
C F G
The ITL node block syntax is shown in Example 1- 4:
Example 1-4 Interconnect test hold state syntax

nodes
silicon node "A" hold high "U1.4", "U2.1"
silicon node "B" test "U1.4", "U2.2"
silicon node "C" test "U1.5", "U2.3"
silicon node "D" test "U2.4", "U3.1"
silicon node "E" test "U2.5", "U3.2"
silicon node "F" test "U2.6," "U3.3"
end nodes
Interconnect test with node G held

If needed, it is possible to control node G to a held state. Add the
statement in Example 1- 5 to the ITL code shown above.
Example 1-5 Silicon node G held low

silicon node "G" hold low "U3.6"

Interconnect test held high

If it is necessary to hold node A high, modify the ITL code as shown in
Example 1- 6.
In this example, A would no longer be tested at both states, but the
receiving pin U2.1 would be monitored for the held state.
Example 1-6 Interconnect test with node A held high

nodes
silicon node "A" hold high "U1.4", "U2.1"
silicon node "C" test "U1.6", "U2.3"
silicon node "F" test "U2.6", "U3.3"
end nodes
Buswire Test
In Figure 1- 17, the buswire test specifies and tests the three nodes D, E,
and F. Node G cannot be tested, but can be held.
The ITL node block syntax is shown in Example 1- 7.
Figure 1-17 Buswire hold state
TDI
D
U1 U2
E
F
TDO
D
U3 U4
E
F G
Example 1-7 Buswire hold state syntax

nodes
silicon node "D" hold high "U1.4", "3.4", "U2.1", "U4.1"
silicon node "E" hold high "U1.5", "3.5", "U2.2", "U4.2"
silicon node "F" hold high "U1.6", "3.6", "U2.3", "U4.3"
silicon node "F" hold low "3.6" ! G held low, not part of test
end nodes

In a situation where a tested bus wire node must be held, there can be
two outcomes which depend on the control cell structure inside the IC (as
shown in Figure 1- 18).
Figure 1-18 Bus wire topology interacting with internal control cell format
TDI
D
U1 U2
E
F
TDO
D
U3 U4
E
F G
In Figure 1- 18, U1 has a dedicated control cell for each driver. When node
D is held high, the MSPD finds a dedicated control cell for the driver on
node D (U3). Only the coverage of pins on node D is affected.
In Example 1- 8, if node E is held high (or low), and the control cell for
node E’s driver is used to control the driver for node F, U3 cannot be fully
tested.
Example 1-8 Buswire syntax with node E held high

nodes
silicon node "D" test "U1.4", "U3.4", "U2.1", "U4.1" ! D is testable
silicon node "E" hold high "U1.5", "U3.5", "U2.2", "U4.2" ! Hold node
silicon node "F" test "U1.6", "U3.6", "U2.3", "U4.3" ! Also not tested
end nodes

Powered Shorts Tests

A powered shorts test consists of a mix of silicon node statements and
nodes statements. The silicon node statements refer to un- nailed
boundary- scan nodes. The node statements refer to nailed nodes that do
not have boundary- scan support. All node statements directly following a
silicon node statement identify nodes that are adjacent to the silicon node.
The ITL node block syntax for is shown in Example 1- 9:
Example 1-9 Powered shorts test hold state syntax

nodes
silicon node "U1_U3_10" hold high "u1.10","u2.15", "u3.10", "u4.15"
silicon node "U1_U3_9" hold low "u1.9","u2.16", "u3.9", "u4.16"
silicon node "U1_U3_8" test "u1.8","u2.17", "u3.8", "u4.17"
silicon node "U1_2" test "u1.2","u2.23"
node "IN_05" family "CMOS" test "u1.1"
node "IN_04" test "u2.24"
silicon node "U3_5" test "u3.5" ! NC
end nodes
A single node may be described by one or more lines in the code. If a

NOTE
silicon node statement is to be converted to a hold statement, ensure
that all statements for that node are converted.
Disable Tests
Disable tests are used to disable all the drivers in a chain.
Turning on a driver for hold purposes may also turn on other drivers
NOTE
that share the control cell with the hold node driver.
Disable tests are their own test type. An ITL may also specify a disable
flag for a single device in the chain description (using the disable
keyword). This disable keyword is strictly interpreted and overrides any
attempt to use a driver in that device for hold node purposes. If a hold is
overridden, MSPD displays a message similar to the following:
Device U47 is to be disabled and also has a hold pin, hold
ignored.

Silicon Nails Tests

Silicon Nails tests can support hold statements. Hold statements are not
automatically generated by a Silicon Nails test; you must manually enter
the hold statement and remove it from the PCF order and vectors.
In Figure 1- 19, device U4 is unused and is therefore in Bypass mode.
There are two options, a hold node controlled by a device not used by the
test, or a hold node controlled by a device also used by the test.
Figure 1-19 Silicon Nails hold state
(In Extest) (Non-scan) (In Extest) (In Bypass)

TDI TDO
A D
U1 U2 U3 U4
B E
C F G
Example 1-10 Silicon Nails test hold state syntax

silicon node "A" test "U2.1", "U1.4"
inputs "A", "B", "C"
outputs "D", "E", "F"
... ! PCF Order and Vector definition omitted
end nodes
Silicon Nails test with node G held

If node G is to be held, simply add a hold statement (Example 1- 11) to
the node block.
Example 1-11 Silicon Nails test with node G held high

silicon node "G" hold high "U4.6"

Silicon Nails test with node G held high and A held low
To hold node G high and node A low, the node block would look like
Example 1- 12:
Example 1-12 Silicon Nails test with node G held high and node A held low
nodes
silicon node "A" hold low "U2.1", "U1.4"
! No longer used in test
silicon node "G" hold high "U4.6"
inputs "B", "C" ! Node A deleted from I/O list
outputs "D", "E", "F"
... ! PCF Order and Vector definition omitted
end nodes
If node A is declared as an input and used in a PCF order statement, an

error message is issued:
Node A is a hold node, cannot be used for I/O.
This error is corrected by removing A from the input and PCF order
specifications.
Custom Tests
Custom Test ITL files are used to describe the chain structure and disable
methods to MSPD. The node block is ignored because all programming
action is register- based and derived from SPD. Any hold statements
included in the node block will be ignored.
When using custom tests, hold states can be implemented if a nail is
present on either select node.

Test Functions
IEEE Standard 1149.1 describes the types of functions that a conforming
boundary- scan device must perform, and provides guidelines for additional
(optional) functions. Each function has a corresponding instruction.
Mandatory public instructions described in the standard include EXTEST,
BYPASS, and SAMPLE/PRELOAD. Optional instructions outlined by the
standard include INTEST, RUNBIST, IDCODE, and USERCODE. The
manufacturer may provide additional instructions that test the internal
logic of a device. These instructions are given specific names and access
codes by the manufacturer and should be documented to indicate the
function of each instruction.
The standard also outlines the implementation of private instructions
typically used by the component manufacturer for design verification,
production testing, and fault diagnosis. Private instructions are usually
invisible to the user; however, if a user could damage the component if a
private instruction code were inadvertently included in the board test, the
manufacturer is obliged to identify the potential hazard to the user. The
manufacturer also might not indicate what registers are used by private
instructions. You should determine whether a private instruction could
affect your test development.
Familiarize yourself with IEEE Standard 1149.1 to further your
understanding of boundary- scan testing techniques, and what you can
expect from device manufacturers implementing the standard.
Boundary-Scan Test Instructions

The following sections describe mandatory instructions and
commonly- used optional instructions.
• EXTEST (mandatory)
• BYPASS (mandatory)
• SAMPLE/PRELOAD (mandatory)
• INTEST (optional)
• RUNBIST (optional)
• IDCODE (optional)
• USERCODE (optional)
• CLAMP (optional)
• HIGHZ (optional)
The binary codes for the mandatory instructions BYPASS and EXTEST are
identified here. The binary codes for optional instructions are selected by
the component's designer.
You can find more details about the instructions in IEEE Standard 1149.1.

EXTEST (mandatory)
EXTEST is primarily concerned with testing the circuitry from the
Boundary Register of the device to some point outside the device. This
might include just the Boundary Register, bond wires, terminals, and
circuit board traces, or it could also include devices and interconnections
between two boundary- scan devices (depending on the board topology).
EXTEST has three functions:
• Stand- alone function allows you to test the Boundary Register and the
circuitry that connects the device to the circuit board.
• Interconnect function allows you to test the Boundary Register and the
circuitry that connects one boundary- scan device to another.
• Cluster function allows you to test the Boundary Register and the
circuitry (non- boundary scan devices or clusters) mounted between one
boundary- scan device and another.
During EXTEST, all I/O pins are connected to the Boundary Register and
the core logic is isolated. The primary advantage is that you can test all
I/O pins with no knowledge of the internal logic. Another advantage is
that you get better fault diagnosis on the input pins.
In a conventional test, you can apply patterns on the input pins and
observe the results on the output pins. If one of the input pins is open, it
can only be detected on an output pin; you have no clue as to which input
pin caused the problem. In a boundary- scan device, you can detect exactly
which input pin is not making contact with the circuit board trace. In
production, that could be the difference between repairing a solder joint or
replacing a 250- pin device.
Stand- alone function
The stand- alone function tests the Boundary Register cells, the bond wires
between the register cells and the terminals, and the solder connections
between the terminals and the circuit board traces. The broken lines in
Figure 1- 20 indicate the region tested.
Bits applied to the device inputs are captured by the input register cells
and shifted out for analysis. Similarly, the outputs are tested by serially
shifting bits into the output register cells, then latching them out (in
parallel) for examination.

Figure 1-20 EXTEST stand-alone function tests the connections of a single

boundary-scan device

Interconnect function
The EXTEST interconnect function is used when a board has two or more
boundary- scan devices connected together. Figure 1- 21 illustrates how you
can set up one output of a device in the boundary- scan chain, propagate
the signal to the next device and latch the signals on the input cells, then
scan out the result to TDO for examination.
The broken lines in Figure 1- 21 indicate the region tested. In this case,
you do not need a probe on the nodes between the common connections,
which explains why fewer test probes are needed.
Figure 1-21 EXTEST interconnect function tests connections between two boundary-scan devices
Driver Nodes
TDI
Receiver Nodes
TCK
TDO
TMS

Cluster function
The EXTEST cluster function allows you to test blocks of components that
do not incorporate boundary- scan technology. For example, the output
pins of the first boundary- scan device in Figure 1- 22 are used as drivers.
The broken lines indicate the region tested.
Data is shifted to the device/cluster inputs. Outputs from the
device/cluster are captured on the inputs of the second boundary- scan
device; these inputs act as receivers. The test data is then shifted out of
the device for examination.
Because these Boundary Register cells act as test probes, we call them
Silicon Nails. Silicon Nails use the output cells of one boundary- scan
device as drivers, and the input cells of another boundary- scan device as
receivers.
Figure 1-22 EXTEST cluster function tests non-boundary-scan devices located between boundary-scan devices.
Silicon Nails
Drivers Receivers
TDI
TCK
TDO
TMS

BYPASS (mandatory)
The BYPASS instruction places a single shift- register, called the Bypass
Register, between TDI and TDO. This provides a minimum- length serial
path during scan operations. When this instruction is in effect, the device
is in normal operation mode.
Figure 1- 23 shows the first device in BYPASS while INTEST is run on the
second device.
Use the BYPASS instruction when you do not want to test a particular
component, but must shift through that component to test another device.
The required binary code for BYPASS is a logic 1 loaded into every
Instruction Register cell. IEEE Standard 1149.1 also allows other
designer- defined codes for this instruction.
Figure 1-23 BYPASS instruction allows quicker access to a downstream device

Device in BYPASS Device in INTEST
TDI
TCK
TDO
TMS

SAMPLE/PRELOAD (mandatory)
SAMPLE/PRELOAD is one instruction that performs two functions: it
allows you to take a sample of normal component operation, and to place
an initial data pattern at the latched parallel outputs of the Boundary
Register cells. The binary values for this instruction are selected by the
component's designer.
PRELOAD can be used to load data onto the latched outputs prior to
selecting an instruction, such as EXTEST. As soon as that instruction is
transferred to the parallel output of the Instruction Register, the preloaded
data is driven through the output pins.
For example, Figure 1- 24 shows a chip- select device with boundary- scan
that controls two ROM chips connected to the same bus. You would not
want a random set of output signals to select both ROM devices at the
same time. If both ROMs were enabled, there would be a bus fight on
nodes D0 and D1, which could damage the ROMs. PRELOAD allows you to
latch the proper signals onto the output cells.
Figure 1-24 PRELOAD instruction prevents a bus fight

Chip-select device ROM
D0
D1
TDI
TDO
TCK
TMS
SAMPLE allows you to look inside the device during normal operation and
see what is happening at a specified time. As data bits flow into the
device, they pass through the input cells of the Boundary Register, then
through the internal logic, then through the output cells of the Boundary
Register and out of the device.

While the device operates in this mode, you can tell the Boundary Register
cells to take a sample, that is, to capture the bits that are flowing through
the cells at a specified time. Then the bits can be serially shifted through
the Boundary Register to TDO, where they can be examined. Samples can
be taken by the input or output Boundary Register cells. In Figure 1- 25,
the shaded interior of the first device shows that it is in normal operation;
the internal logic is working. The bold lines show normal data flow. The
broken line shows how the sample is taken, then shifted out for
examination.
Figure 1-25 SAMPLE instruction performed on an operating device
TDI
TCK
TDO
TMS
Internal logic working
(bold) Normal data flow
(broken) Sample taken and shifted out

INTEST (optional)
INTEST allows static testing (in single- step mode) of the device's internal
logic when the device is installed on the board. This means that the device
is not operating; it is in test mode. In single- step mode, all data must be
shifted in one bit at a time and applied to the internal logic. Results are
captured and shifted out in the same manner.
Test patterns and responses are serially shifted through the Boundary
Register. Note that the signals are going from the Boundary Register into
the internal logic for processing, then back out of the internal logic and
latched onto the output Boundary Register cells. From here, the bits can
be shifted out of TDO for examination.
Because this test is executed in test operation mode, it is not affected by
board topology. That is, the input and output pins are essentially inactive
and the device is effectively isolated, so you don't have any problems with
upstream devices.
Figure 1-26 INTEST instruction performed on a device in test mode

Internal logic working
Nodes have no impact Device in INTEST
TDI
TCK
TDO
TMS

RUNBIST (optional)
RUNBIST causes the device to run a self- contained self- test. The TAP
Controller is in the RUN- TEST/IDLE state when this test executes. The
device executes the self- test, then the captured information can be shifted
out to TDO. This information is then compared to the expected
information for the test.
RUNBIST allows you to verify that the device's internal logic is in good
condition without writing complex test vectors and without running in
single- step mode as you would with the INTEST instruction.
As with INTEST, the signals run through the Boundary Register into and
out of the internal logic, and the device is effectively isolated because the
device input and output pins are inactive. The component manufacturer
may include other, similar instructions for further self- test that can be
invoked by instructions other than RUNBIST.
Figure 1-27 RUNBIST instruction performed on a device in test mode
TDI
TCK TDO
TMS

IDCODE (optional)
IDCODE allows you to access an optional, identification register (labeled
ID in Figure 1- 28) that determines the identity of the component. The
current instruction loads the vendor identification code into the IDCODE
Register. The primary elements of this code include the device's part
number, manufacturer's ID, and variant for the component.
A few common applications for this instruction include identifying devices
with different programming, locating misplaced devices, and distinguishing
between similar devices supplied by different manufacturers.
Note that IEEE Standard 1149.1 requires that this register be 32 bits long.
(Figure 1- 28 shows only three bits. This is a representation only.)
Figure 1-28 IDCODE instruction provides device identification
TDI
TCK
TDO
TMS

USERCODE (optional)
The USERCODE instruction allows a user- programmable identification
code to be loaded into or shifted out of the device for examination. The
instruction allows the programmed function of the device to be
determined. When this instruction is selected, the user- programmed code
is loaded into the IDCODE Register, then shifted out for examination. This
is essentially an extended function of IDCODE for programmable devices.
You should note that for this function to be valid, an identification register
(and therefore an IDCODE instruction) must also be implemented for the
device.
Figure 1-29 USERCODE instruction provides user-programmed device information
TDI
TCK
TDO
TMS

CLAMP (optional)
CLAMP is used for digital guarding. It is an optional instruction performed
in test mode.
When testing a board, it is often necessary to force static 0s or 1s on
selected nodes in order to set up testable conditions or to block
interfering signals. CLAMP freezes the states of digital outputs during
some testing operations while placing the BYPASS register between TDI
and TDO for fast shifting. It also places all output and bidirectional pins
under control of the Boundary Register, which should be set up previously
using a PRELOAD sequence. Using CLAMP, you can set fixed values on to
an IC's output pins without using the entire Boundary Register.
You cannot partition the Boundary Register within a device.

NOTE
HIGHZ (optional)
HIGHZ is an optional instruction performed in test mode.
HIGHZ enhances the ability of in- circuit test Automatic Test Equipment
(ATE) systems to test complex boards, by reducing the potential for
overdrive damage. HIGHZ disables all output and bidirectional pins, so
that you can overdrive them indefinitely during in- circuit testing.
Problems with Boundary-Scan Testing

Some of the problems associated with boundary- scan test strategies
include:
• longer test times caused by the serialization of test data
• potential problems with overdrive limits
• potential problems with keeping dynamic logic operating
The last two problems result from the longer test times. In the case of
dynamic devices, the longer times might result in the clock not operating
quickly enough to keep the device operating. You should consider these
limitations when you develop your board test.

Tap Controller State Diagram

The TAP Controller State Diagram shown in Figure 1- 30 allows you to
track the sequence of any boundary- scan test through the TAP Controller.
This state diagram applies to all components that comply with IEEE
Standard 1149.1.
Use this diagram to write custom boundary- scan tests. Keep the TAP
Controller State Diagram available as you read this manual, and make
copies that you can mark up as you work with this software tool.
Figure 1-30 TAP Controller State Diagram

Each position in the Data Register and Instruction Register columns

represents a state of the TAP Controller (the 16- state machine that
controls each boundary- scan device). The states in the two columns vary
only by the suffixes. These suffixes identify the column and the register
operation that they affect.
• DR is the Data Registers column; data instructions passed through this
column affect the operation and contents of the data registers. As
mentioned earlier, the data registers can be the Boundary Register or
Bypass Register, which all boundary- scan devices must contain, or they
can be the optional IDCODE or USERCODE Registers, or even a
designer- specified register that complies with the IEEE standard.
• IR is the Instruction Register column; data instructions passed through
this column affect the operation and contents of the Instruction
Register, which is a mandatory component of every boundary- scan
device.
Along the data flow lines connecting each tap state, you see a number: a
0 or a 1. These numbers are the bits states of the TMS input signal
required to move from one state to the next.
Boundary-Scan devices in a chain are synchronized and follow

NOTE
identical paths through the TAP Controller State Diagram
(Figure 1-31). They are in lock-step and only move in response to a
rising edge on TCK. All the devices are at the same state in the TAP
Controller State Diagram at all times.
Figure 1-31 Devices connected in a chain

TAP Controller States - Summary
1-46
1
This section briefly describes the behavior of the TAP Controller in each of the controller states.
Table 1- 2 shows how the TAP Controller changes from state to state, depending on the logic
level of TMS (Test Mode Select).
Changes only occur when a rising edge is applied to TCK (Test Clock).
NOTE
Table 1-2 Summary of TAP Controller state changes
On a rising edge of TCK:

When the TAP . . . if TMS is high (1), . . . if TMS is low (0), Do selected test data Does the current Does the Instruction
Controller is in the Tap Controller the Tap Controller registers retain their instruction change Register retain its
this state changes to: changes to: previous state? while the Tap Controller state?
is in this state?
TEST-LOGIC-RESET Test-Logic Run-Test/Idle NO N/A NO
RUN-TEST/IDLE Select-DR-Scan-Scan Run-Test/Idle See Run-Test/Idle NO YES
SELECT-DR-SCAN Select-IR-Scan Capture-DR YES NO YES
CAPTURE-DR Exit1-DR Shift-DR See CAPTURE State NO YES
SHIFT-DR Exit1-DR Shift-DR See SHIFT State NO YES
EXIT1-DR Update-DR Pause-DR YES NO YES
PAUSE-DR Exit2-DR Pause-DR YES NO YES
EXIT2-DR Update-DR Shift-DR YES NO YES
UPDATE-DR Select-DR-Scan Run-Test/Idle See UPDATE State NO YES

SELECT-IR-SCAN Test-Logic Capture-IR YES NO YES
CAPTURE-IR Exit1-IR Shift-IR YES NO See CAPTURE State
SHIFT-IR Exit1-IR Shift-IR YES NO See SHIFT State
Table 1-2 Summary of TAP Controller state changes
On a rising edge of TCK:

When the TAP . . . if TMS is high (1), . . . if TMS is low (0), Do selected test data Does the current Does the Instruction
Controller is in the Tap Controller the Tap Controller registers retain their instruction change Register retain its
this state changes to: changes to: previous state? while the Tap Controller state?
is in this state?
EXIT1-IR Update-IR Pause-IR YES NO YES
PAUSE-IR Exit2-IR Pause-IR YES NO YES
EXIT2-IR Update-IR Shift-IR YES NO YES
UPDATE-IR Select-DR-SCAN-SCAN Run-Test/Idle YES YES NO
1-47
1
Sample Device and Cell Functions

The following sections show sample device and cell functions in the
following states:
• CAPTURE State
• SHIFT State
• UPDATE State
See also Run- Test/Idle.
CAPTURE State
During the CAPTURE state, data or instruction bits are loaded in parallel
into the appropriate registers (data or instruction). CAPTURE- DR loads
data bits into the specified data register. CAPTURE- IR loads instruction
bits into the Instruction Register. Figure 1- 32, using CAPTURE- DR and the
Boundary Register as an example, shows how data is loaded from the
input pins onto the input cells of the Boundary Register.
Figure 1-32 Sample device and cell function in the CAPTURE State
Shift out MUX

Mode

1
MUX
Flip-Flop Flip-Flop
1 CAP UPD
1

Capture and Shift

SHIFT State
During the SHIFT state, data in the designated registers (Instruction or
data) is shifted out to TDO and new data is shifted in from TDI. This
state can be repeated as many times as needed to shift in or shift out the
necessary data. Note that the last bit is shifted on the transition out of
the SHIFT state. Figure 1- 33 shows how data is shifted through the
Boundary Register; the circuit is active between TDI and TDO.
Figure 1-33 Sample device and cell function in the SHIFT State
Shift out MUX

Mode

1
MUX
Flip-Flop Flip-Flop
1 CAP UPD
1

Capture and Shift

UPDATE State
As the TAP Controller passes through the UPDATE state, data is latched
onto the parallel outputs of the selected register. Then, the new data and
instruction become the current data and instruction.
Figure 1-34 Sample device and cell function in the UPDATE State
Shift out MUX

Mode
Internal Logic 1 Output Pin

1
MUX
Flip-Flop Flip-Flop
1 CAP UPD
1

Capture and Shift
Run-Test/Idle
If the instruction loaded in the instruction register is a standard BSCAN
instruction, the test data register retains its previous state. If the
instruction is a user- defined instruction, it is possible that the data may
be changed.

Tap Controller States - Reference

The IEEE standard describes the circumstances required for an event to
occur during a particular state. Unless otherwise specified, the following
circumstances apply to all controller states.
• A rising edge must be applied to TCK for an event to occur.
• All registers not selected by the current instruction retain their
previous states.
• A change of state does not change the instruction unless specified.
Each of the Tap Controller states in Figure 1- 35 is briefly described in the
following sections. Click on any of the states in the diagram to view its
description.
Figure 1-35 TAP Controller State Diagram

TEST-LOGIC-RESET
In this controller state, the test logic is disabled so that normal operation
of the device's system logic can continue unhindered. The Instruction
Register is initialized to contain the IDCODE instruction if the device
contains an identification register, or the BYPASS instruction if the device
does not contain an identification register. Regardless of the controller's
original state, it will enter TEST- LOGIC- RESET when TMS is held high (1)
for at least five rising edges of TCK. (You can verify this by looking at the
TAP Controller State Diagram and stepping through it from any state.) The
controller remains in this state while TMS is high.
If TMS goes low (0) for a short period (glitches) it will recover to the
TEST- LOGIC- RESET state within three TCK clocks. If a Test Reset (TRST)
port is provided, a low applied to TRST will force the TAP Controller to
the TEST- LOGIC- RESET state. Power- up will also force the TAP Controller
to this state.
RUN-TEST/IDLE
Once entered, the controller will remain in the RUN- TEST/IDLE state as
long as TMS is held low. When TMS is high, the controller moves to the
SELECT- DR- SCAN state.
In the RUN- TEST/IDLE state, activity in selected test logic occurs only
when certain instructions are present. For example, the RUNBIST
instruction causes a self- test on the device's internal logic to execute.
Self- tests selected by other instructions can also be designed to execute in
this state.
For instructions that do not cause functions to execute in this state, all
test data registers selected by the current instruction retain their previous
states.
SELECT-DR-SCAN
This is a temporary controller state. Here, a decision is made whether to
enter to Data Register (DR) column, or to continue on to the Instruction
Register (IR) column. If TMS is held low when the controller is in this
state, the controller moves into the CAPTURE- DR state and a scan
sequence is initiated for the selected test data register. If TMS is held high,
the controller moves on to the SELECT- IR- SCAN state.

SELECT-IR-SCAN
This is a temporary controller state. Here, a decision is made whether to
enter the Instruction Register (IR) column, or to reset the TAP Controller
by returning to the TEST- LOGIC- RESET state. If TMS is held low when
the controller is in this state, then the controller moves into the
CAPTURE- IR state and a scan sequence is initiated for the Instruction
Register. If TMS is held high, the controller returns to the
TEST- LOGIC- RESET state.
CAPTURE-IR
In this controller state, the shift- register contained in the Instruction
Register loads a pattern of fixed logic values on the rising edge of TCK.
The two least significant bits are assigned the values 0 an 1 respectively.
In addition, design- specific data that are not required to be set to fixed
values can be loaded into shift- register states.
When the TAP Controller is in this state, the controller enters either the
EXIT1- IR state if TMS is high or the SHIFT- IR state if TMS is low.
SHIFT-IR
In this controller state the shift- register part of the Instruction Register is
connected between TDI and TDO and shifts, on each rising edge of TCK,
the captured pattern one stage towards its serial output. It also shifts the
new instruction bits into the Instruction Register from TDI.
EXIT1- IR state if TMS is high or remains in the SHIFT- IR state if TMS is
low.
EXIT1-IR
This is a temporary controller state. At this point, a decision must be
made whether to enter the PAUSE- IR state, or the UPDATE- IR state. If
TMS is held high while in this state, the controller enters the UPDATE- IR
state, which terminates the scanning process. If TMS is held low, the
controller enters the PAUSE- IR state.
PAUSE-IR
This controller state allows shifting of the Instruction Register to be
temporarily halted. It is used, for example, when ATE equipment loads
tester RAM.
The controller remains in this state while TMS is low. When TMS goes
high, the controller moves on to the EXIT2- IR state.

EXIT2-IR
This is a temporary controller state. Once again a decision must be made
whether to move on to the UPDATE- IR state, or return to the SHIFT- IR
state. If TMS is held high while in this state, the scanning process
terminates and the TAP Controller enters the UPDATE- IR state. If TMS is
held low, the controller enters the SHIFT- IR state.
UPDATE-IR
The instruction shifted into the Instruction Register is latched, on the
falling edge of TCK, onto the parallel output from the shift- register path.
The instruction bits are shifted out from the shift- register flip- flops of the
Instruction Register onto the latches that decode the instruction. Once the
new instruction has been latched, it becomes the current instruction.
SELECT- DR- SCAN state if TMS is high or the RUN- TEST/IDLE state if
TMS is low.
CAPTURE-DR
In this controller state, data can be parallel- loaded into test data registers
selected by the current instruction on the rising edge of TCK.
EXIT1- DR state if TMS is held high or the SHIFT- DR state if TMS is held
low.
If a test data register selected by the current instruction does not have a
parallel input, or if capturing is not required for the selected test, the
register retains its previous state.
SHIFT-DR
In this controller state, the test data register connected between TDI and
TDO as a result of the current instruction shifts on each rising edge of
TCK, data one stage towards its serial output. At the same time, it shifts
data into data registers from TDI.
EXIT1- DR state if TMS is held high or remains in the SHIFT- DR state if
TMS is held low.

EXIT1-DR
This is a temporary controller state. At this point, a decision must be
made whether to enter the PAUSE- DR state, or the UPDATE- DR state. If
TMS is held high while in this state, the controller enters the UPDATE- DR
state, which terminates the scanning process. If TMS is held low, the
controller enters the PAUSE- DR state.
PAUSE-DR
This controller state allows shifting of the test data register in the serial
path between TDI and TDO to be temporarily halted. It is used, for
example, when ATE equipment loads tester RAM.
The controller remains in this state while TMS is low. When TMS goes
high, the controller moves on to the EXIT2- DR state.
EXIT2-DR
This is a temporary controller state. Once again a decision must be made
whether to move on to the UPDATE- DR state, or return to the SHIFT- DR
state. If TMS is held high while in this state, the scanning process
terminates and the TAP Controller enters the UPDATE- DR controller state.
If TMS is held low, the controller enters the SHIFT- DR state.
UPDATE-DR
Some test data registers might be provided with a latched parallel output
to prevent changes at the parallel output while data is shifted in the
associated shift- register path in response to certain instructions. Data is
latched, on the falling edge of TCK, onto the parallel outputs of these test
data registers from the shift- register path. The data held at the latched
parallel output changes only in this state. (An exception to this rule is
when an operation such as RUNBIST requires the output data to change
during its operation. In this case, the TAP controller does not change
states. The changing outputs are controlled by the function of the
instruction.)
SELECT- DR- SCAN state if TMS is high or the RUN- TEST/IDLE state if
TMS is low.

Moving Through the TAP Controller State Diagram

Before you can examine a sample test program for a boundary- scan
device, you need to know how the TAP Controller works. This section
steps through the TMS sequence needed to program a new instruction into
the Instruction Register, then shows you the TMS sequence needed to
execute the new instruction.
Note that the main objective here is to see how the values of TMS
NOTE
move from state to state. The sequence applies to all instructions, so
we are not concerned with the values for TDI or TDO. One point to
remember while you study this section is that the TAP Controller State
Diagram changes to the state indicated by the TMS value only on a
rising edge of TCK.
The 0s and 1s in the Tap Controller State Diagram are the values of TMS.
In the upper left corner you can see TEST- LOGIC- RESET. This is the
normal starting state of the device.
To program the Instruction Register, starting at TEST- LOGIC- RESET, a
TMS logic sequence of “011001” is needed. As shown in Figure 1- 36, this
sequence takes you through the SHIFT- IR state to the EXIT1- IR state. The
right- most bit is shifted first, and is considered the least significant bit
(LSB). The new instruction is shifted into the Instruction Register at the
SHIFT- IR state by continuing with TMS low and applying the needed bits
to TDI. The last bit of the instruction is shifted on the transition from the
SHIFT- IR state to the EXIT1- IR state.

Figure 1-36 TMS logic sequence needed to move to SHIFT-IR State
* Iterated “N-1” times to shift N-1 new

instruction bits into IR. The last bit is
Source: IEEE Standard 1149.1 shifted on transition to Exit1-IR.
After all bits for the new instruction have been shifted into the Instruction
Register, you can exit the IR- SCAN column. When you exit the IR- SCAN
column through UPDATE- IR, the new instruction that was shifted into the
Instruction Register latches onto the parallel output of the Instruction
Register. Here, the instruction is decoded and becomes the current
instruction.
To go into the DR column from EXIT- IR, apply the sequence “110” on
TMS. As shown in Figure 1- 37, this sequence takes you to the
CAPTURE- DR state. In this state, data signals on the device's input pins
are latched into the data register according to the instruction
programmed.

Figure 1-37 TMS logic sequence needed to move to CAPTURE-DR State
The data captured must now be shifted to TDO for examination. By

applying a “01” to TMS, you can move through the SHIFT- DR state to the
EXIT1- DR state as shown in Figure 1- 38, so you can shift the data out (at
the same time, new data is shifting in from TDI). Because data shifts one
stage towards its serial output for each rising edge of TCK, you must keep
TMS at “0” during the SHIFT- DR state until the data required is
completely shifted out of TDO. Remember that you must shift out the last
data bit by moving from the SHIFT- DR state to EXIT1- DR. Once you have
shifted out all the test data, you can terminate the scan sequence.

Figure 1-38 TMS logic sequence needed to move to SHIFT-DR State
* Iterated “N-1” times to shift N-1 data bits

into target register. The last bit is shifted
Source: IEEE Standard 1149.1 on transition to Exit1-DR.
To get to UPDATE- DR, apply “11” to TMS. In the UPDATE- DR state, the
scan sequence terminates and the test data can be latched onto the
parallel outputs to prevent changes.

Figure 1-39 TMS logic sequence needed to move to o UPDATE-DR State
Micro-programming for Boundary-Scan

Understanding how the TAP Controller changes states will prove valuable
when you need to do custom tests on a boundary- scan device. Some
devices might not be equipped with RUNBIST or other tests that test the
internal logic of the device. Others might not have the type of test that
you want to run on a particular device. For these or other reasons, you
might want to write your own program (micro- program) for the device. To
do this, you'll need to know exactly what occurs within the TAP Controller
at any given moment in the program, or during any execution of a binary
code.
Scan Port Driver describes the Scan Port Driver Interface and how it is
used during micro- programming.

1 Introduction To Boundary-Scan

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1 Introduction To Boundary-Scan

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Medalist i3070 In-circuit Test System

1-2 Boundary-Scan Testing

Boundary-Scan Background and Applications

Figure 1-1 A boundary-scan device

There are other registers within a boundary- scan device.

Boundary-Scan Testing 1-3

• An Identification Register, called the IDCODE Register, identifies the

Figure 1-2 Simplified block diagram of a boundary-scan device

Test Data Registers

1-4 Boundary-Scan Testing

Boundary-Scan Testing 1-5

How Can Boundary-Scan Solve These Problems?

1-6 Boundary-Scan Testing

Figure 1-3 Few boundary-scan components, not connected to each other

Boundary-Scan Component Conventional Components

Boundary-Scan Testing 1-7

1-8 Boundary-Scan Testing

In the implementations described in Scenario 2, EXTEST could be

Boundary-Scan Testing 1-9

The Manufacturing Fault Spectrum

Figure 1-5 The manufacturing fault spectrum

Bonding faults Internal errors Open pin

1-10 Boundary-Scan Testing

The Boundary-Scan Device

Boundary-Scan Device Elements

Boundary-Scan Testing 1-11

Figure 1-6 Boundary-Scan Device

1-12 Boundary-Scan Testing

TAP Controller State Shift-Register Flip-Flop Parallel Output Latch

Boundary-Scan Testing 1-13

Sample Instruction Register Cell

Figure 1-7 A sample instruction register cell

1-14 Boundary-Scan Testing

Sample Data Register Cell

Boundary-Scan Testing 1-15

Figure 1-8 A sample data register cell

Shift out MUX

Input Pin 1 Internal Logic

Shift in Clock-DR Update-DR

Input Pin Internal Shift In

TCK TAP Controller TMS

1-16 Boundary-Scan Testing

Test Data In (TDI)

Test Data Out (TDO)

Test Clock (TCK)

Test Mode Select (TMS)

Boundary-Scan Testing 1-17

While in test mode, you can execute:

Test Reset (TRST)

Figure 1-9 Block diagram of a boundary-scan device

Test Data Registers

Device Inputs Internal Logic Device Outputs

Device Identification Register

Reset* Instruction Register

1-18 Boundary-Scan Testing

Operation Modes and Instructions

Normal Operation Mode

Boundary-Scan Testing 1-19

Figure 1-10 Cell status during normal operation mode

Test Operation Mode

1-20 Boundary-Scan Testing

Figure 1-11 Cell status during test operation mode

Boundary-Scan Testing 1-21