KEYNOTE ADDRESS

3D FinFET and other sub-22nm Transistors

Chenming Hu
Dept. of EECS, University of California, Berkeley, Ca., USA.

Abstract-FinFET provides needed relief to ICs from
performance, power, and device variation predicaments. It also
provides higher carrier mobility, especially at low voltage near
the threshold voltage, giving promise to practical near-threshold
circuits. Another new transistor conceived simultaneously
with FinFET, UTB-SOI FET, is also entering production.
Together they showed a new scaling path forward: scale the
body thickness in proportion to gate length.
interfere with Vg's role as the sole controlling voltage. As Lg
decreases, Cd increases [1,2] and Vg loses its absolute
control. In extreme cases, Vg has less control than Vd and
the transistor can be turned on by Vd alone without Vg as
shown in top curve of Fig. 1. Before reaching that extreme,
we get the other deteriorating curves in Fig.1. The classical
solution has been to increase Cg by reducing gate
oxide/high-k dielectric thickness in proportion to Lg.

I. CONVENTIONAL MOSFET SCALING LIMIT

The IC design window of performance, dynamic power,
static power, and device variation has shrunk to the point that
major investment for a new transistor structure can be
justified. In order to understand the benefits of the new
structures, we must first understand the limitations of the
conventional planar MOSFETs.

As gate length shrinks, MOSFET's Id-Vg characteristics

degrade as illustrated in Fig. 1. First the subthreshold swing Fig. 2. With decreasing L, rising Cd allows Vd to control the channel
(S) degrades and Vt decreases, i.e. the device cannot be potential (lower figure) just as Vg [1]. Scaling gate oxide thickness can
turned off easily by lowering Vg. Second, S and Vt become solve this classical problem.
increasingly sensitive to Lg variations, i.e. device variations
become more problematic. These problems are known as the
short-channel effects. In the early 1990's, I realized that a second root cause
would limit Lg scaling even if an ideal "zero thickness"
dielectric were available. Fig 3. shows that subthrshold
current does not have to flow along the silicon-dielectric
interface. In fact the electron wave density is nearly zero at
the silicon-dielectric interface. The subthreshold current
density may peak several nm below the interface, especially
when the body is undoped. Leakage paths far from the gate
(see Fig. 3) are worse than the surface leakage path because
they are weakly controlled by Vg (Cg is small even with
"zero" oxide thickness) and their potential barriers can be
easily lowered by Vd through the large Cd in a small Lg
device.

Fig. 1. Shrinking gate length made sub-Vt swing larger, Vt and Ioff more
sensitive to gate CD variation and random dopant fluctuation.

Fig. 2 shows the root cause of short channel effects in

modern MOSFETs [1]. A transistor is turned on and off when
Vg lowers and raises the potential of the channel (and thus
the potential barrier between the channel and the source)
Fig. 3. Beyond 20nm even a 0nm thin gate dielectric cannot stop Vd
through the gate to channel capacitance, Cg. In an ideal
from lowering the potential barrier along leakage paths a few nm below
transistor, the channel potential is only controlled by Vg and the interface [1].
Cg. In a real transistor, the channel potential is also subject to
the influence of Vd through Cd. When Lg is large, Cd is
much smaller than Cg and the drain voltage does not
 To address this second root cause, two structure concepts
were proposed in response to a DARPA request for proposal
for "Sub-25nm Switches" in 1996. We called them FinFET
and Ultra-Thin Body SOI (UTB-SOI). Both of them would
eliminate leakage paths that are far from the gate by not
allowing semiconductor body to exist far from the gate.
II. FINFET
Fig. 4 shows a MOSFET whose body is a thin piece of
undoped silicon with gates above and below it. If the body is
thin, any lines drawn between source and drain (leakage
paths) would not be far from one or the other gates. Channel
doping is not needed for suppressing the short channel
effects. Thus random dopant fluctuation, a major
contributor to device variation, is eliminated.
Fig. 4. Top: A thin Si body eliminates the leakage paths in Fig. 3. Bottom:
Leakage current density is low near the gate and highest in the center of
the body [1].
FinFET in Fig. 5 is a manufacturable version of the
structure in Fig. 4. The thin body is shaped like a fish fin and
created with the usual patterning and etching technologies.
The fin can be constructed on SOI or the lower-cost bulk
substrates. The fin is then coated with gate stack and
patterned much as a planar MOSFET. The structure is
quasi-planar as the fin is lower than the gate thickness.
Fig. 5. FinFET with a thin body (TSI<LG) dramatically reduces short
channel effects including device variation and IOFF
If the fin is thin enough, with Tsi smaller than Lg, the
short channel effects are very well suppressed and the
subthreshold swing is basically the theoretical best case,
~62mV/decade at room temperature (Fig. 6). A new scaling
path was born: Lg can be scaled by scaling the fin (body)
thickness. If lithography and etching can produce 5nm Lg,
for example, they can produce ~5nm Tsi. Therefore the
condition Tsi~<Lg can always be satisfied. We reported
18nm and 45nm working FinFETs and 10nm FinFET
simulation results in 1999 [3]. Soon after, 10nm and 5nm and
FinFETs and FinFETs with triple gates [4] were reported by
IC manufacturers. FinFET is scalable to single digit nm.
FinFET is dense and manufacturable. The only major
new fabrication step is over-etching of the STI oxide to
expose the fins. FinFET occupies lest Si area than planar
MOSFET because the channel width (W) of triple-gate
FinFET [4] is twice the fin height plus the fin width and W is
larger than the fin pitch. Multiple fin heights can be achieved
rather easily [5].
Fig. 6. 1999 FinFET with excellent subthreshold swing and Ioff and
undoped body eliminating random dopant effect. LG=45nm TSI=30nm
[3].
III. ULTRA-THIN BODY SOI (UTB-SOI)
Partially depleted SOI MOSFET has no better scaling
potential then bulk MOSFET. By reducing the silicon film
thickness (or Si doping concentration) from partially to fully
deleted SOI (from 40nm to 15nm for example), one would
not improve short channel effects and may worsen it by
eliminating the ground plane provided by the undepleted Si
body [6]. However, if the Si film is only several nm thin as
shown in Fig. 7, short channel effects can be greatly
suppressed [7]. Fig. 8 illustrates the surprising benefit of
UTB-SOI: simulated leakage current is reduced by ~10X for
every nm drop in Tsi. Fig. 9 shows UTB-SOI with 3nm Si
body, mid-gap gate, with raised source and drain [8].
Fig.7. Ultra Thin Body UTB-SOI has no vulnerable leakage paths if Si
exists only within a few nm from the gate [7].
 IV. VACUUM SPACER TRANSISTOR
1.E-02
Drain Current [A/um]
1.E-04 Fig. 11 shows a MOSFET with a vacuum spacer between
the gate side walls. The vacuum space is very effective in
1.E-06
reducing the capacitance between the gate and the
1.E-08 Tsi=8nm drain/source diffusion regions and contact plugs. The
Tsi=6nm reduction is particularly beneficial on the drain side where
1.E-10 Tsi=4nm the capacitance is amplified by the Miller effect. With the
capacitance well suppressed, we propose to introduce
1.E-12
self-aligned contact (SAC) into embedded SRAM and SOC
0 0.2 0.4 0.6 0.8 1 circuits as shown in Fig. 11. The fabrication flows have been
Gate Voltage [V] proposed for gate first [11] and gate last [12] technologies
and their benefits in simulated inverter switching energy and
Fig. 8. Simulation shows UTB-SOI has excellent Ioff and S if speed and expected SRAM cell size have been reported.
TSI<LG/4. LG=20nm, VDS=1V, lightly doped body [7].
Fig. 12 shows that a summary of the simultaneous
improvements in speed, power, and density.
We can expect that FinFET UTB-SOI will benefit even
more from vacuum spacer because of the raised S/D
structure.

Fig. 9. 2001 UTB-SOI with 3nm ultra-thin Si body. Ge raised

source/drain reduces the series resistance [8].

Fig. 10. UTB-SOI (left) can be back-gated similar to well biasing.

UTB-SOI requires SOI substrates with Si film uniformity FinFET (right) top gate can be removed for back gating [9].
of +-0.5nm or less than two silicon atoms so that a 5nm
ultra-thin Si film will not have more than +-10%
non-uniformity--across wafer and from wafer to wafer. In
2009 SOI wafer supplier, Soitec, developed SOI wafers with
uniformity of +-0.5nm. The IC industry now have FinFET
and UTB-SOI for future transistors.

UTB-SOI has the attractive feature of back gating that

adjust the Vt better than CMOS well-biasing as illustrated in
Fig. 10. This feature is valuable for power management.
FinFET does not provide back gating in its simple form. A
modified version of FinFET [9], whose top gate is removed
with a CMP process leaving two separate gates, shown in Fig.
11, can provide back gating. It can be used to design small
SRAM cell with excellent noise margin [9]. For general
power management using this device, wiring lay-out needs to
be carefully evaluated. Fig. 11. Gate to S/D/contact-plug capacitance can be reduced with
vacuum spacer allowing self-aligned contact for gate first [11] and gate
last [12] processes.
UTB-SOI needs less technology development investment
than FinFET but has a higher substrate cost. IC
manufacturers must evaluate the relative wafer processing
costs for full cost comparison. Quantization effect in Si body
thinner than 5nm will cause electron and hole mobility
degradation and increase Vt sensitivity to Tsi variation [10].

Fig. 12. Relative to conventional oxide spacer, vacuum spacer with self
aligned contact (SAC) improves speed, power, and density
simultaneously [13].
V. CONCLUSIONS
Developed in the same research project, FinFET and
UTB-SOI demonstrate a new scaling path: scaling body
thickness with Lg to take CMOS below 10nm. Intel is using
FinFET starting at 22nm and foundries will do so at 14nm.
ST Microelectronics will introduce UTB-SOI product at
28nm, taking advantage of easier ramp up and back-gating.
Future opportunities are proposed including multiple fin
height for better density, vacuum spacer for better
power/speed/density (self-aligned contact), and low power
near-threshold circuits with higher performance.
ACKNOWLEDGMENT
This study is sponsored by SRC and UC-IMPACT.
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