Synopsys® Design Compiler® and Design

Compiler NXT Release Notes

Version P-2019.03
March 11, 2019 1
These release notes present the latest information about Design Compiler version
P-2019.03 in the following sections:
• New Features, Enhancements, and Changes
• Resolved STARs
• Safety-Related Issues

© 2019 Synopsys, Inc. All rights reserved.

Design Compiler Release Notes Version P-2019.03

New Features, Enhancements, and Changes

Design Compiler version P-2019.03 provides the following new features, enhancements,
and changes in the following tools:
• Design Compiler NXT
• Design Compiler

Design Compiler NXT

The Design Compiler NXT tool extends topographical technology by providing
• Better QoR through advanced optimizations
• Enhanced physical guidance to IC Compiler II, with improved RC and timing correlation
• Faster runtime, with improved multithreading synthesis for better scalability
• Plug-and-play user interface and script compatibility with Design Compiler Graphical
The following features are new in the Design Compiler NXT tool:
• Increase in the Size of EST and Installation Images
• Performing Buffering-Aware Placement With the IC Compiler II Link
• Performing Automatic Timing Control With the IC Compiler II Link
• Performing Congestion-Driven Restructuring With the IC Compiler II Link
• Applying Required Settings for High Performance Cores
• Performing RC Extraction With the RC Model
• Mapping Site Names While Reading a DEF File

Increase in the Size of EST and Installation Images

Begin with the P-2019.03 release, the Design Compiler NXT tool installation includes the IC
Compiler II tool. Therefore, the file size of
• The Electronic Software Transfer (EST) image is approximately increased by 3.5 GB
• The installation image is approximately increased by 7.6 GB

New Features, Enhancements, and Changes 2

Design Compiler Release Notes Version P-2019.03

Performing Buffering-Aware Placement With the IC Compiler II Link

Beginning with the P-2019.03 release, you can consider high-fanout nets and long nets
during the initial placement with the buffering-aware placement feature to improve Quality of
Results (QoR). To enable buffering-aware timing-driven placement when you use the
compile_ultra -spg command, use the new placer_buffering_aware variable. The
default is false.
To use the buffering-aware placement feature, you must use the set_icc2_options
command as follows:
dcnxt_shell-topo> set_app_var placer_buffering_aware true
dcnxt_shell-topo> set_icc2_options –ref_libs "lib1.ndm lib2.ndm" \
-technology tech.tf

When you set the placer_buffering_aware variable to true during the initial placement
with the compile_ultra -spg command ,
• Design Compiler NXT enables timing-driven placement with an approximate timing
model that estimates the effects of buffering high-fanout nets and long nets. The netlist
does not change.
• Before invoking the IC Compiler II tool, Design Compiler NXT issues the following
message:
Information: Buffering aware placement is enabled. (SPG-129)

• After invoking the IC Compiler II tool, the following message is issued in the IC Compiler
II log file:
Create Placement Options:
Buffering Aware Timing Driven: true

Performing Automatic Timing Control With the IC Compiler II Link

Beginning with the P-2019.03 release, you can use the automatic timing control feature to
improve total negative slack (TNS) during direct timing-driven placement. To enable
automatic timing control when you use the compile_ultra -spg and compile_ultra
-incremental -spg commands, use the new placer_auto_timing_control variable.
The default is false.
Note:
If you set both the placer_buffering_aware and placer_auto_timing_control
variables to true, the tool performs both buffering-aware placement and automatic
timing control during the initial placement. However, the tool still performs automatic
timing control during the direct timing-driven placement.
To use the automatic timing control feature, you must use the set_icc2_options command
as follows:

New Features, Enhancements, and Changes 3

Design Compiler Release Notes Version P-2019.03

dcnxt_shell-topo> set_app_var placer_auto_timing_control true

dcnxt_shell-topo> set_icc2_options –ref_libs "lib1.ndm lib2.ndm" \
-technology tech.tf

When you set the placer_auto_timing_control variable to true,

• Design Compiler NXT enables the IC Compiler II direct timing-driven placement along
with the Zroute-based congestion-driven placement when you use the compile_ultra
-spg command.

• Design Compiler NXT enables only the IC Compiler II direct timing-driven placement
when you use the compile_ultra -incremental -spg command. However, to enable
the IC Compiler II Zroute-based congestion-driven placement during the incremental
compile, you must set the spg_congestion_placement_in_incremental_compile
variable to true.
• The direct timing-driven placement tries to focus the timing optimization on the most
critical timing paths to balance between reducing the worst negative slack (WNS) and
reducing the total negative slack (TNS)
• Before invoking the IC Compiler II tool, Design Compiler NXT issues the following
message:
Information: Auto timing control is enabled in the placer. (SPG-129)

• After invoking the IC Compiler II tool, the following message is issued in the IC Compiler
II log file:
Printing options for 'place.coarse.*' (non-default only)
place.coarse.auto_timing_control: true

Performing Congestion-Driven Restructuring With the IC Compiler

II Link
Beginning with the P-2019.03 release, you can improve congestion in the design that is
caused by commutative and associative logic trees, such as OR trees, AND trees, and XOR
trees. You can improve congestion by rewiring input signals of the logic trees with the
congestion-driven restructuring feature.
To enable congestion-driven restructuring when you use the compile_ultra -spg
command, use the new placer_cong_restruct variable. The default is false. To use the
congestion-driven restructuring feature, you must use the set_icc2_options command as
follows:
dcnxt_shell-topo> set_app_var placer_cong_restruct true
dcnxt_shell-topo> set_icc2_options –ref_libs "lib1.ndm lib2.ndm" \
-technology tech.tf

New Features, Enhancements, and Changes 4

Design Compiler Release Notes Version P-2019.03

When you set the placer_cong_restruct variable to true,

• Design Compiler NXT performs restructuring of the net during the initial placement with
the compile_ultra -spg command
• Before invoking the IC Compiler II tool, Design Compiler NXT issues the following
message:
Information: Congestion driven restructuring placement is enabled.
(SPG-131)

• After invoking the IC Compiler II tool, the following message is issued in the IC Compiler
II log file:
Printing options for 'place.coarse.*' (non-default only)
place.coarse.cong_restruct: on

Applying Required Settings for High Performance Cores

Beginning with the P-2019.03 release, you can apply tool settings required for achieving the
best QoR for high performance cores by using the new set_technology and
set_hpc_options commands. The applied settings affect synthesis, placement,
optimization, and timing analysis. The 16, 12, and 7 nanometer technology nodes are
supported with the set_technology command.
As shown in the following example, you must use
• The set_technology command to apply technology-node settings before using the
set_hpc_options command

• The set_hpc_options command before using the compile_ultra and

compile_ultra -incremental commands to set the stage-specific settings
# read the setup, design, and constraints
set_technology –node 7
set_hpc_options –core A55 -stage compile
compile_ultra -spg
...
insert_dft
...
set_hpc_options –core A55 -stage compile_inc
compile_ultra -spg -incremental

Note:
If you apply any tool settings after using the set_hpc_options command, the last
setting overrides the previous settings.

To report the core and technology-node settings applied by the tool, use the -report_only
option of the set_hpc_options command.

New Features, Enhancements, and Changes 5

Design Compiler Release Notes Version P-2019.03

Performing RC Extraction With the RC Model

Beginning with the P-2019.03 release, you can perform RC extraction for improving the RC
correlation with the pre place_opt results from the IC Compiler II tool. To perform the RC
extraction, use the new spg_icc2_rc_correlation variable to correlate the RC value of
Design Compiler with the IC Compiler II tool, which helps in solving timing miscorrelation
issues.
This feature is available only
• When you use the compile_ultra -spg command
• In the advanced-technology nodes (16 nm and lower-process nodes) when metal layers
have a significant difference in resistance value
When you set this variable to true (the default is false),
• The extract_rc command performs RC extraction by using the advanced RC model
• The tool issues the “Turning on advanced RC model” message to indicate that this
feature is enabled for optimization and extraction when you use the compile_ultra,
compile_ultra - incremental, and optimize_netlist commands and explicitly run
the extract_rc command

Mapping Site Names While Reading a DEF File

In previous releases, when you created a DEF file in the tool to hand off a design while
invoking IC Compiler II, the site name in the DEF file was from the Milkyway reference
library. When you read this DEF file in the IC Compiler II link, site name mismatch between
the Milkyway reference library and the NDM reference library occurred resulting in the
following DEFR-004 error message:
Error: Cannot find site 'unit'. (DEFR-004)

Beginning with the P-2019.03 release, use the new -convert_sites {from_site
to_site} option with the set_icc2_options command, so the tool does not issue the
DEFR-004 error message due to site name mismatch. Use the new option as shown in the
following example:
prompt> set_icc2_options -ref_libs "lib1.ndm" -technology tech.tf \
-convert_sites {unit CORE}

In this example,
• from_site (unit) is the site name in the Milkyway reference library

• to_site (Core) is the site name in the NDM reference library

New Features, Enhancements, and Changes 6

Design Compiler Release Notes Version P-2019.03

The set_icc2_options -convert_sites command converts the site name from "unit" to
"CORE" when the tool reads the DEF file after invoking IC Compiler II and issues the
following message:
Information: Converted site definition 'unit' to 'CORE'. (DEFR-031)

Design Compiler
The following features are new in the Design Compiler tool:
• Linking Physical Libraries
• Runtime Improvement With Multiple Clocks Per Register
• DesignWare minPower Merged With DesignWare Building Blocks

Linking Physical Libraries

In previous releases, the Design Compiler tool did not link physical libraries automatically
when you use the analyze and elaborate commands to read your designs. It issued the
LINK-5 error and the OPT-1428 warning messages.
Beginning with the P-2019.03 release, you can manually link the physical libraries by using
the new enable_phys_lib_during_elab variable, as shown in the following example.
prompt> set_app_var enable_phys_lib_during_elab true

When the enable_phys_lib_during_elab variable is set to true,

• The tool links the physical libraries before using the analyze and elaborate
commands.
• The analyze and elaborate flow behaves the same way as the read_verilog flow.

Runtime Improvement With Multiple Clocks Per Register

In previous releases, the compile_ultra command issued the TIM-099 message when
clock pins were driven by multiple clocks. Therefore, concurrent analysis of multiple clocks
might have resulted in long runtime due to increased timing complexity.
Beginning with the P-2019.03 release, the compile_ultra command by default considers
multiple clock-related constraints without affecting QoR. You can improve the runtime further
by reducing clock interactions.
For more information, see “Reporting Runtime Issues Related to SDC Constraints” in
Chapter 8, “Defining Design Constraints,” in the Design Compiler User Guide.

New Features, Enhancements, and Changes 7

Design Compiler Release Notes Version P-2019.03

DesignWare minPower Merged With DesignWare Building Blocks

Beginning with the P-2019.03 release, the DesignWare minPower product is merged with
the DesignWare Building Blocks product and the following changes are made:
• minPower components and minPower optimization do not require the DesignWare-LP
license.
• To instantiate minPower components in a RTL file, you must set only the
dw_foundation.sldb file in the synthetic_library list
• To enable the minPower optimization, use the new power_enable_minpower variable as
follows. The default is false.
prompt> set_app_var power_enable_minpower true

Note that
• The DesignWare-LP license is required when the tool loads the .ddc file generated using
the DesignWare-LP license from previous releases of Design Compiler
• If the existing script has the dw_minpower.sldb file set in the synthetic_library list, the tool
automatically enables the new power_enable_minpower variable

Resolved STARs
Design Compiler version P-2019.03 resolves the Synopsys Technical Action Requests
(STARs) listed in the following table.
Table 1 Resolved Design Compiler STARs

STAR ID Title

9001465090 Update the Design Compiler user guide to correctly mention the default value of
the spg_place_enable_precluster command

9001457761 The -start_end_pair option of the report_timing command does not filter timing
paths correctly

9001447596 The set_clock_sense command is written out in the SDC file after incremental
compile, but it is not used by the input SDC file

9001428568 The tool issues the UIED-39 error message with the remove_port command

9001413416 Fatal error occurs when compiling with the set_net_routing_layer_constraints

command

9001372473 The remove_port and remove_net commands have very long runtime

Resolved STARs 8
Design Compiler Release Notes Version P-2019.03

Table 1 Resolved Design Compiler STARs (Continued)

STAR ID Title

9001367190 Fatal error occurs during the DesignWare elaboration when

template_separator_style is set to {/}

9001347124 The group_path command should use weights for integrated clock-gating paths
before compile

9001332882 Fatal error occurs with the write_icc2_files command

9001281017 Block clock-gate pin gets disconnected when loading a block abstraction model

9001192245 Update the extract_physical_constraints man page with the -no_incremental

option behavior details

Safety-Related Issues
A list of known ISO 26262 automotive safety-related issues for the Design Compiler tool is
available in SolvNet article 2830153, “Design Compiler Safety-Related Issues Master List.”

Safety-Related Issues 9