25073a PDF

MCP6N11
500 kHz, 800 µA Instrumentation Amplifier

Features Description
• Rail-to-Rail Input and Output Microchip Technology Inc. offers the single MCP6N11
• Gain Set by 2 External Resistors instrumentation amplifier (INA) with Enable/VOS Cali-
• Minimum Gain (GMIN) Options: bration pin (EN/CAL) and several minimum gain
1, 2, 5, 10 or 100 V/V options. It is optimized for single-supply operation with
rail-to-rail input (no common mode crossover distor-
• Common Mode Rejection Ratio (CMRR): 115 dB
tion) and output performance.
(typical, GMIN = 100)
• Power Supply Rejection Ratio (PSRR): 112 dB Two external resistors set the gain, minimizing gain
(typical, GMIN = 100) error and drift-over temperature. The reference voltage
(VREF) shifts the output voltage (VOUT).
• Bandwidth: 500 kHz (typical, Gain = GMIN)
• Supply Current: 800 μA/channel (typical) The supply voltage range (1.8V to 5.5V) is low enough
to support many portable applications. All devices are
• Single Channel
fully specified from -40°C to +125°C.
• Enable/VOS Calibration pin: (EN/CAL)
These parts have five minimum gain options (1, 2, 5, 10
• Power Supply: 1.8V to 5.5V
and 100 V/V). This allows the user to optimize the input
• Extended Temperature Range: -40°C to +125°C offset voltage and input noise for different applications.
Typical Applications Typical Application Circuit

• High Side Current Sensor VBAT
• Wheatstone Bridge Sensors 10 Ω +1.8V
IDD
• Difference Amplifier with Level Shifting VDD to
U1 +5.5V
• Power Control Loops
MCP6N11
VOUT
Design Aids
RF
• Microchip Advanced Part Selector (MAPS) VFG 200 kΩ
• Demonstration Board
RG
• Application Notes
10 kΩ
VREF
Block Diagram
Package Types
VOUT VDD VSS
MCP6N11 MCP6N11
VOUT RM4
I4 SOIC 2×3 TDFN *
RF
VFG
VFG 1 8 EN/CAL VFG 1 8 EN/CAL
RG GM2 Σ VIM 2 7 VDD VIM 2 7 VDD
VREF I2 I3 EP
VREF VIP 3 6 VOUT VIP 3 9
6 VOUT
I1
VSS 4 5 VREF VSS 4 5 VREF
VIP GM3
VIP
GM1 * Includes Exposed Thermal Pad (EP); see Table 3-1.
VTR
VIM
VIM
Low Power
POR
VOS Calibration
EN/CAL
© 2011 Microchip Technology Inc. DS25073A-page 1

MCP6N11
Minimum Gain Options
Table 1 shows key specifications that differentiate
between the different minimum gain (GMIN) options.
See Section 1.0 “Electrical Characteristics”,
Section 6.0 “Packaging Information” and Product
Identification System for further information on GMIN.
TABLE 1: KEY DIFFERENTIATING SPECIFICATIONS

Eni eni
GMIN VOS ∆VOS/∆TA CMRR (dB) PSRR VDMH GBWP
(µVP-P) (nV/√Hz)
Part No. (V/V) (±mV) (±µV/°C) Min. (dB) (V) (MHz)
Nom. Nom.
Nom. Max. Typ. VDD = 5.5V Min. Max. Nom.
(f = 0.1 to 10 Hz) (f = 10 kHz)
MCP6N11-001 1 3.0 90 70 62 2.70 0.50 570 950
MCP6N11-002 2 2.0 45 78 68 1.35 1.0 285 475
MCP6N11-005 5 0.85 18 80 75 0.54 2.5 114 190
MCP6N11-010 10 0.50 9.0 81 81 0.27 5.0 57 95
MCP6N11-100 100 0.35 2.7 88 86 0.027 35 18 35
DS25073A-page 2 © 2011 Microchip Technology Inc.

MCP6N11
1.0 ELECTRICAL † Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
CHARACTERISTICS
the device. This is a stress rating only and functional
operation of the device at those or any other
1.1 Absolute Maximum Ratings † conditions above those indicated in the operational
VDD – VSS .......................................................................6.5V listings of this specification is not implied. Exposure to
maximum rating conditions for extended periods may
Current at Input Pins †† ...............................................±2 mA
affect device reliability.
Analog Inputs (VIP and VIM) †† ..... VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V †† See Section 4.2.1.2 “Input Voltage Limits” and
Difference Input Voltage....................................... |VDD – VSS| Section 4.2.1.3 “Input Current Limits”.
Output Short Circuit Current ................................ Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ...................................-65°C to +150°C
Max. Junction Temperature ........................................ +150°C
ESD protection on all pins (HBM, CDM, MM) .≥ 2 kV, 1.5 kV, 300V
1.2 Specifications
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD,
VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and GDM = GMIN; see Figure 1-6 and Figure 1-7.
Parameters Sym Min Typ Max Units GMIN Conditions
Input Offset
Input Offset Voltage, VOS -3.0 — +3.0 mV 1 (Note 2)
Calibrated -2.0 — +2.0 mV 2
-0.85 — +0.85 mV 5
-0.50 — +0.50 mV 10
-0.35 — +0.35 mV 100
Input Offset Voltage VOSTRM — 0.36 — mV 1
Trim Step — 0.21 — mV 2
— 0.077 — mV 5
— 0.045 — mV 10
— 0.014 — mV 100
Input Offset Voltage ΔVOS/ΔTA — ±90/GMIN — µV/°C 1 to 10 TA= -40°C to +125°C
Drift — ±2.7 — µV/°C 100 (Note 3)
Power Supply PSRR 62 82 — dB 1
Rejection Ratio 68 88 — dB 2
75 96 — dB 5
81 102 — dB 10
86 112 — dB 100
Note 1: VCM = (VIP + VIM) / 2, VDM = (VIP – VIM) and GDM = 1 + RF/RG.
2: The VOS spec limits include 1/f noise effects.
3: This is the input offset drift without VOS re-calibration; toggle EN/CAL to minimize this effect.
4: These specs apply to both the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (VREF takes VCM’s place).
5: This spec applies to the VIP, VIM, VREF and VFG pins individually.
6: Figure 2-11 and Figure 2-19 show the VIVR and VDMR variation over temperature.
7: See Section 1.5 “Explanation of DC Error Specs”.

MCP6N11
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Input Current and Impedance (Note 4)
Input Bias Current IB — 10 — pA all
Across Temperature — 80 — pA TA= +85°C
Across Temperature 0 2 5 nA TA= +125°C
Input Offset Current IOS — ±1 — pA
Across Temperature — ±5 — pA TA= +85°C
Across Temperature -1 ±0.05 +1 nA TA= +125°C
Common Mode Input ZCM — 1013||6 — Ω||pF
Impedance
Differential Input ZDIFF — 1013||3 — Ω||pF
Impedance
Input Common Mode Voltage (VCM or VREF) (Note 4)
Input Voltage Range VIVL — — VSS − 0.2 V all (Note 5, Note 6)
VIVH VDD + 0.15 — — V
Common Mode CMRR 62 79 — dB 1 VCM = VIVL to VIVH,
Rejection Ratio 69 87 — dB 2 VDD = 1.8V
75 101 — dB 5
79 107 — dB 10
86 119 — dB 100
70 94 — dB 1 VCM = VIVL to VIVH,
78 100 — dB 2 VDD = 5.5V
80 108 — dB 5
81 114 — dB 10
88 115 — dB 100
Common Mode INLCM -1000 ±115 +1000 ppm 1 VCM = VIVL to VIVH,
Non-Linearity -570 ±27 +570 ppm 2 VDM = 0V,
VDD = 1.8V (Note 7)
-230 ±11 +230 ppm 5
-125 ±6 +125 ppm 10
-50 ±2 +50 ppm 100
-400 ±42 +400 ppm 1 VCM = VIVL to VIVH,
-220 ±10 +220 ppm 2 VDM = 0V,
VDD = 5.5V (Note 7)
-100 ±4 +100 ppm 5
-50 ±2 +50 ppm 10
-30 ±1 +30 ppm 100

MCP6N11
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Input Differential Mode Voltage (VDM) (Note 4)
Differential Input VDML -2.7/GMIN — — V all VREF = (VDD – GDMVDM)/2
Voltage Range VDMH — — +2.7/GMIN V (Note 6)
Differential Gain Error gE -1 ±0.13 +1 % VDM = VDML to VDMH,
Differential Gain Drift ΔgE/ΔTA — ±0.0006 — %/°C VREF = (VDD – GDMVDM)/2
Differential INLDM -500 ±30 +500 ppm 1 (Note 7)
Non-Linearity -800 ±40 +800 ppm 2, 5
-2000 ±100 +2000 ppm 10, 100
DC Open-Loop Gain AOL 61 84 — dB 1 VDD = 1.8V,
68 90 — dB 2 VOUT = 0.2V to 1.6V
76 98 — dB 5
78 104 — dB 10
86 116 — dB 100
70 94 — dB 1 VDD = 5.5V,
77 100 — dB 2 VOUT = 0.2V to 5.3V
84 108 — dB 5
90 114 — dB 10
97 125 — dB 100
Output
Minimum Output VOL — — VSS + 15 mV all VDM = -VDD/(2GDM),
Voltage Swing VDD = 1.8V,
VREF = VDD/2 – 1V
— — VSS + 25 mV VDM = -VDD/(2GDM),
VDD = 5.5V,
VREF = VDD/2 – 1V
Maximum Output VOH VDD − 15 — — mV VDM = VDD/(2GDM),
Voltage Swing VDD = 1.8V,
VREF = VDD/2 + 1V
VDD − 25 — — mV VDM = VDD/(2GDM),
VDD = 5.5V,
VREF = VDD/2 + 1V
Output Short Circuit ISC — ±8 — mA VDD = 1.8V
Current — ±30 — mA VDD = 5.5V
Power Supply
Supply Voltage VDD 1.8 — 5.5 V all
Quiescent Current IQ 0.5 0.8 1.1 mA IO = 0
per Amplifier
POR Trip Voltage VPRL 1.1 1.4 — V
VPRH — 1.4 1.7 V

MCP6N11
TABLE 1-2: AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = 1.8V to 5.5V, VSS = GND,
EN/CAL = VDD, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN;
see Figure 1-6 and Figure 1-7.
AC Response
Gain Bandwidth GBWP — 0.50 GMIN — MHz 1 to 10
Product — 35 — MHz 100
Phase Margin PM — 70 — ° all
Open-Loop Output ROL — 0.9 — kΩ 1 to 10
Impedance — 0.6 — kΩ 100
Power Supply PSRR — 94 — dB all f < 10 kHz
Rejection Ratio
Common Mode CMRR — 104 — dB 1 to 10 f < 10 kHz
Rejection Ratio — 94 — dB 100 f < 10 kHz
Step Response
Slew Rate SR — 3 — V/µs 1 to 10 VDD = 1.8V
— 9 — V/µs VDD = 5.5V
— 2 — V/µs 100 VDD = 1.8V
— 6 — V/µs VDD = 5.5V
Overdrive Recovery, tIRC — 10 — µs all VCM = VSS – 1V (or VDD + 1V) to VDD/2,
Input Common Mode GDMVDM = ±0.1V, 90% of VOUT change
Overdrive Recovery, tIRD — 5 — µs VDM = VDML – (0.5V)/GMIN
Input Differential (or VDMH + (0.5V)/GMIN) to 0V,
Mode VREF = (VDD – GDMVDM)/2,
90% of VOUT change
Overdrive Recovery, tOR — 8 — µs GDM = 2GMIN, GDMVDM = 0.5VDD to 0V,
Output VREF = 0.75VDD (or 0.25VDD),
90% of VOUT change
Noise
Input Noise Voltage Eni — 570/GMIN — µVP-P 1 to 10 f = 0.1 Hz to 10 Hz
— 18 — µVP-P 100
Input Noise Voltage eni — 950/GMIN — nV/√Hz 1 to 10 f = 100 kHz
Density — 35 — nV/√Hz 100
Input Current Noise ini — 1 — fA/√Hz all f = 1 kHz
Density

MCP6N11
TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD,
VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN;
see Figure 1-6 and Figure 1-7.
EN/CAL Low Specifications

EN/CAL Logic VIL VSS — 0.2 VDD V all
Threshold, Low
EN/CAL Input Current, IENL — -0.1 — nA EN/CAL = 0V
Low
GND Current ISS -7 -2.5 — µA EN/CAL = 0V, VDD = 5.5V
Amplifier Output Leakage IO(LEAK) — 10 — nA EN/CAL = 0V
EN/CAL High Specifications
EN/CAL Logic VIH 0.8 VDD VDD V all
Threshold, High
EN/CAL Input Current, IENH — -0.01 — nA EN/CAL = VDD
High
EN/CAL Dynamic Specifications
EN/CAL Input Hysteresis VHYST — 0.2 — V all
EN/CAL Low to Amplifier tOFF — 3 10 µs EN/CAL = 0.2VDD to VOUT = 0.1(VDD/2),
Output High-Z Turn-off VDMGDM = 1 V, VL = 0V
Time
EN/CAL High to tON 12 20 28 ms EN/CAL = 0.8VDD to VOUT = 0.9(VDD/2),
Amplifier Output VDMGDM = 1 V, VL = 0V
On Time
EN/CAL Low to tENLH 100 — — µs Minimum time before externally
EN/CAL High low time releasing EN/CAL (Note 1)
Amplifier On to tENOL — 100 — µs
EN/CAL Low Setup Time
POR Dynamic Specifications
VDD ↓ to Output Off tPHL — 10 — µs all VL = 0V, VDD = 1.8V to
VPRL – 0.1V step,
90% of VOUT change
VDD ↑ to Output On tPLH 140 250 360 ms VL = 0V, VDD = 0V to VPRH + 0.1V step,
90% of VOUT change
Note 1: For design guidance only; not tested.
TABLE 1-4: TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = 1.8V to 5.5V, VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA -40 — +125 °C
Operating Temperature Range TA -40 — +125 °C (Note 1)
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8L-SOIC θJA — 150 — °C/W
Thermal Resistance, 8L-TDFN (2×3) θJA — 53 — °C/W
Note 1: Operation must not cause TJ to exceed the Absolute Maximum Junction Temperature specification (+150°C).

MCP6N11
1.3 Timing Diagrams
tENLH
±(1V)/GDM
EN/CAL
VDM
tOFF tENOL
tON
VCM
VOUT High-Z
tIRC
FIGURE 1-5: EN/CAL Timing Diagram.
VOUT
FIGURE 1-1: Common Mode Input

Overdrive Recovery Timing Diagram.
VDD/2
VCM
VDM
tIRD
VOUT
FIGURE 1-2: Differential Mode Input

Overdrive Recovery Timing Diagram.
VDD/2
VCM
VDM
tOR
VOUT
FIGURE 1-3: Output Overdrive Recovery

Timing Diagram.
1.8V
VPRH + 0.1V
VPRL – 0.1V
VDD 0V
tPHL
tPLH
VOUT High-Z
FIGURE 1-4: POR Timing Diagram.

MCP6N11
1.4 DC Test Circuits 1.4.2 DIFFERENTIAL GAIN TEST CIRCUIT
Figure 1-7 is used for testing the INA’s differential gain
1.4.1 INPUT OFFSET TEST CIRCUIT error, non-linearity and input voltage range (gE, INLDM,
Figure 1-6 is used for testing the INA’s input offset VDML and VDMH; see Section 1.5.3 “Differential Gain
errors and input voltage range (VE, VIVL and VIVH; see Error and Non-linearity”). RF and RG are 0.01% for
Section 1.5.1 “Input Offset Related Errors” and accurate gain error measurements.
Section 1.5.2 “Input Offset Common Mode Non-
linearity”). U2 is part of a control loop that forces VOUT
VDD
to equal VCNT; U1 can be set to any bias point.
VL
VDD VCM + VDM/2 2.2 µF
2.2 µF VL RL
VCM 1 kΩ 100 nF
100 nF VOUT
VOUT U1
RL
1 kΩ MCP6N11 RF 6.34 kΩ
1 kΩ 0.01% +
U1 1 kΩ 100 nF VM
MCP6N11 RG –
VCM – VDM/2 VFG
VREF 0.01% 6.34 kΩ
RG
U2 VREF
MCP6H01 63.4 kΩ FIGURE 1-7: Test Circuit for Differential
RF
Mode.
RCNT
The output voltages are (where VE is the sum of input
12.7 kΩ 63.4 kΩ offset errors and gE is the gain error):
VM
100 nF CCNT
VCNT EQUATION 1-2:
10 nF
G DM = 1 + RF ⁄ RG
FIGURE 1-6: Test Circuit for Common
Mode (Input Offset). V OUT = V REF + G DM ( 1 + g E ) ( V DM + VE )
V M = VOUT – VREF
When MCP6N11 is in its normal range of operation, the
DC output voltages are (where VE is the sum of input = G DM ( 1 + g E ) ( VDM + V E )
offset errors and gE is the gain error):
To keep VREF, VFG and VOUT within their ranges, set:
EQUATION 1-1:
G DM = 1 + R F ⁄ R G
EQUATION 1-3:
V OUT = V CNT V REF = ( V DD – G DM V DM ) ⁄ 2
V M = V REF + G DM ( 1 + g E )V E
Table 1-6 shows the recommended RF and RG. They
Table 1-5 gives the recommended RF and RG values produce a 10 kΩ load; VL can usually be left open.
for different GMIN options. TABLE 1-6: SELECTING RF AND RG
TABLE 1-5: SELECTING RF AND RG GMIN RF RG GDM
GMIN RF RG GDM GDMVOS BW (V/V) (Ω) (Ω) (V/V)
(V/V) (Ω) (Ω) (V/V) (±V) (kHz) Nom. Nom. Nom. Nom.
Nom. Nom. Nom. Nom. Max. Nom. 1 0 Open 1.000
1 100k 499 201.4 0.60 2.5 2 4.99k 4.99k 2.000
2 0.40 5.0 5 8.06k 2.00k 5.030
5 100k 100 1001 0.85 2.5 10 9.09k 1.00k 10.09
10 0.50 5.0 100 10.0k 100 101.0
100 0.35 35

MCP6N11
1.5 Explanation of DC Error Specs Based on the measured VE data, we obtain the
following linear fit:
1.5.1 INPUT OFFSET RELATED ERRORS
The input offset error (VE) is extracted from input offset EQUATION 1-6:
measurements (see Section 1.4.1 “Input Offset Test V CM – VDD ⁄ 2
Circuit”), based on Equation 1-1: V E_LIN = VOS + -----------------------------------
CMRR
Where:
EQUATION 1-4: VOS = V 2
V M – V REF 1 V3 – V1
V E = --------------------------------- ----------------- = ------------------------------
G DM ( 1 + g E ) CMRR V IVH – VIVL
VE has several terms, which assume a linear response The remaining error (ΔVE) is described by the Common
to changes in VDD, VSS, VCM, VOUT and TA (all of which Mode Non-Linearity spec:
are in their specified ranges):
EQUATION 1-7:
EQUATION 1-5:
max Δ V E
Δ V DD – Δ V SS Δ V CM Δ V REF INL CM = ------------------------------
VIVH – V IVL
V E = V OS + --------------------------------- + ----------------- + -----------------
PSRR CMRR CMRR Where:
Δ V OUT Δ V OS Δ VE = VE – VE_LIN
+ ----------------- + Δ T A ⋅ -------------
A OL ΔTA
Where: The same common mode behavior applies to VE when
VREF is swept, instead of VCM, since both input stages
PSRR, CMRR and AOL are in units of V/V
are designed the same:
ΔTA is in units of °C
VDM = 0 EQUATION 1-8:
VREF – V DD ⁄ 2
Equation 1-2 shows how VE affects VOUT. VE_LIN = V OS + -------------------------------------
CMRR
1.5.2 INPUT OFFSET COMMON MODE max Δ V E
INL CM = ------------------------------
NON-LINEARITY VIVH – V IVL
The input offset error (VE) changes non-linearly with

VCM. Figure 1-8 shows VE vs. VCM, as well as a linear 1.5.3 DIFFERENTIAL GAIN ERROR AND
fit line (VE_LIN) based on VOS and CMRR. The op amp NON-LINEARITY
is in standard conditions (ΔVOUT = 0, VDM = 0, etc.).
VCM is swept from VIVL to VIVH. The test circuit is in The differential errors are extracted from differential
Section 1.4.1 “Input Offset Test Circuit” and VE is gain measurements (see Section 1.4.2 “Differential
calculated using Equation 1-4. Gain Test Circuit”), based on Equation 1-2. These
errors are the differential gain error (gE) and the input
offset error (VE, which changes non-linearly with VDM):
VE, VE_LIN (V)
VE_LIN EQUATION 1-9:
V3 VE G DM = 1 + RF ⁄ RG
V2 VM = G DM ( 1 + g E ) ( V DM + VE )
These errors are adjusted for the expected output, then

referred back to the input, giving the differential input
V1 error (VED) as a function of VDM:
ΔVE
VCM (V) EQUATION 1-10:
VIVL VDD/2 VIVH VM
V ED = ------------ – V DM
FIGURE 1-8: Input Offset Error vs. G DM
Common Mode Input Voltage.

MCP6N11
Figure 1-9 shows VED vs. VDM, as well as a linear fit
line (VED_LIN) based on VE and gE. The op amp is in
standard conditions (ΔVOUT = 0, etc.). VDM is swept
from VDML to VDMH.
VED, VED_LIN (V)

VED_LIN
V3 VED
V2
V1
ΔVED
VDM (V)
VDML 0 VDMH
FIGURE 1-9: Differential Input Error vs.

Differential Input Voltage.
Based on the measured VED data, we obtain the
following linear fit:
EQUATION 1-11:
VED_LIN = ( 1 + g E )VE + g E V DM
Where:
V3 – V 1
g E = ----------------------------------- – 1
V DMH – V DML
V2
VE = ----------------
1 + gE
Note that the VE value measured here is not as

accurate as the one obtained in Section 1.5.1 “Input
Offset Related Errors”.
The remaining error (ΔVED) is described by the
Differential Mode Non-Linearity spec:
EQUATION 1-12:
max Δ V ED
INL DM = -----------------------------------
VDMH – V DML
Where:
Δ VED = V ED – VED_LIN

MCP6N11
NOTES:

MCP6N11
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, EN/CAL = VDD, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and GDM = GMIN; see Figure 1-6 and Figure 1-7.
2.1 DC Voltages and Currents

35% 25%
330 Samples No VOS Re-calibration
ces
330 Samples
p
es
TA = +25°C
currenc
30%
Percenttage off Occurrence
VDD = 1.8V and 5.5V 20% GMIN = 1 to 10

RTO VDD = 5.5V
25% RTO
entage of Occ
15%
20% GMIN = 1
GMIN = 2 to 10
15% 10%
10%
Perce
5%
5%
P
0%
0
100
200
300
400
500
600
-600
-500
400
-300
200
-100
0%
4
-4
-2
-2.0
0
-1.6
6
-1.2
2
-0.8
8
-0.4
4
0.0
0
0.4
4
0.8
8
1.2
2
1.6
6
2.0
0
Normalized Input Offset Voltage Drift;

Normalized Input Offset Voltage; GMINVOS (mV) GMIN(VOS/TA) (μV/°C)
FIGURE 2-1: Normalized Input Offset FIGURE 2-3: Normalized Input Offset
Voltage, with GMIN = 1 to 10. Voltage Drift, with GMIN = 1 to 10.
14% 18%
330 Samples No VOS Re-calibration
ces
GMIN = 100 16% 330 Samples

p
tage off Occurrences
currenc
12% TA = +25°C GMIN = 100

VDD = 1.8V and 5.5V
14%
VDD = 5.5V
10% RTO 12% RTO
entage of Occ
10%
8%
8%
6% 6%
4%
Perce
Percent
4%
2%
2% 0%
P
1200
1000
-800
-600
-400
-200
0
200
400
600
800
1000
1200
0%
-1
-1
1
1
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
18
-18
-16
-14
-12
-10
Normalized Input Offset Voltage Drift;

Normalized Input Offset Voltage; GMINVOS (mV) GMIN(VOS/TA) (μV/°C)
Voltage, with GMIN = 100. Voltage Drift, with GMIN = 100.

MCP6N11
2.5 10
Representative Part
d Input Offset Voltage;

2.0 8 VCM = VDD

GMIN = 100
1.5 6 RTO
1.0 4
GMINVOS (mV)
GMINVOS (mV)
0.5 2
0.0 0
-0.5 -2
-40°C
Normalized
Normalized
-1.0 +25°C -4
+85°C Representative Part -40°C
-1.5 +125°C VCM = VSS
-6 +25°C
-2.0 GMIN = 1 to 10 -8 +85°C
RTO +125°C
-2.5 -10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Power Supply Voltage Power Supply Voltage
Voltage vs. Power Supply Voltage, with Voltage vs. Power Supply Voltage, with
VCM = 0V and GMIN = 1 to 10. VCM = VDD and GMIN = 100.
25 2.0
age;
Representative Part

20 GMIN = 1 to 10
1.5
et Volta
15 RTO
VDD = 1.8V
1.0
10
d Inputt Offse
GMINVOS (mV)
5 GMINVOS (mV) 0.5

VDD = 5.5V
0 0.0
-5
-0.5
malized
Normalized
-10
-40°C Representative Part -1.0
-15 25°C VCM = VSS
Norm
85°C GMIN = 100

-20 125°C -1.5
RTO
-25 -2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage Output Voltage (V)
Voltage vs. Power Supply Voltage, with Voltage vs. Output Voltage, with GMIN = 1 to 10.
VCM = 0V and GMIN = 100.
1.2 6
Representative Part Representative Part
1.0 VCM = VDD

5 GMIN = 100
0.8 GMIN = 1 to 10 4 RTO
RTO VDD = 1.8V
0.6 3
0.4 -40°C 2
GMINVOS (mV)
GMINVOS (mV)
+25°C
0.2 +85°C
1
VDD = 5.5V
0.0 +125°C 0
-0.2 -1
Normalized
Normalized
-0 4
-0.4 2
-2
-0.6 -3
-0.8 -4
-1.0 -5
-1.2 -6
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage Output Voltage (V)
Voltage vs. Power Supply Voltage, with Voltage vs. Output Voltage, with GMIN = 100.
VCM = VDD and GMIN = 1 to 10.

MCP6N11
0.5 2.0

1 Wafer Lot VDD = 5.5V
om
0.4 VIVH – VDD Representative Part

Headroo
1.5
GMIN = 1 to 10
0.3 RTO
1.0
0.2
ange H
GMINVOS (mV)
0.1 0.5
VDD = 1.8V
V)
Input Volttage Ra
00
0.0 0.0
(V
VDD = 5.5V
-0.1 -0.5 +125°C
Normalized
02
-0.2 +85
+85°C
-1.0 +25°C
-0.3 -40°C
-0.4 VIVL – VSS -1.5
-0.5 -2.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C) Input Common Mode Voltage (V)
FIGURE 2-11: Input Common Mode FIGURE 2-14: Normalized Input Offset
Voltage Headroom vs. Ambient Temperature. Voltage vs. Common Mode Voltage, with
VDD = 5.5V and GMIN = 1 to 10.
2.0 15
VDD = 1.8V

VDD = 5.5V
1.5 GMIN = 1 to 10 10 GMIN = 100
RTO RTO
1.0
5
GMINVOS (mV)
GMINVOS (mV)
0.5
0.0 0
-0.5
Normalized
Normalized
-5
+125°C +125°C
-1.0 +85°C
+85°C
+25°C -10 +25°C
-1.5 -40°C -40°C
-2.0 -15
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-0.5 0.0 0.5 1.0 1.5 2.0 2.5
Input Common Mode Voltage (V) Input Common Mode Voltage (V)
Voltage vs. Common Mode Voltage, with Voltage vs. Common Mode Voltage, with
VDD = 1.8V and GMIN = 1 to 10. VDD = 5.5V and GMIN = 100.
15 110
VDD = 1.8V
CMRR / GMIN, VDD = 1.8V: CMRR / GMIN, VDD = 5.5V:

B)
Representative Part 105

SRR / GMIN (dB
GMIN = 1,
1 100 GMIN = 1 to 10
PSRR;
10 GMIN = 100 GMIN = 2 to 10 GMIN = 100

RTO 100
MRR, P
5 95
GMINVOS (mV)
90
Normalized CM
CMRR / GMIN, PS
0 85
80
Normalized
-5
+125°C 75
+85°C
-10 +25°C
70 PSRR / GMIN:
N
-40°C 65 GMIN = 1 to 10
GMIN = 100
-15 60
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 -50 -25 0 25 50 75 100 125
Input Common Mode Voltage (V) Ambient Temperature (°C)
FIGURE 2-13: Normalized Input Offset FIGURE 2-16: Normalized CMRR and
Voltage vs. Common Mode Voltage, with PSRR vs. Ambient Temperature.
VDD = 1.8V and GMIN = 100.

MCP6N11
110 5
Representative Part
ain;
Normalized Differential Input

105 4 VED = (VOUT – VREF)/GDM – VDM
oop Ga
VDD = 5.5V GMIN = 1

100 3
Errror; GMINVED (mV)

VDD = 1.8V RTO
2
Open-Lo
95
MIN (dB))
VDD = 1.8V
1
90
0
AOL / GM
d DC O
85
-1
80 VDD = 5.5V
-2
2
malized
75
-3
70 GMIN = 1 to 10
Norm
GMIN = 100 -4
65
-5
60 -5 -4 -3 -2 -1 0 1 2 3 4 5
-50 -25 0 25 50 75 100 125 Normalized Differential Input Voltage;
Ambient Temperature (°C) GMINVDM (V)
FIGURE 2-17: Normalized DC Open-Loop FIGURE 2-20: Normalized Differential Input
Gain vs. Ambient Temperature. Error vs. Differential Voltage, with GMIN = 1.
6.0 5
put
5.5 VDD = 5.5V 4 VED = (VOUT – VREF)/GDM – VDM
ized Diifferenttial Inp

5.0 3 GMIN = 2 to 100
MINVED (mV)
4.5 RTO
oltage (V)
GDM = 100 2
40
4.0 GDM = 1 1
3.5
0
Outtput Vo
30
3.0 Errror; GM
2.5 -1
VIM = -0.20V
2.0 -2
2
Normal
VIM = VDD + 0.15V

1.5 -3
1.0 -4
4
N
0.5
-5
0.0
-5 -4 -3 -2 -1 0 1 2 3 4 5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Normalized Differential Input Voltage;

Non-inverting Input Voltage; VIP (V) GMINVDM (V)
FIGURE 2-18: The MCP6N11 Shows No FIGURE 2-21: Normalized Differential Input
Phase Reversal vs. Common Mode Voltage. Error vs. Differential Voltage, with
GMIN = 2 to 100.
4.0 5.5
1 Wafer Lot Representative Part
3.8 GMINVDMH = -GMINVDML 5.0
ut
VDD = 5.5V
V)
ormalizzed Diffferentiial Inpu
e; GMINVDMH (V
RTO VREF = (VDD – GDMVDM)/2

3.6 4.5
Outtput Voltage (V)
3.4 4.0
3.5
3.2
3.0
30
3.0
oltage Range
2.5
2.8
2.0
2.6 GMIN = 1
1.5
2.4 GMIN = 2
1.0 GMIN = 5
Vo
No
2.2 Note: For GMIN = 1, 0.5 GMIN = 10

VDMH = minimum of plot value and VDD GMIN = 100
2.0 0.0
-50 -25 0 25 50 75 100 125 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
Axis Title Differential Input Voltage (V)
FIGURE 2-19: Normalized Differential FIGURE 2-22: The MCP6N11 Shows No
Mode Voltage Range vs. Ambient Temperature. Phase Reversal vs. Differential Voltage, with
VDD = 5.5V.

MCP6N11
1.E-08
10n 2.5
VDD = 5.5V Representative Part
s, Offset Currents (nA)

2.0
s, Offset Currents (A)
VCM = VDD TA = +125°C

VDD = 5.5V
1.5
1.E-09
1n
1.0 IB
0.5
1.E-10
100p IB 0.0
IOS
-0.5
Input Bias
Input Bias
10
-1.0
1.E-11
10p
| IOS | -1.5
-2.0
1.E-12
1p -2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
25 45 65 85 105 125
Ambient Temperature (°C) Common Mode Input Voltage (V)
FIGURE 2-23: Input Bias and Offset FIGURE 2-26: Input Bias and Offset
Currents vs. Ambient Temperature, with Currents vs. Common Mode Input Voltage, with
VDD = +5.5V. TA = +125°C.
1m
1.E-03 1000
mV)
100μ
1.E-04
urrent Magnitude (A)
oom (m
10μ
1.E-05 VDD = 5.5V
VDD = 1.8V
1 8V
Headro
1μ
1.E-06
100n
1.E-07 Output Voltage H
+125°C 100
10n
1.E-08 +85°C VDD – VOH
+25°C
1n
1 E 09
1.E-09 -40 C
-40° VOL – VSS
Input Cu
100p
1.E-10
10p
1.E-11
1p
1.E-12 10
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 1 10
Input Voltage (V) Output Current Magnitude (mA)
FIGURE 2-24: Input Bias Current vs. FIGURE 2-27: Output Voltage Headroom
Input Voltage (below VSS). vs. Output Current.
100 10
Representative Part
s, Offset Currents (pA)
80 TA = +85°C 9
VDD = 5.5V
droom (mV)
60 8 VDD – VOH
40 IB 7
VDD = 5.5V
20 6
0
ut Head
5
IOS
-20 4
Input Bias
Outpu
-40 3 VDD = 1.8V
-60 2
-80 1
VOL – VSS
-100 0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-50 -25 0 25 50 75 100 125

Common Mode Input Voltage (V) Ambient Temperature (°C)
FIGURE 2-25: Input Bias and Offset FIGURE 2-28: Output Voltage Headroom
Currents vs. Common Mode Input Voltage, with vs. Ambient Temperature.
TA = +85°C.

MCP6N11
50 1100
ort Circuit Current (mA)
40 1000
30 900 VDD = 5.5V
urrent (μA)
20 800
700
10 +125°C VDD = 1.8V
+85°C 600
0
Supply Cu
+25°C 500
-10 -40°C
400
Output Sho
-20 300
-30 200
-40 100
-50 0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Power Supply Voltage (V) Common Mode Input Voltage (V)
FIGURE 2-29: Output Short Circuit Current FIGURE 2-31: Supply Current vs. Common
vs. Power Supply Voltage. Mode Input Voltage.
1100
1000
900
Supply Current (μA)
800
700
600
+125°C
500 +85°C
400 +25°C
40
-40°C
300
200
100
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Power Supply Voltage (V)

FIGURE 2-30: Supply Current vs. Power
Supply Voltage.

MCP6N11
2.2 Frequency Response
100 0.50 150

VDD = 5.5V
90 0.45 140
WP/GMINN (MHz))
ndwith
h
80 0.40 130
argin (°)
70
ain Ban
0 35
0.35 120
CMRR (dB)
60 0.30 GMIN = 1 110

GMIN = 2 GBWP
hase Ma
Normaliized Ga
50
Productt; GBW
0 25
0.25 GMIN = 5 100
40 GMIN = 10
0.20 PM
90
GMIN = 1 GMIN = 100
Ph
30 GMIN = 2 0.15 80
GMIN = 5
20 0.10 70
GMIN = 10
N
10 GMIN = 100 0.05 60
0 0.00 50
1k
1.E+03 10k
1.E+04 100k
1.E+05 1M
1.E+06 -50 -25 0 25 50 75 100 125
Frequency (Hz) Ambient Temperature (°C)
FIGURE 2-32: CMRR vs. Frequency. FIGURE 2-35: Normalized Gain Bandwidth
Product and Phase Margin vs. Ambient
Temperature.
120 1.E+04
10k
VDD = 5.5V
nce
110
mpedan
100
90
GDM/GMIN = 10 GMIN = 1 to 10
op Outtput Im
80 1.E+03
1k
R (dB)
70
()
60
PSRR
GMIN = 100
50
sed-Loo
40 1.E+02
1 E+02
100
GMIN = 1
30 GMIN = 2
20 GMIN = 5
Clos
G = 10
10 G MIN= 100
MIN GDM/GMIN = 1
0 1.E+01
1 E+01
10
1k
1.E+03 10k
1.E+04 100k
1.E+05 1M
1.E+06 1k
1.E+03 10k
1.E+04 100k
1.E+05 1M
1.E+06 10M
1.E+07
Frequency (Hz) Frequency (Hz)
FIGURE 2-33: PSRR vs. Frequency. FIGURE 2-36: Closed-Loop Output
Impedance vs. Frequency.
120 -60 7
100 -90 GMIN = 10
op Gain
op Gain
GMIN = GDM = 1
AOL/GMIN 6 GDM = 20
Magnittude; AOL/GMINN (dB)
=2
80 -120 =5 = 50
OL/GMIN (°)
king (dB)
60 -150 5 = 10
pen-Loo
pen-Loo
= 100
40 | AOL/GMIN | -180
4
Gain Peak
20 210
-210
ase; AO
ormalizzed Op
ormalizzed Op
GMIN = 100
0 -240 3 GDM = 200
= 500
Pha
-20 GMIN = 1 -270 2

-40 GMIN = 2 -300
M
GMIN = 5
No
No
-60 GMIN = 10 -330 1

GMIN = 100
-80 -360 0
10k
1.E+4 100k
1.E+5 1M
1.E+6 10M
1.E+7 10p
1.E+1 100p
1.E+2 1n
1.E+3
Frequency (Hz) Normalized Capacitive Load; CL(GMIN/GDM) (F)
FIGURE 2-34: Normalized Open-Loop FIGURE 2-37: Gain Peaking vs.
Gain vs. Frequency. Normalized Capacitive Load.

MCP6N11
2.3 Noise
1000
1m 0.5
RTO Representative Part Analog NPBW = 0.1 Hz
age
0.4 GMIN = 1 to 10 Sample

p Rate = 4 SPS
e Volta
RTO
Noise;
Densitty; GMINeni (V//Hz)
0.3
100
100μ
02
0.2
ut Noise
alized Input N
GMINeni(tt) (mV))
GMIN = 100
0.1
10
10μ
10 00
0.0
ed Inpu
-0.1
Norma
Norrmalize
GMIN = 10 -0.2
1
1μ GMIN = 5
GMIN = 2
-0.3
GMIN = 1 -0.4
100n
0.1 -0.5
0.1 1.E+0
1.E-1 1 1.E+1
10 1.E+2
100 1.E+3
1k 1.E+4
10k 1.E+5
100k 1.E+6
1M 0 5 10 15 20 25 30 35
Frequency (Hz) Time (min)
FIGURE 2-38: Normalized Input Noise FIGURE 2-41: Normalized Input Noise
Voltage Density vs. Frequency. Voltage vs. Time, with GMIN = 1 to 10.
14 2.0
Representative Part Analog NPBW = 0.1 Hz
GMIN = 100 Sample
p Rate = 4 SPS
malized Input Noise Voltage
12 15
1.5
Noise; RTO
Hz)
1.0
10
ensity;; GMINeni (μV/
GMIN = 100
alized Input N
GMINeni(tt) (mV))
GMIN = 10 VDD = 1.8V 0.5

8 GMIN = 5 VDD = 5.5V
GMIN = 2 00
0.0
GMIN = 1
6
-0.5
Norma
4
-1.0
De
2
Norm
f = 100 Hz -1.5
RTO
0 -2.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0 5 10 15 20 25 30 35
Common Mode Input Voltage (V) Time (min)
FIGURE 2-39: Normalized Input Noise FIGURE 2-42: Normalized Input Noise
Voltage Density vs. Input Common Mode Voltage vs. Time, with GMIN = 100.
Voltage, with f = 100 Hz.
4.0
malized Input Noise Voltage
35
3.5
Hz)
3.0
ensity;; GMINeni (μV/
GMIN = 100
2.5 GMIN = 10
VDD = 1.8V
VDD = 5.5V
GMIN = 5
20
2.0 GMIN = 2
GMIN = 1
1.5
1.0
De
Norm
05
0.5 f = 10 kHz
RTO
0.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
FIGURE 2-40: Normalized Input Noise

Voltage Density vs. Input Common Mode
Voltage, with f = 10 kHz.

MCP6N11
2.4 Time Response
10
VDD = 5.5V
ximum Output Voltage Swing

GDM = GMIN
mV/div))
RF + RG = 10 k
VDD = 5.5V
Voltage (10 m
VDD = 1.8V
(VP-P)
GMIN = 1 to 10 1
GMIN = 100 GMIN = 1 to 10
GMIN = 100
Output
O
Max
0
0 2 4 6 8 10 12 14 16 18 20 10k
1.E+4 100k
1.E+5 1M
1.E+6
Time (μs) Frequency (Hz)
FIGURE 2-43: Small Signal Step FIGURE 2-46: Maximum Output Voltage
Response. Swing vs. Frequency.
5.5 1000
VDD = 5.5V GDMVDM = ±1V
5.0
ge
GDM = GMIN
s)
overy; tIRC (μs
n Mode Voltag
mV/div))
4.5 RF + RG = 10 k
4.0 VDD = 5.5V

e (10 m
100
3.5 VDD = 1.8V
3.0
Voltage
ve Reco
ommon
GMIN = 1 to 10
2.5 GMIN = 100
2.0
V
10
verdriv
put Co
Output
1.5
1.0 GMIN = 100
Inp
Ov
O
GMIN = 10
0.5 GMIN = 1
0.0 1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 10 100
Time (μs) Normalized Gain; GDM/GMIN
FIGURE 2-44: Large Signal Step FIGURE 2-47: Common Mode Input
Response. Overdrive Recovery Time vs. Normalized Gain.
10 1000
age
9
s)
overy; tIRD (μs
e Volta
8
s)
7 VDD = 5.5V
al Mode
ew Ratte (V/μs
100
6
VDD = 1.8V
ve Reco
VDD = 5.5V
5 5V
erentia
5 GMIN = 1 tto 10
GMIN = 100 VDD = 1.8V
4
10
put Diffe
Sle
verdriv
3
2 GMIN = 100
Ov
Inp
1 GMIN = 10
GMIN = 1
0 1
-50 -25 0 25 50 75 100 125 1 10 100
Ambient Temperature (°C) Normalized Gain; GDM/GMIN
FIGURE 2-45: Slew Rate vs. Ambient FIGURE 2-48: Differential Input Overdrive
Temperature. Recovery Time vs. Normalized Gain.

MCP6N11
1000 4
GDM = 2GMIN VDD = 5.5V VIP
Output Overdrive Recovery;
VREF = 0.75VDD
3
ges (V)
2
Output Voltag
100 VDD = 5.5V
tOR (μs)
1 VOUT, GMIN = 1
VDD = 1.8V GMIN = 1 VOUT, GMIN = 100
GMIN = 10 0
10 -1
nput, O
GMIN = 100
-2
In
-3
VIM
1 -4
1 10 100 0 10 20 30 40 50 60 70 80 90 100
Normalized Gain; GDM/GMIN Time (μs)
FIGURE 2-49: Output Overdrive Recovery FIGURE 2-51: The MCP6N11 Shows No
Time vs. Normalized Gain. Phase Reversal vs. Differential Input Overdrive,
with VDD = 5.5V.
6
VDD = 5.5V
VCM
ut
GDMVDM = +0.1V
0.1V
put Common Mode,, Outpu
5 f = 10 kHz
4
es (V)
3
Voltage
2
V
VOUT, GMIN = 1
1 VOUT, GMIN = 100
Inp
-1
0 10 20 30 40 50 60 70 80 90 100
Time (μs)
FIGURE 2-50: The MCP6N11 Shows No
Phase Reversal vs. Common Mode Input
Overdrive, with VDD = 5.5V.

MCP6N11
2.5 Enable/Calibration and POR Responses
2.0 30
VDD = 1.8V
ms)
1.8 VL = 0V
EN/CAL, Output Voltage (V)
n Time;; tON (m
1.6 25
VDD = 5.5V
1.4
1.2 Calibration INA INA 20
turns off VDD = 1.8V
Starts turns on
1.0
EN//CAL Turn On
15
0.8
0.6 10
0.4
EN/CAL VOUT
0.2 5
0.0
-0.2 0
0 10 20 30 40 50 60 70 80 90 100 -50 -25 0 25 50 75 100 125
Time (ms) Ambient Temperature (°C)
FIGURE 2-52: EN/CAL and Output Voltage FIGURE 2-55: EN/CAL Turn On Time vs.
vs. Time, with VDD = 1.8V. Ambient Temperature.
6.0 1.8
VDD = 5.5V
e (V)
5.5 VL = 0V
VL = 0V 1.6
EN/CAL, Output Voltage (V)
Voltage
5.0
4.5 1.4
4.0 utput V 12
1.2
Calibration INA INA
3.5 Starts turns on turns off 1.0
3.0 On
er Supply, Ou
08
0.8
2.5
2.0 0.6 VDD VOUT
1.5 0.4
1.0 EN/CAL VOUT
0.2
Powe
0.5 Off Calibrating Off

0.0 0.0
-0.5 -0.2
0 10 20 30 40 50 60 70 80 90 100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Time (ms) Time (s)
FIGURE 2-53: EN/CAL and Output Voltage FIGURE 2-56: Power Supply On and Off
vs. Time, with VDD = 5.5V and Output Voltage vs. Time.
0.60 1.7 0.18

0.55
1.6 0.16
0.50
steresis (V)
POR Trip Voltages (V)
0.45 1.5 0.14

VDD = 5.5V R Hysteresis (V)
0.40 1.4 0.12
VPRH – VPRL
0.35
1.3 0.10
AL Hys
0 30
0.30
0.25 1.2 0.08
VPRH
EN/CA
0.20
0 20
POR
11
1.1 0 06
0.06
0.15 VDD = 1.8V
1.0 0.04
0.10
0.05 0.9 VPRL 0.02
0.00 0.8 0.00
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Ambient Temperature (°C) Ambient Temperature (°C)
FIGURE 2-54: EN/CAL Hysteresis vs. FIGURE 2-57: POR Trip Voltages and
Ambient Temperature. Hysteresis vs. Temperature.

MCP6N11
0.0 1.E-07
100n
EN/CAL = 0V EN/CAL = 0V
ent;
VDD = 5.5V
A)
y Curre
ge Currrent (A
-0.5 1.E-08
10n
+125°C
Supply
-1.0 1.E-09
1n
μA)
+85°C
Power S
ISS (μ
Leakag
-1.5 1.E-10
100p
utput L
Negative P
+125°C 1.E-11
-2.0 10p
Ou
+85°C
+85 C +25°C
25°C
+25°C
-40°C
-2.5 1.E-12
1p
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Power Supply Voltage (V) Output Voltage (V)
FIGURE 2-58: Quiescent Current in FIGURE 2-59: Output Leakage Current vs.
Shutdown vs. Power Supply Voltage. Output Voltage.

MCP6N11
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE

MCP6N11
Symbol Description
SOIC TDFN
1 1 VFG Feedback Input
2 2 VIM Inverting Input
3 3 VIP Non-inverting Input
4 4 VSS Negative Power Supply
5 5 VREF Reference Input
6 6 VOUT Output
7 7 VDD Positive Power Supply
8 8 EN/CAL Enable/VOS Calibrate Digital Input
— 9 EP Exposed Thermal Pad (EP); must be connected to VSS
3.1 Analog Signal Inputs 3.5 Power Supply Pins

The non-inverting and inverting inputs (VIP, and VIM) The positive power supply (VDD) is 1.8V to 5.5V higher
are high-impedance CMOS inputs with low bias than the negative power supply (VSS). For normal
currents. operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
3.2 Analog Feedback Input supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply; VDD will
The analog feedback input (VFG) is the inverting input
need bypass capacitors.
of the second input stage. The external feedback
components (RF and RG) are connected to this pin. It is
a high-impedance CMOS input with low bias current. 3.6 Digital Enable and VOS Calibration
Input
3.3 Analog Reference Input This input (EN/CAL) is a CMOS, Schmitt-triggered
The analog reference input (VREF) is the non-inverting input that controls the active, low power and VOS
input of the second input stage; it shifts VOUT to its calibration modes of operation. When this pin goes low,
desired range. The external gain resistor (RG) is the part is placed into a low power mode and the output
connected to this pin. It is a high-impedance CMOS is high-Z. When this pin goes high, the amplifier’s input
input with low bias current. offset voltage is corrected by the calibration circuitry,
then the output is re-connected to the VOUT pin, which
becomes low impedance, and the part resumes normal
3.4 Analog Output
operation.
The analog output (VOUT) is a low-impedance voltage
output. It represents the differential input voltage 3.7 Exposed Thermal Pad (EP)
(VDM = VIP – VIM), with gain GDM and is shifted by
VREF. The external feedback resistor (RF) is connected There is an internal connection between the Exposed
to this pin. Thermal Pad (EP) and the VSS pin; they must be
connected to the same potential on the Printed Circuit
Board (PCB).
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (θJA).

MCP6N11
NOTES:

MCP6N11
4.0 APPLICATIONS The input offset voltage (VOS) is corrected by the
voltage VTR. Each time a VOS Calibration event occurs,
The MCP6N11 instrumentation amplifier (INA) is VTR is updated to the best value (at that moment).
manufactured using Microchip’s state of the art CMOS These events are triggered by either powering up
process. It is low cost, low power and high speed, (monitored by the POR) or by toggling the EN/CAL pin
making it ideal for battery-powered applications. high. The current out of GM3 (I3) is constant and very
small (assumed to be zero in the following discussion).
4.1 Basic Performance The input signal is applied to GM1. Equation 4-2 shows
the relationships between the input voltages (VIP and
4.1.1 STANDARD CIRCUIT VIM) and the common mode and differential voltages
Figure 4-1 shows the standard circuit configuration for (VCM and VDM).
these INAs. When the inputs and output are in their
specified ranges, the output voltage is approximately: EQUATION 4-2:
EQUATION 4-1: V IP = VCM + V DM ⁄ 2
VOUT ≈ VREF + GDMVDM VIM = V CM – VDM ⁄ 2
Where: VCM = ( VIP + V IM ) ⁄ 2
GDM = 1 + RF / RG V DM = V IP – V IM
VDD The negative feedback loop includes GM2, RM4, RF and

U1 RG. These blocks set the DC open-loop gain (AOL) and
VIP MCP6N11 the nominal differential gain (GDM):
VOUT
EQUATION 4-3:
VIM RF
VFG A OL = G M2 R M4
G DM = 1 + R F ⁄ R G
RG
VREF AOL is very high, so I4 is very small and I1 + I2 ≈ 0. This
FIGURE 4-1: Standard Circuit. makes the differential inputs to GM1 and GM2 equal in
magnitude and opposite in polarity. Ideally, this gives:
For normal operation, keep:
• VIP, VIM, VREF and VFG between VIVL and VIVH EQUATION 4-4:
• VIP – VIM (i.e., VDM) between VDML and VDMH
( VFG – V REF ) = V DM
• VOUT between VOL and VOH
V OUT = V DM G DM + V REF
4.1.2 ARCHITECTURE
Figure 4-2 shows the block diagram for these INAs. For an ideal part, changing VCM, VSS or VDD produces
no change in VOUT. VREF shifts VOUT as needed.
The different GMIN options change GM1, GM2 and the
VOUT VDD VSS internal compensation capacitor. This results in the
VOUT RM4 performance trade-offs shown in Table 1.
RF I4
VFG
RG GM2 Σ
VREF I2 I3
VREF
I1
VIP GM3
VIP
GM1
VTR
VIM
VIM
Low Power
POR
VOS Calibration
EN/CAL
FIGURE 4-2: MCP6N11 Block Diagram.

MCP6N11
4.1.3 DC ERRORS EQUATION 4-6:
Section 1.5 “Explanation of DC Error Specs” I
defines some of the DC error specifications. These Δ V IP = – I BP R IP = ⎛⎝ – I B – -------
OS⎞
- R
2 ⎠ IP
errors are internal to the INA, and can be summarized
I
as follows: Δ V IM = – IBM R IM = ⎛⎝ – I B + ------- OS⎞
- R
2 ⎠ IM
EQUATION 4-5: Δ V IP + Δ V IM
Δ V CM = --------------------------------
-
2
VOUT = V REF + GDM ( 1 + g E ) ( V DM + Δ V ED ) R IP + R IM – I OS – R IP + R IM
+ G DM ( 1 + g E ) ( VE + Δ V E ) = – I B ⎛ -------------------------⎞ + ----------- ⎛ ----------------------------⎞
⎝ 2 ⎠ 2 ⎝ 2 ⎠
Where: Δ V DM = Δ V IP – Δ VIM
Δ VDD – Δ V SS Δ VCM Δ V REF
V E = VOS + --------------------------------- + ----------------- + ----------------- I OS
PSRR CMRR CMRR = I B ( – R IP + R IM ) – -------- ( RIP + RIM )
2
Δ V OUT Δ VOS
+ ----------------- + Δ T A ⋅ ------------- Δ V
Δ TA Δ V OUT = G DM ⎛ Δ V DM + -----------------⎞
CM
A OL
⎝ CMRR⎠
Δ V ED ≤ INLDM ( VDMH – VDML ) Where:
Δ V E ≤ INLCM ( VIVH – V IVL )
CMRR is in units of V/V
Where:
PSRR, CMRR and AOL are in units of V/V The best design results when RIP and RIM are equal
ΔTA is in units of °C and small:
The non-linearity specs (INLCM and INLDM) describe

EQUATION 4-7:
errors that are non-linear functions of VCM and VDM, Δ V OUT ≈ G DM Δ V DM
respectively. They give the maximum excursion from ≈ G DM ( ± 2I B εRTOL – I OS )R IP
linear response over the entire common mode and
differential ranges. Where:
The input bias current and offset current specs (IB and RIP = RIM
IOS), together with a circuit’s external input resistances, εRTOL = tolerance of RIP and RIM
give an additional DC error. Figure 4-3 shows the
resistors that set the DC bias point. The resistors at the feedback input (RR, RF and RG)
and its input bias currents (IBR and IBF) give the
VDD following changes in the INA’s bias voltages:
IBP U1
RIP
VIP MCP6N11 EQUATION 4-8:
VOUT
I OS2
VIM IBF RF ΔV REF = – I BR R R = ⎛ – IB2 – ----------⎞ R R
⎝ 2 ⎠
IBM RIM ΔVFG ≈ ΔV REF, due to high AOL
VFG
IOS2
RR IBR RG ΔV OUT ≈ I B2 ( R F – G DM R R ) + ---------- ( RF + G DM R R )
2
VREF Where:
IB2 meets the IB spec, but is not equal to IB
FIGURE 4-3: DC Bias Resistors.
IOS2 meets the IOS spec, but is not equal to IOS
The resistors at the main input (RIP and RIM) and its
input bias currents (IBP and IBM) give the following
changes in the INA’s bias voltages: The best design results when GDMRR and RF are equal
and small:
EQUATION 4-9:
ΔV OUT ≈ ( ± ( 2I B2 εRTOL + I OS2 ) )RF
Where:
GDMRR = RF
εRTOL = tolerance of RR, RF and RG

MCP6N11
4.1.4 AC PERFORMANCE 4.2 Functional Blocks
The bandwidth of these amplifiers depends on GDM
and GMIN: 4.2.1 RAIL-TO-RAIL INPUTS
Each input stage uses one PMOS differential pair at the
EQUATION 4-10: input. The output of each differential pair is processed
using current mode circuitry. The inputs show no
f GBWP
f BW ≈ --------------- crossover distortion vs. common mode voltage.
G DM
With this topology, the inputs (VIP and VIM) operate
≈ ( 0.50 MHz ) ( G MIN ⁄ G DM ), GMIN = 1, …, 10 normally down to VSS – 0.2V and up to VDD + 0.15V at
≈ ( 0.35 MHz ) ( G MIN ⁄ G DM ), GMIN = 100 room temperature (see Figure 2-11). The input offset
Where: voltage (VOS) is measured at VCM = VSS – 0.2V and
VDD + 0.15V (at +25°C), to ensure proper operation.
fBW = -3 dB bandwidth
fGBWP = Gain bandwidth product 4.2.1.1 Phase Reversal
The input devices are designed to not exhibit phase
The bandwidth at the maximum output swing is called inversion when the input pins exceed the supply
the Full Power Bandwidth (fFPBW). It is limited by the voltages. Figures 2-18 and 2-50 show an input voltage
Slew Rate (SR) for many amplifiers, but is close to fBW exceeding both supplies with no phase inversion.
for these parts:
The input devices also do not exhibit phase inversion
when the differential input voltage exceeds its limits;
EQUATION 4-11:
see Figures 2-22 and 2-51.
SR
f FPBW ≈ ---------- 4.2.1.2 Input Voltage Limits
π VO
≈ fBW , for these parts In order to prevent damage and/or improper operation
Where: of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1 “Absolute Maximum
VO = Maximum output voltage swing
Ratings †”). This requirement is independent of the
≈ VOH – VOL current limits discussed later on.
The ESD protection on the inputs can be depicted as
CMRR is constant from DC to about 1 kHz. shown in Figure 4-4. This structure was chosen to
protect the input transistors against many (but not all)
4.1.5 NOISE PERFORMANCE overvoltage conditions, and to minimize input bias
As shown in Figures 2-41 and 2-42, the 1/f noise current (IB).
causes an apparent wander in the DC output voltage.
Changing the measurement time or bandwidth has little
effect on this noise. Bond
VDD
We recommend re-calibrating VOS periodically, to Pad
reduce 1/f noise wander. For example, VOS could be
re-calibrated at least once every 15 minutes; more
often when temperature or VDD change significantly. VIP Bond Input Bond V
IM
Pad Stage Pad
of
INA Input
VSS Bond
Pad
FIGURE 4-4: Simplified Analog Input ESD

Structures.

MCP6N11
The input ESD diodes clamp the inputs when they try It is also possible to connect the diodes to the left of the
to go more than one diode drop below VSS. They also resistor R1 and R2. In this case, the currents through
clamp any voltages that go too far above VDD; their the diodes D1 and D2 need to be limited by some other
breakdown voltage is high enough to allow normal mechanism. The resistors then serve as in-rush current
operation, but not low enough to protect against slow limiters; the DC current into the input pins (VIP and VIM)
overvoltage (beyond VDD) events. Very fast ESD should be very small.
events (that meet the spec) are limited so that damage A significant amount of current can flow out of the
does not occur. inputs (through the ESD diodes) when the common
In some applications, it may be necessary to prevent mode voltage (VCM) is below ground (VSS); see
excessive voltages from reaching the op amp inputs. Figure 2-25.
Figure 4-5 shows one approach to protecting these
inputs. D1 and D2 may be small signal silicon diodes, 4.2.1.4 Input Voltage Ranges
Schottky diodes for lower clamping voltages or diode- Figure 4-7 shows possible input voltage values
connected FETs for low leakage. (VSS = 0V). Lines with a slope of +1 have constant VDM
(e.g., the VDM = 0 line). Lines with a slope of -1 have
VDD constant VCM (e.g., the VCM = VDD/2 line).
For normal operation, VIP and VIM must be kept within
U1 the region surrounded by the thick blue lines. The
D1
MCP6N11 horizontal and vertical blue lines show the limits on the
V1 individual inputs. The blue lines with a slope of +1 show
D2 the limits on VDM; the larger GMIN is, the closer they are
to the VDM = 0 line.
V2
The input voltage range specs (VIVL and VIVH) change
FIGURE 4-5: Protecting the Analog Inputs with the supply voltages (VSS and VDD, respectively).
The differential input range specs (VDML and VDMH)
Against High Voltages.
change with minimum gain (GMIN). Temperature also
4.2.1.3 Input Current Limits affects these specs.
In order to prevent damage and/or improper operation To take full advantage of VDML and VDMH, set VREF
of these amplifiers, the circuit must limit the currents (see Figure 1-6 and Figure 1-7) so that the output
into the input pins (see Section 1.1 “Absolute Maxi- (VOUT) is centered between the supplies (VSS and
mum Ratings †”). This requirement is independent of VDD).
the voltage limits previously discussed.
Figure 4-6 shows one approach to protecting these VIP
inputs. The resistors R1 and R2 limit the possible VIVH
current in or out of the input pins (and into D1 and D2). VDD
The diode currents will dump onto VDD.
H
M
D
V
=
DM
VDD
V
VC
M
=
U1
VD
D1
D
/2
MCP6N11
0
V1
M
=
R1
H
D
D2
DM
V
V
=
V2 VIM
M
D
V
R2 0
VIVL
VSS – min(V1, V2)
VIVL
0
VDD
VIVH
min(R1, R2) >

2 mA
max(V1, V2) – VDD
min(R1, R2) > FIGURE 4-7: Input Voltage Ranges.
2 mA
FIGURE 4-6: Protecting the Analog Inputs
Against High Currents.

MCP6N11
4.2.2 ENABLE/VOS CALIBRATION 4.3 Applications Tips
(EN/CAL)
4.3.1 MINIMUM STABLE GAIN
These parts have a Normal mode, a Low Power mode
and a VOS Calibration mode. There are different options for different Minimum Stable
Gains (1, 2, 5, 10 and 100 V/V; see Table 1-1). The
When the EN/CAL pin is high and the internal POR
differential gain (GDM) needs to be greater than or
(with delay) indicates that power is good, the part
equal to GMIN in order to maintain stability.
operates in its Normal mode.
Picking a part with higher GMIN has the advantages of
When the EN/CAL pin is low, the part operates in its
lower Input Noise Voltage Density (eni), lower Input
Low Power mode. The quiescent current (at VSS) drops
Offset Voltage (VOS) and increased Gain Bandwidth
to -2.5 µA (typical), the amplifier output is put into a
Product (GBWP); see Table 1. The Differential Input
high-impedance state. Signals at the input pins can
Voltage Range (VDMR) is lower for higher GMIN, but the
feed through to the output pin.
output voltage range would limit VDMR anyway, when
When the EN/CAL pin goes high and the internal POR GDM ≥ 2.
(with delay) indicates that power is good, the amplifier
internally corrects its input offset voltage (VOS) with the 4.3.2 CAPACITIVE LOADS
internal common mode voltage at mid-supply (VDD/2)
Driving large capacitive loads can cause stability
and the output tri-stated (after tOFF). Once VOS Calibra-
problems for amplifiers. As the load capacitance
tion is completed, the amplifier is enabled and normal
increases, the feedback loop’s phase margin
operation resumes.
decreases, and the closed-loop bandwidth is reduced.
The EN/CAL pin does not operate normally when left This produces gain peaking in the frequency response,
floating. Either drive it with a logic output, or tie it high with overshoot and ringing in the step response. Lower
so that the part is always on. gains (GDM) exhibit greater sensitivity to capacitive
loads.
4.2.3 POR WITH DELAY
When driving large capacitive loads with these
The internal POR makes sure that the input offset instrumentation amps (e.g., > 100 pF), a small series
voltage (VOS) is calibrated whenever the supply resistor at the output (RISO in Figure 4-8) improves the
voltage goes from low voltage (< VPRL) to high voltage feedback loop’s phase margin (stability) by making the
(> VPRH). This prevents corruption of the VOS trim reg- output load resistive at higher frequencies. The
isters after a low-power event. bandwidth will be generally lower than the bandwidth
After the POR goes high, the internal circuitry adds a with no capacitive load.
fixed delay (tPLH), before telling the VOS Calibration
circuitry (see Figure 4-2) to start. If the EN/CAL pin is VDD U1
toggled during this time, the fixed delay is restarted
MCP6N11
(takes an additional time tPLH). V1 RISO
VOUT
4.2.4 PARITY DETECTOR
V2 RF CL
A parity error detector monitors the memory contents VFG
for any corruption. In the rare event that a parity error is
detected (e.g., corruption from an alpha particle), a
RG
POR event is automatically triggered. This will cause
the input offset voltage to be re-corrected, and the op VREF
amp will not return to normal operation for a period of
time (the POR turn on time, tPLH). FIGURE 4-8: Output Resistor, RISO
stabilizes large capacitive loads.
4.2.5 RAIL-TO-RAIL OUTPUT Figure 4-9 gives recommended RISO values for
The Minimum Output Voltage (VOL) and Maximum different capacitive loads and gains. The x-axis is the
Output Voltage (VOH) specs describe the widest output normalized load capacitance (CL GMIN/GDM), where
swing that can be achieved under the specified load GDM is the circuit’s differential gain (1 + RF / RG) and
conditions. GMIN is the minimum stable gain.
The output can also be limited when VIP or VIM exceeds
VIVL or VIVH, or when VDM exceeds VDML or VDMH.

MCP6N11
In this data sheet, RF + RG = 10 kΩ for most gains (0Ω
1.E+04
10k for GDM = 1); see Table 1-6. This choice gives good
Phase Margin. In general, RF (Figure 4-10) needs to
ommended RISO ()
meet the following limits to maintain stability:
1.E+03
1k EQUATION 4-12:
For GDM = 1:
Reco
GMIN = 1 to 10
RF = 0
GMIN = 100
1.E+02
100
100p
1.E-10 1n
1.E-09 10n
1.E-08 100n
1.E-07 1μ
1.E-06
For GDM > 1:
Normalized Load Capacitance; 2
CL GMIN/GDM (F) α G DM
R F < ------------------------------
FIGURE 4-9: Recommended RISO Values 2 π f GBWP C G
for Capacitive Loads. Where:
After selecting RISO for your circuit, double check the α ≤ 0.25
resulting frequency response peaking and step GDM ≥ GMIN
response overshoot on the bench. Modify RISO’s value
until the response is reasonable. fGBWP = Gain Bandwidth Product
CG = CDM + CCM + (PCB stray capacitance)
4.3.3 GAIN RESISTORS
Figure 4-10 shows a simple gain circuit with the INA’s 4.3.4 SUPPLY BYPASS
input capacitances at the feedback inputs (VREF and
VFG). These capacitances interact with RG and RF to With these INAs, the power supply pin (VDD for single
modify the gain at high frequencies. The equivalent supply) should have a local bypass capacitor (i.e.,
capacitance acting in parallel to RG is CG = CDM + CCM 0.01 µF to 0.1 µF) within 2 mm for good high frequency
plus any board capacitance in parallel to RG. CG will performance. Surface mount, multilayer ceramic
cause an increase in GDM at high frequencies, which capacitors, or their equivalent, should be used.
reduces the phase margin of the feedback loop (i.e., These INAs require a bulk capacitor (i.e., 1.0 µF or
reduce the feedback loop's stability). larger) within 100 mm, to provide large, slow currents.
This bulk capacitor can be shared with other nearby
analog parts as long as crosstalk through the supplies
VDD
U1 does not prove to be a problem.
V1 MCP6N11
VOUT
V2 RF
VFG
CCM
CCM CDM RG
VREF
FIGURE 4-10: Simple Gain Circuit with

Parasitic Capacitances.

MCP6N11
4.4 Typical Applications 4.4.3 HIGH SIDE CURRENT DETECTOR
Figure 4-13 shows the MCP6N11 INA used as to detect
4.4.1 HIGH INPUT IMPEDANCE and amplify the high side current in a battery powered
DIFFERENCE AMPLIFIER design. The INA gain is set at 21 V/V, so VOUT changes
Figure 4-11 shows the MCP6N11 used as a difference 210 mV for every 1 mA of IDD current. The best GMIN
amplifier. The inputs are high impedance and give good option to pick would be a gain of 10 (MCP6N11-010).
CMRR performance.
VBAT
VDD U1 10 Ω IDD +1.8V
VDD to
MCP6N11 U1 +5.5V
VIP
VOUT MCP6N11
VOUT
VIM RF RF
VFG
VFG 200 kΩ
RG RG
VREF 10 kΩ
VREF
FIGURE 4-11: Difference Amplifier.
(VBAT – VDD)
4.4.2 DIFFERENCE AMPLIFIER FOR IDD =
(10 Ω)
VERY LARGE COMMON MODE (VOUT – VREF)
SIGNALS =
(10 Ω) (21.0 V/V)
Figure 4-12 shows the MCP6N11 INA used as a
difference amplifier for signals with a very large FIGURE 4-13: High Side Current Detector.
common mode component. The input resistor dividers
(R1 and R2) ensure that the voltages at the INA’s inputs 4.4.4 WHEATSTONE BRIDGE
are within their range of normal operation. The Figure 4-14 shows the MCP6N11 single
capacitors C1, with the parasitic capacitances C2 (the instrumentation amp used to condition the signal from
resistors’ parasitic capacitance plus the INA’s input a Wheatstone bridge (e.g., strain gage). The overall
common mode capacitance, CCM), set the same INA gain is set at 201 V/V. The best GMIN option to pick,
division ratio, so that high-frequency signals (e.g., a for this gain, is 100 V/V (MCP6N11-100).
step in voltage) have the same gain. Select the INA
gain to compensate for R1 and R2’s attenuation. Select
R1 and R2’s tolerances for good CMRR. VDD
RW1 RW2 U1
R1 R2
V1 MCP6N11
C1 C2 RW2 RW1 VOUT

RF
VDD U
1 VFG 200 kΩ
MCP6N11
RG
VOUT
1 kΩ
RF VREF
VFG
FIGURE 4-14: Wheatstone Bridge
C1 C2 RG Amplifier.
V2
VREF
R1 R2
FIGURE 4-12: Difference Amplifier with

Very Large Common Mode Component.

MCP6N11
NOTES:

MCP6N11
5.0 DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP6N11 instrumentation amplifiers.
5.1 Microchip Advanced Part Selector

(MAPS)
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design
requirement. Available at no cost from the Microchip
website at www.microchip.com/maps, the MAPS is an
overall selection tool for Microchip’s product portfolio
that includes Analog, Memory, MCUs and DSCs. Using
this tool, a customer can define a filter to sort features
for a parametric search of devices and export
side-by-side technical comparison reports. Helpful links
are also provided for Data sheets, Purchase and
Sampling of Microchip parts.
5.2 Analog Demonstration Board

Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help customers achieve faster time
to market. For a complete listing of these boards
and their corresponding user’s guides and technical
information, visit the Microchip web site at
www.microchip.com/analog tools.
5.3 Application Notes

The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
reference resources.
• AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
• AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
• AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
Some of these application notes, and others, are listed
in the design guide:
• “Signal Chain Design Guide”, DS21825

MCP6N11
NOTES:

MCP6N11
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
8-Lead SOIC (150 mil) (MCP6N11) Example
6N11001E
SN^^
e3 1121
256
NNN
Note: The example is for a

MCP6N11-001 part.
8-Lead TDFN (2×3) (MCP6N11) Example
Device Code
MCP6N11-001 AAQ
MCP6N11-002 AAR AAQ
MCP6N11-005 AAS 121
25
MCP6N11-010 AAT
MCP6N11-100 AAU
Note: Applies to 8-Lead 2x3 TDFN
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

MCP6N11
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

MCP6N11

MCP6N11

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MCP6N11

MCP6N11

MCP6N11

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MCP6N11
NOTES:

MCP6N11
APPENDIX A: REVISION HISTORY
Revision A (October 2011)

• Original Release of this Document.

MCP6N11
NOTES:

MCP6N11
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. –X X /XX Examples:

Device Gain Temperature Package a) MCP6N11T-001E/MNY: Tape and Reel,
Option Range Minimum gain = 1,
Extended temperature,
8LD 2×3 TDFN.
b) MCP6N11-002E/SN: Minimum gain = 2,
Device: MCP6N11 Single Instrumentation Amplifier
Extended temperature,
MCP6N11T Single Instrumentation Amplifier
8LD SOIC.
(Tape and Reel)
Gain Option: 001 = Minimum gain of 1 V/V

002 = Minimum gain of 2 V/V
Temperature Range: E = -40°C to +125°C
Package: MNY = 2×3 TDFN, 8-lead *

SN = Plastic SOIC (150mil Body), 8-lead
* Y = nickel palladium gold manufacturing designator. Only
available on the TDFN package.

MCP6N11
NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PIC32 logo, rfPIC and UNI/O are registered trademarks of
MICROCHIP MAKES NO REPRESENTATIONS OR
Microchip Technology Incorporated in the U.S.A. and other
WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control
QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip
FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, chipKIT,
devices in life support and/or safety applications is entirely at chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
hold harmless Microchip from any and all damages, claims, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
suits, or expenses resulting from such use. No licenses are Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
conveyed, implicitly or otherwise, under any Microchip MPLINK, mTouch, Omniscient Code Generation, PICC,
intellectual property rights. PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-685-3
Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

Worldwide Sales and Service
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MCP6N11

500 kHz, 800 µA Instrumentation Amplifier

Typical Applications Typical Application Circuit

© 2011 Microchip Technology Inc. DS25073A-page 1

TABLE 1: KEY DIFFERENTIATING SPECIFICATIONS

DS25073A-page 2 © 2011 Microchip Technology Inc.

TABLE 1-1: DC ELECTRICAL SPECIFICATIONS

© 2011 Microchip Technology Inc. DS25073A-page 3

DS25073A-page 4 © 2011 Microchip Technology Inc.

© 2011 Microchip Technology Inc. DS25073A-page 5

DS25073A-page 6 © 2011 Microchip Technology Inc.

EN/CAL Low Specifications

TABLE 1-4: TEMPERATURE SPECIFICATIONS

© 2011 Microchip Technology Inc. DS25073A-page 7

FIGURE 1-1: Common Mode Input

FIGURE 1-2: Differential Mode Input

FIGURE 1-3: Output Overdrive Recovery

FIGURE 1-4: POR Timing Diagram.

DS25073A-page 8 © 2011 Microchip Technology Inc.

VDD VCM + VDM/2 2.2 µF

© 2011 Microchip Technology Inc. DS25073A-page 9

The input offset error (VE) changes non-linearly with

These errors are adjusted for the expected output, then

DS25073A-page 10 © 2011 Microchip Technology Inc.

VED, VED_LIN (V)

FIGURE 1-9: Differential Input Error vs.

Note that the VE value measured here is not as

© 2011 Microchip Technology Inc. DS25073A-page 11

DS25073A-page 12 © 2011 Microchip Technology Inc.

2.1 DC Voltages and Currents

VDD = 1.8V and 5.5V 20% GMIN = 1 to 10

Normalized Input Offset Voltage Drift;

GMIN = 100 16% 330 Samples

12% TA = +25°C GMIN = 100

Normalized Input Offset Voltage Drift;

© 2011 Microchip Technology Inc. DS25073A-page 13

d Input Offset Voltage;

2.0 8 VCM = VDD

d Input Offset Voltage;

5 GMINVOS (mV) 0.5

85°C GMIN = 100

d Input Offset Voltage;

1.0 VCM = VDD

DS25073A-page 14 © 2011 Microchip Technology Inc.

d Input Offset Voltage;

0.4 VIVH – VDD Representative Part

d Input Offset Voltage;

CMRR / GMIN, VDD = 1.8V: CMRR / GMIN, VDD = 5.5V:

Representative Part 105

10 GMIN = 100 GMIN = 2 to 10 GMIN = 100

© 2011 Microchip Technology Inc. DS25073A-page 15

Normalized Differential Input

VDD = 5.5V GMIN = 1

Errror; GMINVED (mV)

ized Diifferenttial Inp

VIM = VDD + 0.15V

Normalized Differential Input Voltage;

RTO VREF = (VDD – GDMVDM)/2

2.2 Note: For GMIN = 1, 0.5 GMIN = 10

DS25073A-page 16 © 2011 Microchip Technology Inc.

s, Offset Currents (nA)

VCM = VDD TA = +125°C

-40 3 VDD = 1.8V