Microprocessors and Microsystems 79 (2020) 103324

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Microprocessors and Microsystems

journal homepage: www.elsevier.com/locate/micpro

Speed optimal FPGA implementation of the encryption algorithms for

telecom applications
Prateek Sikka a, *, Abhijit R Asati b, Chandra Shekhar c
a
Department of EEE, Birla Institute of Technology and Science, Pilani, Rajasthan, India
b
Department of EEE, Birla Institute of Technology and Science, Pilani, Rajasthan, India
c
Department of EEE, Birla Institute of Technology and Science, Vidya Vihar Campus, Pilani, Rajasthan, India

A R T I C L E I N F O A B S T R A C T

Keywords: The last two decades have seen a revolution in telecom technology with the evolution of three wireless mobile
Advanced encryption standard communication standards, namely, GPRS to 3G, 3G to 4G, and 4G to 5G. 5G offers faster download speeds and
Field programmable gate array enables high connectivity between devices such as mobile phones, displays, smart homes, and smart cars because
Register transfer level
of its high reliability and high bandwidths (up to 10 Gbps). However, at the same time, data and personal in­
Telecom
Xilinx high-level synthesis
formation are also more susceptible to theft because of the high connectivity. Such threats can be addressed using
electronic data encryption using the advanced encryption standard (AES). Because of their reconfigurable and
parallel architectures, Field-Programmable Gate Arrays (FPGAs) are getting popular in VLSI design flows to
enable the pre-silicon validation of designs faster data rates in real-time. FPGAs also serve as platforms for
software development in the pre-silicon environment owing to their faster speeds. The design community is also
heavily relying on High-Level Synthesis (HLS) tools in VLSI design flows. HLS platforms enable the new designs
to improve the process with sustained authentication between two analytical selections from conventional
functional specifications. We propose a high-throughput FPGA implementation based on high-level Synthesis for
the AES algorithm. The implementation uses a 128-bit key and is highly suited for telecom applications such as
5G. Researchers have developed and tested the setup and then used the Vivado HLS tool to evaluate various HLS
guidelines as per the implementation. The generated Verilog RTL was verified and implemented on Xilinx Kintex
7 and Virtex 6 FPGAs. Since using the same resources, we have seen significant results than existing methods
achieved by individual investigators. We have also verified the design for functionality by checking the
ciphertext output from our design against a reference design output for the same input plaintext.

1. Introduction
The consumer industry now widely uses communication technology
to connect devices without wires, namely, wireless communication [1].
Mobile technology centered on wireless communication. As mobile
users’ numbers increased significantly worldwide, additional mobile
commerce applications and wireless information services are required
[2]. The transformation of cellular networks from 2G,3G, and 4G, 5G in
the last 2 centuries, was considerable [3]. The physical, the open
transport protocol, the network, and the application layers [4] are 5G. It
has much better reliability and higher bandwidth support than preced­
ing technologies [5]. However, higher connectivity has multiple draw­
backs, like more chances of data theft. This is because we leave more
room for hackers to penetrate the network of connected devices. For
example, online transactions over the web (where multiple devices are
connected) are more susceptible to financial scams than cash payments
at merchants(where only two parties are involved). An interconnected
5G with analytics and control planes separated, and the virtualization of
necessary communication protocols improves significantly added in the
caused by malicious performers, improving reliability and attempting to
protect privacy [6].
Cryptography is one of the methods for ensuring that message is
encrypted, and the reception of the message is done only by the intended
receiver. The AES [7] is one such algorithm for the key encoding process.
AES algorithm is a commonly used algorithm for encryption in different
applications, which include IEEE standards like 802.11i [8], 802.15.4
[9], and ZigBee [10].
Software or CPU based implementations of this algorithm do not

* Corresponding author.
E-mail address: prateeksikka@gmail.com (P. Sikka).

https://doi.org/10.1016/j.micpro.2020.103324
Received 25 August 2020; Received in revised form 1 October 2020; Accepted 7 October 2020
Available online 10 October 2020
0141-9331/© 2020 Elsevier B.V. All rights reserved.
P. Sikka et al.
offer sufficiently high performance. For example, running on a 1.2 GHz,
one can achieve a maximum packet delivery of 400 Mbit/s. The
maximum demonstrated throughput on the fastest 64-bit Athlon pro­
cessor is 1.6 Gbit/s [11]. Due to their parallel architectures (hence high
speed), FPGAs are getting popular for pre-silicon prototyping algorithms
like the AES.
In the recent past, multiple FPGA hardware optimal implementations
of the AES algorithms have been proposed. In 2015, an ultrahigh
throughput implementation of a fully pipelined AES algorithm was
proposed by Soltani and Sharifian. Their implementation is based on the
counter (CTR) mode of the operation [12]. Their implementation tar­
geted for Virtex-6 Xilinx FPGA. In 2018, Zhang et al. [13] proposed
another architecture for AES, which offered increased throughput due to
an inner and outer pipelined architecture. This implementation
demonstrated throughput of above 60 Gbps on Xilinx Virtex-6 FPGA. In
2018, a comparison of two different encryption algorithms presented by
Smekal et al. [14]. They targeted design implementations on two FPGAs,
namely Virtex-7 and Ultrascale+. They achieved a maximum
throughput of about 50 Gbps on both targets. In 2019, a custom
encryption algorithm (AES) was implemented on the Spartan 3 E FPGA
kit by Noorbasha et al. [15]. Their implementation provided better data
security at the cost of slightly reduced throughput.
In 2019, Chen et al. proposed an encryption algorithm for pipelining
for big data applications that achieved over 30 Gbps [16].
In this research work, we proposed an HLS based implementation of
the AES algorithm. We targeted the implementation of Virtex-6 and
Kintex-7 FPGAs. The final FPGA framework was optimized using special
HLS directives. As a result, our implementation’s final throughput
numbers were better than other implementations proposed in the liter­
ature. This high throughput implementation is a particularly critical
need for applications requiring high data rates like 5G systems. Higher
throughput means higher bandwidth as one can process more data in a
finite time interval.
Moreover, when FPGAs run faster, it gets easier to develop and
validate embedded software parallel to hardware development, which is
difficult to achieve on HDL simulators due to speed issues. Section 2 of
this paper provides an overview of HLS. Section 3 explains the detailed
framework of encryption algorithms (AES in our test case). Section 4
presents the details of the implementation. Section 5 presents the
simulation, the synthesis findings, and comparative study with the lit­
erary works, accompanied by a summary in Section 6.
2. High-level synthesis
HLS tools ensure continued functional verification using the high-
level stimulus in the design cycle and enable designers and architects
to use high abstraction levels in the VLSI design process. This method is
error-immune and faster than the standard Register-Transfer Language
(RTL) coding process [17]. Digital designers and architects typically use
HLS, such as Vivado HLS [18], MATLAB HDL coder [19], and various
other tools, including open-source prototype algorithms that target
various application areas such as image processing, machine learning,
communications, and aerospace.
HLS methods also allow design and verification to use some sug­
gestions simulation tools [20]. An efficient h/w-s/w limit is attempting
to increase in most advanced software applications because of the pro­
cessors’ co-operation, memories, and customizable logic on a single
fabric. HLS bridges this gap by allowing designers and architects to
perform faster iterative experiments using C/C++. They can thus
explore a different area, speed, and power tradeoffs.
With FPGAs’ reconfigurable architectural design, algorithm blocks
from a certain amount of hardware resources have better results than the
processor systems. These blocks can be implemented on a target FPGA
by using HLS [21]. HLS gained tremendous commercial importance in
the 1990s with the improvements and wide adoption of RTL-based
synthesis tools. Major corporations, including IBM [22], Motorola
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Microprocessors and Microsystems 79 (2020) 103324
[23], Philips [24], and Siemens [25], owned many patented tools. In
recent decades, major manufacturers of Electronic Design Automation
(EDA) have completed endorsing their HLS tools. Synopsys introduced
the behavioral compiler in 1995 [26], received RTL interfaces from the
code and integrated them into downstream tools. The Catapult HLS from
Mentor Graphics [27] and Cadence Stratus HLS [28] are powerful
competitive tools. Fig. 1 shows a typical HLS design flow adopted for
VLSI chips. A high-level language like C/C++, MATLAB / Python pro­
gramming tool is accepted as an I / O and requires platform-specific
codes transformation and synthesis standardization to generate a syn­
thesizable RTL code. Different optimization directives can optionally be
applied to the high-level code to meet the design specification targets for
the area, power dissipation, and speed of operation.
3. Advanced encryption standard
In cryptographic algorithms, a chip block is a procedure to hide the
symbolic importance of a message we would like to connect. A block
cipher is a computable and deterministic function that generates n-bit
ciphertext using k-bit keys and n-bit plaintext blocks. Since it is deter­
ministic, the same output ciphertext would be generated every time the
input text and keys used are the same. One of the symmetric block cipher
encryption algorithms is the AES. AES receives a 128-bit input for each
block along with a key size are 128, 192, 256 bits and consequently
generates a ciphertext after nearly encryption rounds (Nr), which is the
key size for function. The most commonly used key size is 128 bits,
which corresponds to 10 rounds of the block size. The ciphertext is the
output scrambled version of the input plaintext.
AES encryption rounds(iterations) are performed in a Galois Field
(GF) [29] of 28, which is a finite field. In a GF, mathematical compu­
tations like addition and subtraction can be performed smoothly as data
is presented in vectors.
AES is an iterative algorithm that operates on a square matrix of
symmetric size, also known as a state. The state arranges the message’s
finite number of bytes into columns, each consisting of a fixed no. of
bytes. Once the message is set up, the functions are called on the mes­
sage. The following are the four functions that act on the state.
3.1. Byte substitution function
The byte substitution function in the AES comprises splitting the
input data into separate bytes and passing each byte through what is
known as S-Box. The S-Box uses GF (2) to start reversing computation,
and a fine conversion [30] to consider. This transformation is nonlinear
for each element, and this function introduces confusion to the input
data. Fig. 2 shows the S-Box in AES
3.2. Shift rows function
Each row in the state matrix is shifted by ensures of a linear operation
by a finite number. The I row is ‘0’; the II row has been circularly left
with one byte, the III row is circularly left with a two-byte shift, and the
IV row is circularly shifted to the left with 3 bytes. This method allows
for diffusion. Fig. 3 shows the shift rows function operating on the
cipher.
3.3. Mix column function
Just like the Shift rows function in AES, the Mix columns function
provides diffusion to the data by mixing the inputs. This operation is
performed by splitting the matrix through columns instead of rows.
Matrix multiplication is performed as per the GF 28. There is an inde­
pendent multiplication of each column, as shown in Fig. 4.
P. Sikka et al. Microprocessors and Microsystems 79 (2020) 103324

Fig. 1. High-level synthesis flow for VLSI designs.

Fig. 2. Construction of S-Box for encoding.

3.4. Add round-key 3.5. Key scheduling

Throughout this phase, the state matrix is bit-by-speed by the 16-
byte round-key (128bits) XOR (or addition to GF). This feature is
called 11 times (10 rounds plus once before the first round). Conse­
quently, 11 × 16 = 176 bytes of the key is needed. The 16 Byte Schlüssel
is continued to expand to 176 Bytes with either the important scheduling
feature.
This step derives the keys used in the algorithm from the starting
input key (16 bytes). A distinct key is generated from the previous
fundamental exploitation for each key addition, an XOR of some bits
with the last key value. So while operating on words N to M, the value
used in exclusive or is the previous word of the previous round key, i.e.,
N-1 to M-1. Fig. 5 shows the functions and steps involved in the AES
algorithm.

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P. Sikka et al.
Fig. 3. Shift rows function on block cipher.
Fig. 4. Mix column function on the block cipher.
AES supports multiple modes of operation, which differ in how the
input text is arranged into blocks and how they transform. There are 3
major modes of AES, namely counter (CTR), cipher block chaining
(CBC), electronic codebook (ECB), and cipher feedback.
ECB is the simplest of these. In ECB mode, the encryption and
decryption happen independently of other blocks. The implementation
is more straightforward in ECB mode, but one drawback is replicating
patterns avoided in CTR mode using a counter value and Initialization
Vector (IV). In CBC mode, there is no correlation between i/p and o/p,
making it legally added complicated but also more secure at the same
time. This is achieved through a pseudo-random IV application as an i/p
message to plaintext and the input variable’s derivation as output from
the previous block, hence the name chaining.
We created a 16-byte initialization vector with an unchanged nonce
with an incrementing counter value with each block encryption
completion for our proposed implementation. Because of the parallel
nature of the CTR mode, it is very commonly used in wireless network
application designs with streaming data and ciphers, hence our choice of
application in this work. Fig. 6 depicts the CTR mode of operation
4. Design methodology
To start with, we created a C++ model for the AES algorithm in CTR
mode using 10 rounds and a block length of 128 bits. The algorithm was
simulated using a C++ testbench in Vivado HLS. The input signal was
chosen to be an input text string or a stream of characters, namely,
plaintext. The output from the implementation running on the Vivado
HLS simulator was a ciphertext corresponding to plaintext at any given
point of time. Fig. 7 shows the algorithm model of the design using
floating type data types for design nodes.
Once the baseline model was created, we used Vivado HLS to create
synthesizable Verilog RTL and implemented it on the target FPGA.
Further, to optimize the operation results (throughput), we used HLS
directives offered by Vivado HLS [18], such as pipeline, unroll, and
inline-off, explained below. Please note that directives’ choice is sub­
jective, and directives that prove useful in one application may not be
valid for another application. This is based on understanding and
experience with the tool.
i The pipeline allows the concurrent execution of operations by
reducing the initiation interval for a loop or function and, hence, a
tradeoff exists between timing and area while using this directive. To
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Microprocessors and Microsystems 79 (2020) 103324
optimize this AES implementation, we applied a pipeline with an
initiation interval of two for all design loops.
ii Loop unroll the loop iterations to run parallel by creating multiple
copies of a single loop body in RTL design. This pragma helps in
increasing the throughput by making the loops either fully or
partially unrolled. For our application of AES, we used the partially
unroll directive to improve our performance with a minimal impact
on resource usage. The unroll factor employed on the code is two.
iii After we inline a function, it can no longer be represented as a
separate entity in the hierarchy. Inline functions are merged into the
calling function. These functions, therefore, cannot be shared,
increasing the area occupied on the target FPGA. We used the inline-
off directive in our application to prevent the functions from inline
on their own. This helps mitigate the effect of an area increase caused
by the loop unrolling and pipelining. Table 1 summarizes the
different directives used on different functions or loops in the design.
This proposed design and optimization method is applicable for all
HLS tools and other applications apart from AES. Further, since the RTL
code generated is optimal, the method is also applicable to all ASIC and
FPGA targets. Depending on the types of directives available in the tool
and bottlenecks identified in the application, one can optimize the
synthesis results. In the next section of the manuscript, we discuss the
gains achieved by applying each of the directives, as mentioned earlier,
on top of the base implementation.
5. Results and discussion
5.1. Verification
The findings of performance testing by C++ have been similar to the
standard and conceptual AES features for the inventors who have used
Vivado HLS. We verified the same by comparing the output from
MATLAB against the output(ciphertext) from the HLS model of the
design for the same input text. Fig. 8 shows the encryption results for the
plaintext, “HELLO WORLD THIS IS A SECRET TEXT.” The algorithm
requires the input 2 times (16 bytes per text), with a completed counter
to two (after the increment), since there are 32 characters in the input
file.
As described in Fig. 7 and implementation with the applied di­
rectives, the base implementation’s simulation results were identical.
This proves functional equivalence between high-level synthesis and
design implementation on the target FPGA. Further, the RTL functional
P. Sikka et al. Microprocessors and Microsystems 79 (2020) 103324

Fig. 5. Functional stages of AES.

simulation results (obtained from xSim, an HDL simulator integrated 5.2. FPGA synthesis
with Xilinx Vivado) were also identical to the theoretical AES output for
the same plaintext confirmed by the HLS simulation using a C++ test­ From a guideline configured Vivado HLS framework, the Verilog RTL
bench, as shown in Fig. 8. code was obtained. We implemented the same on the Kintex 7 FPGA

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P. Sikka et al. Microprocessors and Microsystems 79 (2020) 103324

Fig. 6. AES operation in CTR mode.

5.3. FPGA implementation results

The two implementations of AES, with and without using HLS di­
rectives, were created and simulation performed for functional verifi­
cation using the C++ test bench and the Verilog test bench on xSim, as
explained in Sections 5.1 and 5.2. We targeted the same generated RTL
on the Kintex-7 board as well. Tables 2 and 3 present the FPGA imple­
mentation reports from the baseline design with and without using HLS
directives, respectively. The directives applied have been discussed in
Section 4 in detail.
As shown in both Tables 2 and 3, a minimal increase in resource
usage is noticed for the design because of performance improvement
directives (tradeoff between area and performance). But the maximum
frequency of operation that directly impacts the runtime throughput is
almost doubled. Please note that the throughput increase is attributed to
faster synthesis frequency and the pipelining of different loops and
functions, as described in Section 4 (pipeline directive).

5.4. Comparison of results

We compared our implementation with other proposed imple­

mentations in literature [12–14]. Table 4 presents a comparison of re­
Fig. 7. Floating point bit width HLS model for the AES.
sults for Virtex-6 and Kintex-7 targets.
As is clear from Table 4, our proposed implementation has better
Table 1
throughput than other implementations presented in the literature with
Functions and Applied HLS Directives. no difference in functionality. The throughput for our propounded
method is roughly 8% significantly higher by Soltani et al. [12], 17%
Functions Pipeline Unroll Inline (Off)
higher to the design proposed by Zhang et al. [13], and 70% signifi­
Sub bytes Yes Yes Yes cantly higher by Chen et al. [6]. Furthermore, the improvement ach­
Shift rows Yes Yes Yes
ieved is technology independent, i.e., applies to both FPGA as well as
Mix column Yes Yes Yes
Add round KEY Yes Yes Yes ASIC targets even though we have verified and benchmarked the results
AES encrypt (top) Yes No No for two Xilinx FPGAs- Virtex 6 and Kintex 7. From the above analysis, we
L rounds (inner encrypt loop) Yes No Yes conclude that our proposed design implementation is higher in
throughput than other researchers, with a small tradeoff in resource
usage. Further, we confirmed that using these performance directives is
from Xilinx (XC7K70T-FBG676-3) using Vivado 2019.1. A non-
benign for design functionality.
synthesizable Verilog testing using the xSim simulation model also
passed out-degree substitutions for the produced RTL code. We also
6. Conclusion
implemented the generated RTL source code on Xilinx Virtex 6 device
using iSE 14.7 software. This was done to enable a direct comparison
Over the past few years, telecom standards have seen a rapid change
with some of the available literature results for Virtex 6 boards. Section
or evolution from 3G to 4G and 5G technology (fifth-generation stan­
5.4 presents a detailed comparison of the results. Even though our re­
dard). These advancements have been significantly adopted in the mo­
sults are presented for Virtex 6 and Kintex 7 FPGA, the directives help in
bile telecom industry due to improvements in their speed. For example,
optimization at the RTL level. This means the optimizations are tech­
the 5G standard offers high data rates and supports higher and better
nology independent and hence applicable to other ASIC and FPGA
connectivity between phones and other smart appliances. Since higher
targets.
connectivity comes at additional risks of data theft using phishing at­
tacks that could lead to a loss of confidential user information, data

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P. Sikka et al. Microprocessors and Microsystems 79 (2020) 103324

Fig. 8. HLS model simulation results of AES.

Table 2 Table 4
AES on XC7K70T-FBG676 (No directives). Comparison of AES synthesis.
Resource Usage Total Percentage (%) FPGA metrics Our proposed Soltani [12] Zhang [13] Chen [6]
design
LUTs 572 41,000 1.39%
LUT-RAMs 8 13,400 0.06% Max Freq(V6) 542.102 MHz 508.102 471 MHz Not
Flip-Flops 446 82,000 0.54% MHz available
BRAM 4 135 2.96% Throughput 276.5 Gbps 260.14 60.3 Gbps Not
IO 264 300 88% (V6) Gbps available
BUFG 1 32 3.13% Max freq(K7) 425 MHz Not Not 244.4 MHz
available available
Total Power = 0.114 W (Dynamic power = 0.033 W + Static Power = 0.082 W). Throughput 54.2 Gbps Not Not 31.2 Gbps
Maximum Frequency of Operation = 218.8 MHz, Throughput = 28 Gbps. (K7) available available

Table 3 silicon verification goals and help cut short the time to market for system
AES on XC7K70T-FBG676 on chip designs. The shorter time to market is even more critical for
(HLS directives applied as explained in Section 4). applications, such as telecom, where consumers typically move to a new
Resource Used Available Total usage (%) handset almost every other year. Therefore, high-throughput imple­
LUTs 749 41,000 1.83%
mentations of benchmark and popular encryption algorithms like AES
LUT-RAMs 9 13,400 0.07% on FPGAs are necessary before the research and development
Flip-Flops 866 82,000 1.00% community.
BRAM 4 135 2.96% We proposed in this work to implement HLS AES for telecommuni­
IO 264 300 88%
cations application domains. The design is based on 10 size rounds and
BUFG 1 32 3.13%
128-bit key size. To produce a direct comparison of our result obtained
Total Power = 0.124 W (Dynamic power = 0.039 W + Static Power = 0.085 W). with all those reached through other research findings, authors have
Maximum Frequency of Operation = 425 MHz, Throughput = 54.2 Gbps. configured the two FPGAs, particularly regarding Xilinx Virtex 6 and
LUTs: Lookup tables; RAMs: Random access memories; BRAM: Block RAM; IO:
Kintex 7.
Input outputs; BUFG: Global clock buffers.
We created a reference design using Vivado HLS and verified it using
the HLS tool and Verilog RTL simulation using xSim. We optimized the
encryption before transmission is becoming increasingly important, is design performance using appropriate HLS directives of pipelining, loop
achieved using standard encryption algorithms, such as AES telecom­ unrolling, and inline-off. After the directives were applied, the final
munication systems. implementation results were significantly higher throughput, with
FPGAs are furthermore getting increasingly essential in the VLSI and minimal area (resource usage) impact. We saw up to 70% improvement
validation flow of the s/w. They also offer acceleration to multiple pre-

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in the throughput compared with implementations proposed by other
researchers. Therefore, this AES implementation highly suits high-
throughput applications such as telecom, particularly 5 G. The func­
tional verification and equivalence of the generated RTL were proven
again (post directive) using xSim simulator by comparing the outputs
from our RTL implementation against the outputs from a reference
design with the same plaintext input. This proved that the HLS directives
used did not have any adverse effect on the design functionality. Further,
since the optimizations are done at RTL level itself instead of netlist (like
other synthesis optimizations), these optimizations are technology-
independent and applicable to all FPGAs.
The implementation results for our design can be further improved
using more HLS directives. However, we wish to explore them in the
future, and they do not lie in the scope of this study. In the future, we
also plan to extend the usage of HLS directives for other applications like
the signal, image processing, communication systems, etc. and under­
stand their impact on FPGA synthesis. We also plan to extend these
optimizations for ASIC synthesis flows as well.
Declaration of Competing Interest
There is ‘No Conflict of Interest’ for submitting this article in your
Journal for all authors.
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Prateek Sikka is currently pursuing his doctorate at BITS
Pilani, Rajasthan, India while working for NXP Semiconductors
in Noida, Uttar Pradesh, India. He has over 13 years of expe­
rience serving in multiple EDA and semiconductor organiza­
tions, such as STMicroelectronics,Cadence, and Mentor
Graphics in both R&D and customer facing roles. His research
areas include digital systems design and optimization, FPGA
prototyping and emulation, and high-level synthesis. He holds
five patents in the same field and has presented at multiple
conferences. He holds a Bachelor of Engineering degree from
Thapar Institute Patiala and a Master of Technology degree in
Integrated Electronics from IIT, Delhi.
Dr. Abhijit Asati is a senior member at IEEE and is currently an
associate professor in the Electronics and Electrical Engineer­
ing department at BITS, Pilani, Rajasthan, India. He completed
his doctorate in 2010, his Master of Engineering degree in 2002
from BITS Pilani, and his Bachelor of Engineering in 1996 from
Amravati University. He has taught several courses in electrical
and electronics engineering and has supervised three doctoral
and 25 bachelors’ and masters’ theses. He taught at VNIT
Nagpur from 1997 to 1999. He has contributed to over 30
journal and conference papers in the fields of microelectronics,
VLSI design, and embedded systems.
Dr. Chandra Shekhar currently serves as Professor Emeritus at
BITS, Pilani, Rajasthan, India. After attaining his PhD, he
joined the Solid State Devices Division at CEERI, Pilani in 1977
as a scientist. Having worked for IC Design related activities, he
also served as the director at CEERI, Pilani. He was awarded the
UNESCO/ROSTSCA Young Scientist Award in 1986, the CEERI
Foundation Day Merit award in 1988, the ISHEER Science
councilor Award in 2005, the Prof. L K Maheshwari Foundation
Distinguished Alumnus Award in 2010, a Doctor of Science
(honoris causa) by NIT Kurukshetra in 2012, and the IETE
Diamond Jubilee Gold Medal award in 2013.