The Analog Mixed Signal Company

Amplifier ID: 025

Name AMP-15
Description
This amplifier is designed for use in the 1st stage of an instrumentation amplifier. The primary aim in design is to achieve
low noise.

This cell uses pole splitting for compensation. Including feedback, the gain is U11. Therefore stability at unity gain is not
asked for. The internal chopper is implemented to reduce 1/f-noise, input offset voltage and voltage drift. The maximum
clock frequency for the chopper is 6kHz. The clock-glitches on the output-voltage are damped by the use of cascode
stages. Further damping could be reached by the use of a low-pass filter, but this would decrease slew rate and
maximum large signal frequency. To adapt this amplifier to other demands, scale the output stage and the Miller-cap or
change the bias currents. The results are simulated with extracted parasitics.

In the follwing table 'No Clock' means the chn- and the clp-pin of the amp are connected to VSS, the cln- and the chp-pin
are connected to VDD.

Conditions
Temperature 270C
Reference Current (Iref) 10 µA
VDD 2.5 V
VSS -2.5 V
Load 25 kOhm || 2.6 pF

Simulated Data

Parameter Symbol Unit Min Typ Max Condition

Supply Current IDD µA 155 Unity Gain, DC Sim.
Maximum Load Current 1) ILoad µA 52.7 Unity Gain, DC Sim.
2) Unity Gain, No Clock, No
Input Offset Voltage VIO
mV 0.52 Parasitics, delta L=0.1µm 2)
TK VIO 2) TK(VIO) Unity Gain, No Clock, No
µV/K 1.3 Parasitics, delta L=0.1µm 2)
Voltage Gain v Corner Simulation 3), No Clock,
dB 92.3 100 f=10Hz
Transit Frequency fT MHz 4.8 No Clock
Phasemargin Îm deg -111 No Clock
Gain @ Im=60deg 1 11.5 No Clock
Frequency @ Im=60deg f(60deg) kHz 570 No Clock
0.01% Settling Time TS Amplitude = 0.5 V,
µs 2.8 m_verst=1/11, No Clock
Amplitude = 2.5 V,
Slew Rate S
V/µs 2.8 m_verst=1/11, No Clock
Maximum Large Signal THD<2%, Amplitude =1V,
Frequency kHz 315 m_verst=1/11, No Clock
INL < 5 ppm [(Vdd-Vss)/2], No
Output Swing VOUT V -1.21 2 Clock
Common Mode Range VCM V -0.84 1.7 v > 97 dB 4), No Clock, f=10Hz

-1.56 1.74 v > 91 dB 4), No Clock, f=10Hz

Common Mode Rejection Ratio CMRR dB 15.5 fCM= 10 Hz,
51.7 fCM= 6 kHz, No Clock, VCM =0V
Power Supply Rejection Ratio PSRR dB 11.2 fPS= 10 Hz, No Clock
2.7 fPS= 6 kHz, No Clock

1) The positive load current is limited by the pmos transistor of the output stage. To get higher load currents, scale the
pmos (and nmos) transistor of the output stage.

2) The input offset voltage (VIO) and temperature coefficient (TK(VIO)) are strongly dependent on the mismatch of the
differential stage transistors. To emulate this mismatch the length of one differential stage transistor is increased by 'delta
L=0.1µm'. In reality, the mismatch is a stochastical value. For that reason the given values are more theoretical ones.

3) 'min'-value: analog models ('fastsp' and 'slowfp' and 'typ') @ T=150 C; 'typ'-value @ T=27 C

4) -3 dB (-9 dB) to 'typ'-value of v