1.What is Hardware Descriptive Language?

Hardware description languages (HDLs) are extremely important tools for modern digital
designers. Once you have learned System, Verilog or VHDL, you will be able to specify digital systems
much faster than if you had to draw the complete schematics. The debug cycle is also often much faster,
because modifications require code changes instead of tedious schematic rewiring. However, the debug
cycle can be much longer using HDLs if you don't have a good idea of the hardware your code implies.

HDLs are used for both simulation and synthesis. Logic simulation is a powerful way to test a
system on a computer before it is turned into hardware. Simulators let you check the values of signals
inside your system that might be impossible to measure on a physical piece of hardware. Logic
synthesis converts the HDL code into digital logic circuits.

2. What are the three (3) common Hardware Descriptive Language? Differentiate each type.

The three common HDLs are Verilog, VHDL and System C. VHDL and Verilog are considered
general-purpose digital design languages, while System Verilog represents an enhanced version of
Verilog.

 VHDL is a rich and strongly typed language, deterministic and more verbose than Verilog. As a result,
designs written in VHDL are considered self-documenting. Its syntax is non-C-like and engineers
working in VHDL need to do extra coding to convert from one data type to another. VHDL often
catches errors missed by Verilog. VHDL emphasizes unambiguous semantics and allows portability
between tools.

Sample VHDL Code:

reg1: process (rst, clk)

begin
if rst = '1' then
q_reg <= (others => '0');
q_i <= (others => '0');
elsif rising_edge(clk) then
if s_l = '1' then
q_i(0) <= q_i(7);
loop1: for i in 6 downto 0 loop
q_i(i + 1) <= q_i(i);
end loop loop1;
q_reg <= y;
else
q_i <= q_reg;
q_reg <= y;
end if;
end if;
end process reg1;
 Verilog is weakly typed and more concise with efficient notation. It is deterministic. All data types
are predefined in Verilog and each has a bit-level representation. Syntax is C-like.
Sample Verilog Code

always @(posedge CLK or posedge RST)

begin
if (RST) begin
q_reg = 0;
Q = 0;
end else if (S_L) begin
Q[7:0] = {Q[6:0],Q[7]};
q_reg = Y;
end else begin
Q = q_reg;
q_reg = Y;
end
end

 System Verilog or SystemC includes a set of extensions to the Verilog HDL to help engineers design
and verify larger and more complex designs. In fact, many industry watchers consider it the first
Hardware Description and Verification Language (HDVL), because it combines VHDL and Verilog
features with those of Hardware Verification Languages (HVLs) Vera and e, as well as C and C++. It’s
targeted at RTL coding, using constrained random techniques for assertion-based and coverage-
driven verification.

Sample SystemVerilog Code:

property p_push_error;
@ (posedge clk)
not (b_if.push && b_if.full && !b_if.pop);
endproperty : p_push_error
ap_push_error_1 : assert property (p_push_error);
property p_pop_error;
@ (posedge clk)
not (b_if.pop && b_if.empty);
endproperty : p_pop_error
ap_pop_error_1 : assert property (p_pop_error);

always_ff @ (posedge clk) begin

b_if.error <= (b_if.pop && b_if.empty) || (b_if.push && b_if.full && !b_if.pop);

3. How does hardware description language work?

 Hardware description languages allow you to describe a circuit using words and symbols, and
then development software can convert that textual description into configuration data that is loaded
into the FPGA in order to implement the desired functionality.

References:

https://www.sciencedirect.com/topics/computer-science/hardware-description-languages?
fbclid=IwAR2VyvHwge_n9TxuwfHOXBH0RBhf4JARC19Y_xGQumvvtbWcO2lowuU9JD4

https://www.electronicdesign.com/resources/whats-the-difference-between/article/21800239/whats-
the-difference-between-vhdl-verilog-and-systemverilog

https://www.allaboutcircuits.com/technical-articles/what-is-a-hardware-description-language-hdl/?
fbclid=IwAR1Ir3r8cAT_tp9j0RCDhGuBqwnicAACD1bEmFutyDLIIT7LHAf5jEf7kcM