IEEE Vehicle Power and Propulsion Conference (VPPC), September 3-5, 2008, Harbin, China

A Nine-Switch Three-Level Inverter for Electric

Vehicle Applications
Mingyan Wang* and Kai Tian**
*Postdoctoral Workstation of Harbin Fenghua Aerospace Hi-Tech Holding Group Co.,Ltd
**Dept. of Electrical Engineering, Harbin Institute of Technology, Harbin 150001, Heilongjiang, P.R. China
tk2002_0@163.com

Abstract—This paper presents a nine-switch three-level
inverter used as an application for all-electric vehicle (EV)
and hybrid-electric vehicle (HEV) motor drives. The
proposed three-level inverter consists of a three-phase two-
level inverter and three bidirectional power switches. The
proposed inverter overcomes some shortcomings of two-
level inverters, such as high switching frequency, high dv/dt
and electromagnetic interference (EMI). The proposed
inverter also reduces the number of power switches from
twelve to nine compared with conventional three-level
inverters. Fewer switches reduce system cost and improve
system reliability. The proposed three-level inverter is
suitable for low voltage applications because the voltage
stress across part of power switches in this circuit is full of
the DC bus voltage. Losses of the proposed inverter are
analyzed and compared with other two inverters. The basic
principle and control scheme of the proposed three-level
inverter are introduced. Analytical, simulation, and
experimental results show the superiority of the proposed
three-level inverter for electric vehicle applications.
Keywords — New Topology; Nine-Switch Three-Level
Inverter; EV Motor Drive
I. INTRODUCTION
The development of electric vehicles (EV) and hybrid-
electric vehicles (HEV) has offered many challenges to
the power electronics industry, especially in the
development of the main traction motor drives [1]. Many
current and future designs will incorporate the use of
induction motors as the primary source for traction in
electric vehicles.
Three-phase two-level inverter, known as six switches
inverter, is widely used. This topology has the merits of
low cost, easily controlled and high reliability, but it also
has some shortcomings such as: high switching frequency,
high dv/dt and electromagnetic interference (EMI) [2].
Motor damage and failure has been reported by industry
as a result of adjustable speed drive inverters’ high
switching frequency PWM. The main problems reported
have been “motor bearing failure” and “motor winding
insulation breakdown” because of the high dv/dt [3]. High
switching frequency also causes high switching loss and
EMI. These shortcomings are not in accord with the
design requirements of EV/HEV propulsion systems.
To overcome these shortcomings of conventional two-
level inverter motor drives, some multilevel inverters,
such as conventional three-level diode-clamped inverters
Project Supported by Postdoctoral Fund of Heilongjiang Province,
China
and cascade inverters, have been used as EV/HEV motor
drives in some literatures [4-6]. Multilevel inverters have
shown the superiority over two-level inverters in EV/HEV
motor drive applications, but the use of a large number of
power switches in these topologies is a main drawback
which will increase the system cost, control complexity
and reduce the system reliability.
This paper presents a nine-switch three-level inverter
used for EV/HEV motor drives. The proposed inverter
overcomes some shortcomings of two-level inverters, such
as high switching frequency, high dv/dt and EMI. The
proposed inverter also reduces the number of power
switches from twelve to nine compared with conventional
three-level inverters. The reduction of power switches
could reduce system cost and improve system reliability.
The novel inverter has all advantages of the conventional
three-level inverters except that the voltage stresses across
part of power switches are full the DC bus voltage, so it is
suitable for low voltage applications, such as for electric
vehicle motor drives.
This paper includes: 1) system configuration and
analysis of the proposed three-level inverter; 2) space
vector pulse width modulation (SVPWM) and neutral-
point potential balancing for the proposed inverter; 3)
losses analysis and comparison with other two inverters;
4) simulation and experimental results; 5) conclusion.
II. SYSTEM CONFIGURATION AND ANALYSIS
A. Main Circuit of Three-Level Inverter
The proposed nine-switch three-level inverter used as
EV motor drives is shown in Fig. 1.
The nine-switch three-level inverter consists of one
conventional six-switch two-level inverter, three
bidirectional switches and two dc power supplies in series.
The bidirectional switch is consists of four power diodes
and one power switch. Voltage stress across the power
diodes and switches in the bidirectional switches when
they are switched off is half of the DC bus voltage, and
voltage stress across other six switches is full the DC bus
Figure 1. The proposed nine-switch three-level inverter

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C 2008 IEEE
 IEEE Vehicle Power and Propulsion Conference (VPPC), September 3-5, 2008, Harbin, China

voltage. This characteristic made the proposed inverter TABLE I.

THREE VOLTAGE LEVELS OF THE PROPOSED THREE-LEVEL INVERTER
suitable for low voltage applications.
The dc bus voltage consists of two dc power supplies in Voltage Output T1 T2 T7 Current path
iu
series. The dc power supplies could be batteries used for level voltage
EV drives or capacitors used for HEV drives. For series iu >0 on off off P→T1→U
P Vdc/2
HEV, a back-to-back-connection of the proposed inverters iu <0 on off off P←D1←U
can be used to drive traction motors. The series HEV O→Du1→T7
system configuration with back-to-back-connected nine- iu >0 off off on
→Du4→U
switch three-level inverter is shown in Fig.2. O 0
O←Du2←T7
iu <0 off off on
B. System Analysis ←Du3←U
Each phase of the inverter could produce three different iu >0 off on off N→D2→U
N -Vdc/2
voltage levels. Current paths of these three voltage levels iu <0 off on off N←T2←U
in the proposed three-level inverter are shown in Fig. 3.
The three levels are denoted with ‘P’, ‘O’ and ‘N’
respectively. The output terminal ‘U’ is connected to ‘P’ if Compared with conventional three-level inverter, the
switch T1 is turned on while T2 and T7 is turned off; The main advantage of the proposed inverter is that it reduces
output terminal ‘U’ is connected to ‘N’ if switch T2 is the number of power switches used in the circuit from
turned on while T1 and T7 is turned off; The output twelve to nine. The reduction of power switches can
terminal ‘U’ is connected to ‘O’ if switch T7 is turned on reduce system cost and increase system reliability. This
while T1 and T2 is turned off. States of the three output nine-switch three-level inverter has all the merits of
levels are summarized in Table I. conventional three-level inverter except the voltage stress
Compared with two-level inverter, the proposed across part of power switches is full the DC bus voltage.
inverter could reduce dv/dt and EMI with low switching III. SPACE VECTOR PULSE WIDTH MODULATION AND
frequency.
NEUTRAL-POINT POTENTIAL BALANCING
A. Space Vector Pulse Width Modulation
So far various pulse-width modulation (PWM)
techniques have been studied and a good plenty of results
are published such as modified two-level triangular
carrier-based modulation, selective harmonic elimination
modulation method (SHEPWM), space vector PWM
(SVPWM) and some combination PWMs.
Among various modulation techniques for multilevel
inverter, SVPWM is an attractive candidate due to the
following merits. It directly uses the control variable given
by the control system and identifies each switching vector
as a point in complex (α, β) space. It is suitable for digital
signal processor (DSP) implementation. It can optimize
switching sequences. The definition of the switching
Figure 2. Series HEV system configuration with back-to-back- space vector is shown in (1).
connected nine-switch three-level inverter 2π 2π
1 j −j
V ( Sa , Sb , Sc ) = Vdc ( Sa + Sb * e 3 + Sc * e 3 ) (1)
3
where Si (i=a, b, c) is switching function. The given
reference vector Vref is synthesized by space vector
modulation (SVM) using three switching space vectors
that are nearest to the reference vectors at every sampling
instant. The reference vector is synthesized as (2) and (3).
Vref = d0V0 + d1V1 + d 2V2 (2)
(a) (b) d 0 + d1 + d 2 = 1 (3)
where d0, d1, d2 are the duty cycles of the nearest three
switching vectors V0, V1, V2. Vi is vector (Sa, Sb, Sc).
B. Neutral-Point Potential Balancing Technique
Used as EV motor drives, the propose three-level
inverter can select two batteries in series as the DC bus
power supply, which is denoted with Vdc1 and Vdc2 in Fig.1.
The voltage of the two batteries should be chosen equal.
However, the average neutral-point current should be
(c) (d) controlled to zero to make sure the two batteries share
Figure 3. Current paths of the three voltage levels: (a) voltage level ‘P’; energy in equal, or else neutral-point potential will
(b) voltage level ‘N’; (c) and (d) voltage level ‘O’ unbalance and system performance will deteriorate, so
 IEEE Vehicle Power and Propulsion Conference (VPPC), September 3-5, 2008, Harbin, China

neutral-point potential balance should be assured when the IV. LOSSES ANALYSIS AND COMPARISON
inverter is used as EV motor drives.
A. Losses Analysis
Neutral-point potential unbalance is a key problem
widely known in back-to-back-connected three-level Converter efficiency is one of the fundamental
inverters. Obviously when the proposed inverter is used as performance indices. Losses produced by the switching
series HEV motor drives shown in Fig.2, the neutral-point elements are usually considered as a main challenge
potential balancing control should be made. during converter design. Voltage stresses across the
To assure the neutral-point potential balance, a neutral- switches directly influence their power rating, thus their
point potential balancing technique which is based on zero size, weight and cost. System losses consist of two parts:
average neutral-point current in a switching period is conduction losses and switching losses, so two part losses
introduced in this sect. The control scheme of neutral- should be analyzed.
point potential is shown in Fig. 4. t0, t1, t2 are the operation The switch conduction losses dissipated during single
times of vector V0, V1, V2. iinvz0, iinvz1, iinvz2, iinvz3 are PWM cycle is expressed by (10). The diode conduction
neutral-point currents when negative small vector V0, losses dissipated during single PWM cycle is expressed by
vector V1, V2 and positive small vector V0 act on inverter. (11).
The control aim in the nth period is expressed with (4). Pcond = U ce I c dTi (10)
Qn −1 + ΔQn = 0 (4) Pcond = U ce I c d Di (11)
where Qn −1 is the remaining charges in neutral-point at where Uce, Ic is the collector-to-emitter on-state voltage
the end of (n-1) period, and Qn −1 could be got by (5). ΔQn and collector current, and dTi and dDi is the duty cycle of
is new charges produced in nth period, and it could be power switches and diodes. The duty cycle of power
calculated with (6) and (7). ρ is a parameter which is switches could be achieved from the calculation of
reference vector synthesis in section III. For the first leg,
used to regulate the ΔQn . With the parameter ρ , duty to calculate the duty cycle dTi, define the power switch
cycle of negative small vector is d 0 (1 + ρ ) / 2 , and duty switching function STi as (11).
cycle of positive small vector is d 0 (1 − ρ ) / 2 . ⎧ ST 1 = Sa ( Sa + 1) / 2
⎪
Qn −1 = Q2 − Q1 = C *(Vdc2 − Vdc1 ) = C * ΔVdc (5) ⎨ ST 7 = −( S a − 1)( Sa + 1) (11)
(1 + ρ ) t0 (1 − ρ ) t0
⎪ S = S ( S − 1) / 2
ΔQn = * * iinvZ0 + t1 * iinvZ1 + t2 * iinvZ2 + * *iinvZ3 (6) ⎩ T2 a a
2 2 2 2 then dTi could be expressed as (12).
ΔQn == ρ * t0 * iinvZ0 + t1 * iinvZ1 + t2 * iinvZ2 (7) dTi = STi (V0 ) d0 + STi (V1 ) d1 + STi (V2 ) d 2 (i = 1, 2, 7) (12)
According to (4~7), the ρ can be calculated out with
There are always two diodes turned on in diodes Du1, Du2,
(8) in a switching period. Du3, Du4 when power switch T7 is turned on, and all the
four diodes are turned off when power switch T7 is turned
C * ΔVdc + t1 * iinvZ1 + t2 * iinvZ2 off, so dDui could be expressed as (13).
ρ=− (8) d Dui = dT 7 (i = 1, 4 or 2,3) (13)
t0 * iinvZ0
The parameter ρ is limited by (9) to avoid the duty The switching loss Psw could be easily obtained from
datasheets. The total losses in a period could be expressed
cycle of space vectors become negative. as (14).
⎧1, ρ >1 1 2π

ρ0 = ⎨ ρ ,
⎪
ρ ≤1 (9)
Ploss =
2π ∫0
( Pcond + Psw )d ωt (14)
⎪−1, ρ < −1
⎩ B. Losses Comparison
The neutral-point potential balancing method could To show the efficiency of the proposed three-level
assure the balance of voltage Vdc1 and Vdc2. Balanced inverter, following discussion takes into consideration
neutral-point potential could guarantee the performance of three inverter topologies: conventional two-level inverter,
inverter. conventional three-level neutral point clamped (NPC)
T
inverter, and the proposed nine-switch three-level inverter.
s For comparison purposes, it was assumed that each
topology is built of the same IGBT (MGY25N120D), the
V −V 0 same diode bridge (GBJ2510). The DC bus voltage
dc2 dc1 Vdc=500V. Fig.5 shows total losses generated by three
t0 t1 t2 t0 t2 t1 t0 different inverters. The curves present the losses versus
(1+ρ) (1− ρ) (1+ρ) output current magnitude. Total harmonic distortions
4 2 2 2 2 2 4
(THD) of the three type inverters are given in Fig.6.
i These three topology inverters are compared under the
invZ 0 same switching frequency (fsw=3.24kHz) firstly. The
losses of conventional three-level inverter are the largest.
iinvZ0 iinvZ1 iinvZ2 iinvZ3 iinvZ2 iinvZ1 iinvZ0 The losses of conventional two-level inverter are the
smallest. The losses of the proposed inverter are between
Figure 4. The control scheme of neutral-point potential that of conventional two-level and three-level inverters.
 IEEE Vehicle Power and Propulsion Conference (VPPC), September 3-5, 2008, Harbin, China

15
90
The proposed inverter, f sw=3.24kHz 10

Output current (A)

80
Conventional tw o level inverter, f sw=3.24kHz
5
70 Conventional tw o level inverter, f sw=9.72kHz
0
Conventional three level inverter, f sw=3.24kHz
60
-5
Loss (W)

50 -10
40 -15
0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1
30 time (s)

20 Figure 8. Output line current of inverter

10
300
0

Output phase voltage (V)

0 2 4 6 8 10 200
Current magnitude (A)
100
Figure 5. Loss of three different inverter
0

-100

The proposed inverter, f sw=3.24kHz -200

1.2 Conventional tw o level inverter, f sw=3.24kHz -300
0.075 0.08 0.085 0.09 0.095
Total harmonic distortion (%)

Conventional tw o level inverter, f sw=9.72kHz

1.1
time (s)
Conventional three level inverter, f sw=3.24kHz

Figure 9. Output phase voltage of inverter

1

0.9
To show voltage stress on switches and diodes, the
voltage stress waveforms of power switches T1, T7 and
0.8 diode Du1 are given in Fig. 10, Fig. 11, and Fig. 12
respectively. The voltage stresses on power switches T1
0.7
has three different levels: 0, Vdc/2, and Vdc. The voltage
0.6 stresses on power switch T1 and diode Du1 all have two
0 2 4 6 8 10 levels: 0 and Vdc/2. Although the maximal voltage stress
Current magnitude(A)
on switch T1 is Vdc, the dv/dt is Vdc/2 which is half that of
Figure 6. THD of three different inverter two-level inverters.
The THD of conventional two-level inverter is the 500
highest. When switching frequency is increased to 3fsw 400
(9.72kHz), two-level inverter’s THD is reduced, while its
VT1 (V)

300
total losses are smaller than the proposed inverter’s when 200
current is large, but larger than the proposed inverter’s
100
when current is small. The loss comparison shows that the
proposed inverter’s losses are acceptable when current is 0

not too large. 0.085 0.09 0.095

time (s)

V. SIMULATION AND EXPERIMENTAL RESULTS Figure 10. Voltage stress on switch T1

A. Simulation Results 300

The proposed three-level inverter with SVPWM
method and neutral-point potential balancing technique 200
has been simulated using MATLAB 7.1. DC bus voltage
VT7 (V)

is 500V. Modulation index is 0.8. Switching frequency is 100

3.24kHz, and the output fundamental frequency is 50Hz.
The active and reactive power are 3.3kW and 330var. 0

The output line voltage, current and phase voltage are 0.095 0.096 0.097 0.098 0.099 0.1
given in Fig. 7, Fig. 8 and Fig. 9 respectively. The line time (s)

voltage has five voltage levels, while phase voltage has Figure 11. Voltage stress on switch T7
three voltage levels. The current is nearly sinusoidal.
500
Output line voltage (V)

0
V Du1 (V)

-100
0

-200

-500 -300
0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1 0.095 0.096 0.097 0.098 0.099 0.1
time (s) time (s)

Figure 7. Output line voltage of inverter Figure 12. Voltage stress on diode Du1
 IEEE Vehicle Power and Propulsion Conference (VPPC), September 3-5, 2008, Harbin, China
Simulation results show that the proposed inverter is
correct and effective.
B. Experimental Results
The proposed inverter is experimented with a 27V DC
bus voltage and an asynchronous motor as load. The
inverter output line voltage and current are shown in Fig.
13. The inverter output phase voltage is shown in Fig. 14.
Figure 13. Output line voltage and current of the three-level inverter
Figure 14. Output phase voltage of the three-level inverter
The line voltage has five voltage levels and phase
voltage has three voltage levels. The current is nearly
sinusoidal. The experimental results show that the
proposed nine-switch three-level inverter is correct.
VI. CONCLUSION
This paper presents a nine-switch three-level inverter
used as an application for EV/HEV motor drives. The
proposed inverter overcomes some shortcomings of two-
level inverters, such as high switching frequency, high
dv/dt and EMI. The proposed inverter also reduces the
number of power switches from twelve to nine compared
with conventional three-level inverter. Fewer switches
reduce system cost and improve system reliability. Losses
analysis and comparison show that the proposed inverter’s
losses are acceptable when current is not too large.
Simulation and experimental results show that the
proposed nine-switch three-level inverter is correct and
effective.
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