Order this document

by MC146818/D
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
MC146818

Advance Information
REAL-TIME CLOCK PLUS RAM (RTC)
The MC146818 Real-Time Clock plus RAM is a peripheral device which includes the unique MO- ?;i.i,
“{J:&>\)+,/
\::.’
,:}.T:.$
‘“r{!.,
:,.!*
TEL concept for use with various microprocessors, microcomputers, and larger computers. This ,.<?~v..
~ $)),:,,,.,.
.J~~k
~;k? ,,,1,,.
,1
part combines three unique features: a complete time-of-day clock with alarm and one hundred .y,~,$.~“’”
year calendar, a programmable periodic interrupt and square-wave generator, and 50 bytes of low- ,$:*J3+,J’*
power static RAM. The MC146818 uses high-speed CMOS technology to interface with 1 MHz pro- ‘~:%+,+~r ‘
cessor buses, while consuming very little power. ?:;j\. *.
.J.!. .,
The Real-Time Clock plus RAM has two distinct’uses. First, it is designed as a battery po~~~~’;~?
CMOS part (in an otherwise NMOS/TTL system) including all the common battery backed<#~4ufi$-
tions such as RAM, time, and calendar. Secondly, the MC146818 may be used with a CMQ,~:,@!cro-
processor to relieve the software of the timekeeping workload and to extend the avail$@~@~kAM of
‘*..
~,i..:,tti~t,
an MPU such as the MC146805E2.
●

●
,+.?,.,
,.\,K<:,
● Counts Seconds, Minutes, and Hours of the Day .!,,,?:
,t>i ‘A:$
o Counts Days ,of the Week, Date, Month, and Year .,,:$
,.?.~
*:\$,.,
● 3 V to 6 V Operation *.>’+~x~t. “k
● Time Base Input Options: 4.194304 MHz, 1.048576 MHz, O~$~R~#b kHz
k(v.,-c.
... )\,.
.<,Y,,,,
,,5$<>......>.
● Time Base Oscillator for Parallel Resonant Crystals

● 40 to 200 pW Typical Operating Power at Low Fregue~$y ‘~ime Base

● 4.0 to 20 mW Typical Operating Power at High ~$&uency Time Base
Binary or BCD Representation of Time, Caleu.d~k%,a#d Alarm
~‘.\\::;~s,l:~.,~ae.,
12- or 24-Hour Clock with AM and PM in ~-S:&&qr ‘Mode
.:’.$*:<
~~ ,.,,<,>
Daylight’Savings Time Option .:<.:~,t,,
‘,-:. .,:(,X,
,,,*,
)il.,,,‘~?$
.,;;l
● Automatic End of Month Recogniti~&~~,
● Automatic Leap Year Compensat@~,~~ ““’
● Microprocessor Bus Compati@” *‘+
. >,s.‘!$,...’.
● MOTEL Circuit for Bus Un~~UP~$l*Y
● Multiplexed Bus for P[~@{~~@hcy
● Interfaced with So~wa’~$$~ 64 RAM Locations
e 14 Bytes of Cloc~~~@,,Qontrol Registers
50 Bytes of G~q~,a*@urpose RAM
,:, L..%atpa
Status Bit l~,@~ates Data Integrity
Bus Co.~~$%# Interrupt Signals (IRQ)
● Three~~ntq~fupts are Separately Software Maskable and Testable
.~~}jfl&J~f-Day Alarm, Once-per-Second to Once-per-Day
J3& ‘x~eflodic Rates from 30,5 ps to 500 ms
~$YJ~End-of-Clock Update Cycle
. ~rogrammable Square-Wave Output Signal
● Clock Output May Be Used as Microprocessor Clock Input
At Time Base Frequency + 1 or + 4
● 24-PinDual-in-Line Package

This document contains information on a new product. Specifications and information herein are subject to change without notice.

m MOTOROLA =
@MOTOROU INC., 1988 w
AD1856R3
 FIGURE1 – BLOCK DIAGRAM

I T T T CKOUT

Oscl
OSC2

us —q Intertace

‘date,:=
R/m Clock/
Calendar
AS

ADO-AD7 8

i r

.,5L
User RAM
(50 Bytes)

‘**<?
:,.
.~
“:$:’~,
\ ~.,,
,!~
,*.,..i~,...
,!+
~.$*\ ..*. .

MNIMUM RATINGS (~&+,#ferenced to Vss)

Ratings ‘Q\~6)%
~$ Symbol Value Unit
Supply Voltage ~~~’’”t:k ‘$ VDD -0.3 to +8.0 v
All Input Voltage~~%Wt OSC1 Vin VSS-O.5 to VDD+O.5 v
Current DraiNQ@W* Excluding
VDD a~~~~~+
I 10 mA This device contains circuitry to protect the in-
puts against damage due to high static voltages
OPer~&gSYq,mDerature Range
or electric fields; however, it is advised that nor-
Mql~8 TL to TH
mal precautions be taken to avoid application of
&$~2?W18C
‘.*;$
,,,/.,~~y
\ (VDD=3.O to 5,5 V TA o to 70 ‘c any voltage higher than maximum rated voltages
.. ,,, ~y.,,ooeration)
\J>, –40t085 to this high-impedance circuit. For proper opera-
‘~!>brage Temperature Range Tstg -55to +150 Oc tion it is recommended that Vin and Vout be con-
strained to the range Vsss (Vin or Vout)
s VDD. Reliability of operation is enhanced if
THERMAL CHARACTERISTICS unused inputs are tied to an appropriate logic
Characteristic I Symbol I Valua Unit voltage level (e. g., either VSS or VDD).
I
Thermal Resistance I I 1

I Plastic
I OJA 120 ‘cm

MOTOROLA
MC146818/D
2
AD1856R3
 DC ELECTRICAL CHARACTERISTICS (VDD = 3 Vdc, VSS = O Vdc, TA = TL to TH unless otherwise noted)
Characteristics
Frequency of Operation
I Symbol
I 4
I
I
Min
. . 7.0
I Max Unit

I ‘Osc I JL. /w I 32.7~ kHz

Output Voltage —

D lLoad<lopA
IDD – Bus Idle
Vnl
VOH
v-

VD[~–o.l ]
0.1
–
v

CKOUT= fosc, CL= 15 pF; SQW Disabled, ~= VDD– O.2; CL (OSC2) = 10 pF

fosc= 32.7~ kHz IDD3 – 50 PA
IDD – Quiescent —
IDD4 50 P&k:~
fosc= DC; OSCI = DC; ,.$J.,
‘+y~j.;t:,,,,.
All Other Inputs= VDD– 0.2 V; p.
~:~’”<t;. ?$.,,
NO Clock
“x, ~:~:i,,+<:.
,e,
Output High Voltage
(LLoad= –0.25 mA, All Outputs)
I 27
I VOH I $:;’$’,&”&l
,, I

Input High Voltage ADO-AD7, DS, AS, F

RESET, CKFS, P
Input Low Voltage (All Inputs)
I ‘IL ~ “~
l--, ,+n,, -----
n,, ,, ,pu Lo
I ‘In.,t
Three-State Leakage
—,. .—---- r~.w<?;,~x,
I I
\,.,
)C ELECTRICAL CHARACTERISTICS (VDD= 5 Vdc f 10%, VSS =0 Vdc, TA= TL:#&%
bless otherwise noted)
Characteristics ,:j:...’ ,,!‘~!~y,,,,
... Symbol
,,,.,, Min Max Unit
Frequency of Operation ~,,,,$
fosc 32.768 41M.3M kHz
VOL — 0.1
— v
VOH VDD– O.1

IDD1 — 3
IDD2 — 8W
IDD3 — 50
IDD4 — 50

——

vOH 4.1 — v

vOL — 0.4 v
—
VDD–2,0 VDD
VIH VDD–0,8 v~D v
VDD–1.O VDD
Vss 0,8
VIL Vss .0.8 v
Vss O.B
Iin — *I
ITSL *1O

MC146818/D
MOTOROLA
AD1856R3
3
 BUS TIMING
VDD=5.O V
* 10%
v~n=3.o v 2 TTL and
Ident. ~ ~F Load 130 pF Load
Number Characteristics Symbol Min Max Min Max Unit
1 Cycle Time tcyc m – 953 dc ns
2 Pulse Width, DS/E Low or ~/WR High PWEL lW – 3m – ns
——
3 Pulse Width, DS/E High or RD/WR Low PWEH 1500 – 325 – ns
4 Input Rise and Fall Time tr, tf – Im – 30
8 R/~ Hold Time tRWH 10 – 10 – ns
13 R/~ Setup Time Before DS/E tRWS 200 – 80 –
14 Chip Enable Setup Time Before AS/ALE Fall tcs 200 * 55 *, ~
15 Chip Enable Hold Time tCH 10 – o
18 Read Data Hold Time tDHR 10 Im 10 lqe$~ ~ ns
lm – ,.:.,:
~,~,>.,,
~.:,>.%
21 Write Data Hold Time tDHW o ,..\~, ~ (’ ns
24 Muxed Address Valid Time to AS/ALE Fall tASL 200 – 50 ~; ns
... “’~’?$:$
25 Muxed Address Hold Time tAHL lm –
26 Delay Time DS/E to AS/ALE Rise tASD w – *
27 Pulse Width, AS/ALE High pWASH m
.{;..’:,+J,J,
>-.,~
.28 Delay Tima, AS/ALE to DS/E Rise tASED w %>> ..>.. 60 – ns
+t,,.
30 Peripheral Output Data Delay Time from DS/E or ~ tDDR 1300 ,*;,$:$ – 20 240 ns
!?:.?l,,..,~..,
31 Peripheral Data Setup Time tDSW 1gb.,~$bh, - 200 – ns
NOTE: Designations E, ALE, ~, and ~R refer to signals from alternative micrw~cesbr signals.
* Refer to IMPORTANT NOTICES appearing on page-20 of this data sheet. ,~~~v’“$%:*’* -
..

AS~l-- ‘.$-
1-
k

WRITE

ADO-
AD7
READ
I
NOTE: VHIGH= VDD-2.O V, VLOW=O.8 ;, for VDD=5.O V + 10%

MOTOROLA MC146818/D
4 AD1856R3
 FIGURE 3 – BUS READ TIMING COMPETITOR MULTIPLEXED BUS

‘LE’AddressLatc
= (Read Output Enable)
(DS Pin)
L

* ~
3;
“Low
4
28

~E (Chip Enable)

ADO-AD7
(P\ddress/ Data Bus) Address
Valid

II — II

II

NOTE: VHIGH=VDD–2,0 V, VL0w=0,8 V, for VDD=5.O V +10%

MC146818/D MOTOROLA
AD1856R3 5
 TABLE 1 – SWITCHING CHARACTERISTICS (VDD=5.0 Vdc + 10%, VSS=O Vdc, TA= TL to TH)

Description Symbol Min Max Unit

Oscillator Startup tRC _ 1~ ~~

Reset Pulse Width

Reset Delay Time

tRWL

tRLH
~

5
—

—
~s

#s
9
Power Sense Pulse Width tpWL 5 — #s

Power Sense Delay Time tpLH 5 — j KS

l= Release from DS tlRDS — 2 : p;?~~

~ Release from RESET tlRR — ;g;$ $’+>5

tVRTD ,.,
VRT Bit Delay —. ~?.::.. , ,, #s
~ !yl

FIGURE 5 – tiQ RELEASE DELAY

RESET

NOTE: VHIGH=VDD

VDD

2k (FQ Only} 4.02 k

Test Point

4
130pF
MMD7m
or Equivalent

I
— —

All Outputs Except 0SC2 (See Figure 10)

MOTOROLA MC146818/D
6 AD1856R3
 FIGURE 7 – POWER-UP

ff
))

VDD Pin

Ov

VDD Pin

Ov

PS Pin

@ The VRT bit is set to a “1,, by reading Register d, The VRT bit can only be cleared by pulling the PS pin low (see REGISTER D ($OD)),

MC146818/D MOTOROLA
AD1856R3 7
 MOTEL bus structure is now available. The MOTEL concept is
shown logically in Figure 9,
The MOTEL circuit is a new concept that permits the MOTEL selects one of two in~erpretations of two pins. In
MC146818 to be directly interfaced with many types of the Motorola case, DS and R/~aregated together to pro-
microprocessors. No external Iogicis needed toadapt to the duce the internal read enable. Theinternal write enable isa
differences in bus control signals from common multiplexed similar gating of t~e inverse of R/~. With competitor buses, a
bus microprocessors. the inversion of RD and ~ create functionally identical in-
Practically all microprocessors interface with one of two ternal read and write enable signals.
‘synchronous bus structures. One bus was originated by the The MC148818 automatically selects the p~ocessor type by
Motorola MC6800 and the other by the Intel 8080 and its using AS/ALE to latch the state of the DS/RD pin. Since DS
companion part, the 8228. is always low and ~D is always high during AS and ,.% Ak~. the
,, ,~.h
The MOTEL circuit (for ~Torola and Intfl bus com- latch automatically indicates which processor tyRe+:&%n-
,$.*’~~..
. ‘r\ii*
patibility) is built into peripheral and memory ICS to permit netted. ~.i, ,,~+>,
direct connection to either type of bus. An industry standard *6 &,$v$
,*>.!~J.i$..~
>,.$,~.
.-,.,,
:?/..,*>:J1
,$*Ys,+$<w~}
FIGURE 9 – FUNCTIONAL DIAGRAM OF MOTEL CIRCUIT ,,:~.:; ,;~.si,
\<,$.\i-

Motorola Type Competitor Type MC146818

MPU Signals MPU Signals Pin Signals .
DO

AS ALE AS c
d

+
DS, E, or@2 m DS - able

AT cut crystal at 4,184304 MHz or 1.048576 MHz frequen-

]$:, ,~ cies, The crystal connections are shown in Figure 11 and the
The block diagram in Figure l:@$~~~$the pin connection crystal characteristics in Figure 12.
with the major internal function$.of ’’~keMC146818 Real-Time
Clock plus RAM. The fo~&W&’:Faragraphs describe the
function of each pin. ~ ‘$,<$ CKOUT – CLOCK OUT, OUTPUT
~...,jl~ ~.,
.4‘~’?;?’:’ ,:;: The. CKOUT pin is an output at the time-base frequency
VDD, VSS Y< $.,~:.,:.,..’ divided by 1 or 4. A major use for CKOUT is as the input
,,. ‘t,...:~ ,
DC power is,,~$ti~~ to the part on these two pins, VDD clock to the microprocessor; thereby saving the cost of a se-
being the rn$r~.~kitive voltage. The minimum and maxi- cond crystal. The frequency of CKOUT depends upon the
mum VOlJ~Q~~.aS&listed in the Electrical Characteristics time-base frequency and the state of the CK FS pin as shown
tables,. $ .<.‘~’ in Table 2.
. -.-?i!d!:$,~:’>
,.,::,,s.
:?l:h.~
O~C%&~9~2 – TIME BASE, INPUTS CKFS – CLOCK OUT FREQUENCY SELECT, INPUT
‘&@fime base for the ~me functions may bean external
sighl or the crystal oscillator. External square waves at When the CKFS pin is tied to VDD it causes CKOUT to be
4.1%304 MHz, 1.048576 MHz, or 32.768 kHz may be con- the same frequency as the time base at the OSC1 pin. When
nected to OSC1 as shown in Figure 10. The internal time- CKFS is tied to Vss, CKOUT is the OSCI time-base fre
base frequency to be used is chosen in Register A, quency divided by four, Table 2 summarizes the effect of
The on-chip oscillator is designed for a parallel resonant CKFS.

MOTOROLA MC146818/D
8 AD1856R3
 FIGURE 10 – EXTERNAL TIME-BASE CONNECTION

VDD

Optional
(VDD–1.O V)
!
4.194304 MHz I
I 2
1.0485;6 MHz Oscl
32.7: kHz 3
(Open)+— OSC2

Mclm18

FIGURE 11 – CRYSTAL OSCILUTOR CONNECTION ~~>:

MC146B1B

cl RS

3 2

101
f Osc 4.184304 MHz 1.-76 MHz 32.766 kHz
RS (Maximum) 75 Q 700 Q 50 k
CO (Maximum) 7 pF 5 pF 1.7 pF
cl 0.012 pF 0.008 pF 0.003 pF
Q 50 k 35 k 30 k
Cin/C~ut 15-30 pF 15-40 pF 10-22 pF
R — — 303470 k
Rf 10 M 10 M 22M

MC146818/D MOTOROLA
AD1856R3 9
 TABLE 2 – CLOCK OUTPUT FREQUENCIES the DS pin must remain high during the time AS/ALE is
high.
Tme Base Clock Frequency Clock Frequency
{Oscl) Select Rn Output Rn R/~ – READ/WRiTE, INPUT
Frequency (CKFS) (CKOUT)
The MOTEL circuit treats the R/~ pin in one of two_ways.
4,184304 MHz High 4.184304 MHz
When a Motorola type processor is connected, R/W is a
4,184304 MHz Low 1.M576 MHz a
level which indicates whether the current cycle is a read or
1,048576 MHz High 1.046576 MHz write. A read cycle is indicated with a high level on R/~
1,048576 MHz Low 262,1M kHz while DS is high, whereas a write cycle is a low on R/~ dur-
32.768 kHz High 32.768 kHz ing DS
32,7@ kHz Low 8.192 kHz The second interpretation of R/~ is as a negati~e~~{[te
pulse, ~, MEMW, and l/OW from competitor&y~:pb-
cessors. The MOTEL circuit in MS mode gives ~~~:-~ifl’ the
SQW – SQUARE WAVE, OUTPUT same meaning as the write (W) pulse Ot~&~~$%~~eneric
~\,~,:,ht$)
,,,,
The SQW pin can output a signal from one of the 15 taps RAMs. ,.~s!,,~. .,:;
~~)- . ‘<y’
provided by the 22 internal-divider stages. The frequency of \$*h,...
*,,,<:
‘~,*Y..
the SQW may be altered by programming Register A, as C= – CHIP ENABLE, INPUT ,...:~ii’!:i$k
.,$Z:j
~
shown in Table 5. The SQW signal may be turned on and off The chip-enable (CT) signal rnus$:~~~~sserted (lo@ for a
using the SQWE bit in Register B. bus cycle in which the MC146818~s to’%e accessed. CE is not
latched and must be stabl$i~$~~~ DS and AS (Motorola
ADO-AD7 – MULTIPLEXED BIDIRECTIONAL AD-
case of MOTEL) and @r~@RD and ~R (in the other
DRESS/DATA BUS
MOTEL case). Bus cy@~~&h take place without asserting
Multiplexed bus processors save pins by presenting the CE cause no actioti~@~~~e place within the MC146818,
address during the first portion of the bus cycle and using When FE is hi~:~~ithe’multiplexed bus output is in a high-
the same pins during the second portion for data. Address- Impedance st:~w+iw$$
then-data multiplexing does not slow the access time of the When C—&f#-~i@,ail address, data, DS, and R/~ inputs
MC146818 since the bus reversal from address to data .is oc- from th~~?~a~or are disconnected within the MC146818.
curring during the internal RAM access time. This pdw?s ‘the MC146B18 to be isolated from a powered-
The address must be valid just prior to the fall of AS/ALE do~f pro?essor. When C—Eis held high, an. unpowered
at which time the MC146818 latches the address from ADO
~@j&$annOt receive power through the input pins from the
to AD5. Valid write data must be presented and held stable
, :~,rea~time clock power source. Battery power consumption
during the latter portion of the DS or ~R Dulses. In a read
~<,~%~b~ thus be reduced by using a pullup resistor or active
cycle, the MC146818 outputs eight bits of data during the
‘“’’-:;~~%lamp on ~E when the main power is off. When ~ is not us-
latter portion of the DS or ~ pulses, then ceases driving the
‘“ ed, it should be grounded,
bus (returns the output drivers to the hiah-imDedance state) i~”
when DS falls in the Motorola case of M-OTEL or ~D risds~ 9
the other case. ~Q – INTERRUPT REQUEST, OUTPUT
The ~Q pin is an active low output of the MC146818 that
AS – MULTIPLEXED ADDRESS STROBE, l~:$~~? may be used as an interrupt input to a processor. The ~Q
A positive going multiplexed address str%~~we serves output remains low as long as the status bit causing the in-
to demultiplex the bus. The falling edge qf %$~&P~LE causes terrupt is prasent and the corresponding interrupt-enable bit
the address to be latched within .L$&a$~146818. The is set. To clear the ~Q pin, the processor program normally
automatic MOTEL circuit in the MC$~@$8’’also latches the reads Register C. The RESET pin also clears pending inter-
state of the DS pin with the fall~~~~$pof AS or ALE. rupts.
~:J:N$
,$:P When no interrupt conditions are present, the ~Q level is
DS – DATA STROBE OR .@’~~tiPUT in the high-impedance state. Multiple interrupting devices
may thus be connected to an ~Q bus with one pullup at the
The DS pin has two i~rpr~%~ons via the MOTEL circuit.
processor.
When emanating fro~+~~,~torola type processor, DS is a
positive pulse duri~q t~e~fier portion of the bus cycle, and
is variously callq,~:~~a~~ata strobe), E (enable), and 42 (+2 RESET – RESET, INPUT
clock). During ;Wsycles, DS signifies the time that the The RESET pin does not affect the clock, calendar, or
RTC is to ~f&e$$e bidirectional bus. In write cycles, the trail- RAM functions. On powerup, the RESET pin must be held
ing edge ${ ~.$’’causes the Real-Time Clock plus RAM to low for the specified time, tRLH, in order to allow the power
latch .~~~~~~~en data supply to stabilize. Figure 13 shows a typical representation
TQe&cond MOTEL interpretation of DS is that of ~D, of the RESET pin circuit.
w;r ~R emanating from the competitor type pro- When RESET is low the following occurs:
cess@r. In this case, DS identifies the time period when the a) Periodic Interrupt Enable (PIE~ bit is cleared to zero,
real-time clock plus RAM drives the bus with read data. This b) Alarm Interrupt Enable (AIE) bit is cleared to zero,
interpretation of DS is also the same as an output-enable c) Update ended Interrupt Enable (U IE) bit is cleared to
signal on a typical memory. zero,
The MOTEL circuit, within the MC146818, latches the d) Update ended Interrupt Flag (UF) bit is cleared to zero,
state of the DS pin on the falling edge of ASIALE. When the e) Interrupt Request status Flag (IRQF) bit is cleared to
Motorola mode of MOTEL is desired DS must be low during zero,
AS/ALE, which is the case with the Motorola multiplexed f) Periodic Interrupt Flag (PF) bit is cleared to zero,
bus processors, TO ensure the competitor mode of MOTEL, g) The part is not accessible. @

MOTOROLA MC146818/D
10 AD1856R3
 g) Alarm Interrupt Flag (AF) bit is cleared to zero,
h) ~ pin is in high-impedance state, and
i) Square Wave output Enable (SQWE) bit is cleared to
FIGURE 13 – TYPICAL POWERUP DELAY
zero.
CIRCUIT FOR RESET

D PS – POWER SENSE, INPUT

DI D2 The power-sense pin is used in the control of the valid
Svstem Batterv
RAM and time (VRT) bit in Register D. When the PS pin is
d
Backup low the VRT bit is cleared to zero.
VDD
When using the VRT feature during powerup, the PS“~<~
must be externally held low for the specified tpLH tj,@&~x~S
VDD power is applied, the VRT bit remains low i~dicatin~’tw]~~e
contents of the RAM, time registers, and tale.~~~~d not
D3 l.Ok MC148818
guaranteed, PS must go high after poweru~,~s;~d%ow the
VRT bit to be set by a read of register D,.,F’,,,. :~:i
~,,
..
“r
.:,1t. ,.
m

.‘~
~~ ,!...,, ?’>,
,\.,.
~1.<>*<.;,\

I 0.005 pF Vss
I
In most systems, the M~{@~
time when system powe~ ?~:~~~ved.

usually a battery, must~%%de,

— system to battery @’~er, the designer of a battery backed-up
Dl = MBD701 (SchottkV) or Equivalent
D2= D3= 1N4148 or Equivalent ,,
Note: If the RTC is isolated from the MPU or MCU power bv a
diode drop, care must be taken to meet Vin requirements.
FIGURE 14 – TYPICAL POWERUP DELAY CIRCUIT
‘bust continue to keep
In such systems, a
conversion from syste~,@k~,&~Xo an alternate power suPPly,
During the transition from
RTC system ~~~~~~r~~ect data integrity, minimize power
consumptio,n$an&& hsure hardware reliability.
The chi~~$@B#&(C~) pin controls all bus inputs (R/~, DS,
AS, AQO-A@.7). CT, when negated, disallows any unintend-
ed a~cation of the RTC data by the bus. CT also reduces
~m consumption by reducing the number of transitions
,:~~,l$ternally
~l~.i.t+$ower consumption may be further reduced by removing
‘:%tesistive and capacitive loads from the clock out (CKOUT)
~,. pin and the squarewave (SQW) pin.
~\~.~i%. During and after the power source conversion, the VIN
maximum specification must never be exceeded. Failure to
meet the VIN maximum specification can cause a virtual
SCR to appear which may result in excessive current drain
and destruction of the part.

ADDRESS MAP

Figure 15 shows the address map of the MCl@18. The

memory consists of 50 general purpose RAM bytes, 10 RAM
bytes which normally contain the time, calendar, and alarm
data, and four control and status bytes. All W bytes are
directly readable and writable by the processor program ex-
cept for the following: 1) Registers C and D are read only, 2)
bit 7 of Register A is read only, and 3) the high-order bit of
the seconds byte is read only. The contents of four control
and status registers (A, B, C, and D) are described in
REGISTERS.

,)<. TIME, CALENDAR, AND ALARM LOCATIONS

‘b~
-
The processor program obtains time and calendar infor-
mation by reading the appropriate locations. The program
DI = MBD701 (Schottky) or Equivalent may initialize the time, calendar, and alarm by writing to
D2= 1N4143 or Equivalent
these RAM locations. The contents of the 10 time, calendar,
and alarm bytes may be either binary or binary-coded deci-
mal (BCD).

MC146818/D MOTOROLA
AD1856R3 11
 Before initializing the internal registers, the SET bit in O-to-23. The 24/12 bit cannot be changed ,without reinitializ-
Register B should be set to a “l” to prevent time/calendar ing the hour locations. When the 12-hour format is selected
updates from occurring. The program initializes the 10 loca- the high-order bit of the hours byte represents PM when it is
tions in the selected format (binarv or BCD), then indicates a “l”.
the format in the data mode (DM) bit of Register B. All 10 The time, calendar, and alarm bvtes are not a!wavs ac-
time, calendar, and alarm bvtes must use the same data cessible by the processor program, Onceper-second the 10
a
mode, either binarv or BCD. The SET bit mav now be cleared bytes are switched to the update logic to be advanced bv one
to allow updates. Once initialized the real-time clock makes second and to check for an alarm condition. If any of the 10
all updates in the selected data mode. The data mode cannot bytes are read at this time, the data outputs are undefined.
be changed without reinitializing the 10 data bytes. The update lockout time is 24B KS at the 4. IW304 MHz and
Table 3 shows the binary and BCD formats of the 10 time, 1.M567 MHz time bases and 1946 ps for the 32i7~ kHz
calendar, and alarm locations. The 24/ 12 bit in Register B time base. The Update Cycle section shows how$tt&*m-
,, :;+
establishes whether the hour locations represent 1-to-12 or modate the update cvcle in the processor pro@~G& ~~~

FIGURE 15 – ADDRESS MAP

o
14
Bytes
13 )D
—
14 )E

Binary
or BCD
Contents

50
Bytes
User
RAM

63 3F

,:! . . >!, ,.,

.,? $. ..>,. ~! !

hample*
Address “J. ~~@cimal Range
Function Yij “Ng
Location .<,~ ~~ Range Binary Data Mode BCD Data Mode Da:pM:de Dat:c;da
.,,:.:
,,,. .>.,..
,
0 059 $Q$3B $M-$59 15 21
1 0-59 $00-$3B $00-$59 15 21
2 0-59 $00-$3B $m-$59 3A w
3 0-59 $W$3B $00-$59 3A B
?.:. ,>:.
.’$\,%k!
.,+ .,, ,.:$ Hours $01-$OC (AM) and $01-$12 (AM) and 05
;I?l ‘::z~ (12 Hour Mode) 1~12 05
$B1-$BC (PM) $81-$92 (PM)
, ,(:>.&>
Hours
~,s$i.~.j, O-23 $00-$17 $0$23 05 05
.*, *$,\y\< ~~ {24 Hour Mode)
~,:;,? ~,~J
‘,.
,i:::~, *3,+ ,. Hours Alarm
1-12
$01-$OC (AM) and $01-$12 (AM) and 05
05
Y* ,:>.
.,
~,,x*\ :,.Y (12 Hour Mode) $81-$8C [PM} $81-$92 [PM)
.’..il:.’:
,<.?7- , $. 5
,*. ,$.&:*.> Hours Alarm
~..<:.,
, G23 $m-$17 $W-23 05 05
,.<4$..,>.‘...~l~ (24 Hour Mode)
$?.’.i~i3J
~f*J& Day of the Week -1-7
:*$> 6 $01-s07 $01-$07 05 05
Sunday= 1
7 Date of the Month 1-31 $01-$1 F $01-$31 OF 15
8 Month 1-12 $01-$oc $01-$12 02 02
9 Year 0-99 $00-$63 $00-$98 4F 79

“Example: 5:58:21 Thursday 15 February 1979 (time is AM)

MOTOROLA MC146818/D
12 AD1856R3
 The three alarm bytes may be used in two ways. First,
when the program inserts an alarm time in the appropriate
hours, minutes, and seconds alarm locations, the alarm
interrupt is initiated at the specified time each day if the
alarm enable bit is high. The second usage is to insert a
D “don’t care” state in one or more of three alarm bytes, The
“don’t care” code is any hexadecimal byte from CO to FF,
That is, the two most-significant bits of each byte, when set
to “1”, create a “don’t care” situation. An alarm interrupt
each hour is created with a “don’t care” code in the hours
alarm location. Similarly, an alarm is generated every minute
with “don’t care” codes in the hours and minutes alarm
bytes. The “don’t care” codes in all three alarm bytes create
an interrupt every second.
STATIC CMOS RAM
The 50 general purpose RAM bytes are not dedicated
within the MC148818. They can be used by the processor
program, and are fully available during the update cycle,
When time and calendar information must use battery
back-up, very frequently there is other non-volatile data that
must be retained when main power is removed. The 50 user
RAM bytes serve the need for low-power CMOS battery-
backed storage, and extend the RAM available to the pro-
gram.
When further CMOS RAM is needed, additional
MC1W18S may be included in the system, The time/calen-
dar functions may be disabled by holding the DVO-DV2
dividers, in Register A, in the reset state by setting the SET
bit in Register B or by removing the oscillator. Holding the
dividers in reset prevents interrupts or SQW output from
operating while setting the SET bit allows these functions to
occur. With the dividers clear, the available user RAM is ex-
tended to 59 bytes. The high-order bit of the seconds byte,
D bit 7 of Register A, and all bits of Registers C and D cann#
effectively be used as general purpose RAM.
,>$-
.::i,.$
.?!j,,\ ‘.-<:~!t,
,s.q$t,,,$~p>.,
,$\tfs.~:;,>:,.8,
INTERRUPTS ,~ii
> ,,), .,,,
The RTC plus RAM includes three separate f~$~~~~~fiatic
sources of interrupts to the processor. The .m&tnterrupt
may be programmed to occur at rates fro.~’$~c$per-second
to one-a-day. The periodic interrupt,?~~,$$& selected for
rates from half-a-second to 30,517 Es. ~he updat~ended
i t,j. ‘:~<?
i’!...$.
interrupt may be used to indicatefb ~~rogram that an up-
date cycle is completed. Each%&~J,,M+@ndependentinterrupt
conditions are described in X,a?& detail in other sections.
The processor progra~selewywhich interrupts, if any, it
wishes to receive. Th~#’&,@’t$in Register B enable the three
interrupts. Writing ,,,@,,
1$],’P*X6a interrupt-enable bit permits
that interrupt to ~$~~h$~ed when the event occurs. A “O’ in
the interrupt-mm~bit prohibits the IRQ pin from being
asserted d~&to?$e interrupt cause.
If an ,~nW[r,@t flag is already set when the interrupt
becom#5&~a~led, the l~Q pin is immediately activated,
tha&~~’’~&’?nterrupt initiating the event may have occurred
mu~~~~rlier. Thus, there are cases where the program
shou~ clear such earlier initiated interrupts before first
enabling new interrupts.
MC146818/D
AD1856R3
When an interrupt event occurs a flag bit is set to a “l” in
Register C. Each of the three interrupt sources have separate
flag bits in Register C, which are set independent of the state
of the corresponding enable bits in Register B. The flag bit
may be used with or without enabling the corresponding
enable bits.
In the software scanned case, the program does not
enable the interrupt. The “interrupt” flag bit becomes a
status bit, which the software interrogates, when it wishes.
When the software detects that the flag is set, it is an indica-
tion to software that the “interrupt” evenl occurred sin~~;$~,
bit was last read. .$!iw “+’~~~,~
,*} ‘ ““
~t ‘~
,.i.’~.,
However, there is one precaution. The flag bl~~~%~ister
C are cleared (record of the interrupt event ~~~#@W) when
Register C is read. Double latching is inc[@,@ Wlh Register
C so the bits which are set are stabl$,\~t~~@out the read
cycle. All bits which are high when -d hy’?he program are
:*, .(.
cleared, and new interrupts (on a~ blM@are held until after
the read cycle. One, two, or thf~~~g bits may be found to
be set when Register C is r@&$:~e’program should inspect
all utilized flag bits ever~jtie}Register C is read to insure
that no interrupts are @$j+}~r~p
The second flag ,bit’’~~~e method is with fully enabled
interrupts. Whe&%~. interrupt-flag bit is set and the cor-
responding i~~~&#~~enable bit is also set, the ~Q pin is
asserted lo~]~mi> asserted as long as at least one of the
three int~$,~~~tiurces has its flag and enable bits both set.
The l~QF ~in Register C is a “l” whenever the ~Q pin is
beiti@6@ven low.
;~~~ “~rocessor program can determine that the RTC
$W~R~Qq*d the interrupt by reading Register C. A “1” in bit 7
‘S::J~$lRQFbit) indicates that one or more interrupts have been
,,y. ‘%*initiated by the part. The act of reading Register C clears ail
,,~
the then-active flaa bits, plus the IRQF bit. When the pro-
gram finds IRQF s;t, it should look at each of the individual
flag bits in the same byte which have the corresponding
interrupt-mask bits set and service each interrupt which is
set. Again, more than one interrupt-flag bit may be set.
DIVIDER STAGES
The MCl~18 has 22 binary-dividef stages following the
time base as shown in Figure 1. The output of the dividers is
a 1 Hz signal to the update-cycle logic. The dividers are con-
troller by three divider bus (DV2, DV1, and DVO) in Register
A.
DIVIDER CONTROL
The divider-control bits have three uses, as shown in Table
4. Three usable operating time bases may be selected
(4. IW04 MHz, 1.048576 MHz, or 32.7~ kHz). The divider
chain may be held reset, which allows precision setting of
the time. When the divider is changed from reset to an
operating time base, the first update cycle is one-half second
later. The divider-control bits are also used to facilitate
testing the MCl@18,
MOTOROLA
13
 TABLE 4 – DIVIDER CONFIGURATIONS
I I

E
Divider Bits
Time-Base Operation Divider Bypass First
Frequency Register A
Mode Reset N-Divider Bits
DV2 “DV1 DVO

4. IW304 MHz o 0 0 Yes –

1.046576 MHz o
I
0
I
1
I
Yes
I
– N=2 I
32,768 kHz 010 I Yes – N=7 I

SQUARE-WAVE OUTPUT SELECTION
Fifteen of the 22 divider taps are made available to a
l-of-15 selector as shown in Figure 1. The first purpose of
selecting a divider tap is.to generate a squarewave output
signal at the SQW pin. The RSO-RS3 bits in Register A
establish the square-wave frequency as listed in Table 5. The
SQW frequency selection shares the l-of-15 selector with
periodic interrupts.
Once the frequency is selected, the output of the SQW pin
may be turned on and off under program control with the
square-wave enable (SQWE) bit in Register B. Altering the
divider, squar~wave output selection bits, or the SQWE
output-enable bit may generate an asymmetrical waveform
at the time of execution. The squarewave output pin has a ,~::$r
number of potential uses. For example, it can serve as a fr~
quency standard for external use, a frequency synthesize~, oF@
could be used to
program control.
-:’l:l,A*,*:J
PERIODIC INTERRUPT SE+$,~~lOW
The periodic interrupt,a~~{$%e ~Q pin to be triggered
from once every 5~~J@ “~~ once every 30.517 ps. The
periodic interrupt is *$~#e from the alarm interrupt which
may be output fro~+~#&&per-second to onc~per-day,
Table 5 sh~%tha~the periodic interrupt rate is selected
with the s,@~&,~~~ter A bits which select the square-wave
frequency;, C@hging one also changes the other, But each
func~~~~$~~$be separately enabled so that a program could
s~Jtcfi:@ween the two features or use both. The SQW pin
.,~~.~nabled by the SQWE bit in Register B. Similarly the
#*~~rl@dic interrupt is enabled by the PIE bit in Register B.
‘*>S
,i,:.$
~ ,\\.
‘Periodic interrupt is usable by practically all real-time
systems. It can be used to scan for all forms of inputs from
‘“~. ‘ contact closures to serial receive bits or bytes. It can be used
in multiplexing displays or with software counters to mea-

\!ia,&\L
“ ‘$\?
. ~ %f.,. .,,,,.
\ 4.194304 or 1.W76 MHz 32.766 kHz
s~: y.$\,\:,..>.
~,t~ Time Base Time Base
~~w A Periodic Periodic
I DC* I Den Interrupt Rate SQW Output Interrupt Rate SQW o“t~ut

‘~ololllo
O1o
,
1111
,
! 61.035 #S ! 16,W kHz ! 7,a~25 ms ! 12a Hz
1
I 122.070 #S I a.192 kHz I 122.070 #S a,192 kHz
01110’10 244.141 US 4.096 kHz 2M. 141 11s 4.096 kH7
01110]1 I 488.2al ~S 2.048 kHz w,2al ~S 2.048 kHz
0111110
I I I I
976.W2 AS ,I 1,024 kHz !
1
976,562 US i
1
1.024 kHz I
0111111
, t , 1
1.953125ms I
I
512 Hz 1
1 953175 ms
..-
1
512
------ H7 I
1101010 3-------
~75 ms.,.- 256 Hz 3,90625 ms 256 HZ
1 0 0 1 7,a125 ms
1 12a Hz 7.a~25 ms 12a Hz I
1 0 1 0 15.625 ms 64 Hz 15,625 ms 64 Hz I
1 0 1 1 31.25 ms 32 HZ 31,25 ms 32 HZ
1 1 0 0 62.5 ms 16 Hz 62.5 ms 16 Hz
1 1 0 1 125 ms a Hz 125 ms a Hz
1 I 11110 250 ms I 4 Hz 250 ms 4 Hz
1 1 11 ~ ms 2 Hz ~ ms 2 Hz

MOTOROLA MC146818/D
14 AD1856R3
 UPDATE CYCLE time needed to read valid time/calendar data to exceed
The MC146818 executes an uDdate cvcle once-oer- 244 ps.
second, assuming one of the proper time bases isin place, The third method uses a periodic interrupt to determine if
the DVO-DV2divider isnotclear, andthe SET bit in Register an update cvcle is in progress. The UIP bit in Register A is set
Bis clear. The SET bitinthe’’I’’ state permits the program high between the setting of the PF bit in Register C (see
to initialize the time and calendar bvtes bv stopping an exist- Figure 16). Periodic interrupts that occur at a rate of greater
ing update and preventing new one from occurring. than tBUC + tuc allow valid time and date information to be
The primary function of theupdate cycle is to increment read at each occurrence of the periodic interrupt. The reads
thesecondsbvte, check for overflow, increment the minutes should be completed within .(Tpl + 2) + tBUC to ensure that
bvtewhen appropriate and so forth through tothevearof data is not read during the update cvcle,
the centurv bvte. The update cvcle also compares each To properlv setup the internal counters for davlight sav-
alarm bvte with the corresponding time bvte and issues an ings time operation, the user must set the time at least t~:{
alarm if a match or if a “don’t care” code (1lXXXXXX) is seconds before the rollover will occyr, Likewise, th.9,&~&*J
present in all three positions, must be set at least two seconds before the end of $~;-~th ,i”..
With a 4.194304 MHz or 1.048576 MHz time base the up- or 30th dav of the month. ~t’ii,,i:~?..,:.,,.~.t.
\,R.*
\ Ysl .,,
date cvcle takes 248 KSwhile a 32,768 kHz time base update ,1$,,+.+,. ‘,,~,
REGISTERS ~,$,,t,jth>;},
i
cycle takes 1984 ps. During the update cvcle, the time, calen-
dar, and alarm bvtes are not accessible bv the processor The MC146818 has four registers which<~$d ~~~essible to
program. The MC146818 protects the program from reading the processor program. The four regi~w,~~i~lso fullv ac-
transitional data, This protection is provided bv switching cessible during the update cvcle. . ‘~$~~,~:
‘i\ *
the time, calendar, and alarm portion of the RAM off the
microprocessor bus during the entire update cvcle. If the
processor reads these RAM locations before the update is
complete the output will be undefined. The update in pro-
gress (UIP) status bit is set during the interval,
A program which randomlv accesses the time and date in-
l$;..,.,.:$:.,,,+;
formation finds data unavailable statistically once everv 4032
UIP – The q@&@k progress (UIP) bit is a status flag that
attempts. Three methods of accommodating nonavailabilitv
mav be mOpt&ed~~V the program. When UIP is a “ 1” the
during update are usable bv the program. In discussing the
uDdate cv&R.i& in;roaress or will soon begin, When UI P is a
three methods it is assumed that at random points user pro-
“O’ th~~pda% cvcle;s not in progress and will not be for at
grams are able to call a subroutine to obtain the time of dav.
leaqJ.~&+~s (for all time bases). This is detailed in Table 6.
The first method of avoiding the update cycle uses the
T~~?~e, calendar, and alarm information in RAM is fullv
updat~ended interrupt, If enabled, an interrupt occurs after
‘%PWfe to the program when the UIP bit is zero – it is not
everv update cvcle which indicates that over 999 ms are **,,<...
>.i~~,.
*:/~l~ansition. The UIP bit is a read-onlv bit, and is not af-
available to read valid time and date information. During this
,, f~cted bv Reset. Writing the SET bit in Register B to a “l”
time a displav could be updated or the information could be$~
inhibit anv update cvcle and then clear the UIP status bit.
transferee to continuously available RAM, Before Ieavina tM-
interrupt service routine, the IRQF bit in Register C shou~d’~, ‘J*
fyy:,3$* TABLE 6 – UPDATE CYCLE TIMES
cleared.
Minimum Time
The second method uses the update-in-progres~$~~~~~) Time Base Jpdate CVcle Time
UIP Bit Before Update
in Register A to determine if the update cvcle i~,}&~,Ntess (Oscl) (t”c) Cycle (tB”C)
or not. The UI P bit will pulse once-per-seco~#@~~$tical ly,
1 4,194304 MHz 248 #s —
the U1P bit will indicate that time and d~{,e’’’?~f~~mation is
1 1.048576 MHz 248 ps —
unavailable once everv 2032 attempts. ~$*rWUl P bit goes
high, the update cycle begins 244 ps [<~&l.,~~erefore, if a-low 1 32.768 kHz 1* $s —
is read an the UI P bit, the user ha~ft~~st ’244 ps before the 0 4.194304 MHz — 244 #s
time/calendar data will be chq,-2:&a “1” is read in the 0 1.046576 MHz — 244 KS
U1P“bit, the time/calendar da:?~~~~y not be valid. The user 32.760 ‘kHz — 244 ps
0
should avoid interrupt se~$~ rod~ines that would cause the
+.,*.
\.i,i, ,~>
:%~$+,,
.,,:t,,:~:i~~
“>~\ >
:,ts~.:$.>,
.:,)
-Jiq,, .,.\;+
,3:,“.!:
.“L,, ‘ FIGURE 16 – UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIPS
.’+$;,i,l,
..t
,*L.
f:’.<,, ~*~+~,
,.*I*+\:J%.

+ tpl+2
~ tpl+2
‘~ ‘p’ .%
A
PF bit in
Register C

tpl = Periodic Interrupt Time Interval (5M ms, 250 ms, 125 ms, 62,5 ms, etc. per Table 5)
tuc= Update CVcle Tme (248 ys or 1864 ps)
tBUC = Delay Time Before Update CVcle (244 ps)

MC146818/D MOTOROLA
AD1856R3 15
 DV2, DVI, DVO – Three bits are used to permit the pro- quency specified in the rate selection bits (RS3 to RSO) ap-
gram to select various conditions of the 22-stage divider pears on the SQW pin. When the SQWE bit is set to a zero
chain. The divider selection bits identify which of the three the SQW pin is held low. The state of SQWE is cleared by
tim~base frequencies is in use. Table 4 shows that time the RESET pin. SQWE is a read/write bit,
bases of4.194304 MHz, 1,048576 MHz, and 32.768 kHz may
be used, The divider selection bits are also used to reset the DM – The data mode (DM) bit indicates whether time
divider chain. When the time/calendar is first initialized, the and calendar updates are to use binary or BCD formats. The
program may start the divider at the precise time stored in DM bit is written by the processor program and may be read
the RAM. When the divider reset is removed the first update by the program, but is not modified by any internal functions
cycle begins one-half second later. These three readlwrite or ~. A “l” in DM signifies binary data, while a “O” in
,*!.
bits are not affected by ~, DM specifies binary-coded-decimal (BCD) data. ‘*{,3,
es:<.\.*:<2~,
“*rit. ~
“:,..>> .:
RS3, RS2, RS1, RSO – The four rate selection bits select 24/12 – The 24/12 control bit establishes~h~-~~b’?matof
one of 15 taps on the 22-stage divider, or disable the divider the hours bytes as either the 24-hour m@’~:~&J@!”) or the
output. The tap selected may be used to generate an output 12-hour mode (a “O”). This is a read/~~@{’~~ which is af-
square wave (SQW pin) and/or a periodic interrupt. The pro- fected only by software. ,} J,.
,.i~:~~’ ,~“
~:.,
L*%$i> .4
gram may do one of the following: 1) enable the interrupt ,,>....,5., ..’
with the PIE bit, 2) enable the SQW output pin with the ‘%“~id ~’~
DSE – The daylight sayin’&., ~able (DSE) bit is a
SQWE bit, 3) enable both at the same time at the same rate, read/write bit which allow~~~ghe“’~rogram to enable two
or 4) enable neither. Table 5 lists the periodic interrupt rates .{;’{.>;,
,-{}t:,
, ,,
special updates (when ~~,~~~”~.- 1 ). On the last Sunday in
and the square-wave frequencies that may be chosen with April the time increm~’~~frb~ 1:59:59 AM to 3:00:00 AM.
the RS bits. These four bits areread/write bits which are not On the last Sundav$~8,~$6ber when the time first reaches
affected by RESET. 1:59:59 AM it chafi~@% 1:00:00 AM. These special updates
do not occur,:@@n t~e DSE bit is a “O’. DSE is not changed
REGISTER B ($OB) by any int,~~~~&~@rations or reset.
MSB LSB ,~s”-.$$,\’
Read/Write
b7 b6 b5 b4 b3 b2 bl bo
Register
SET PIE AIE UIE SOWE DM 24/12 DSE LSB
Read-Only
b5]b4 b3 b bl I bO Register
SET – When the SET bit is a “O’, the update cycle func- IAFIUFIOIO]OIO
tions normally by advancing the counts once-per-second,
When the SET bit is written to a “ l“, any update cycle in ‘:w.~$,
~J,\. IRQF – The interrupt request flag (IRQF) is set to a “l”
progress is aborted and the program may initialize the time ~~
and calendar bytes without an update occurring in the ~tist :“ when one or more of the following are true:
of initializing. SET is a read/write bit which is not ~~’f~~d PF=PIE=”l”
by RESET or internal functions of the MC146818.,..,<>\\\,~*e,i.+:~Jt,
‘~’$., ‘“ AF=AIE=”l”
* ,i.
-i:,
~y ,:* ‘$i$ UF=UIE=”I”
PIE – The periodic interrupt enable ,~~@ ,Mt is a i.e., IRQF=PFo PIE+ AFoAIE+UF*UIE
read/write bit which allows the petiodic-@~#~~flag (PF)
bit in Register C to cause the ~ pin to ~k~~$~n low. A pro- Any time the IRQF bit is a “l”, the FQ pin is dflven Iow,
gram writes a “l” to the PIE bit in~~~~,~ receive periodic All flag bits are cleared after Register C is read by the pro-
interrupts at the rate specified by{~~e .,~~~, RS2, RSI, and gram or when the RESET pin is low.
RSO bits in RegisterA. A zero.Jwt@~?ocks ~ from being
initiated by a periodic interru~~,bugthe periodic flag (PF) bit PF – The periodic interrupt flag (PF) is a read-only bit
is still set at the periodic [~teY!~]~s not modified by any in- which is set to a “ 1“ when a particular edge is detected on
ternal MC14W18 fu~cti~~J’but is cleared to “U’ by a the selected tap of the divider chain. The RS3 to RSO bits
RESET. ,,,.: .,x. establish the periodic rate. PF is set to a “ 1” independent of
~>
\\A.~,’*,,
,>~”,$.:~
,~\\
\;“<..,,J$ the state of the PIE bit. PF being a “l” initiates an ~ signal
AIE – The,,&~fi~&terrupt enable (AIE) bit is a read/write and sets the IRQF bit when PIE is also a “l”. The PF bit is
bit which ~~~~~~to a”1” permits the alarm flag (AF) bit in cleared by a RESET or a software read of Register C.
Registe~.@?&~s~&rt ~. An alarm interrupt occurs for each
second~~~at$~e three time bytes equal the three alarm bytes AF – A “l” in the AF (alarm interrupt flag) bit indicates
(in~&4&~&’’don’t care” alarm code of binary 1lXXXXXX). that the current time has matched the alarm time. A “1” in
,~t~%j~fi~ AIE bit is a “O’, the AF bit does not initiate an ~ the AF causes the ~Q pin to go low, and a “l” to appear in
%~d~~otR~;~ ~;~ltAIE to “U’. The internal func- the IRQF bit, when the AIE bit also is a “1,” A RESET or a
read of Register C clears AF,

UIE – The UIE (updateended interrupt enable) bit is a UF – The update-ended interrupt flag (UF) bit is set after
read/write bit which enables the updateend flag (UF) bit in each update cycle. When the UIE bit is a “l”, the “1” in UF
Register C to assert ~, The = pin going low or the causes the IRQF bit to be a “l”, asserting ~Q. UF is cleared
SET bit going high clears the UIE bit, by a Register C read or a RESET.

SQWE – When the square-wave enable (SQWE) bit is set b3 TO bO – The unused bits of Status Register 1 are read
to a “1” by the program, a square-wave signal at the fre as “OS”. They can not be written.

MOTOROLA MC146818/D
16 AD1856R3
REGISTER D ($OD) processors. These interfaces assume that the address
MSB LS B decoding can be done quickly. However, if standard metal-
b7 b6 b5 M b3 b2 bl gate CMOS gates are used the = setup time may be
bo Read Only
violated. Figure 19 illustrates an alternative method of chip
VRT o 0 0 0 0 0 0 Register
selection which will accommodate such slower decoding.
The MCI%18 can be interfaced to singlschip microcom-
puters (MCU) by using eleven port lines as shown in Figure
20, Non-multiplexed bus microprocessors can be interfaced
VRT – The valid RAM and time (VRT) bit indicates the with additional support.
condition of the contents of the RAM, provided the power There is one method of using the multiplexed bus
sense (PS) pin is satisfactorily connected. A “V’ appears in MC146818 with non-multiplexed bus processors. The i~t:~y<,
the VRT bit when the power-sense pin is low. The processor face uses available bus control signals to multip~~ ‘~~$~)
program can set the VRT bit when the time and calendar are address and data bus together. :’<.-
, ‘.)jl.,,t$j$ “
initialized to indicate that the RAM and time are valid. The An example using either the Motorola MC~@3WW2,
VRT is a read only bit which is not modified by the RESET MC~08, or MC~09 microprocessor is sho~.~jm’~fire 21.
pin. The VRT bit can only be set by reading Register D. Figure 22 illustrates the subroutines whiq~”~y-ti used for
data transfers in a non-multiplexed sys{m~j?~~’subroutines
b6 TO bO – The remaining bits of Register D are unused. should be entered with the registers coh~~l,~g the following
They cannot be written, but are always read as “US.” data: $,:\ ,:+
Accumulator A: The addressti~~%+,RTC to be accessed.
WPICAL INTERFACING Accumulator B: Write: T\@~@$~~$obe written.
The MCl@18 is best suited for use with microprocessors Read: ~~~~~fa read from the RTC.
which generate an address-then-data multiplexed bus. The RTC is mapped to t~&?~ecutive memory locations –
Figures 17 and 18 show typical interfaces to bus-compatible RTC and RTC + 1 .~9,sh@n in Figure 21.
-,. $>:
‘<5;$:
.&
~i::,
+s.\$.*,)
. .!’z ~t,},t
,
~?”
,< ‘“<*:*,\

MOTOROLA COMPATIBLE MULTIPLIED BUS Multiprocessors

8 Address/Data Multiplexed

● High-Speed Silicon-
Gate CMOS or TTL
Address Decoding

MC146818/D MOTOROLA
AD1856R3 17
 FIGURE 18- MC148B18 INTERFACED WITH
COMPETITOR COMPATIBLE MULTIPLEXED BUS MICROPROCESSORS

Address Latch Enable IALE)

8085 . * >
Read ~)
8048 Write (Xl Peripherals
~ and Memory
Interrupt Request
8M9
<

8/4 Address

Address
Decode

@ l= Rlfi DS AS A@%k@* $
,>>:.
> RESET
1
m

~,~

FIGURE 19 – M~14681& INTERFACE WiTH MCl~5~

CMOS MULTIPLEXED MICR@~OCESSOR WITH SLOW ADDRESSING DECODING

. ,,, .,,: ,x.

I I

,,:,.
MC146905E2
5-7 Non-multiplexed address

I I

A12

v v——
AS. R/W. .,, IRO
.-. AnO-AD7
.--, .- , I

I
4.194304 MHz
I MC14~18
iTyp)
I
I
I
I
+1
I
&-- — — - — ---------- 4 I
VDD
t
This illustrates the use of CMOS gating for address decoding.

MOTOROLA MC146818/D
18 AD1856R3
 FIGURE 20 – MC146618 INTERFACED WITH THE PORTS OF A
TVPICAL SINGLE CHIP MICROCOMPUTER

4.194304 MHz (TvP)

fin~
Q

MCW70
M C8805
MC 148805
Szm
1 I
MC148818

SQW
8021 ADO-AD7

AS CKFS
DS

RIG

‘9
5 I
I
I
I
I I
I I
I Port I
Lines
L -——- —-—— - ——

,$.
;+ .
,...~,:

FIGURE 21 – MC146618 lNT~~k~D WITH MOTOROLA PROCESSORS

,1,,,

DS

Mclm18

AS

DO-D7 ADO-AD7

Vss’—s

e
C7

MC146818/D MOTOROLA
AD1856R3 19
 FIGURE Z – SUBROUTINE FOR R-DING AND WRITING
THE MC146B18 WITH A NON-MULTIPLIED BUS

MOTOROLA MC146818/D
20 AD1856R3
 PACMGE DIMENSIONS

a r L-
NOTES:
1. POSITIONAL TOLERANCE
OF LEAOS (D) SHALL BE
WITHIN 0.25 mm (O,O1O)AT
MAXIMUM MATERIAL
CONDITION;RELATION
TO SEATING PLANE ANO
EACH OTHER.
2. OIMENSIONLTO CENTER
OF LEAOS WHEN FORMEO
PARALLEL.
~
3. OIMENSION B OOESNOT
~dk
+’LM INCLUOE MOLD FLASH.

VDD

sow
Ps

ADO 4 21 CKOUT

.1 1-
AD1 5 20 CKFS

AD2 6 19 ITQ

AD3 7 18 RESET

u
AD4 8 17 DS

AD5 9 16 NC

AD6 10 15 R[~
AD7 11 14 AS

Vss 12 13 CT

MC146818/D
MOTOROLA
AD1856R3
21
 ,.

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design, Motorola does
not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under ita
patent rights nor the rights of ethers. Motorola and M are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity/
Affirmative Action Employer.

Uterature Distribution Centers:

USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
EUROPE: Motorola Ltd.; European Literature Center; 88 Tanners Drive, Blakelands Milton Keynes, MK145BP, England,
ASIA PACIFIC: Motorola Semiconductor H. K. Ltd.; P. O.. Box 80300; Cheung Sha Wan Post Office; Kowloon Hong Kong.