TIP140, TIP141, TIP142,

(NPN); TIP145, TIP146,

TIP147, (PNP)

Darlington Complementary
Silicon Power Transistors
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Designed for general−purpose amplifier and low frequency
switching applications.
10 AMPERE
Features DARLINGTON
• High DC Current Gain − COMPLEMENTARY SILICON
Min hFE = 1000 @ IC POWER TRANSISTORS
= 5.0 A, VCE = 4 V
60−100 VOLTS, 125 WATTS
• Collector−Emitter Sustaining Voltage − @ 30 mA
VCEO(sus) = 60 Vdc (Min) − TIP140, TIP145
= 80 Vdc (Min) − TIP141, TIP146
= 100 Vdc (Min) − TIP142, TIP147
• Monolithic Construction with Built−In Base−Emitter Shunt Resistor
• These are Pb−Free Devices*

MAXIMUM RATINGS SOT−93 (TO−218)

CASE 340D
TIP140 TIP141 TIP142 STYLE 1
Rating Symbol TIP145 TIP146 TIP147 Unit
Collector − Emitter Voltage VCEO 60 80 100 Vdc
Collector − Base Voltage VCB 60 80 100 Vdc
TO−247
Emitter − Base Voltage VEB 5.0 Vdc
CASE 340L
Collector Current IC Adc STYLE 3
− Continuous 10
− Peak (Note 1) 15

Base Current − Continuous IB 0.5 Adc NOTE: Effective June 2012 this device will
Total Power Dissipation PD 125 W
be available only in the TO−247
@ TC = 25_C package. Reference FPCN# 16827.

Operating and Storage TJ, Tstg −65 to +150 _C

Junction Temperature Range
ORDERING INFORMATION
THERMAL CHARACTERISTICS See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Characteristic Symbol Max Unit
Thermal Resistance, RqJC 1.0 °C/W
Junction−to−Case

Thermal Resistance, RqJA 35.7 °C/W

Junction−to−Ambient
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. 5 ms, v 10% Duty Cycle.

*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2012 1 Publication Order Number:

May, 2012 − Rev. 6 TIP140/D
 TIP140, TIP141, TIP142, (NPN); TIP145, TIP146, TIP147, (PNP)

MARKING DIAGRAMS
TO−247
TO−218

TIP14x
AYWWG AYWWG
TIP14x

1 BASE 3 EMITTER 1 BASE 3 EMITTER

2 COLLECTOR 2 COLLECTOR

TIP14x = Device Code

A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package

DARLINGTON SCHEMATICS
NPN COLLECTOR PNP COLLECTOR
TIP140 TIP145
TIP141 TIP146
TIP142 TIP147

BASE BASE

≈ 8.0 k ≈ 40 ≈ 8.0 k ≈ 40

EMITTER EMITTER

ORDERING INFORMATION
Device Package Shipping
TIP140G SOT−93 (TO−218) 30 Units / Rail
(Pb−Free)
TIP141G SOT−93 (TO−218) 30 Units / Rail
(Pb−Free)
TIP142G SOT−93 (TO−218) 30 Units / Rail
(Pb−Free)
TIP145G SOT−93 (TO−218) 30 Units / Rail
(Pb−Free)
TIP146G SOT−93 (TO−218) 30 Units / Rail
(Pb−Free)
TIP147G SOT−93 (TO−218) 30 Units / Rail
(Pb−Free)
TIP140G TO−247 30 Units / Rail
(Pb−Free)
TIP141G TO−247 30 Units / Rail
(Pb−Free)
TIP142G TO−247 30 Units / Rail
(Pb−Free)
TIP145G TO−247 30 Units / Rail
(Pb−Free)
TIP146G TO−247 30 Units / Rail
(Pb−Free)
TIP147G TO−247 30 Units / Rail
(Pb−Free)

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2
 TIP140, TIP141, TIP142, (NPN); TIP145, TIP146, TIP147, (PNP)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (TC = 25_C unless otherwise noted)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic Symbol Min Typ Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
OFF CHARACTERISTICS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Collector−Emitter Sustaining Voltage (Note 2) VCEO(sus) Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(IC = 30 mA, IB = 0) TIP140, TIP145 60 − −
TIP141, TIP146 80 − −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Collector Cutoff Current
TIP142, TIP147

ICEO
100 − −

mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VCE = 30 Vdc, IB = 0) TIP140, TIP145 − − 2.0
(VCE = 40 Vdc, IB = 0) TIP141, TIP146

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
− − 2.0
(VCE = 50 Vdc, IB = 0) TIP142, TIP147 − − 2.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
Collector Cutoff Current
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VCB = 60 V, IE = 0) TIP140, TIP145
ICBO
− − 1.0
mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VCB = 80 V, IE = 0) TIP141, TIP146 − − 1.0
(VCB = 100 V, IE = 0) TIP142, TIP147 − − 1.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Emitter Cutoff Current (VBE = 5.0 V) IEBO − − 20 mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ON CHARACTERISTICS (Note 2)
DC Current Gain
ÎÎÎ hFE −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(IC = 5.0 A, VCE = 4.0 V) 1000 − −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(IC = 10 A, VCE = 4.0 V) 500 − −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Collector−Emitter Saturation Voltage VCE(sat) Vdc
(IC = 5.0 A, IB = 10 mA)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
− − 2.0
(IC = 10 A, IB = 40 mA) − − 3.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Base−Emitter Saturation Voltage VBE(sat) − − 3.5 Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(IC = 10 A, IB = 40 mA)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Base−Emitter On Voltage VBE(on) − − 3.0 Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(IC = 10 A, VCE = 4.0 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS
Resistive Load (See Figure 1)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Delay Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ td − 0.15 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ms
Rise Time (VCC = 30 V, IC = 5.0 A, tr − 0.55 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ms
IB = 20 mA, Duty Cycle v 2.0%,
Storage Time ts − 2.5 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
IB1 = IB2, RC & RB Varied, TJ = 25_C) ms
Fall Time tf − 2.5 − ms
2. Pulse Test: Pulse Width = 300 ms, Duty Cycle v 2.0%.

10
VCC PNP
RB & RC VARIED TO OBTAIN DESIRED CURRENT LEVELS -30 V
5.0 NPN
D1, MUST BE FAST RECOVERY TYPE, eg:
1N5825 USED ABOVE IB ≈ 100 mA RC ts
MSD6100 USED BELOW IB ≈ 100 mA SCOPE
TUT 2.0
t, TIME (s)

V2 RB tf
μ

approx
+12 V 1.0
D1 ≈ 8.0 k
51 ≈ 40 tr
0
0.5
V1
appox. +4.0 V VCC = 30 V
td @ VBE(off) = 0
-8.0 V 25 ms 0.2 IC/IB = 250
for td and tr, D1 is disconnected
and V2 = 0
IB1 = IB2
tr, tf ≤ 10 ns TJ = 25°C
DUTY CYCLE = 1.0% 0.1
0.2 0.5 1.0 3.0 5.0 10 20
For NPN test circuit reverse diode and voltage polarities.
IC, COLLECTOR CURRENT (AMP)

Figure 1. Switching Times Test Circuit Figure 2. Switching Times

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3
 TIP140, TIP141, TIP142, (NPN); TIP145, TIP146, TIP147, (PNP)

TYPICAL CHARACTERISTICS
NPN PNP
TIP140, TIP141, TIP142 TIP145, TIP146, TIP147
20,000

5000 TJ = 150°C
TJ = 150°C
100°C 10,000 100°C
hFE , DC CURRENT GAIN

hFE , DC CURRENT GAIN

7000
2000 25°C 25°C
-55°C 5000

-55°C
1000 3000

2000
500 VCE = 4.0 V VCE = 4.0 V
300 1000
0.5 1.0 2.0 3.0 4.0 5.0 7.0 10 0.5 0.7 1.0 2.0 3.0 4.0 5.0 7.0 10
IC, COLLECTOR CURRENT (AMPS) IC, COLLECTOR CURRENT (AMPS)
Figure 3. DC Current Gain versus Collector Current
VCE(SAT) , COLLECTOR-EMITTER SATURATION VOLTAGE (VOLTS)

5.0 VCE(SAT) , COLLECTOR-EMITTER SATURATION VOLTAGE (VOLTS) 5.0

3.0 3.0

2.0 2.0 IC = 10 A, IB = 4.0 mA

IC = 10 A, IB = 4.0 mA

IC = 5.0 A, IB = 10 mA IC = 5.0 A, IB = 10 mA
1.0 1.0
IC = 1.0 A, IB = 2.0 mA IC = 1.0 A, IB = 2.0 mA
0.7 0.7

0.5 0.5
-75 -50 -25 0 25 50 75 100 125 150 175 -75 -50 -25 0 25 50 75 100 125 150 175
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 4. Collector−Emitter Saturation Voltage

4.0 4.0
VBE, BASE-EMITTER VOLTAGE (VOLTS)

VBE, BASE-EMITTER VOLTAGE (VOLTS)

3.6 VCE = 4.0 V 3.6 VCE = 4.0 V

3.2 3.2

2.8 2.8

2.4 2.4
IC = 10 A IC = 10 A
2.0 2.0

1.6 5.0 A 1.6

5.0 A
1.2 1.2
1.0 A 1.0 A
0.8 0.8
-75 -25 25 75 125 175 -75 -25 25 75 125 175
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Base−Emitter Voltage

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 TIP140, TIP141, TIP142, (NPN); TIP145, TIP146, TIP147, (PNP)

ACTIVE−REGION SAFE OPERATING AREA

There are two limitations on the power handling ability of The data of Figure 6 is based on TJ(pk) = 150_C; TC is
a transistor: average junction temperature and second variable depending on conditions. At high case
breakdown. Safe operating area curves indicate IC − VCE temperatures, thermal limitations will reduce the power that
limits of the transistor that must be observed for reliable can be handled to values less than the limitations imposed by
operation; i.e., the transistor must not be subjected to greater second breakdown.
dissipation than the curves indicate.

20
IC, COLLECTOR CURRENT (AMP) (mA)

15

IC, COLLECTOR CURRENT (AMPS)

10
7.0 10
5.0
7.0
3.0 dc
5.0
2.0 TJ = 150°C 100 mJ
SECONDARY BREAKDOWN LIMIT
1.0 BONDING WIRE LIMIT
THERMAL LIMITATION @ TC = 25°C
2.0
TIP140, 145
TIP141, 146
0.2 TIP142, 147 1.0
10 15 20 30 50 70 100 0.5 1.0 2.0 5.0 10 20 50 100
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) L, UNCLAMPED INDUCTIVE LOAD (mH)

Figure 6. Active−Region Safe Operating Area Figure 7. Unclamped Inductive Load

VCE MONITOR w ≈ 7.0 ms (SEE NOTE 1)

INPUT 5.0 V
MPS-U52 VOLTAGE 0
COLLECTOR 100 ms
RBB1 100 mH
TUT CURRENT 0
50
INPUT 1.5k VCC = 20 V 1.42 A
50 RBB2 IC
MONITOR VCE(sat)
= 100 -20 V
VBB2 = 0
RS = 0.1 COLLECTOR
VBB1 = 10 V
VOLTAGE

V(BR)CER
TEST CIRCUIT
NOTE 1: Input pulse width is increased until ICM = 1.42 A. VOLTAGE AND CURRENT WAVEFORMS
NOTE 2: For NPN test circuit reverse polarities.
Figure 8. Inductive Load

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5
TIP140, TIP141, TIP142, (NPN); TIP145, TIP146, TIP147, (PNP)

100

hfe , SMALL-SIGNAL FORWARD CURRENT

70 VCE = 10 V
50 IC = 1.0 A
TJ = 25°C
PNP

TRANSFER RATIO
20 PNP
NPN
10 NPN
7.0
5.0

2.0

1.0
1.0 2.0 3.0 5.0 7.0 10
f, FREQUENCY (MHz)

Figure 9. Magnitude of Common Emitter

Small−Signal Short−Circuit Forward
Current Transfer Ratio

5.0
PD, POWER DISSIPATION (WATTS)

4.0

3.0

2.0

1.0

0
0 40 80 120 160 200
TA, FREE-AIR TEMPERATURE (°C)

Figure 10. Free−Air Temperature Power Derating

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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

SOT−93 (TO−218)
CASE 340D−02
ISSUE E DATE 01/03/2002

NOTES:
SCALE 1:1 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
C 2. CONTROLLING DIMENSION: MILLIMETER.
B Q E
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A --- 20.35 --- 0.801
B 14.70 15.20 0.579 0.598
U 4 C 4.70 4.90 0.185 0.193
A D 1.10 1.30 0.043 0.051
S L E 1.17 1.37 0.046 0.054
G 5.40 5.55 0.213 0.219
H 2.00 3.00 0.079 0.118
1 2 3
K J 0.50 0.78 0.020 0.031
K 31.00 REF 1.220 REF
L --- 16.20 --- 0.638
Q 4.00 4.10 0.158 0.161
S 17.80 18.20 0.701 0.717
U 4.00 REF 0.157 REF
V 1.75 REF 0.069

D J MARKING DIAGRAM
H
V
G

STYLE 1: STYLE 2: AYWW

PIN 1. BASE PIN 1. ANODE
2. COLLECTOR 2. CATHODE xxxxx
3. EMITTER 3. ANODE
4. COLLECTOR 4. CATHODE

A = Assembly Location
Y = Year
WW = Work Week
xxxxx = Device Code

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42643B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOT−93 PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

TO−247
CASE 340L−02
ISSUE F
DATE 26 OCT 2011

SCALE 1:1
−T− NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
C Y14.5M, 1982.
−B− 2. CONTROLLING DIMENSION: MILLIMETER.
E
MILLIMETERS INCHES
U L
DIM MIN MAX MIN MAX
A 20.32 21.08 0.800 8.30
N B 15.75 16.26 0.620 0.640
4
C 4.70 5.30 0.185 0.209
A D 1.00 1.40 0.040 0.055
−Q− E 1.90 2.60 0.075 0.102
1 2 3
0.63 (0.025) M T B M F 1.65 2.13 0.065 0.084
G 5.45 BSC 0.215 BSC
H 1.50 2.49 0.059 0.098
P J 0.40 0.80 0.016 0.031
−Y− K 19.81 20.83 0.780 0.820
L 5.40 6.20 0.212 0.244
K N 4.32 5.49 0.170 0.216
P --- 4.50 --- 0.177
Q 3.55 3.65 0.140 0.144
U 6.15 BSC 0.242 BSC
W 2.87 3.12 0.113 0.123
W J
F 2 PL H GENERIC
G
D 3 PL MARKING DIAGRAM*
0.25 (0.010) M Y Q S

STYLE 1: STYLE 2: STYLE 3: STYLE 4: XXXXXXXXX

PIN 1. GATE PIN 1. ANODE PIN 1. BASE PIN 1. GATE
2. DRAIN 2. CATHODE (S) 2. COLLECTOR 2. COLLECTOR AYWWG
3. SOURCE 3. ANODE 2 3. EMITTER 3. EMITTER
4. DRAIN 4. CATHODES (S) 4. COLLECTOR 4. COLLECTOR

STYLE 5: STYLE 6:
PIN 1. CATHODE PIN 1. MAIN TERMINAL 1
2. ANODE 2. MAIN TERMINAL 2
3. GATE 3. GATE
4. ANODE 4. MAIN TERMINAL 2

XXXXX = Specific Device Code

A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.

DOCUMENT NUMBER: 98ASB15080C Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed
STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
NEW STANDARD:
© Semiconductor Components Industries, LLC, 2002 http://onsemi.com Case Outline Number:
DESCRIPTION:
October, 2002 − Rev. 0 TO−247 1 PAGE 1 OFXXX 2
 DOCUMENT NUMBER:
98ASB15080C

PAGE 2 OF 2

ISSUE REVISION DATE

D CHANGE OF OWNERSHIP FROM MOTOROLA TO ON SEMICONDUCTOR. DIM A 25 AUG 2000
WAS 20.80−21.46/0.819−0.845. DIM K WAS 19.81−20.32/0.780−0.800. UPDATED
STYLE 1, ADDED STYLES 2, 3, & 4. REQ. BY L. HAYES.
E DIM E MINIMUM WAS 2.20/0.087. DIM K MINIMUM WAS 20.06/0.790. ADDED 26 FEB 2010
GENERIC MARKING DIAGRAM. REQ. BY S. ALLEN.
F ADDED STYLES 5 AND 6. REQ. BY J. PEREZ. 26 OCT 2011

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
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SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

© Semiconductor Components Industries, LLC, 2011 Case Outline Number:

October, 2011 − Rev. 02F 340L
 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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