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A Reconfigurable 5-To-14 Bit SAR ADC For Battery-Powered Medical Instrumentation
A Reconfigurable 5-To-14 Bit SAR ADC For Battery-Powered Medical Instrumentation
Abstract—In battery-powered medical instrumentation, the range, is highly attractive to also justify the significant costs con-
resolution and signal bandwidth of analog-to-digital converters sisting of research, application specific integrated circuit (ASIC)
(ADCs) have to be adapted to the needs of the application to avoid
power wastage. This paper presents a reconfigurable successive manufacturing, operating costs, and in particular medical regu-
approximation register (SAR) ADC implemented in 130 nm latory approval. However, multi-functional SoCs often experi-
CMOS that resolves 5–14 bit with a maximum achievable effective ence a time-to-market pressure because of their increased de-
number of bits (ENOB) of 13.5 using non-subtractive dither. sign complexity [3]. A solution to this problem is design-reuse
In the proposed ADC design, the power consumption can be
traded for accuracy to improve the energy efficiency and extend [4] which demands for flexible and reconfigurable circuits.
its application range, while reducing system integration com- In this paper, we propose a flexible and reconfigurable ADC
plexity. A figure-of-merit (FoM) of 59 fJ/conversion is achieved to be employed in a multi-channel biomedical ASIC, which
at 1.2 V supply and the converter occupies an area of 0.42 .
Measurement results of the ADC integrated in a multi-channel adapts the performance of the conversion to the characteristics
analog front-end (AFE) circuit show the suitability of the ADC for of the biopotential signals to avoid consuming power on unnec-
portable medical monitoring devices. essary signal bandwidths and accuracies [5]–[7]. Reconfigura-
Index Terms—Analog front-end, biopotential signals, fully dy- tion of the ADC is essential to enhance the lifetime of battery
namic comparator, majority voting, multi-channel biomedical in- powered medical devices. The proposed flexible ADC can be
strumentation, non-subtractive dither, perturbation based digital tuned to operate at ultra low-power to only fulfill minimal spec-
calibration, reconfigurable analog-to-digital converter, successive ifications on the signal quality, e.g., when awaiting activity or a
approximation register. specific pattern in biopotential signals. The system, however, is
able to recover full performance if required, e.g., when activity
I. INTRODUCTION or the specific pattern is detected.
The energy efficiency of the SAR ADC architecture makes
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2686 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 11, NOVEMBER 2015
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FATEH et al.: A RECONFIGURABLE 5-TO-14 BIT SAR ADC FOR BATTERY-POWERED MEDICAL INSTRUMENTATION 2687
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2688 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 11, NOVEMBER 2015
Fig. 4. (a) Timing diagram of SAR ADC to achieve highest resolution without
dithering and (b) a resolution of 6 bit. Each square corresponds to one clock
cycle. A conversion always starts with sampling and ends with a capacitor array
reset. If necessary, the ADC is able to stay for more than one clock cycle in the
reset state. Achieving highest resolution in the ADC requires majority voting
which corresponds to consecutive comparisons and comparator resets in the
LSBs of the ADC.
Fig. 6. Schematic of the on-chip reference buffers for (a) the negative and
(b) positive reference, respectively. For the common-mode reference voltage,
the same reference buffer architecture as designed for the negative reference is
used. It covers a voltage range of 0.1–0.6 V.
D. Reference Buffers
In order to allow the integration of the converter into a multi-
channel medical instrumentation ASIC, the generation of the re-
Fig. 5. Schematic of the implemented double-tail latch (DTL). quired voltage references on-chip is a compelling necessity. For
such reason, a fully-integrated reference buffer has been imple-
and there is no need to perform any resolution enhancement mented [28] and is shown in Fig. 6. The positive and negative
techniques. voltage references are buffered to feed the ADC core. A third
buffer, identical to the one shown in Fig. 6(a), is employed for
the common-mode reference voltage.
C. Dynamic Comparator
The buffer is composed of a feedback loop, made of transis-
A high-speed fully-dynamic double-tail latch (DTL) com- tors M1–M3, and of the operational amplifier, whose task is to
posed of a pre-amplifier and an output latch has been chosen as sense the band-gap voltage and regulate the gate of the output
comparator [23], [24], and is depicted in Fig. 5. Together with transistor M4. A compensation capacitor has been added to
the inverter, the dynamic pre-amplifier provides a limited gain ensure sufficient stability margins. The open-loop output branch
( 10) that reduces the input-referred offset of the regenerative composed of transistors M4–M5 drives the load, ensuring fast
stage. Furthermore, the kick-back noise of the latch does not settling at the maximum speed. The complete buffer occupies a
propagate backwards towards the capacitor array. A single clock silicon area of 0.043 , and consumes 1 mW from the 1.2 V
signal (clk) is sufficient to control the reset and the supply running at maximum speed.
latch phase . With respect to the scheme in [24],
we added two additional programmable capacitors and E. Resistor Ladder DAC
to the input and the output of the inverter to filter the comparator
The 6-bit resistor ladder DAC enables an autarkic calibration,
noise [25]. The capacitor is dimensioned to make the noise
which is crucial when the ADC is used in a system which does
of the inverter negligible. In each comparison the total noise at
not guarantee a sufficiently conditioned input signal at start-up.
the comparator input can be approximated as
The LMS based start-up calibration is particularly unsuited for
acquiring biopotential signals that have a signal component with
small amplitude superimposed to a slowly moving large offset.
The LMS algorithm imposes only two conditions to the input
where is the input transistors transconductance at the latch signal during calibration: a coverage of the signal range and to
toggling instant, and is the noise bandwidth ensure that all capacitors of the array toggle. Thus, there are no
of the comparator input stage [26]. Since also determines the constraints on the linearity and the noise level. Indeed, circuit
energy per comparison, in a power-efficient implementation it noise can be beneficial since it increases the amount of distin-
cannot be made arbitrarily large. For this reason, is chosen to guishable input values, which allows for a fairly simple circuit
render the sampling noise negligible to achieve an overall SNR realization. During calibration, a triangular wave is generated
of about 85.3 dB. The capacitor is configurable between by the R-ladder. The step size and input range of the calibra-
22–800 fF. However, to operate the SAR ADC efficiently, in- tion sequence can be controlled over SPI. Since the R-ladder is
stead of increasing the value of any further, majority voting connected directly to the supply instead of reference voltages,
is performed at the output of the comparator to provide pro- the 6-bit DAC is even able to go above the input range of the
grammable noise performance at different bit cycles during a ADC. However, digitally controlled resistors are used to scale
conversion [27]. the signal range of the DAC to the one of the SAR ADC.
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FATEH et al.: A RECONFIGURABLE 5-TO-14 BIT SAR ADC FOR BATTERY-POWERED MEDICAL INSTRUMENTATION 2689
Fig. 7. Top-level block diagram of the digital calibration unit and area distri-
Fig. 8. Fixed-point MATLAB simulation of the SAR ADC resolution before and
bution of the main building blocks relative to the total digital area [13].
after calibration for different unit capacitors using 1000 Monte Carlo simulations.
The learning factors have been chosen equal to μ and μ ,
In the presented SAR ADC, a 6-bit resistor ladder has been respectively.
implemented which occupies only a small fraction of the overall
circuit area, that is 0.012 . The learning factors μ and μ determine the convergence
III. DIGITAL START-UP CALIBRATION speed and the precision of the weights. Since the input needs
to be sampled twice, we calibrate the capacitor array during
The capacitor array mismatch is corrected by means of the
start-up and disable the calibration in normal operation to re-
perturbation-based algorithm proposed in [8], [10], which has
cover full speed and to save power. It takes about 5000 samples
been implemented directly on-chip to avoid the need for ex-
before LSB, which is equivalent to a convergence
pensive off-chip computation. A block diagram of the digital
time of 17.5 ms at 286 kS/s. With smaller learning factors
calibration unit is shown in Fig. 7. The calibration sequence is
which can be controlled through the SPI interface, the LMS is
generated by the resistor-ladder DAC discussed earlier.
able to estimate the capacitor values with higher precisions and
Notation: The following notation will be used in the re-
convergence times.
mainder of this paper. Lowercase boldface letters stand for
The achievable resolution of the calibrated SAR ADC was
column vectors having elements, where is the
evaluated from MATLAB Monte Carlo simulations for different
number of SAR iterations required to resolve each sample. The
unit capacitor values, and is shown in Fig. 8. Capacitor mis-
th entry of a vector at time instant k is denoted by .
match is based on the characterization data of the employed
A. Perturbation Injection 130 nm CMOS technology. Each point in the plot represents the
average of 1000 independent simulations with a calibration time
The implementation of the calibration algorithm requires that of samples. A random (up to ) offset on each capacitor
an analog offset is injected into the sampled signal in order to has been added to simulate the effect of capacitor mismatch.
generate two different digital output codes from the same input. Thermal noise is added to the samples, whereas the comparator
This is accomplished with a minimum overhead of two addi- noise is neglected in this analysis.
tional perturbation capacitors which can be connected to either In the current implementation, a unit capacitor value of
the positive or the negative reference, as depicted in Fig. 2. 70 fF has been chosen as a good trade-off between precision
and speed. The LMS based digital calibration improves the
B. Calibration Algorithm
resolution by about 11 dB (1.8 ENOB).
Because the capacitor array is not binary weighted, the two
generated output codes are first converted to a binary represen-
tation according to C. VLSI Circuit Implementation
In order to minimize the power consumption, the calibration
(1) unit is only operating during start-up and is switched off after-
wards using clock gating. The digital circuitry is partitioned into
where is the -th resolved bit of the non-binary three main parts: the memory unit, the correction unit, and the
output code, and is the bit weight of the capacitor array. LMS update (or calibration) unit, as depicted in Fig. 7.
If all the weights of the array were exactly known, the differ- Two shift-registers, denoted as and , are employed at
ence between the two output codes would be identical to twice the input to store the output decision of the comparator for
the digital representation of the analog offset. An error func- both the positive and the negative injected perturbation. In order
tion for LMS can therefore be defined as to correct the resolved sample, the capacitor weights and
the perturbation value are stored in the memory unit. The
correction unit loads the weight vector and adds them according
If is not zero, the calibration algorithm updates the value to (1). A SPI interface is used at the output to minimize the
of the weights trying to minimize the LMS of the error signal, number of required pads.
according to the update equations For minimum area occupation, no multipliers but only three
adders and shift operations are employed. The digital calibration
unit measures 0.156 , corresponding to 28.4 kGE (one gate
equivalent GE corresponds to a 2-input drive-1 NAND gate).
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2690 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 11, NOVEMBER 2015
Fig. 12. Measured output spectrum before (blue) and after (black) calibration
without dithering with a 1.6 input signal at 1.98 kHz. ( points FFT).
Fig. 9. Micrograph of the stand-alone SAR ADC test chip with the most im-
portant sub-circuits marked. The digital circuitry is roughly divided in its main
blocks.
Fig. 13. Measured output spectrum before (blue) and after (black) calibration
with dithering with a 1.6 input signal at 1.98 kHz. ( points FFT).
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FATEH et al.: A RECONFIGURABLE 5-TO-14 BIT SAR ADC FOR BATTERY-POWERED MEDICAL INSTRUMENTATION 2691
TABLE I
COMPARISON OF OUR SAR ADC WITH RECENTLY PUBLISHED MEDIUM-TO-HIGH PRECISION SAR ADCS
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2692 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 11, NOVEMBER 2015
Fig. 15. Architecture block level diagram of our multi-channel biomedical data Fig. 16. Chip micrograph of the multi-channel biomedical data acquisition
acquisition system employing the proposed SAR ADC. ASIC employing the presented SAR ADC.
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2694 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 11, NOVEMBER 2015
Schekeb Fateh (S’03) received the M.S. degree Giovanni Rovere received the M.S. degree in elec-
in electrical engineering from the Eidgenössische trical engineering from the University of Padova,
Technische Hochschule (ETH) Zurich, Switzerland, Padova, Italy, in 2013. He was a visiting student
in 2009. In the same year, he joined the Integrated at the Institute of Neuroinformatics, UZH-ETH,
Systems Laboratory (IIS) of ETH Zurich, where he Zurich, Switzerland. From 2013 to 2014 he was
is currently pursuing his Ph.D. degree. His research an Asynchronous Digital Designer at the Italian
interests include the design of high-speed analog Institute of Technology, Italy, involved in the design
and mixed-signal circuits and systems for wireless of a de/serializer for event-driven vision sensor
communications with emphasis on analog-to-dig- for robotic applications. He is currently working
ital converters as well as the implementation of towards the Ph.D. degree in the Integrated Systems
multi-purpose low-power and miniaturized biomed- Laboratory at ETH, Zurich. His current research
ical devices. Currently, he is Researcher at IIS and Senior Design Engineer at focuses on biomedical acquisition systems, focusing on low power analog front
ACP AG. He received (jointly with Dr. Studer and Dr. Seethaler) the Swisscom end.
and ICTnet Innovations Award 2010 for the work on “VLSI Implementation
of Soft-Input Soft-Output Minimum Mean-Square Error Parallel Interference
Cancellation.”
Luca Benini is Full Professor at the University of
Bologna and he is the chair of Digital Circuits and
Systems at ETHZ. Dr. Benini’s research interests are
Philipp Schönle received the B.Sc. and M.Sc. de- in energy-efficient system design and Multi-Core
grees in electrical engineering from the Swiss Fed- SoC design. He is also active in the area of en-
eral Institute of Technology (ETH), Zurich, Switzer- ergy-efficient smart sensors and sensor networks for
land, in 2009 and 2011, respectively. Currently, he is biomedical and ambient intelligence applications.
working towards the Ph.D. degree in the Integrated He has published more than 700 papers in peer-re-
Systems Laboratory at ETH. His research focuses on viewed international journals and conferences, four
analogue sensor front-end design. books and several book chapters. He is a member of
the Academia Europaea.
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