ELECTRICAL ENGINEERING DEPARTMENT

ACADEMIC SESSION: JUNE 2020

DEC50143 – CMOS IC DESIGN AND FABRICATION
Layout Design and Simulation of CMOS Inverter (NOT Logic
PRACTICAL WORK 2:
Gate)
PRACTICAL WORK
08/09/2020
DATE:
LECTURER’S NAME: Noor Laila Asha’ari
GROUP NO:
TOTAL
STUDENT ID & NAME: MARKS
(100%)

(1) Heryanshah Bin Suhimi @Suhaimi (07DTK18F1016)

DATE SUBMIT: DATE RETURN:

Part 1 : Designing and simulating horizontal CMOS inverter layout.

1) Microwind has been used to perform this practical work

2) Cmos012.rul has been used for foundry file.

3) A CMOS inverter has been designed in horizontal using NMOS and PMOS. There is
no error message appear after checking it using ‘Design Rule Check’. For this
practical work, I’ve used my own design instead of the suggested design on the lab
sheet.

Figure 1.1 – Horizontal CMOS inverter layout

4) After checking the design, A input clock as been added and appropriate setting has been
applied. Visible node ‘Output’ has been added to CMOS inverter output to see , whether
the output is as expected or not.

Figure 1.2 – Clock setting for Input

5) After all the setup, the simulation has been run to test the layout design.

Figure 1.3 – The simulation of Horizontal CMOS Inverter

6) At the end of the design, the layout area must be measured using ruler on microwind.

Figure 1.4 – Optimized Area Layout = 78 λ x 49 λ = 3822 λ2

Part 2 : Designing and simulating CMOS inverter layout with dual contact and substrate.

1) In this part, the CMOS Inverter Layout has been designed as suggested on the lab
sheet. The CMOS Inverter Layout has been designed without error.

Figure 2.1 -The layout

2) Using the same input clock setting at Part A, the clock has been added at input.

Figure 2.2 – Input Clock Settings

3) After that, the layout has been tested using simulation

Figure 2.3 – The Simulation

Part 3 : Designing the layout of IC 4069 (CMOS inverter ).

1) Using CMOS inverter design at part 1, the CMOS inverter has been duplicated
to six to make an IC for IC 4069.

Figure 3.1 – IC 4069 layout

2) To make advanced testing, all the input has been added clock that high after
0.2ns and low at 0.2ns. For every output on inverter was added visible node to
observe whether the output appear as expected or not.

3) No error is found, then the layout design has been tested using simulation.
 Figure 3.2 – Simulation

4) After the simulation is run, the layout area has been measured.

Figure 3.3 – Optimized Area Layout = 252 λ x 198 λ = 49,896 λ2

RESULT:

Part 1: Horizontal CMOS Inverter

i. Inverter Layout

ii. Input/Output Diagram

iii. Layout Area = 67 λ x 26 λ = 1742 λ2

 Part 2: CMOS Inverter with dual contacts and substrate

i. Inverter Layout

ii. Input/Output Timing Diagram

iii. Layout Area = 40 λ x 62 λ = 2480 λ2

Part 3: IC 4069 (CMOS Inverter Gate IC)

i. IC Layout

b) The optimized area of the IC layout = 252 λ x 198 λ = 49,896 λ2

DISCUSSION:

1. Explain the operation of NMOS and PMOS transistors in CMOS inverter by using a suitable
diagram.

When Vi = 0 ,
PMOS switch is ON and
NMOS switch is OFF

Else or When Vi = 1,
PMOS switch will be OFF
and NMOS switch will be
ON.

2. Make a comparison between the optimized area of the layouts in Part 1 and Part 2 and explain your
findings.

Part 1 Part 2
1. Horizontal CMOS inverter 1. Vertical CMOS inverter
2. Using one contact 2. Using two contacts
3. No Substrate 3. Have Substrate

3. Explain the difference between an inverter from the TTL 7400 families and from the CMOS 4000
families.

TTL 7400 families CMOS 4000 families

1. Use FETs 1. Use BJTs
2. High input resistance 2. Low input resistance
3. Low power consumption 3. High power consumption

CONCLUSION:

- Every MOS have their layout and I’m able to draw the layout of Horizontal inverter layout,
Inverter with dual contact layout and substrate IC 4069 layout. Both of layout produce same output
since both are inverter.
- Every MOS layout have its area and size and it can be calculated on Microwind ruler utility
 PRACTICAL SKILL ASSESSMENT RUBRIC
DEC50143 CMOS IC DESIGN & FABRICATION
PRACTICAL WORK 2
Student Name : HERYANSHAH BIN SUHIMI @SUHAIMI Class : DTK5A – S1
Date :
Student ID# : 07DTK18F1016

SCORE DESCRIPTION
ASPECTS EXCELLENT MODERATE POOR SCALE SCORE
4-5 2-3 1
Use correct technology feature Use correct technology feature
A. Technology feature Use other technology feature. x1
for ALL parts of the layout. for parts of the layout.
Follow lambda design rule for
Follow lambda design rule for Follow lambda design rule for
B. Design rule minimum width and spacing for x1
MANY of the polygons. ONLY a few of the polygons.
ALL polygons.
Use correct PMOS and NMOS Use acceptable PMOS and NMOS Use incorrect PMOS and
C. Transistor size x2
transistor size. transistor size. NMOS transistor size.
Use correct number of metal Use correct metal layers but Use incorrect metal layers and
D. Metal layers x2
layers and width. incorrect width. width.
‘No DRC error’ Able to produce ‘No DRC error’ Able to produce ‘No DRC error’ Not able to produce ‘No DRC
E. x2
display display for ALL layouts. display for some of the layouts. error’ display at ALL.
Layout Design Produce acceptable floorplan
Produce good floorplan and Produce appropriate floorplan
F. – input / output / and input / output layout x2
input / output layout design. and input / output layout design.
floorplan design.
Not able to produce any
Able to produce the simulation Able to produce the simulation
G Layout simulation simulation for ALL of the x2
of ALL layouts correctly. for some of the layouts correctly.
layouts.
Layout size (end Produce small layout size (end Produce acceptable layout size Produce large layout size (end
H. x2
product) product). (end product). product).
TOTAL / 70

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Supervisor Name & Signature