PLLs are ubiquitous in RF and mixed signal circuits.

They are utilized as on-chip clock frequency generators to synthesize the higher internal frequency
from the external lower frequency.

noise problems:
Reflection Noise Due to impedance mismatch, stubs, vias and other interconnect discontinuities.
Crosstalk Noise Due to electromagnetic coupling between signal traces and vias.
Power/Ground Noise Due to parasitics of the power/ground delivery system during drivers’ simultaneous switching
output (SSO). It is sometimes also called Ground Bounce, Delta-I Noise or Simultaneous Switching Noise (SSN)
Power/Ground Noise
Power/ground noises occupy 30%+ noise budget in today’s high-speed design.In chip package and printed circuit board,
power/ground planes with vias form power distribution networks. Transient currents drawn by a large number of devices
(core-logic, off-chip drivers) switching simultaneously can cause voltage fluctuations between power and ground planes,
namely the simultaneous switching noise (SSN), or Delta-I noise, or power/ground bounce. SSN will slow down the signals
due to imperfect return path constituted by the power/ground distribution system. It will cause logic error when it couples to
quiet signal nets or disturbs the data in the latch. It may introduce common mode noise in mixed analog and digital design.
And it may increase radiation at resonant frequencies. With ever-increasing IC transition speed and I/O count, packages with
new emerging technologies are capable of switching under 200 ps transition time and sinking up to 20 A of power supply
current.
Inductance effects
Inductance effects in on-chip interconnect structures have become increasingly significant due to longer metal interconnects,
reductions in wire resistance (as a result of copper interconnects and wider upper-layer metal lines) and higher clock
frequencies. These effects are particularly significant for global interconnect lines for high-performance circuits. On-chip
inductance impacts these in terms of delay variations, degradation of signal integrity due to overshoots, Higher device
densities and faster switching frequencies cause large switching currents to flow in the power and ground networks which
degrade performance and reliability. Excessive voltage drops in the power grid reduce switching speeds and noise margins of
circuits, and inject noise which might lead to functional failures. High average current densities lead to undesirable wear of
metal wires due to electromigration. Therefore, the power distribution network must provide excellent voltage regulation at
the consumption points notwithstanding the wide fluctuations in power demand across the chip, while using minimum area
of the metal layers.

Early Mode IR-drop Analysis

At the very early stages of power distribution network design, one needs to address various issues including locations of
the clean VDD/GND pads, nominal pitches and widths of metal layers, via styles (point or bar vias), and parameters of
the chip package. Since at this early stage of the design, the power network has not yet been synthesized and the location
and logic content of the blocks are not known, IR-drop analysis is performed using very simplistic models of the grid
topology and the block currents.
• A mock power grid is constructed using a uniform grid topology, based on user-specified pitch and width for each layer.
• To model the currents drawn by the devices, a simple area-based DC estimate of the current is used.
• Using length-based resistance formulae, a resistive electrical network is constructed for the mock topology.
Fast DC analysis of this network yields the IR-drops at various locations and allows the designer to evaluate different
topologies and to trade-off robustness and metal utilization in the grid
Impedance
Electrical Impedance (Z), is the total opposition that a circuit presents to alternating current. Impedance is measured in ohms
and may include resistance (R), inductive reactance (XL), and capacitive reactance (XC). However, the total impedance is not
simply the algebraic sum of the resistance, inductive reactance, and capacitive reactance. Since the inductive reactance and
capacitive reactance are 90o out of phase with the resistance and, therefore, their maximum values occur at different times,
vector addition must be used to calculate impedance
Whereas a resistor opposes (restricts) a flow of current, an inductor opposes a change of flow of current. So, it allows the
current to flow freely, but it will not let the current flow change rapidly. There is a delay and the change occurs more slowly
than it would if the inductor were not in circuit.
This process of generating electrical current in a conductor by placing the conductor in a changing magnetic field is called
electromagnetic induction or just induction. It is called induction because the current is said to be induced in the conductor
by the magnetic field. Induction is measured in unit of Henries (H) which reflects this dependence on the rate of change of
the magnetic field. One Henry is the amount of inductance that is required to generate one volt of induced voltage when the
current is changing at the rate of one ampere per second. Self-inductance, or simply inductance, is the property of a circuit
whereby a change in current causes a change in voltage in the same circuit. When one circuit induces current flow in a second
nearby circuit, it is known as mutual-inductance. When an AC current is flowing through a piece of wire in a circuit, an
electromagnetic field is produced that is constantly growing and shrinking and changing direction due to the constantly
changing current in the wire. This changing magnetic field will induce electrical current in another wire or circuit that is
brought close to the wire in the primary circuit. It should be noted that since it is the changing magnetic field that is
responsible for inductance, it is only present in AC circuits. High frequency AC will result in greater inductive reactance
since the magnetic field is changing more rapidly.
In the case of self-inductance, the magnetic field created by a changing current in the circuit itself induces a voltage in the
same circuit. Therefore, the voltage is self-induced. The alternating current running through the coil creates a magnetic field
in and around the coil that is increasing and decreasing as the current changes. The magnetic field forms concentric loops that
surround the wire and join to form larger loops that surround the coil as shown in the image below. When the current
increases in one loop the expanding magnetic field will cut across some or all of the neighboring loops of wire, inducing a
voltage in these loops. This causes a voltage to be induced in the coil when the current is changing.

By studying this image of a coil, it can be seen that the number of turns in the coil will have an effect on the amount of voltage
that is induced into the circuit. Increasing the number of turns or the rate of change of magnetic flux increases the amount of
induced voltage

VL = induced voltage in volts

N = number of turns in the coil
dø/dt = rate of change of magnetic flux in webers/second
In a circuit, it is much easier to measure current than it is to measure magnetic flux, so the following equation can be used to
determine the induced voltage if the inductance and frequency of the current are known. This equation can also be
reorganized to allow the inductance to be calculated when the amount of inducted voltage can be determined and the current
frequency is known.

VL = the induced voltage in volts

L = the value of inductance in henries
di/dt = the

Inductive Reactance The reduction of current flow in a circuit due to induction is called inductive reactance. rate of change of
current in amperes per second. Lenz's law, it can be seen how inductance reduces the flow of current in the circuit. In the
image below, the direction of the primary current is shown in red, and the magnetic field generated by the current is shown in
blue. The direction of the magnetic field can be determined by taking your right hand and pointing your thumb in the
direction of the current. Your fingers will then point in the direction of the magnetic field. It can be seen that the magnetic
field from one loop of the wire will cut across the other loops in the coil and this will induce current flow (shown in green) in
the circuit. According to Lenz's law, the induced current must flow in the opposite direction of the primary current. The
induced current working against the primary current results in a reduction of current flow in the circuit. It should be
noted that the inductive reactance will increase if the number of winds in the coil is increased since the magnetic field from
one coil will have more coils to interact with.

Similarly to resistance, inductive reactance reduces the flow of current in a circuit. However, it is possible to distinguish
between resistance and inductive reactance in a circuit by looking at the timing between the sine waves of the voltage and
current of the alternating current. In an AC circuit that contains only resistive components, the voltage and the current will be
in-phase, meaning that the peaks and valleys of their sine waves will occur at the same time. When there is inductive
reactance present in the circuit, the phase of the current will be shifted so that its peaks and valleys do not occur at the same
time as those of the voltage.
AC Resistor Circuits

Pure resistive AC circuit: voltage and current are in phase. Voltage and current “in phase” for resistive circuit.If we were to
plot the current and voltage for a very simple AC circuit consisting of a source and a resistor, (Figure above) Because the
resistor allows an amount of current directly proportional to the voltage across it at all periods of time, the waveform for the
current is exactly in phase with the waveform for the voltage. We can look at any point in time along the horizontal axis of the
plot and compare those values of current and voltage with each other (any “snapshot” look at the values of a wave are
referred to as instantaneous values, meaning the values at that instant in time). When the instantaneous value for voltage is
zero, the instantaneous current through the resistor is also zero. Likewise, at the moment in time where the voltage across the
resistor is at its positive peak, the current through the resistor is also at its positive peak, and so on. At any given point in time
along the waves, Ohm's Law holds true for the instantaneous values of voltage and current.

Instantaneous AC power in a resistive circuit is always positive.

Note that the power is never a negative value. When the current is positive (above the line), the voltage is also positive,
resulting in a power (p=ie) of a positive value. Conversely, when the current is negative (below the line), the voltage is also
negative, which results in a positive value for power (a negative number multiplied by a negative number equals a positive
number). This consistent “polarity” of power tells us that the resistor is always dissipating power, taking it from the source
and releasing it in the form of heat energy. Whether the current is positive or negative, a resistor still dissipates energy.
Capacitors do not behave the same as resistors. Whereas resistors allow a flow of electrons through them directly
proportional to the voltage drop, capacitors oppose changes in voltage by drawing or supplying current as they charge or
discharge to the new voltage level. The flow of electrons “through” a capacitor is directly proportional to the rate of
change of voltage across the capacitor. This opposition to voltage change is another form of reactance, but one that is precisely

opposite to the kind exhibited by inductors . Pure capacitive circuit: capacitor voltage lags
capacitor current by 90o

Pure capacitive circuit waveforms => Remember, the current through a capacitor is a reaction against the change in voltage
across it. Therefore, the instantaneous current is zero whenever the instantaneous voltage is at a peak (zero change, or level
slope, on the voltage sine wave), and the instantaneous current is at a peak wherever the instantaneous voltage is at
maximum change .This results in a voltage wave that is -90o out of phase with the current wave. Looking at the graph, the
current wave seems to have a “head start” on the voltage wave; the current “leads” the voltage, and the voltage “lags” behind
the current.

Voltage lags current by 90o in a pure capacitive circuit. In a pure capacitive circuit, the instantaneous power may be positive or negative.
As with the simple inductor circuit, the 90 degree phase shift between voltage and current results in a power wave that
alternates equally between positive and negative. This means that a capacitor does not dissipate power as it reacts against
changes in voltage; it merely absorbs and releases power, alternately. A capacitor's opposition to change in voltage translates
to an opposition to alternating voltage in general, which is by definition always changing in instantaneous magnitude and
direction. For any given magnitude of AC voltage at a given frequency, a capacitor of given size will “conduct” a certain
magnitude of AC current. Just as the current through a resistor is a function of the voltage across the resistor and the
resistance offered by the resistor, the AC current through a capacitor is a function of the AC voltage across it, and the reactance
offered by the capacitor. As with inductors, the reactance of a capacitor is expressed in ohms and symbolized by the letter X
(or XC to be more specific). Since capacitors “conduct” current in proportion to the rate of voltage change, they will pass more
current for faster-changing voltages (as they charge and discharge to the same voltage peaks in less time), and less current for
slower-changing voltages. What this means is that reactance in ohms for any capacitor is inversely proportional to the
frequency of the alternating current:

For a 100 uF capacitor:

Frequency (Hertz) Reactance (Ohms)
----------------------------------------
| 60 | 26.5258 |
|----------------------------------- -- |
| 120 | 13.2629 |
|--------------------------------------|
| 2500 | 0.6366 |
---------------------------------------- Please note that the relationship of capacitive reactance to frequency is exactly opposite from
that of inductive reactance. Capacitive reactance (in ohms) decreases with increasing AC frequency. Conversely, inductive
reactance (in ohms) increases with increasing AC frequency. Inductors oppose faster changing currents by producing greater
voltage drops; capacitors oppose faster changing voltage drops by allowing greater currents. As with inductors, the reactance
equation's 2πf term may be replaced by the lower-case Greek letter Omega (ω), which is referred to as the angular velocity of
the AC circuit. Thus, the equation XC = 1/(2πfC) could also be written as XC = 1/(ωC), with ω cast in units of radians per second.
Alternating current in a simple capacitive circuit is equal to the voltage (in volts) divided by the capacitive reactance (in
ohms), just as either alternating or direct current in a simple resistive circuit is equal to the voltage (in volts) divided by the
resistance (in ohms). The following circuit illustrates this mathematical relationship by example: Capacitive reactance.
 Voltage lags current by 90o in an inductor.

However, we need to keep in mind that voltage and current are not in phase here. As was shown earlier, the current has a
phase shift of +90o with respect to the voltage. If we represent these phase angles of voltage and current mathematically, we
can calculate the phase angle of the capacitor's reactive opposition to current. Mathematically, we say that the phase angle of
a capacitor's opposition to current is -90o, meaning that a capacitor's opposition to current is a negative imaginary quantity.
(Figure above) This phase angle of reactive opposition to current becomes critically important in circuit analysis, especially for
complex AC circuits where reactance and resistance interact. It will prove beneficial to represent any component's opposition
to current in terms of complex numbers, and not just scalar quantities of resistance and reactance.

REVIEW:

 Capacitive reactance is the opposition that a capacitor offers to alternating current due to its phase-shifted storage and
release of energy in its electric field. Reactance is symbolized by the capital letter “X” and is measured in ohms just
like resistance (R).
 Capacitive reactance can be calculated using this formula: XC = 1/(2πfC)
 Capacitive reactance decreases with increasing frequency. In other words, the higher the frequency, the less it opposes
(the more it “conducts”) the AC flow of electrons.

When and Where to Consider Inductance Inductance is a single measure of the distribution of the magnetic field created by a
current. Since line inductance is negligible at low clock speeds, on-chip interconnect is conventionally modeled only with RC
components;
However, when the clock frequency enters the gigahertz regime, the impedance contributed by the line inductance (jωL)
becomes comparable to the line resistance R, and can even dominate the total metal impedance (Z = R + jωL) of global lines.
The impact of inductance manifests in many important circuit design issues; it not only increases the signal delay but may
also cause voltage overshoot and reduced slew rate, which can increase crosstalk noise on neighboring lines.

Inductive Coupling Noise Continuous increases in operating frequency and global line length not only lead to pronounced
inductance effects, but also exacerbate crosstalk noise in the nanometer regime. There are two fundamental differences
between capacitive crosstalk and inductive crosstalk:
1. Polarity of noise. In capacitive coupling, crosstalk noise [C(dV/dt)] always occurs in the same direction as the aggressor
switches. However, inductive coupling induces noise [L(dI/dt)] through the return current, which opposes the direction of the
aggressor switching and occurs more instantaneously than does C(dV/dt). Hence, given an aggressor switching, inductive
noise generally has the opposite polarity of capacitive noise and appears earlier in time,
For RC lines, the most effective way to reduce interconnect delay through tuning is to increase the wire width. Wider lines
generally have less delay because when the width is increased, the reduction of resistance occurs faster than the increase in
total capacitance
Some simple rules of thumb for RC net tuning are:
1. To reduce delay, increase interconnect width (more effective than increase spacing) or insert repeaters.
2. To reduce crosstalk, increase spacing (more effective than increase width), reorder nets, or insert repeaters. Some simple
rules of thumb for RC net tuning are:

Widening the wire can lead to more inductance on the dominant line, which can exhibit inductive ringing and extra delay.
Furthermore, the increase of loop inductance caused by the increase of wire spacing will offset some benefits of the reduction
in coupling capacitance. When wide lines are needed to drive a large load, they may need to be divided into small fingers
interspersed with VDD/GND shields.
The use of VDD/GND as shield wires within high-speed buses is the most common design technique to limit signal-line
coupling, but at the cost of an increased routing area. It effectively eliminates capacitive coupling and the associated delay
uncertainty. For RLC nets, ground shields provide close current-return paths and reduce the loop inductance. They also
reduce the inductive noise generation because the magnetic field outside the pair occurs in opposite directions and cancel
each other Repeater Insertion Repeater (buffer) insertion is a key solution for reducing the large delay of long interconnects,
but with the penalty of increased chip area and power consumption. This technique breaks down long interconnects
and inserts drivers (repeaters) in between the resulting segments. It also vastly
improves signal slew rate at the far-end receiver because of the regenerative
nature of CMOS drivers.
Also in
practice, the repeaters are usually implemented by a cascaded inverter pair to
achieve the best delay reduction
This small noise is easily suppressed by the regenerative nature of
the buffer. For inductive noise coupling, the length of the original current return
path is now shortened by returning the current through the repeaters, resulting in
a smaller current loop and hence smaller inductive coupling.
The repeaters are offset so that each gate is placed in the middle of its neighboring
gates’ interconnect loads.
With
staggered repeaters, the delay uncertainty due to neighboring wire switching
condition can be greatly reduced.

New ideas have emerged in recent years to drive a long interconnect

more efficiently, including the regenerative booster [60,61]. Unlike repeaters, the
booster is attached along the wire to locally enhance the transmitted signal and
does not intrude on the interconnect routing. It senses when a voltage transition
is occurring on interconnect and provides an additional current boost to speed
up the transition.

Keeper Circuit Dynamic gates are often used in performance-critical units of

microprocessors and other high-performance VLSI circuits. Unlike static CMOS
gates, the charge lost from a dynamic node due to noise cannot be restored, and
as a result, dynamic gates are more vulnerable to noise than static CMOS gates.
Dynamic floating nodes can be avoided by employing a static path through a
pull-up and/or pull-down device referred to as a keeper (Figure 8.24) [62]. The
keeper circuit restores the lost charge due to coupling noise, charge sharing, and
subthreshold leakage current. However, with increasingly large noise and leakage
current, the keepers much be sized up accordingly, which can significantly
degrade the performance of dynamic circuits.
Differential Signaling Differential signals are inherently more robust to noisy
environments than single-ended signals.

The basic idea behind differential signaling is illustrated in Figure 8.25, in which
two tightly coupled lines are used to transmit the data differentially. At the receiving location, these two signals are compared
to determine their logic polarity. Differential signaling can be implemented in both voltage and current modes. The
differential signaling approach offers a high rejection of common-mode interferences such as crosstalk noise and supply-rail
variations. It also provides other advantages compared with single-ended signaling, including: (1) it has a built-in nearby
return path for every signal wire, so less noise is coupled to
other nets; (2) because of its high noise immunity, a low signal swing can be used to reduce power consumption—operation
with swings as low as 200 mV has been demonstrated; and (3) the signal is isolated from the supply rails and the associated
noise, making all supply noise occur in common mode to the differential receiver, which is usually designed to have excellent
common-mode rejection. However, implementation of this technique comes with significant costs because it requires 2 × N
routing tracks for N signals. Also, the transmitter
and receiver require extensive design management and may still be vulnerable to clock skew and jitter variations. For future
generations of high-performance circuits, when the inductive noise become a significant issue on-chip as the chip operation
frequency increases or when the skew generated by the power noise is too high, this technique may become a promising
solution for on-chip interconnections.