J=S Step 3: Draw the circuit of SR flip-flop using si Fig. 3.24. SR flip-flop using JK flip-flop A group of flip-flops connected together to form a register. Those regisie capable of counting the number of clock pulses arriving at its clock input is call counter. ‘A counter is a sequential circuit consisting a set of flip-flops to count the sequen the input pulses in digital form. The input pulses may be clock pulses or any other source. The sequence of states may follow the binary number or any other sequen states. A counter that follows the binary number sequence is called binary counter. bit binary counter consists of n-flip-flops and it can count in binary from 0 to 2-1. Counters can be classified into two categories. {i) Asynchronous Counter (or) Ripple Counter Counters are classified according to input of the clock pulse. Since we know tha counter are the sequential circuit consists of a set of flip-flop connected together.synchronous Counter jn synchronous counter, the input of the clock Pulse of all flip-flops receives the clock pulse. ie., a common clock Pulse is parallelly connected to all the flip- ‘ASYNCHRONOUS (OR) RIPPLE COUNTER Abinary ripple counter consists ofa series connection of complementing flip-flops with output of each flip-flop connected to the clock input of the next higher order flip-flop. Mie flip-flop holding the least significant bit receives the incoming clock pulses. A jeanlementing flip-flop can be obtained from a JK flip-flop with the J and K input tied pgether or from a T flip-flip and the third Possibility is to use a D flip-flop with the gomplement output connected to the D input. The D input is always the complement of the present state, and the next clock pulse will cause the flip-flop to complement. Consider a two bit ripple counter using JK flip-flop as shown below. Q Fig. 3.25. Two-bit Ripple Counter ; The number binary bit is equal to the number of flip-flops. For two bit binary value, it ired two JK flip-flops. The first flip-flop carry the LSB bit, so the input clock is given othe first flip-flop (A) and the output of first flip-flop is given to the clock of second flip- ®P. 4e., Q, is given to the clock input of second flip-flop (B).is triggered by the Qa output of the fal gation delay time through a Tipo s 7 of the Qa output of first flip-flop " fore, the two flip-flops are vel unter operation. " (00, 01, 10, 11). This outp i e. There’ | lustrated by the fo! Qs a oo | 00 ot ie Counter = | output Fig. 3.26. Timing diagram for 2-bit rip! The changes in the state of the flip-flop outputs are response to the clock. 4 The negative-going edge of CLK-I causes the Qa output of first flip-flop to go! (HIGH). It causes no effect on second flip-flop because a negative-going transitin must occur to trigger the flip-flop. ‘After the leading edge of CLK-1, Qa = 1 and Q,= 001). + The negative-going edge of CLK-2 causes the Q, to go 0 (LOW) and it trigger the second flip-flop, Qp to go 1 (HIGH). After the leading edge of CLK-2 Q,=0, and Qp =! (10). 4 The negative-going edge of CLK-3 causes the Qy to go 1 (HIGH) again and itis no effect on second flip-flop, Qg has 1 (HIGH). After the leading edge of CLK? Qu = 1 and Qp = 1 (11). & on ee edge of CLK-4 causes the Q to go 0 (LOW) and it causes the 1p to go 0 (LOW). After the leading edge of CLK-4 Q, = 0 and Qp = 0 (00). | Three-Bit Ripple Counter Je counter For a 3-bi a "1 or a 3-bit counter, it required 3-flip-flops. Consider the 3-JK flip-flop and connect | them serially with the conditic ion of asynchronous counter. The counter output should be —= hy,3.35 100, 101, 110, 111. It is illustrated with the following counter design 1} it: ° 011 8 + 1 ‘ T |p) 1 1 ! (b) Timing diagram Fig. 3.27. Three-Bit Ripple Countereee Digital g), z = AS (0000 | 0001 | 0010 (b) Timing diagram Fig. 3.28. Four-Bit Ripple Counter | sat aswcHtONoUSBOWN COUNTERS “| We discussed about the Up counter which is incremented by one from zero maximum count. Now we are going to it will count downward from a maximum count to zero. Consider a 3-bit synchronous down counter using JK flip-flops. discuss Down counter which decrement by one je HIGH — ta. “Onl dg Os Hd o— Chk +} cee kK, A = Kp Sis] fc, Q ms oo Q, Q A IB Fig, 3.29. 3-Bit Asynchronous Down Counter Here the clock si i A .. aad E connected to the clock input of only first flip-flop. This triggered by the Qy ait en However the clock input of the remaining flip-ios" le previous stage instead of Q, output of the previous su The output of the ‘ Counter is fro i maximum count is 111, then the out m the maximum count to zero. For 3-bit count" 1s 111, 110, 101, 100, 011, 010, 001, 000.Cire ni fiming diagram gives the count of Down counter. oe Ch = W 1 | 2LJal Ia] Fel2rs ; apd ie 1 ' { ! ri ' ' r | ic ee ag a oe | t { ' \ i { i 1 { 110 | ! t ' 100 | O11 ! col ! Fig. 3.30. Timing Diagram of 3-bit Asynchronous Down Counter eee nO LS counter has the capability of counting from zero to maximum count as well maximum count to zero. To activate the Up counter as well as Down counter, one #gpt Up DOW is necessary to control the operation of the up/down counter. en Up/ Down = 0, the counter will count down and Up/ Down = 1, the counter will ctv. TO achieve this, the M input should be used to contro! whether the normal flip- capt (Q) oF the inverted flip-flop output (Q) is fed to drive the clock signal of the pesve tage flip-flop. ces {etus form the Truth Table for Up/Down counter with respect to Up/ Down control Output ey: Qs| 0 0 0 0 0 | 1 Y =Q for down 1 0 0 counter 1 fi 1 0 0 0 0 1 0 Y =Q for Up 1 0 1 counter i 1 iDigital py. p/Down Q ae y = Up/Down Q+U input of each higher flip-flop. Depending ty n to the clock n counter or up counter. ut Y is give one? he counter will act as dow control input Up/ Down t Consider a 3-bit up/down counter. = es vupldawn + aaa Se HIGH —q— Lt ea, 2D aR tia Qe Ds ck b> Ke Ge [ee Ke oH Fig. 3.31, 3-bit asynchronous up/down counter When Up/ Down =I, it enables the AND gates 1 and 2 and disables AND gate 3 ani! | This allows the Q, and Qp outputs to drive the clock inputs of their respective next stags So that counter will be a up counter. When Up/Down Down = 0, it enables the AND gates 3 and 4 and disables AND gate al 2. This allows the ome and Q% outputs to drive the clock inputs of their respective stages. So that counter will bea down counter. | The following timing diagram gives the count of up/down counter. e ithe clock pulse of all flip-flops e ives 4 the} time in successi red to ripple counter. ‘synchronous Counter ion as in a ripple countes, y * er. ley common clock pulse, han one at @ jon delay comp er and Synchronous Counter rrison Of: Asynchronous Count [Anchoress = 1. _| All the flip-flops are not clocked ‘All the flip-flops are clocke | simultaneously. bs simultaneously. el No common clock input. Propagation delay is more. Logic circuit is Very. simple. Minimum number of logic devices More number of ‘lo are needed. needed than Ripple counter. Very cheaper, “Coster than pple counter. {i) Two-Bit synchronous Up Counter we r - $ e know that for a two-bit counter, it required two flip-flops. Consider a two JK-fi quired vo JK fin} input. The clock signal is connected in parallel to clock input 4 0 flop and a common clock i both the fli ip-flops. But the Qa output of first stage is used to drive the J and K inputs oft sof the second stage. Fig. 3.33. Two-bit Let oes it synch us see the operation of circuit. ronous counter Initially the counter bi a er Sry positive edge of the states is 0 ie, bi = CLK- , both the = 2 LK-1 occurs, the first Aono Me a RESET. Whe " — R le because J, = Ka”?ci aa [3.41] if jp-flop output will remai ig! snd fli lop iP ill remain zero because J Bet hn 000 use Ja = Ky = 0. Le, after iy a ix! inane ease OF CLK-2 occurs, the first flip-flop will toggle tee tip-top has a HIGH (Q, = 1) on its Jy and gle and Q, will go ee Jy and Ky inputs at the triggering Ny a lock pulse, the flip-flop toggles and Q, goes HIGH, Thus afler CLK-2, Qy ye edge of CLK-3 occurs, the firs i pe leans edge of CL occurs, the first flip-flop toggles to SET state ie second flip-top remains SET (Qy = 0) because its Jy and Ky inputs and both la’? 20) ‘After this triggering edge Qy = 1 and Qy = 1 (11), Fe vaya leading exige of CLK-4, Qa and Qs go low bec ont" on their J and K inputs i.2., Q, = Qy = 0 (00), ise they both have a Justrated in the following timing diagram. Boel LeU this operation is il ‘ | i } ' \ | \ | | | | oe | 1 Geen 0 | ORO) qt 0 | 98 1 1 1 caer [ oo} of } 10 | 14 |} oo | ' ' ' i | - } Fig. 3.34. Timing diagram of Two-Bit Synchronous Up Counter i) hree-Bit synchronous Up Counter = % Op Forathree-bit counter, it required three flip-flops. Fig. 3.35. Three Bit Synchronous Up Counter Weknow the operation of two-bi synchronous up counter.Digital g1.. > e first flip-flop (Q,) and second flip-flop (Q, 8) are i inthree-bit counter, the output of fo AND function and then pass (© the Jc and Ke pecause the output of second 4,1 (Qy) goes 10 the opposite S ring the CLK 2, CLK 4, CLK 6 andCLK8, Alipay 1 ‘To produce the correct operation» Q is connected to the Ja and Ky of first fino | when Qy = | and a clock pulse occurs, the first flip-flop 1s" toggle mode ang lip changes its state Sema 2" remain in the present state. there Qe changes state both times, it is preceded by the unique condition in which condition is detected by the AND gate and applied to 5 both Qt Ne Joao ED and Qp are HIGH. This Ke. Whenever Qa = Oy respective flip-flop toggles on the following ©! are held low by the AND gate and the third {flip-flop does not change its state. a oo ieee . e AND gate makes the Jo = Ke =] co | and = |, the output of th Jock pulse. Otherwise the Jo and Ki Py { { oo1 } o10 | 011 1 1 ! on foes 9 mw | Fig. ing diagram of Three-Bit inchronous Up Counter ig. 3.36. Timi ig diag! of Three-Bit Sy h Up Countei (iii) Four-Bit Synchronous Up Counter For a four-bit counter, it required four-flip-flops. HIGH Oy ne Qcqt 0 \ felt: H (0110 | 0111 ! 1000! 1001 0000 | 1 { i +o t 1 : | } ra ano | ai | era st hoi! eet ay Poot (b) Timing diagram 37. Four-Bit Synchronous Up Counter nt the sequence in downward i.e., from maximum count to zero. counter, which has the maximum count of 1111, so it counts from 3.38. Four-Bit ‘Synchronous Down Counter tary outputs are connected to the input of - all the ———Pigital py Coty, with AND operated : ~ d Kp are connected wit AND operated output of @ a imilarly, Jp 204 SD and Qp- Sit ilar Qe sranently 1, flip-flop A ghiness a in the occ, since J, and Ka are Pa pulse The flip-flop B chang: pes ate when 6 3, secavewansion task c0CK PU rp. nop C chan sme the flip-flop toggles: ene Fa at boa input, Similarly, flip- op D changes ’ ane i A ed wien there is negative transition at clock input, when Q= =05 Ss i et 10 Initially all the flip-flops are St dge of OnOs = 1111. At negative Qe QcQ Qs Q Qq= 110 Similarly it count downward to 0000 step by step for cay a fr 80e 08 On LG signal. nter is 1111, 1110, 1101, 1100, 1011, 1010, 109), ih The count output of the cou! 11, 0110, 0101, 0100, 0011, 0010, 0001 and 0000. : he count ofid gown counter. Tie follows fol owing timing esr Ui tl cou ; produce ‘I’ outputs i.e., Maximum, | first clock pulse, the output condition thay tt a =. 3.39. Timing diagram of Four-bit Synchronous Down Counter 3.6.3, SYNCHRONOUS UP/DOWN COUNTER A Up/Down counter has the capability of counting from zero to maximum count asi8 wi | as from maximum count to zero, To activate the up down, one control input Up! Dow! [Dow § necessary to control the operation of the up/down counter. | When Up/ Down =0, the counter will count down and Up/Down Down = 1, the counters } count up. Similarly to the asynchronous up/down counter (Sec 3.5.3). | ——|) it enables the AND gates 3 and 4 and disables AND gate land respective next afl Q3 outputs to drive the clock inputs of their ill be a down counter.