CHAPTER 2 COMBINATIONAL CIRCUITS Design procedure ~ Half adder ~ Full adder ~ Half subtractor - Full subtractor ~ Parallel binary | sader, parallel binary subtractor ~ Fast adder ~ Carry look ahead adder ~ Serial adder/subtractor | BCD adder - Binary multiplier ~ Binary divider ~ Multiplexer/Demultiplexer ~ Decoder ~ Encoder | ~ parity checker ~ Parity generators ~ Code converters ~ Magnitude comparator. Design of logic circuit for digital systems may be a combinational or sequential. Both the circuits are interconnections of logic gates and variables. But the difference states the storage (or) memory elements. | Combinational Circuits ‘A combinational circuit consists of logic gates whose outputs at any time are determined from only the present combination of inputs (ie., the output of circuit only depends on the present combination of inputs). ‘A combinational circuit performs an operation that can be specified logically by a set of Boolean functions. A combinational circuit consists of an interconnection of logic gates. Combinational logic gates react to the values of the signals at their inputs and produce the value of the output signal, transforming binary information from the given input data to a required output data. A block diagram of a combinational circuit shown below. I eae, } a eye | | X, ——+} Y | | minputs Xp ———+| Combinational Circuit[23] Here the m input binary variables come from an external source and m i a i I logic circuit i are produced by the internal combinationa logi ‘uit and Biven e N destination, \ 2.1, DESIGN PROCEDURE The design of combinational Circuits starts from the SPECification of objectives and ends in a logic circuit diagram or a set of Boolean fiy logic diagram can be obtained, “eh nctions from ‘ My Step by Step Procedure to Design of Combinational Circuit Step 1: From the Specification, determine the required (Number of inputs (i) Number of outputs and assign a symbol to each, Step 2: Derive the truth table that dk lefines the Fequires relationshi, ip between input, ie outputs, (Minimum number of gates @ Minimum number (i) Minimum pro (i) Minimum nui of inputs to a Bate. Pagation time of, the signal through the circuit. imber of interconnections, (©) Limitations of the driving capabilities Of each gate SOLVED EXAMPLES Step 1: From the speci fication,‘ymbinational Circuits In the given objective, there are, % Vinputs namely A, B,C & Loutput it is named as *Y? Stop 2: Derive the truth table from the objectives In the given problem, it states that the output is 1 whenever the input A or C, both A and C are logic | : : : inati 1, Here 3 inputs, therefore 2” = 2" 8, combination of inputs are possible, Input | B Input Cis 1 Input C is 1 Input A is | and also A and C is 1 in two combination BC 000 10024 Step 4: Draw the logic diagram for the output Y: Y= A+tC Renee Te L fecsesst (J Fig. 2.2. Logie diagram Example 2.2 | Design a combinational cireuit with three inputs and one outpy, () The output is 1 when the binary value of the input is less than 6. Other, output is 0. (ii) The ouput is 1 when the binary value of the input is an even number, (iti) The ouput is 1 when the binary value of the input is an odd number. © Solution: Step 1: Determine the required number of input and outputs. From the objective, there are + 3 inputs named as A, B,C 1 output named as Y. | () The output is 1 when the binary value of the input is less than 6, othervie output is 0. Step 2: Equivalent | Input Output a a ora Output will be 1 for the binary Value less than 6.‘The ontpst is 1 when the binary value of inputs is an even number. Suep?: Troth Tableonal Circuits Sombinn cl? Com Ficops ovis the simplified expression BG oa A Btea6 Alo nee | (alga ele w the logic diagram ee DM the t step Design a combinational circuit with three inputs, x ABC ; ys 2 and three When the binary input is 0, 1, 2 or 3, the binary output is one greater than Lae hen the binary input is 4, 5, 6 or 7, the binary output is two less than the input. he solution? ‘The inputs are x, y, z and outputs are A, B, C, ose ihe objective, we know the required logic. From for input 0, 1, 2, 3, the output is one greater and for input 4, 5, 6, 7. The output is | ies san by 0. Equivalent Input__| _ Output decimal xl/y/z/alBic Greater by one Less than by twoi ig. 2.6. Li ogic diagram B=xX¥+YZ+ XYZ @ Solution: ie, aaput. The output is high Design a combinational logic circuit ifboth A and B are ‘The given objective is the output is I. y = 1 if A=B=1 or y= 1 if C>Dal that has four inputs and one high or C and D are high.Obtain simplified exprenion for Y. Draw the logic diagram A a eb AW Au ep 0 AB 0 G AD Yea AND | 42 { pals i AND Fig. 2.7, Log Input 0 Cc » 0 0 0 ! 1 0 | | 0 0 0 ! 1 0 | 1 0 0 0 ! 1 0 | 1 0 Hae oR We Magram,inational Cirewits sign a combinational logic eireuit with three in i ; Put variable and The output will be | when more than one input variables = Output variable are logic | /) The output will be 1 when more than one input BD ae aed. C+ BC + AB ic (Ans. ¥ = A+ BE + AC) BINARY ADDER ~ SUBTRACTOR Digital computers perform a variety of information processing tasks, among thar ymon function are various arithmetic operations. The most basic srithmetie yas auldition of two binary digits, The simple addition with two variable consists of tone ible element. 040 =.0 O+1=1 1+0 = 1 I+1 = 10 the first three operations produce a sum as one digit, but when both the digits are |, the sum consists of two digits. In this condition, the higher significant bit of this result alled a ‘carry’. A combinational circuit that performs the addition of two bits is called a ‘half adder’. d the circuit which performs addition of three bits i.¢., with two significant bits and a ious carry is called a ‘full adder’. + ee 1. HALF ADDER eee age ee | The half adder performs addition operation on two binary inputs and produce two ary output as a sum and a carry bit.Sum = AB+AB = A@B Logic Diagram Sum = A ®B is Ex-OR operation, LApe B | | Ex-OR oo = Carry = AB | | AND | Fig. 2.9. Logic diagram fop half adder 2.2.2. FULL ADDER Full Adder Fig. 2.10. Logic symbolnal Circuits —pinational con" — gap simplification K or sum: or carry? e. "Ae bog BGs BCin BS_ Al} o|l@| 0 | A|@] 0 | a sum = ABC,, + ABC, + ABC, + ABC, BCin BCin BCin BCin BCin (1\| 0 0 0 CTT) |) = = Ca¥ AB+BC, > }2\¢ ° 2 —Digital El °C, m 2.14 Implementation of Full Adder using Half Adder { FIRST HALF ADDER ‘SECOND HALF ADDER a cae Ure | cman, €* | t a i =A®B@ G ' (A®B)Cn | { Cout ! = (A®B) Ca oy Fig. 2.11. Logic diagram of full adder using half adder Sum = C,, ® (A @ B) => ABC,, + ABC,, + ABC,, + ABC,, ie, Sum = ABC), + ABC,,+ ABC, + ABC, = C,, (AB + AB) +G,, (AB + AB) = Cin (A © B)+C,, (A ® B) = Cin(A ®B)+C,, (A@ B) Sum = Cin ® (A @ B) he above sum can be obtained by n to two half r vy the cascade connectio ircui (0 half adder circuit, = AB+AC,,+BC,, (A+ A) ~ AB+AC, + ABC, + ABC, = AB(I+C,)+AC, +ABC,, = AB+ AC,, + ABC,, = AB+AC,,(B+B)+ABC,, = AB+ABC,, + ABC,, + ABC, = _AB(1+C,)+Ci, (AB + AB) a = ABYCa(ASB)]Half Subtractor Borrow (Br) Fig. 2.12. Logic symbol A Fig. 2.13. Logic diagram. for half subtractor The fll subtractor performs subtraction operation on three binary inputs and produce sadifference and a carry bit. The three inputs consists of two significant bits and a | \gevions stage borrow.P| ee Fig. 2.14. Logic symbol Coe aos bE ie-une 2 Sim K-Map Simplification For D: D = ABB, + ABB, + ABB,, + ABB,, [ be Ease aaa A\_BBin_BBin BBin BBin | 4] 0 |G [@pry For B, | Al ooo] (i) | eae bal Lea Boy = ABj, + AB + BB, Logic Diagram = ABB, +ABB,, + ABB,, + ABB, = AB+AB,+BB,,ional Circuits Fig. 215. jon Full Subtractor using Half Subtractor = ABB,, + ABB, + ABB,, + ABB,, B,, (AB + AB) + B,, (AB + AB) B,, (A @ B) + Bj, (A ® B) in plement at pifference, D B,, (A © B) + B,, (A ® B) in D = B,®A@B AB+ AB, + BBiy AB + ABiq + BB), (A+ A) AB + ABi, + ABBi, + ABB AB + AB, (1 +B) + ABBj, AB + ABj, + ABBj, 5 B. outDigital by AB + AB, (B +B) + ABB _ AB+ABB,, + ABB;, + ABBi, AB (1 + Bi.) + Bin (AB + AB) = AB+B,,(A © B) B,, = AB+By(A@B) Logic Diagram SECOND HALF SUBTRACTOR FIRST HALF SUBTRACTOR D=A@BOp, | | | Bout =AB + By (A@B) Fig. 2.16. Logic diagram of full subtractor using half subtractor