EE5320 ANALOG IC DESIGN

PROJECT
INTER-STAGE GAIN AMPLIFIER FOR A 12-
BIT 100 MSAMPLES/SEC TWO-STEP ADC

Submitted By:
P.Aravind (EE17M090)
Akhilesh Chandra Sati (EE17M059)
Benson M. Sunny (EE17M061)

1
DESIGN APPROACH:

 In order to meet the settling error requirements the DC gain of the

amplifier has to be more than 94dB and the open loop gain bandwidth has

to be more than 1.83GHz which cannot be met by a single stage

amplifier. So a two stage amplifier configuration is chosen.

 The first stage of the amplifier is implemented with a folded cascode

architecture because it provides high gain along with better ICMR as

compared to telescopic amplifier, CS differential amplifier.

 In order to meet gain spec gain boosting technique is implemented for the

folded cascode architecture.

 The trade-off for implementing folded cascode architecture is more

power dissipation and more noise as compared to telescopic.

 The second stage of the amplifier is implemented with CS amplifier so as

to get large output swings to maximize Peak SNR.

 In order to stabilize the Common mode voltages at the outputs of first and

second stages of the amplifier, two CMFB loops are employed.

2
SCHEMATIC:

Figure 1 Schematic of Fully Differential Feedback Amplifier

Figure 2 Schematics of CMFB loop for 1st (left) and 2nd (right) stage

3
 Parameters
W (μm) L (μm) gm (mS) Id (mA)
Vod(V)
Transistor
M1 4000 4 47.8 7.71 0.259
M2 1035 0.25 29.6 2.03 0.075
M3 400 4 6.13 0.86 0.25
M4 1000 1 41.3 3.86 0.152
M5 1000 1 41.3 3.86 0.152
M6 500 1 20.7 2.03 0.164
M7 500 1 20.7 2.03 0.164
M8 500 1 21.1 2.03 0.16
M9 500 1 21.1 2.03 0.16
M10 1035 0.25 29.6 2.03 0.075
M11 985 0.25 53.6 5.89 0.175
M12 985 0.25 53.6 5.89 0.175
M13 98.5 0.25 6.62 0.86 0.214
M14 189.38 0.18 2.41 0.12 0.042*
M15 189.38 0.18 2.41 0.12 0.042*
M16 1400 0.18 443 63.6 0.183
M17 8360 0.24 553 63.6 0.183
M18 1400 0.18 443 63.6 0.211
M19 8360 0.24 553 63.6 0.183
M20 5 1 0.273 0.0342 0.222
M21 5 0.25 0.281 0.0338 0.195
M22 5 0.25 0.281 0.0338 0.195
M23 2.5 1 0.135 0.0167 0.218
M24 2.5 1 0.135 0.0167 0.218
M25 2.5 0.25 0.144 0.0167 0.186
M26 2.5 0.25 0.146 0.0171 0.188
M27 2.5 0.25 0.146 0.0171 0.188
M28 2.5 0.25 0.144 0.0167 0.186
M29 15 0.5 1.27 0.12 0.15
M30 15 0.5 1.27 0.12 0.15
M31 2.4 0.24 0.131 0.0138 0.164
M32 2.4 0.24 0.132 0.0139 0.165
M33 2.5 1 0.131 0.0138 0.164
M34 2.5 1 0.132 0.0139 0.165
M35 5 1 0.238 0.0276 0.198

*M14, M15 operate in subthreshold region

4
 PERFORMANCE TABLE
Simulated
Design parameter/variable Specification
performance
Supply voltage 1.8V ≤ 1.8V

Closed loop gain 3.9992 4

≤ 2.0 × 10−4
Settling error (static + dynamic) 1.7× 10−4 V
V
Load capacitance (CL) 4pF 2pF

Settling time 4.78ns ≤ 5ns

Peak SNR 64.34dB ≥ 62dB

Differential r.m.s noise voltage [µV] 282.45* -

THD (Fin = 1MHz) -71.44dB ≤ -70dB

THD (Fin = 49MHz) -42.02dB ≤ -70dB

Amplifier core power consumption [mW] 250.792 Minimum

Bias power consumption [mW] 1.54 Minimum

Total power consumption [mW] 252.34 Minimum

Differential DC loop gain (vod = 0) [dB] 99.4 -

Differential DC loop gain (vod = vod,max) [dB] 91.52 -

Differential loop-gain unity gain bandwidth
650.28 -
[MHz]
Differential loop-gain phase margin [deg] 64.71 -

Differential loop-gain gain margin [dB] 31 -

Common-mode loop-gain UGB 1st stage [MHz] 13.34 -

Common-mode loop-gain PM 1st stage [deg] 75.83 -

Common-mode loop-gain UGB 2nd stage [MHz] 2.56 -

Common-mode loop-gain PM 2nd stage [deg] 89.87 -

*Since there is no for provision for plotting differential O/P noise in LTspice single ended
O/P noise plot has been taken as well for peak SNR calculation.

5
6
7
Figure 3 Differential-mode loop-gain AC response

8
Figure 4 Differential-mode DC loop gain versus differential output swing

9
Figure 5 Common-mode Feedback 1st stage loop-gain AC response

Figure 6 Common-mode Feedback 2nd stage loop-gain AC response

10
 Figure 7 Positive step response with maximum-allowed input step of 130mV

Figure 8 Positive step response with maximum-allowed input step of 130mV (zoomed-in plot)

11
 Figure 9 Negative step response with maximum-allowed input step of 130mV

Figure 10 Negative step response with maximum-allowed input step of 130mV (zoomed-in plot)

12
Figure 11 Single-ended output noise versus frequency plot

13
Figure 12 Output spectrums of ∼1MHz output sine-wave with maximum-allowed O/P swing = 2.72V pk-pk

Figure 13 Output spectrums of ∼49MHz output sine-wave with maximum-allowed O/P swing = 2.5V pk-pk

14
REFERENCES :
1. ‘A Low-Power Class-AB Residue Amplifier for a 12bit 500MS/sec
Pipeline ADC with Digital Calibration’ thesis by Md. Shakil Akter.

2. B. Razavi ‘ Design of Analog CMOS integrated Circuits ’. Mcgraw Hill

Education. Indian Edition

15
16