FOUR BIT FULL ADDAR DISPLAYED IN DECIMAL

SYSTEM

by

Safia Mansoor
BCS183086

A Project Report submitted to the

DEPARTMENT OF COMPUTER
SCIENCE
in partial fulfillment of the requirements for the
degree of BACHELORS OF SCIENCE IN
COMPUTER SCIENCE

Faculty of Computing
Capital University of Science & Technology,
Islamabad
May, 2020
DECLARATION
It is declared that this is an original piece of my own work, except where
otherwise acknowledged in text and references. This work has not been submitted in
any form for another degree or diploma at any university or other institution for tertiary
education and shall not be submitted by me in future for obtaining any degree from this
or any other University or Institution.

Safia Mansoor
BCS183086

May, 2020

ii
 ACKNOWLEDGMENT

I would like to thank first and foremost Allah Almighty for his never ending grace. I
am highly obliged to my supervisor, Mr. Ahmed Ali for giving me the opportunity to
work on this project and giving me the knowledge and advice to complete this project
with ease. We dedicate this acknowledgement to all my professors who shared their
ideas and guided me during our project making process.

iii
 ABSTRACT

Digital computation lies at the basis of nearly all modern pursuits of knowledge.
This computation is performed utilizing only a single voltage, manipulating the voltage
on or off to simulate a base two number of either a one or a zero. Numerous logic
devices have sprung up to implement computations in this digital space, and most
modern computers perform their computations through the use of addition and nothing
else. The half adder, and consequently the full adder, makes everything in the Central
Processing Unit possible. Their logic may be extended through the use of a carry out
signal to another adder, all the way up to an arbitrary amount of n bits. In the interest of
minimizing complexity the four-bit binary adding machine was chosen to showcase
these fundamentals of computer processing. In order to realize binary computation, a
circuit design was first approached through the use of a Simulation Program with
Integrated Circuit Emphasis (SPICE). Once the SPICE was complete, a working circuit
was implemented with integrated circuit logic gates on a solderless breadboard.

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 TABLE OF CONTENTS

DECLARATION ..................................................................................................... ii
ACKNOWLEDGMENT ......................................................................................... iii
ABSTRACT ........................................................................................................... iv
LIST OF FIGURES ................................................................................................ vi
Chapter 1 ................................................................................................................. 1
INTRODUCTION ................................................................................................... 1
1.1 Overview .................................................................................................................................... 1
1.2 Project Idea................................................................................................................................. 1
1.3 Purpose of the Project ................................................................................................................ 2
1.4 Project Specifications ................................................................................................................ 3
1.5 Applications of the Project ........................................................................................................ 4
1.6 Project Plan ................................................................................................................................ 4
1.7 Report Organization .................................................................................................................. 4
Chapter 2 ................................................................................................................. 5
LITERATURE REVIEW ........................................................................................ 5
2.1 Background Theory ................................................................................................................... 5
2.2 Related Technologies ................................................................................................................ 5
2.2.1 Related Technology 1 ................................................................................................ 5
2.2.2 Related Technology 2 ................................................................................................ 5
2.3 Related Projects ......................................................................................................................... 5
2.3.1 Bit Full adder: ............................................................................................................. 6
2.3.2 Four Bit Binary Adder Using Reversible Logic Gates: ........................................... 6
2.4 Related Studies/Research .......................................................................................................... 6
2.5 Problem Statement ..................................................................................................................... 7
2.6 Summary .................................................................................................................................... 7

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Chapter 3 ................................................................................................................. 8
PROJECT DESIGN AND IMPLEMENTATION .................................................... 8
3.1 Proposed Design Methodology ................................................................................................. 8
3.2 Analysis Procedure .................................................................................................................... 8
3.3 Design of the Project Hardware ................................................................................................ 8
3.3.1 Logic probe ................................................................................................................. 9
3.3.2 AND Gate ................................................................................................................... 9
3.3.3 OR Gate ...................................................................................................................... 9
3.3.4 IC 7447............................................................................................................................ 9
3.3.5 Common Anode 7 Segment Display ............................................................................... 9
3.4 Design of the Project Software/Algorithm ............................................................................. 10
3.5 Implementation Procedure ...................................................................................................... 11
3.6 Details of Simulations / Mathematical Modeling .................................................................. 12
3.7 Details of Final Working Prototype........................................................................................ 15
3.8 Summary .................................................................................................................................. 15
Chapter 4 ............................................................................................................... 16
CONCLUSION AND FUTURE WORK ............................................................... 16
REFERENCES ...................................................................................................... 17

LIST OF FIGURES
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Figure 1 Truth Table for Full Adder............................................................................................................ 10
Figure 2circuit diagram for full adder ......................................................................................................... 11
Figure 3simulation figure ............................................................................................................................. 13
Figure 4Simulation diagram ........................................................................................................................ 14

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Chapter 1

INTRODUCTION

In daily routine, we need to perform several operations on digital computers for our
ease. So our computers make use of combinational circuits to perform required
operations. As computers do not understand the human language (high level language),
the compilers in computers translate the high level language in to low level language
i.e. binary language (0’s and 1’s). So, all the computations are performed in binary
language. Our computers can perform variety of arithmetic operations, out of which
addition is one. To carry out addition in computers, adders are used. These adders are
used for the addition of binary numbers. These adders are basically combinational
circuits that use gates like AND, XOR and OR. In further chapters, we discuss the
working of these gates and how the additions are performed using these adders.

1.1 Overview
Digital computers carry out a variety of information-processing tasks. Combinational
circuits can perform many arithmetical operations. Among these circuits, adders are of
significant importance. “A combinational circuit that performs the addition of two bits
is called a half adder; one that performs the addition of three bits (two significant bits
and a previous carry) is a full added. The names of the circuits stern from the fact that
two half adders can be employed to implement a full adder.”[1]. Combining four full
adders, a four bit full binary adder is formed. It simply performs the addition of two
binary numbers.

1.2 Project Idea

Out of the many arithmetic operations which digital computers perform, addition is one.
Digital computers have adders for this purpose. “In Digital Circuits, A Binary Adder is
one which is capable of addition of binary numbers in one circuit itself. The operation
being performed depends upon the binary value the control signal holds. It is one of the
components of the ALU (Arithmetic Logic Unit). This Circuit requires prerequisite
knowledge of XOR Gate, Binary Addition and Full Adder.”[2]. In case of

1
4 bit 4adders, the input is given and the output of each adder is acted as the input for
the next adder. A hierarchy design is followed to develop these circuits. The idea of this
project is to explain that how the additions in digital computers take place through
adders.

1.3 Purpose of the Project

An adder is a digital circuit that performs addition of numbers. In many
computers and other kinds of processors adders are used in the arithmetic logic units or
ALU. They are also used in other parts of the processor, where they are used to calculate
addresses, table indices, increment and decrement operators and similar operations.

Although adders can be constructed for many number representations, such as binary-
coded decimal or excess-3, the most common adders operate on binary numbers. In
cases where two's complement or ones' complement is being used to represent
negative numbers, it is trivial to modify an adder into an added subtractor. Other signed
number representations require more logic around the basic adder.

A full adder is a combinational circuit that forms the arithmetic sum of three bits. It
consists of three inputs and two outputs. Two of the input variables, denoted by r and
y, represent the two significant bits to be added. The third input, represents the carry
from the previous lower significant position. Two outputs are necessary because the
arithmetic sum of three binary digits ranges in value from 0 to 3.and binary 2or 3 needs
two digit. The two outputs are designated by the symbols S for sum and C for carry.
The binary variable S gives the value of the least significant bit of the sum. The binary
variable C gives the output carry. So the purpose of this project is to design this four bit
full adder.

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1.4 Project Specifications
We designed a circuit of four bit full adder. Following are the project specifications:

Table 1 Project Specifications

Specifications Explanation

Logic probe Each type of switch has its own application, even though
same operation is performed by other type of switches. But
logic probe used for circuits of that type in which we check
output again and again during running time.

Power 5V is the value assigned to a 7 segment display for the

purpose of displaying it.

Ground Proteus maximum in all simulation software ground is

needed to be given in the circuit as all these soft wares
performs contain voltage probes which measure potentials
at any point in the circuit needs a reference potential so the
circuit is needed to be grounded just for observing the
simulation

Adders Four full adders are used. These adders perform the binary
additions of numbers.

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1.5 Applications of the Project
Following are the applications of the project:

 As ALU is a component of CPU that performs arithmetic operations, so it uses

adders for this purpose.

 “Any electronic device that has a microcontroller or a CPU in it is using an adder.

Generally speaking most home electronics are probably going to use 8bit
microcontrollers or 32/64bit CPUs.” [3]

 They are used in washing machines, dryers, smart thermostats, digital wrist
watches, game consoles, digital bathroom scales or network equipment such as
routers.

 Adders are also used in multiplication circuits.

 Computers also make use of adders in their program counters.

1.6 Project Plan

Here, the whole project plan and time division is discussed.

1.7 Report Organization

This report further contains three chapters. In chapter 2, the topics discussed are related
technologies and their description, limitation of the project, idea of existing work,
related research and a comprehensive summary. In chapter 3, the topics discussed are
design methodology, hardware and software used, designing of software and hardware,
analysis procedure, prototype, simulations, implementation and working. In the last
chapter of the report, all the conclusions are written in detail.

4
Chapter 2

LITERATURE REVIEW

2.1 Background Theory

Several technologies are used in this project. Depending upon the need of the circuit,
we made use of several technologies and components. Our circuit cannot be completed
without the use of required technologies.

2.2 Related Technologies

As four bit full adder can be only made by the use of the four full adders, so we need
four full adders to make a four bit full adder. Similarly, we need switches, resistors,
power supply, IC and seven segments. All these are arranged in proper order to obtain
the required circuit.

2.2.1 Related Technology 1

Most importantly, we need four full adders to make a four bit full adder. All these four
full adders are connected in sequence such that carry in is given initially, and then
carryout of each full adder acts as carry in for the next full adder.

2.2.2 Related Technology 2

Seven segments are also used in this circuit. A seven-segment display is a form of
electronic display device for displaying decimal numerals that is an alternative to the
more complex dot matrix displays. Seven-segment displays are widely used in digital
clocks, electronic meters, basic calculators, and other electronic devices that
display numerical information.

2.3 Related Projects

Related projects with description are as follows:

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2.3.1 Bit Full adder:

The most timing critical part of logic design usually contains one or more arithmetic
operations, in which addition is commonly involved. Addition is a fundamental
arithmetic operation and it is the base for arithmetic operations such as multiplication
and the basic adder cell can be modified to function as subtractor by adding another
XOR gate. Therefore, 1-bit Full Adder cell is the most important and basic block of an
arithmetic unit of a system. Hence in order to improve the performance of the digital
computer system one must improve the basic 1-bit full adder cell based application. In
this paper simulate the performance of 4 bit adder- subtractor, 4 bit Carry skip adder
and 4-bit multipliers are designed using 9T full adder. All the simulation results are
using TSMC-0.18μM CMOS Technology.

2.3.2 Four Bit Binary Adder Using Reversible Logic Gates:

This paper proposes the design of 4-bit adder and implementation of adder Reversible
logic gate to improve the design in terms of garbage outputs and delay. In the recent
years, reversible logic has emerged as a promising technology having its applications
in low power CMOS, quantum computing, nanotechnology and optical computing
because of its zero power dissipation under ideal conditions. Thus, the project will
provide the reversible logic implementation of the conventional 4-bit adder using
Toffler gate, Peres gate and using both Peres gate and Fredkin gate. The proposed
reversible logic implementation of the 4-bit adder is optimized to obtain minimum
number of logic gates and garbage outputs. This project work on the reversible 4-bit
adder circuits designed and proposed here form the basis of the decimal ALU of a
primitive quantum CPU. The designed and optimized 4-bit reversible adder is
implemented in VHDL Using Xilinx ISE 12.1 tool.

2.4 Related Studies/Research

Some new topics in analogue/digital electronics and microelectronics:
 FPGA implementation of neural network digital systems
 Digital calibration in time-interleaved data converters using FPGA
 FPGA implementation of all-digital PLL/DLL.
 TDC chip design.
 Serializer/deserializer in microelectronics.


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2.5 Problem Statement
A full adder adds two 1-bit numbers and also has a carry-in bit. The 3-bit addition of
the two inputs and the carry-in produces a sum output bit and a carry output bit. The
three inputs are A, B and C in, and the outputs are Sout and C out. A logic circuit is required
to add multi-bit binary numbers. A multilevel circuit that would add two 4- bit numbers
would have 9 inputs and 5 outputs. Although a multi-level SOP or POS circuit
theoretically would be very fast, it has numerous drawbacks that makes it impractical.
The design would be very complex in terms of number of logic gates. Testing would be
difficult. In addition this approach cannot be extended easily to add binary numbers
with a higher number of bits. Multiple full adders can be used instead to make
comparatively simpler multilevel implementations with far fewer logic gates and wired
connections. Each full adder is designed and tested and then these full adders are used
in the design of a larger circuit. The cost of this simplification is a longer delay between
an input level change and a valid output level. The issues that could affect the course of
research are: Financial crunch in academia.

 Poor study design in published papers.

 Lack of replication studies.

 Problems with peer review.

 The problem of research accessibility.

 Lack of adequate and accurate science communication

2.6 Summary
In this chapter, the technology used to make the project is described with detail. The
related projects to four bit binary adder are discussed. The working of this project is
been described in detail. Also the hot research on related topics is been discussed. A
problem statement lets the reader know what problem he can face during research. So
he should avoid those things.

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Chapter 3

PROJECT DESIGN AND IMPLEMENTATION

3.1 Proposed Design Methodology

According to the project requirement, the design must be combinational and the
obtained output should be Boolean functions or the truth table. The truth table for 4- bit
full adder requires 512 entries which is not possible to be obtained directly. Hence, a
single full adder is considered first. When the all working related to single full adder is
completed, a full adder with two half adders and an OR gate is implemented.

As a 4-bit full adder is required, other three other full adders are implemented in the
same way. The bits of resultant sum are obtained from the sum bit of each full adder.
The carry bit for each full adder is used as an input for the next full adder. The sum bit
obtained from the first full adder is the least significant while the carry bit obtained
from last full adder is the most significant bit of the resultant sum.

The most significant bit of the numbers taken as input is given to the last full adder
while the least significant of the numbers is given to the first full adder. Through this
methodology, the resultant sum of the given numbers is obtained which in decimal.

3.2 Analysis Procedure

As mentioned above, full adders with two half adders and an OR gate are implemented.
“The half adder adds two binary and produces two outputs as sum and carry; XOR is
applied to both inputs to produce sum while AND gate is applied to both inputs to
produce carry.” [4] The results are displayed in decimal numbering system because
decimal numbering is used in our daily life and easily understandable by non-
professionals as well.

3.3 Design of the Project Hardware

Following is a list of the hardware used in the project:

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3.3.1 Logic probe
Logic probe is used to analyzing and troubleshooting the logical states (Boolean 0 or
1) of a digital circuit. While most are powered by the circuit under test, some devices
use batteries.

3.3.2 AND Gate

“The AND gate is a basic digital logic gate that implements logical conjunction. A
HIGH output (1) results only if all the inputs to the AND gate are HIGH (1). If none or
not all inputs to the AND gate are HIGH, a LOW output results. The function can be
extended to any number of inputs.” [5]

3.3.3 OR Gate
The OR gate is a digital logic gate that implements logical disjunction. A HIGH output
(1) results if one or both the inputs to the gate are HIGH (1). If neither input is high, a
LOW output (0) results.
3.3.4 IC 7447
“The 7447 IC is used to drive 7 segment display. It must be used with a common anode
7-segment display. The input to the 7447 is a binary number. DCBA where D is 8s, C
is 4s, B is 2s and A is 1s. The inputs DCBA often come from a binary counter. The
display is only sensible if the binary number is between DCBA=0000 (0) and
DCBA=1001 (9); this is called Binary Coded Decimal or BCD for short. If the number
is larger than 9, we get a strange output on the display.” [7]

3.3.5 Common Anode 7 Segment Display

A common anode 7 Segment LED Display is a 7 segment display in which all the anode
leads/pins of the LEDs are wired together, meaning they are common. Once voltage is
placed on the positive anode pin, they will all have voltage across them. LED is turned
on when you connect the cathode pin to ground. The LEDs which are connected to
ground turn on. Those which are not connected to ground stay shut off. This is how
common anode LED displays work.

9
 3.4 Design of the Project Software/Algorithm

3.4.1 Full Adder

“A full adder is a digital circuit that performs addition. Full adders are implemented
with logic gates in hardware. A full adder adds three one-bit binary numbers, two
operands and a carry bit. The adder outputs two numbers, a sum and a carry bit. The
term is contrasted with a half adder, which adds two binary digits.” [8]

3.4.1.1 Truth Table

Following is the truth table for a full adder:

Figure 1 Truth Table for Full Adder

3.4.1.2 K-maps

Now k-maps can be used to obtain the functions of sum and carry. K-Maps for Cout
and S are given below:

Cout = AB + BC + CA S= A + C + ABC +

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3.4.1.2 Circuit Diagram

Now the next step is to design the circuit diagram for full adder that is given below:

Figure 2circuit diagram for full adder

3.5 Implementation Procedure

In a 4-bit full adder, two 4-bit binary numbers are added and a sum and a carry-bit are
obtained. The maximum output is 31.

3.5.1 Input
When the switch is open, current goes into the 4-bit full adder as Logic 1. When the
switch is close, the current goes to the ground indicating the Logic 0. The carry-bit is
taken 0 initially. Then two 4-bit binary numbers are taken as inputs in the 4-bit full
adder. The inputs are given in binary form in 4-bit full adder.

3.5.2 Sum
There are four full adders in the circuit. The first full adder activates when C in is taken
as input to the first full adder. A0, B0 and Cin are given as inputs in the first full adder.
The sum bit and carry bit is obtained. The resultant value of S 0 can be determined by
the expression S0 = A0 ⊕ B0 ⊕ Cin. The value of C0 can be determined by the expression

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C0 = A0B0 + B0 Cin + C inA0. Then C0 is fed as input to the second full adder and A1, B1
and C0 are given as inputs. The process is repeated till fourth full adder until the values
of S3 and C3 is obtained.
The sum bit produced by each full adder is used to determine the output along with the
carry-bit produced by the last full adder. The sum is then displayed in decimal
numbering system.

3.6 Details of Simulations / Mathematical Modeling

Example 1: A = 2, B = 4 and Cin = 0
The given example states the, A = 2 and B = 4 in decimal numbering system. In binary
these numbers become 0010 and 0100 respectively.

0 0 1 0 0 1 0 0

A3 A2 A1 A0 B3 B2 B1 B0

The decimal sum of A and B is 2 + 4 = 6. The binary addition of A and B is given as:

0 0 1 0

+ 0 1 0 0

0 1 1 0

C4 S3 S2 S1 S0

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 The result obtained is i.e. (0110)2 which when converted to decimal gives (6) 10. The 7
segment used to display the digit on tens place displays 0 while the 7 segment used to
display the digit on units place displays 6.
The results from running simulation of this example on Proteus are given below:

Figure 3simulation figure

Example 2: A = 3, B = 5 and C in = 0

The given example states the, A = 3 and B = 5 in decimal numbering system. In binary
these numbers become 0011 and 0101 respectively.

0 0 1 1 0 1 1 1

A3 A2 A1 A0 B3 B2 B1 B0

The decimal sum of A and B is 3 + 7 = 10. The binary addition of A and B is given as:

0 0 1 1

+ 0 1 1 1

1 0 1 0

C4 S3 S2 S1 S0
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The result obtained is i.e. (1010)2 which when converted to decimal gives (10)10. The 7
segment used to display the digit on tens place displays 1 while the 7 segment used to
display the digit on units place displays 0.
The results from running simulation of this example on Proteus is given

Figure 4Simulation diagram

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3.7 Details of Final Working Prototype
The inputs are given in binary form in 4-bit full adder. The given numbers to be added
are in decimal form so first they are converted to binary. If the bit is 1 the switch is kept
open for that bit. If the bit is 0, the switch is kept closed for that respective bit. Two 4 -
bit binary numbers A and B are taken as input in 4-bit full adder. Cin can be 1 or 0
according to the output requirement.

3.8 Summary
Full adder is a logic circuit that adds two input operand bits plus a carry in bit and
outputs a carry out bit and a sum bit. When the switch is open, current goes into the 4 -
bit full adder as Logic 1. When the switch is close, the current goes to the ground
indicating the Logic 0. The carry-bit is taken 0 initially. Then two 4-bit binary numbers
are taken as inputs in the 4-bit full adder. The inputs are given in binary form in 4-bit
full adder. There are four full adders in the circuit. The first full adder activates when
Cin is taken as input to the first full adder. A0, B0 and Cin are given as inputs in the first
full adder. The sum bit and carry bit is obtained. Then C 0 is fed as input to the second
full adder and A1 , B1 and C0 are given as inputs and the process is repeated till fourth
full adder until the values of S3 and C 3 is obtained. The sum-bit obtained from the first
full adder is the least significant bit of the sum while the sum- bit obtained from the last
full adder is the most significant bit of the sum. The resultant sum is obtained in decimal
numbering system.

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Chapter 4

CONCLUSION AND FUTURE WORK

Digital electronic devices make use of adders to a greater extent. So among other
combinational circuits, adders are of significant importance. If we ever come to meet
the reader, six months from now, we would want him to remember that how we drew
the four bit full adder making use of the four full adders. The whole working of the four
bit full adder that how we initially give carry in. Moreover, the carry out of each adder
acts as carry in for each circuit. And lastly, observing the final carry out and sums. The
new observations we made, was in the part of obtaining output. We observed that the
output of the additions performed by four bit full adder can be in the form of Binary,
decimal or Hex decimal numbers, depending upon in which number system we are
required to display our output. So for displaying output in different number system, the
approach is entirely different. Out recommendations to anyone who wants to carry on
with our work is that he/she should amend the circuit in a way that it displays result in
these three number systems binary, decimal or Hex decimal. So the resulting adder can
become that component of device which have multiple choice of number system to
display results in.

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 REFERENCES
[1] https://www.studocu.com/hk/document/comsats-university-islamabad/design-
technologies-i/other/digital-design4th-editionm-morris-mano/4446752/view
[2] https://www.geeksforgeeks.org/4-bit-binary-adder-subtractor/
[3] https://www.quora.com/What-are-the-applications-of-a-4-bit-parallel-
adder#:~:text=in%20Electronic%20and%20Communications%20Engineering,Electro
nics%20Hobbyist.&text=Adders%20are%20digital%20logic%20devices%20that%20
add%20or%20sum%20binary%20numbers%20together.&text=So%20if%20you%20
had%20a%204%20bit%20adder%20it%20would,to%20form%20an%208bit%20adde
r.
[4] https://www.elprocus.com/half-adder-and-full-adder/
[5] https://en.wikipedia.org/wiki/AND_gate
[6] https://en.wikipedia.org/wiki/XOR_gate
[7]http://www.davidswinscoe.com/electronics/components/7447/#:~:text=The%2074
xx47%20chip%20is%20used,come%20from%20a%20binary%20counter.
[8] https://www.techopedia.com/definition/7346/full-adder

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