Low Power clock-synchronizer for SOC with delay line controller

(DLC) in 45nm CMOS Technology.

Srivathsava.N.L, Tripti Kulkarni
Department of Electronics and Communication,
PES Institute of Technology,
100-ft Ring Road, BSK 3rd Stage,
Bangalore-560085, Karnataka, India.
srivathsava51@gmail.com, triptikulkarni@pes.edu.
Abstract – Clock synchronizer is the circuit which
synchronizes the clock provided to different loads (modules
or functional blocks). The advancement of the VLSI has led
to new field- SoC. The clock synchronizer finds its
application in SoC. The clock-synchronizer in SoC has to
maintain the clock skew between modules zero. This paper
presents clock synchronizer architecture. This synchronizer
is designed on 45nm CMOS technology, simulated using
Tanner EDA tool and T-SPICE, with 2V power supply. The
average power consumed is 6.688514e-002 watts.

Keywords: System On Chip (SoC), Dynamic Voltage and

Frequency scaling (DVFS), Phase locked loop (PLL), variable
delay line (VCDL), Phase Frequency Detector (PFD) Charge
Pump (CP),Duty Cycle to Digital, pulse-triggered capturing
circuit, delay line controller (DLC), dead lock state.
Fig. 2. General clk-synchronizer architecture.
I. INTRODUCTION
SoC can be defined as the system with number of In this paper we present clock synchronizer architecture,
standalone devices which are tailored together to work as a i.e. Clock synchronizer with digital feedback.
single system on a single chip [1]. Thus the SoC consists
of the numerous of modules working as a single system. In II. VOLTAGE CONTROLLED DELAY LINE (VCDL)
SoC to save the power, the DVFS (Dynamic Voltage and
VCDL is the circuit where the delay of the signal
Frequency Scaling) technique is used to save the power.
path can be varied by the control voltage.
Due to extensive use of the DVFS module, the work load
as seen by the clocks in the different module will vary, The VCDL [2] constructed is chain of buffer, with
thus introducing the problem of the skew between clocks transistors used as a switch to by-pass the signal form the
of different modules, Fig 1. To eliminate the clock skew, chain to get variable delay based on the transistor that is
clock synchronizer is used, Fig 2. turned on.

The VCDL constructed is as in Fig 3. The chain of

two buffers is used as a unit; the signal is extracted via
switch. The delay introduced by single unit is 45.38Ps.
The further stage will introduce the delay in the same
manner.

Fig. 1. Skew in SoC.

The general clock synchronizer architecture is as in Fig 2.

The clock is supplied from the PLL; to the both static and
variable load (variable load is due to use of DVFS
scheme). Due to difference in the loads, the output clocks
will suffer from skew with each other, Fig 1. By adding
the Delay Line Controller (DLC), the error is calculated
and error signal is fed an input to the Voltage Control
Delay Line (VCDL), which adjusts the counter load on the
clock path to the variable load, and thus the load in the
both the path is balanced, and clock out of the modules
will be in phase.
Fig. 3. Voltage Control Delay Line.
III. CLOCK SYNCHRONIZER
The synchronizer constructed is based on the principle
that when two signal of varying skew is fed to phase
frequency detector (PFD) and followed by charge pump
(CP), the duty cycle of the output of the CP will vary. The
variation of the duty-cycle is used as an error and used to
choose the counter delay to make the skew zero.

A. Phase frequency detector (PFD):

A circuit that detect both phase and frequency
difference is preferred in a charge pump PLL than phase
detector, because it increases the acquisition range and
lock speed in PLL. It is called PFD [8]; it produces two
outputs unlike the PD which produces only output.The
used PFD [3], shown in Fig 4, it uses TSPC architecture.
The resetting module has been implemented differently in
relation to the conventional method. When both signals
(up and down) are in the high state then the reset is started,
but the slave part has an asynchronous reset and the master
part is resetting synchronously. PFD is completely
symmetrical, there is no division in its construction
between the master and the slave block, the master block Fig. 5. Phase Frequency Detector driving Charge Pump.
is chosen when first upcoming signal appears.
The CP used contains a simple switch, Fig. 6, the up and
Synchronous reset in PFD increases the maximum
down signal will drive the two switches.
operating frequency and significantly reduces power
consumption. The average power consumed is
0.2293978m W

Fig. 6. Charge Pump.

Fig. 4. Phase Frequency Detector.
C. Duty Cycle to Digital Converter (Delay Line
B. Charge Pump (CP): Controller- DLC)
Cp [4] Converts PFD phase error (digital) to charge The general block diagram of the delay line controller is as
(analog) Charge is proportional to PFD pulse widths, in fig 7.

Qcp = Iup*tfaster – Idn*tslower. (1)

Qcp is filtered/ integrated in low-pass filter.

A typical PFD driving CP is shown in the Fig 5. Two

switches are driven by up and down signal from PFD.
When the up signal is asserted the output node is charged,
it will be discharged when the down signal is asserted.
This will convert the PFD output to voltage pulses which
is proportional to the PFD pulse width.

Fig. 7. Delay Line Controller.

As the skew to the PFD is varied, the duty cycle at the

charge pump output varies. This variation of the duty cycle
is converted in to digital signal to have a digital feedback.

The duty-cycle to digital converter constructed based

on pulse-triggered capturing circuit [5], Fig. 8. It consists
of a buffer chain, and a D-FF chain. The chain of D-FF
will have delayed version of the output of CP as D-IN and
clock. The converter will act as the shift register which
will be activated only during the on time of the pulse
output of CP, thus will generate the bit sequence unique to
the on-time of the pulse or the duty-cycle. Here number of
digital bit, N, used must satisfy the equation,
T = N*tp.
load and also the error is evaluated. The time length of the
evaluation phase is represented as tev.
2) Dealy adjustment phase:
During the dealy adjustment phase, the clock via
refernce path is cutoff and error signal which is latched in
the D-FF shift-register is supplied as the feed back signal
will adjust the counter load i.e., VCDL. The start time of
the dealy adjustment phase is represented as tda.

T: Pulse width. Both the phase must be separated by the sufficient time
gap, which is called ‘guard band’ (tev - tda). If the guard
tp: Delay of the buffer.
band is zero or negetive the circuit will enter in the phase
where the clock out of the variable delay will fall to zero
due to the fact the the feed back signal to the VCDL will
all go high, this state is called as the, ‘dead lock state’. The
guard band chosen in our work is, 1.41ns.

III. SIMULATION RESULTS

1) Performance of the DLC.

Fig. 8. Duty-cycle to Digital converter. The power consumed DLC is 6.688514e-002 watts.

 Skew(PS) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Evaluation Guard Band Total Dealy
Phase (tev ) (tda)
45.38 1 0 0 0 0 0

90.76 1 1 1 0 0 0 1.72 ns 1.41ns 3.13ns

136.14 1 1 1 1 0 0 Table 2: Performance of DLC.

181.52 1 1 1 1 1 0
Table 1: Digital Output of the duty cycle to digital
converter.

Table 1 summarizes the output of the duty cycle to digital

converter. Each of the skew observed will generate the
1) Simulation results:
unique bit pattern, which can be converted in to a single
bit using basic logic design technique. The duty cycle to The output wave form that is discussed is WRT to
digital converter followed by the logic gates to implement the skew 90.76ps.
the control signal will form delay line controller (DLC).

D. Timing Consideration (Clock gating):

The operation of the proposed clock synchronizer
work in two phases,

1. Evaluation phase.

2. Delay adjustment phase.

1) Evaluation phase:
In the evaluation phase, the circuit will evaluate the
skew. During the evaluation phase, the variable load is
supplied with clock via a reference path to evaluate the
skew between the clock out of the varaible load and static

Fig. 9. Simulation of the duty cycle to digital converter.
Fig. 10. Simulation of the DLC.
Fig. 11. Clock synchronizer simulation.
2) Constructed clock synchronizer:
Fig. 12. Constructed clock synchronizer.
IV. CONCLUTION
The constructed clock synchornizer uses a novel
approach to clock synchronizer construction. It uses a new
concept of duty cycle to dugital converter which is very
much effective to have a digital feed-back. The power
consumed by the whole controller is 6.688514e-002 watts.
This architecture can be easily exttened to multiple branch.
The duty cycle to digital converter suffer from a drawback
i.e., it is frequency sensitive i.e., the digital logic
constructed to generate the digital feed back has to be
changed as the frequency varies. This would be the future
enhancement.
V. REFERENCE
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State Circuits Conference November 16-18, 2009.
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