IEEE ELECTRON DEVICE LETTERS, VOL. 39, NO.
9, SEPTEMBER 2018
First Demonstration of a Logic-Process
Compatible Junctionless Ferroelectric FinFET
Synapse for Neuromorphic Applications
Myungsoo Seo, Student Member, IEEE , Min-Ho Kang, Seung-Bae Jeon, Hagyoul Bae, Member, IEEE ,
Jae Hur , Byung Chul Jang, Seokjung Yun, Seongwoo Cho, Wu-Kang Kim , Member, IEEE ,
Myung-Su Kim, Kyu-Man Hwang, Seungbum Hong, Sung-Yool Choi, and Yang-Kyu Choi
Abstract — A highly scalable synapse device based on
a junctionless (JL) ferroelectric (FE) FinFET is presented
for neuromorphic applications. The synaptic behaviors
of the JL metal-ferroelectric-insulator-silicon FinFET were
experimentally demonstrated after verifying the ferroelec-
tric characteristics of the HfZrOX (HZO) film using a
metal-ferroelectric-metal capacitor. The fabricated synapse
showed distinguishable polarization switching behaviors
with gradually controllable channel conductance. From
neural network simulations using the proposed JL FE
FinFET as synapses, the pattern recognition accuracy for
hand-written digits was validated to be approximately 80%
for neuromorphic applications.
Index Terms — Junctionless FET, ferroelectric FET,
FinFET, synapse, neuromorphic computing system.
I. I NTRODUCTION
T HE study of neuromorphic systems, which are inspired by
the structure of the human brain, is an emerging research
field at the advent of the artificial intelligence era because such
systems can achieve more energy-efficient computing than the
classical von Neumann architecture [1]. The synaptic device
is one of the most important components in the neuromorphic
Manuscript received June 12, 2018; revised June 28, 2018; accepted
June 30, 2018. Date of publication July 3, 2018; date of current
version August 23, 2018. This work was supported in part by the
Global Frontier Center for Integrated Smart Sensors funded by the
Ministry of Science and ICT (MSIT) under Grant CISS-2011-0031848,
in part by the Global Frontier Center for Advanced Soft Electronics
funded by MSIT under Grant 2011-0031640, in part by the KAIST
GCORE funded by MSIT under Grant N11180139, and in part by
the IC Design Education Center (EDA Tool and MPW) in South
Korea. The review of this letter was arranged by Editor B. Govoreanu.
(Corresponding author: Yang-Kyu Choi.)
M. Seo, S.-B. Jeon, J. Hur, W.-K. Kim, M.-S. Kim, K.-M. Hwang, and
Y.-K. Choi are with the School of Electrical Engineering, Korea
Advanced Institute of Science and Technology (KAIST), Daejoen 34141,
South Korea (e-mail: ykchoi@ee.kaist.ac.kr).
M.-H. Kang is with the National Nanofab Center, Daejoen 34141,
South Korea.
H. Bae is with the Birck Nanotechnology Center, School of Electrical
and Computer Engineering, Purdue University, West Lafayette, IN 47907
USA.
B. C. Jang and S.-Y. Choi are with the Graphene/2D Materials Research
Center, School of Electrical Engineering, Korea Advanced Institute of
Science and Technology (KAIST), Daejeon 34141, South Korea.
S. Yun, S. Cho, and S. Hong are with the Department of Materials
Science and Engineering, Korea Advanced Institute of Science and
Technology (KAIST), Daejeon 34141, South Korea.
Color versions of one or more of the figures in this letter are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2018.2852698
0741-3106 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: National Institute of Technology Patna. Downloaded on August 27,2020 at 10:35:01 UTC from IEEE Xplore. Restrictions apply.
1445
system, not only for performing intelligent tasks with low
power consumption, but also to reduce a chip size. This
is accomplished by integrating highly dense synapse arrays
in deep neural network hardware [2]. Two-terminal based
emerging non-volatile memories such as resistive random
access memory (RRAM) [3], phase-change RAM (PRAM) [4],
and magnetic RAM (MRAM) [5] have been actively studied
for this purpose because of their small cell size. However,
such memories have difficulty maintaining reliable operation
and mass productivity. Also, the two-terminal memories need
additional circuitry components for selecting a target cell,
when they are integrated in a system [6].
Recently, ferroelectric (FE) FETs have attracted consid-
erable attention as a promising candidate for the synaptic
device thanks to the discovery that a logic-process com-
patible thin hafnium-based material shows excellent ferro-
electric characteristics [7]–[10]. A compact synapse based
on a single FE FET was previously reported with high-
k metal gate (HKMG) technology [11], and an FE FET
analog synapse with symmetric potentiation and depression
characteristics has been demonstrated [12]. However, there
is still an opportunity to develop the synapse array with
higher integration density by using a junctionless (JL) feature.
A JL FET has advantages of smaller area by reducing the
source and drain (S/D) volume, lower cost by reducing the
process steps for shallow and abrupt junction formation, less
device variability by eliminating random dopant fluctuation
from ion-implant or the sensitive epitaxial growth of S/D,
and better reliability from the bulk conduction mechanism
compared to a conventional MOSFET [13], [14]. Challenging
issues in the JL FET, such as its relatively high off-state
leakage current, are not critical when they are employed
in highly scaled synaptic device applications with a thin
channel [15].
In this letter, a highly scaled JL FE FinFET synapse
with a HfZrOX (HZO) layer is presented for the first time.
The synaptic behaviors of the metal-ferroelectric-insulator-
silicon (MFIS) device were successfully demonstrated after
evaluating the ferroelectric characteristics of the HZO film
using a simple metal-ferroelectric-metal (MFM) capacitor.
The synaptic device showed gradual polarization switching
behaviors, with over 32 levels of states. Pattern recognition
performance was also examined using a device-to-system
simulation framework.
1446
Fig. 1. (a) Schematic illustration of a JL FE FinFET synapse for
neuromorphic applications utilizing a HZO layer. (b) Cross-sectional high-
resolution TEM image of the synapse gate stack: MFIS structure. (c) Key
process flow of the n-channel JL FE FinFET.
II. D EVICE S TRUCTURE AND FABRICATION M ETHOD
A schematic illustration of the synaptic device, which
combines the respective advantages of the JL FET and FE FET,
is shown in Fig. 1 (a). By eliminating S/D junctions, the device
becomes highly scalable, and with the thin ferroelectric HZO
layer is logic-process compatible. The fin-type synapse was
fabricated on a bulk silicon wafer with a fin width (W )
of 50 nm, a fin height (HFin) of 100 nm, and a gate length (L G )
of 120 nm. Because the fabricated device has a 3D FinFET
structure, the total effective channel W is 250 nm, which is
5 times wider than the footprint W of 50 nm. Fig. 1 (b) shows
a cross-sectional TEM image of the gate stack. The 8.5 nm
thick HZO deposited via atomic layer deposition (ALD) on a
1.5 nm thick SiO2 interfacial layer is capped by a TiN metal
gate deposited via physical vapor deposition (PVD).
The key process flow of the n-channel JL device is summa-
rized in Fig. 1 (c). Boron was initially implanted for the chan-
nel stop to prevent unnecessary leakage current paths among
adjacent cells, and phosphorous implantation was followed
to form the n-channel and the JL S/D. Then, rapid thermal
annealing (RTA) at 1000 °C for 5 seconds was carried out to
activate the dopants. The fin-type active region was defined
by lithography and a silicon etch process. The field oxide was
deposited and etched for device isolations. The ferroelectric
ALD HZO layer was formed with an interfacial SiO2 layer.
The TiN was deposited by PVD and sequentially patterned
for the metal gate. Finally, post metal annealing at 600 °C
for 30 seconds was performed to crystallize the ferroelectric
films.
III. E XPERIMENTAL R ESULTS AND D ISCUSSION
A. Characterization of the Capacitor and Synapse
The atomic percent ratio of the HZO film was confirmed
by X-ray photoelectron spectroscopy (XPS) depth profiling as
Authorized licensed use limited to: National Institute of Technology Patna. Downloaded on August 27,2020 at 10:35:01 UTC from IEEE Xplore. Restrictions apply.
IEEE ELECTRON DEVICE LETTERS, VOL. 39, NO. 9, SEPTEMBER 2018
Fig. 2. (a) XPS depth profile of the 8.5nm ALD HZO film on Si
substrate and (b) GI-XRD spectrum of the TiN/HZO/Si structure. (c) C-V
characteristics and (d) P-E hysteresis loops (AFM-MFP-3D) of the MFM
capacitor structure (ALD HZO 8.5nm).
Fig. 3. Measured (a) IDS -VGS and (b) IDS -VDS characteristics of the JL
FE FinFET.
shown in Fig. 2 (a), and revealed that the Hf : Zr ratio of the
HZO film was around 0.5 : 0.5 using 1 : 1 number of HfO2 :
ZrO2 ALD cycles. The grazing incidence X-ray diffraction
(GI-XRD) spectrum in Fig. 2 (b) indicates clear ferroelectric
orthorhombic phase peaks after the post metal annealing
(600 °C for 30 seconds by RTA). The ferroelectric charac-
teristics of the MFM capacitor were verified by capacitance
and polarization measurements as shown in Fig. 2 (c) and (d).
The butterfly-like feature of the capacitance-voltage (C-V )
characteristics and the polarization-electric field (P-E) hys-
teresis loops indicate that the post-annealed HZO film has
typical ferroelectric properties.
The transfer (IDS -VGS ) and output (IDS -VDS ) characteristics
show that the JL FE FinFET operates as a typical transistor
(Fig. 3 (a) and (b)). Noting that the transistor has not been
optimized with factors such as channel implantation dose, fin
width to height ratio, and relatively less scaled fin width, it is
expected to improve relatively high off-state current due to JL
scheme. The polarization switching of the ferroelectric layer
was enabled by applying pulses to the gate. The rectangular-
type pulses of +3.7V and −3.2V for 100 µs were used for
potentiation and depression respectively in this work. The
state of the device was measured with sensing sweep voltage
within 1.2 and 1.5 V as depicted in Fig. 4 (a). To exclude
the impact of trapping, which induces conductance change
in the opposite direction compared with the ferroelectric
switching, the sensing sweep was performed with sufficient
delay time within the pulse sequence [16]. The gradually
SEO et al .: FIRST DEMONSTRATION OF A LOGIC-PROCESS COMPATIBLE JL FE FinFET SYNAPSE
Fig. 4. (a) Pulse and sensing sweep scheme, and (b) conductance-pulse
number characteristics of the MFIS synaptic device. Measured sensing
results with repetitive pulses for (c) potentiation and (d) depression.
(e) Cyclic test of the potentiation and depression with weight update set.
modulated channel conductance as a function of pulse numbers
is confirmed as shown in Fig. 4 (b). The conductance of
each polarization state was measured at a VGS of 1.5 V.
The threshold voltage (VT ) was gradually modulated as a
function of pulse numbers both directions of potentiation and
depression as shown in Fig. 4 (c) and (d). The fabricated
synapse has over 32 levels (5 bits) of polarization states. By a
cyclic test of the potentiation and depression, it is confirmed
that the proposed device operates normally up to 100 cycles.
The range between the maximum and minimum conductance
values in each cycle does not significantly differ, as shown in
Fig. 4 (e). However, a descending trend in the early part of the
cycles should be further considered for actual implementation
of a neuromorphic system.
B. Neural Network Simulation and Benchmark
Based on the experimentally measured behavior, numerical
simulation of a neural network was conducted using the back-
propagation supervised learning algorithm [17], to confirm
its feasibility for pattern recognition. A multi-layer neural
network was composed of 528 input neurons, 250 and 125 neu-
rons for 1st and 2nd hidden stages, and 10 output neurons as
shown in Fig. 5 (a). A hand-written digit dataset, the Modified
National Institute of Standards and Technology (MNIST), was
used for the simulation and verification. Recognition accuracy
gradually increased with increasing state levels with the first
5,000 digits of the training set as shown in Fig. 5 (b). When the
Authorized licensed use limited to: National Institute of Technology Patna. Downloaded on August 27,2020 at 10:35:01 UTC from IEEE Xplore. Restrictions apply.
1447
Fig. 5. (a) Schematic diagram of the simulated neural network and
(b) comparison of the pattern recognition accuracy vs. state levels.
TABLE I
B ENCHMARK OF S YNAPTIC D EVICES B ASED ON FE FET
full training set was used, the accuracy was approximately
80 % with the measured 50 synaptic weight state levels.
A benchmark of the FE FET synaptic devices is summarized
in Table 1. While the characteristics of the proposed JL FE
FinFET synapse and the simulation result of the MNIST
digit recognition are comparable to those of conventional
synapses based on the planar FET structure with inversion
mode [11], [12], the proposed device is much highly scalable
with an active area of 0.006 µm2 (approximately 40 times
smaller). If the incremental pulse scheme that was used in
prior works is applied to the proposed device in further work,
it is expected that the linearity of the conductance change and
the recognition accuracy would be improved [17].
IV. C ONCLUSION
A JL FE FinFET was proposed as a synaptic device for
neuromorphic applications. This is the first time that the
JL scheme has applied to HZO-based synaptic devices. The
ferroelectric characteristics of the HZO film were verified
using an MFM capacitor, and then synaptic behavior was
experimentally confirmed with the MFIS synaptic device.
A neural network simulation based on the experimentally mea-
sured conductance-change characteristics was also conducted.
The accuracy of the MNIST hand-written digit recognition was
estimated to be 80 %. The proposed synapse is highly scalable,
logic-process compatible, and cost effective thanks to the JL
FE FinFET scheme. With further study of controlling domains
at a nanoscale level, the device can be readily embedded into a
commercial application processor as an accelerator for a neural
network system with very high integration density in the near
future.
1448
R EFERENCES
[1] G. Indiveri and S.-C. Liu, “Memory and information processing in
neuromorphic systems,” Proc. IEEE, vol. 103, no. 8, pp. 1379–1397,
Aug. 2015, doi: 10.1109/JPROC.2015.2444094.
[2] K. Moon, M. Kwak, J. Park, D. Lee, and H. Hwang, “Improved
conductance linearity and conductance ratio of 1T2R synapse device
for neuromorphic systems,” IEEE Electron Device Lett., vol. 38, no. 8,
pp. 1023–1026, Aug. 2017, doi: 10.1109/LED.2017.2721638.
[3] J. Park, M. Kwak, K. Moon, J. Woo, D. Lee, and H. Hwang,
“TiO x -based RRAM synapse with 64-levels of conductance
and symmetric conductance change by adopting a hybrid pulse
scheme for neuromorphic computing,” IEEE Electron Device
Lett., vol. 37, no. 12, pp. 1559–1562, Dec. 2016, doi: 10.1109/
LED.2016.2622716.
[4] G. W. Burr, R. M. Shelby, S. Sidler, C. di Nolfo, J. Jang, I. Boybat,
R. S. Shenoy, P. Narayanan, K. Virwani, E. U. Giacometti, B. N. Kurdi,
and H. Hwang, “Experimental demonstration and tolerancing of a
large-scale neural network (165 000 synapses) using phase-change
memory as the synaptic weight element,” IEEE Trans. Electron
Devices, vol. 62, no. 11, pp. 3498–3507, Nov. 2015, doi: 10.1109/
TED.2015.2439635.
[5] A. F. Vincent, J. Larroque, N. Locatelli, N. B. Romdhane,
O. Bichler, C. Gamrat, W. S. Zhao, J.-O. Klein, S. Galdin-Retailleau,
and D. Querlioz, “Spin-transfer torque magnetic memory as a sto-
chastic memristive synapse for neuromorphic systems,” IEEE Trans.
Biomed. Circuits Syst., vol. 9, no. 2, pp. 166–174, Apr. 2015,
doi: 10.1109/TBCAS.2015.2414423.
[6] S. Lashkare, N. Panwar, P. Kumbhare, B. Das, and U. Ganguly,
“PCMO-based RRAM and NPN bipolar selector as synapse for
energy efficient STDP,” IEEE Electron Device Lett., vol. 38, no. 9,
pp. 1212–1215, Sep. 2017, doi: 10.1109/LED.2017.2723503.
[7] T. S. Böscke, J. Müller, D. Bräuhaus, U. Schröder, and U. Böttger,
“Ferroelectricity in hafnium oxide thin films,” Appl. Phys. Lett., vol. 99,
no. 10, p. 102903, Sep. 2011, doi: 10.1063/1.3634052.
[8] J. Müller, T. S. Böscke, D. Bräuhaus, U. Schröder, U. Böttger,
J. Sundqvist, P. Kücher, T. Mikolajick, and L. Frey, “Ferroelectric
Zr0.5 Hf0.5 O2 thin films for nonvolatile memory applications,” Appl.
Phys. Lett., vol. 99, no. 11, p. 112901, 2011, doi: 10.1063/1.3636417.
Authorized licensed use limited to: National Institute of Technology Patna. Downloaded on August 27,2020 at 10:35:01 UTC from IEEE Xplore. Restrictions apply.
IEEE ELECTRON DEVICE LETTERS, VOL. 39, NO. 9, SEPTEMBER 2018
[9] M. H. Park, H. J. Kim, Y. J. Kim, W. Lee, T. Moon, and C. S. Hwang,
“Evolution of phases and ferroelectric properties of thin Hf0.5 Zr0.5 O2
films according to the thickness and annealing temperature,” Appl. Phys.
Lett., vol. 102, no. 24, p. 242905, 2013, doi: 10.1063/1.4811483.
[10] J. Müller, T. S. Böscke, S. Müller, E. Yurchuk, P. Polakowski, J. Paul,
D. Martin, T. Schenk, K. Khullar, A. Kersch, W. Weinreich, S. Riedel,
K. Seidel, A. Kumar, T. M. Arruda, S. V. Kalinin, T. Schlösser,
R. Boschke, R. van Bentum, U. Schröder, and T. Mikolajick, “Ferroelec-
tric hafnium oxide: A CMOS-compatible and highly scalable approach
to future ferroelectric memories,” in IEDM Tech. Dig., Washington, DC,
USA, Dec. 2013, pp. 10.8.1–10.8.4, doi: 10.1109/IEDM.2013.6724605.
[11] H. Mulaosmanovic, J. Ocker, S. Müller, M. Noack, J. Müller,
P. Polakowski, T. Mikolajick, and S. Slesazeck, “Novel ferroelectric FET
based synapse for neuromorphic systems,” in Proc. Symp. VLSI Technol.,
Jun. 2017, pp. T176–T177, doi: 10.23919/VLSIT.2017.7998165.
[12] M. Jerry, P.-Y. Chen, J. Zhang, P. Sharma, K. Ni, S. Yu, and S. Datta,
“Ferroelectric FET analog synapse for acceleration of deep neural net-
work training,” in IEDM Tech. Dig., Washington, DC, USA, Dec. 2017,
pp. 6.2.1–6.2.4, doi: 10.1109/IEDM.2017.8268338.
[13] C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and
J. P. Colinge, “Junctionless multigate field-effect transistor,” Appl. Phys.
Lett., vol. 94, p. 053511, Mar. 2009, doi: 10.1063/1.3079411.
[14] J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhava, R. Yan, I. Ferain,
P. Razavi, B. O’Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy,
and R. Murphy, “Nanowire transistors without junctions,” Nature Nan-
otechnol., vol. 5, pp. 225–229, Feb. 2010, doi: 10.1038/nnano.2010.15.
[15] D.-I. Moon, S.-J. Choi, J. P. Duarte, and Y.-K. Choi, “Investigation of
silicon nanowire gate-all-around junctionless transistors built on a bulk
substrate,” IEEE Trans. Electron Devices, vol. 60, no. 4, pp. 1355–1360,
Apr. 2013, doi: 10.1109/TED.2013.2247763.
[16] K. Ni, P. Sharma, J. Zhang, M. Jerry, J. A. Smith, K. Tapily,
R. Clark, S. Mahapatra, and S. Datta, “Critical role of interlayer in
Hf0.5 Zr0.5 O2 ferroelectric FET nonvolatile memory performance,” IEEE
Trans. Electron Devices, vol. 65, no. 6, pp. 2461–2469, Jun. 2018,
doi: 10.1109/TED.2018.2829122.
[17] J.-W. Jang, S. Park, G. W. Burr, H. Hwang, and Y.-H. Jeong, “Optimiza-
tion of conductance change in Pr1–x Cax MnO3 -based synaptic devices
for neuromorphic systems,” IEEE Electron Device Lett., vol. 36, no. 5,
pp. 457–459, May 2015, doi: 10.1109/LED.2015.2418342.