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Reverse Bias Current eliminated, Read-separated,
and Write-enhanced Tunnel FET SRAM
Chunyu Peng, Zhou Yang, Zhiting Lin*, Senior Member, IEEE, Xiulong Wu, and Xuan Li
Abstract—The reverse bias current of the tunneling field-effect
transistor (TFET) could cause serious damage to static
random-access memory (SRAM) circuit performance. To address
this issue, a novel reverse bias current eliminated, read-separated,
and write-enhanced TFET 12T SRAM bitcell is proposed for
ultra-low power applications in this paper. It can prevent reverse
bias currents, increase the hold/read static noise margin
(H/RSNM) and dramatically decrease the static power
consumption. The static power consumption of the proposed
bitcell is reduced by four orders of magnitude compared with that
of the 7T bitcell, demonstrating its great potential for ultra-low
power applications. At a supply voltage of 0.6 V, the H/RSNM of
the proposed bitcell is 25% larger than that of the 7T bitcell. It
also includes a write assist circuit, thus increasing its write static
noise margin (WSNM) and considerably decreasing its write
power consumption. The WSNM of the proposed bitcell is more
than twice that of the 7T bitcell, and is 60% larger than that of the
combinational access bitcell. In addition, the write power
consumption of the proposed bitcell is reduced by 95% compared
with that of the combinational access bitcell at a supply voltage of
0.6 V. In terms of layout, the area of the proposed 12T bitcell is
92% larger than that of the 7T bitcell, but is 6% smaller than the
area of the combinational access bitcell.
Index Terms—power consumption, reverse bias current,
SRAM, static power consumption, TFET, ultra-low power.
I. INTRODUCTION
Rdevices, andthe biomedical
EDUCING power consumption in processors, mobile
electronics is a very challenging
task [1]. Since a static random-access memory (SRAM) array
takes up a large portion of circuits, it is really necessary to
reduce the power consumption of the SRAM array to decrease
the total power of circuits. Usually, reducing the supply voltage
is a very effective way to reduce power consumption. However,
due to the fundamental limit of the subthreshold swing of the
metal-oxide-semiconductor field-effect transistor (MOSFET)
device, continually reducing the supply voltage causes
considerable degradation of the Ion/Ioff ratio and increases the
leakage current of the MOSFET device. Recently, the tunneling
field-effect transistor (TFET) was proposed, using
band-to-band tunneling as the conduction mechanism [2]. Due
to the compatibility of the TFET and MOSFET fabrication
process, the robustness at low voltage [3], and the ultra-low
subthreshold swing of TFET (<60 mV/dec at 300 K), it is
considered to be a promising candidate for ultra-low-power
circuits [4]. There are some papers published in the last 10
years developing mixed device/circuit simulation analysis of
TFET circuits, for digital [5]-[8], analog [9]-[12], and SRAM
cell [13]-[19] applications.
This work was supported in part by National Key R&D Program of China
(Grant No. 2018YFB2202803) and the National Natural Science Foundation of
China (Grant No. 61804001, 61674002, and 61574001).
The authors are with School of Electronics and Information Engineering,
Anhui University, Hefei, Anhui, China, 230601, e-mail: (ztlin@ahu.edu.cn).
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1
In MOSFETs, the source and drain are interchangeable.
However, in TFETs, the source and drain are determined at the
time of fabrication. Accordingly, TFETs can be considered to
be unidirectional, which has significant implications on the
logic and especially the SRAM design. In addition, when the
voltage across the source and drain is large, the reverse bias
current cannot be ignored in an N-type TFET (NTFET), which
actually could lead to severe damage to hold/read static noise
margin (H/RSNM), and significant increase in the static power
consumption of the SRAM circuit [20]. Several discussions
have been done on the unidirectional behavior and reverse bias
current of TFET ([13]-[18]). Although SRAM cells with
outward access transistors could achieve both acceptable read
and write SNMs, the ability to read and write is still weak and
the static power is high [16, 17]. Inward pTFETs are suitable as
the access transistors for the 6T TFET SRAM if assist
techniques are used [17]. Modification of the traditional
6-transistors (6T) SRAM cell with a higher transistor number is
helpful for high speed and stable read/write operation. 7T
SRAM [20], 8T Transmission-Gate (TG) SRAM, 8T/10T
dual-port (DP) SRAM, TFET Schmitt-Trigger (ST) SRAM
[13-14], the 10T combinational access SRAM [21], and 9T
TFET SRAM [15] are reported for solving the unidirectional
behavior. In addition, limiting source-drain voltage [18] can
relieve but not eliminate the impact of the reverse bias current.
In this study, a reverse bias current eliminated,
read-separated, and write-enhanced 12T SRAM bitcell
structure is proposed. The cell structure consists of two
cross-coupled inverters (P1, P2, N1, and N2), access transistors
(N3, N4, N5 and N6), read-decoupled access buffer (N7 and
N8), and write assist transistors (P3 and P4). The main benefits
of the proposed 12T SRAM bitcell are as follows. 1) It
improves the write capability by incorporating write assist
transistors (P3 and P4). 2) It improves the read stability using a
read-decoupled topology, which isolates the storage node from
the read path. 3) By using four outward N type TFETs (NTFET)
as the access transistors and setting the source of the access
transistors (N5 and N6) to the ground (“0”), it avoids reverse
bias currents in the access transistors, thus effectively reducing
static power consumption and increasing H/RSNM. 4) It avoids
the half-selected problem. 5) It improves the circuit
performance by avoiding the reverse bias current when reading.
The rest of this paper is organized as follows. Section II
introduces the devices used in this brief. Section III provides a
detailed description of the working principle and timing of the
proposed 12T bitcell, and analyzes the half-selected and reverse
bias current issues. Section IV gives the evaluation of the write
ability, read ability, hold performance, and layout. Drawn
conclusions are given in Section V.
II. TFET DEVICE CHARACTERISTICS
Fig. 1(a) shows the structure of the 20 nm InAs double-gate
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Gate Parameter Value

Semiconductor band gap (EG ) 0.345 eV WL “1” WL “0”
Source Channel Drain
Reduced effective mass (MR) 0.012
Gate Channel thickness (TCH) 5m P3 P4 P3 P4
(a)

WBL
WBL
dielectric (b)

WBLB
WBLB
“0”
Threshold voltage (VTH) 0.145 V

“0”
“1”

“0”
-5 32 Built-in electric field (E0) 0.507 V/m
P1 P2 P2
10 Gate Length=20nm
Electric field parameter (R2) 1.89 1/m “0” “0” “0” P1 “0”
Gate Width=120nm Q
28 Sub-threshold ideality factor (N1) 1.49 Q
10-6 Vds=0.6V Tunneling window parameter (R0) 0.64 “1” “1”
“0” “0”
N5 N3 N4 N6 N5 N3 N4 N6
Ids (uA)

24 ION (uA) IOFF QB QB

10-7 TFET

C (aF)
ION/IOFF
Vgs=0.5V (uA)
N1 N2
ec

20 nm InAs N1 N2 “0” “1”

V/d

10-8 20 double gate 9.8 1.31e-4 7.5e+4 (a) RWL (b) RWL
42m

NTFET RBL RBL

10-9 16
SS=

Double-gate
InAs
N7 N7
100 2e-3 50e+5 N8 N8
12 Homojunction
0 0.1 0.2 0.3 0.4 0.5 0.6 Tunnel FET
(c) Vgs (d)
Fig. 2. Schematic and current flow paths, (a) the write 1 operation and (b) the
10 0 10 0 read of the proposed 12T SRAM bitcell.
hold W1 hold W0 hold read hold
Id (|Vgs|=0 V) Id (Vgs=0 V)
Ids (uA)
Ids (uA)

10 -2 10 -2 IdId(V
IdI(|V
d (|V gs|=0 V)
gs|=0.3 (Vgsgs=0.3 V)
=0 V) WL
IdI(|V gs|=0.4
d (|V V)V)
gs|=0.4
IdId(V =0.4V)
(Vgsgs=0.4 V)
10 -4 10 -4
WBL
d (|V
IdI(|V gs|=0.5
gs|=0.5 V)V) 10 -6
=0.5V)
(Vgsgs=0.5
IdId(V V)
10 -6
d (|V
IdI(|V gs|=0.6 V)
gs|=0.6V)
IdId(V =0.6V)
(Vgsgs=0.6 V) read
WBLB
-0.5 -0.25 0 0.25 0.5 -0.5 -0.25 0 0.25 0.5 RBL
(e) Vds (V) (f) Vds (V) W1 W0
Q(0 1) Q(1 0)
Fig. 1. (a) Device structure of 20 nm InAs double gate TFET, (b) device QB(1 0) QB(0 1)
parameters of 20 nm InAs double gate TFET, (c) Ids-Vgs and C-Vgs RWL
QB
characteristics of 20 nm InAs double gate NTFET, (d) performance parameters
of the different type of TFET structures, Ids-Vds characteristics of (e) 20 nm Q
InAs double gate PTFET and (f) NTFET on a logarithmic scale. Fig. 3. Diagram of the timing, including write, hold, and read.

TFET used in this paper. The parameters of the device are design [26]. However, with two write-assist TFETs, the
introduced in [22, 23]. Among the available TFET devices, WSNM can be improved. The source of the pull-up transistor
InAs double-gate TFET is an outstanding choice due to using (P1) is connected to the drain of the write-assist transistor (P3),
the double gate and III-V compound material which can and the source of the pull-up transistor (P2) is connected to the
effectively improve the conduction current [24]. Fig. 1(b) drain of the write-assist transistor (P4). The sources of the
shows the parameters of the device used in this paper. Fig. 1(c) write-assist transistors are connected to supply voltage.
shows Ids-Vgs and C-Vgs characteristics of NTFET. Fig. 1(d)
compares the parameters of the device used in this paper with B. SRAM operation
the Double-gate InAs Homojunction Tunnel FET [25]. 1) Hold
However, it should be noted that the proposed structure is In the hold mode, the lines WBL and WBLB are low to turn
independent of the model and can be applied to various TFET off the access transistors (N3 and N4) and turn on the write
devices. Fig. 1(e) and (f) shows the Ids-Vds characteristics of assist transistors (P3 and P4), while the word line (WL) is low
PTFET and NTFET, which will be used in simulations. to turn off the access transistors (N5 and N6). Therefore, the
Although the reverse bias current of the TFET becomes data can be latched with two cross-coupled inverters.
significant around 0.5V, the reverse bias current under low 2) Write
voltage (less than 0.5V) is much larger than the leakage current. If the original storage nodes Q and QB store “0” and “1”,
Therefore, it is necessary to design circuits without the reverse respectively, the voltage of the storage node QB is pulled to low
bias current. through the N4 and N6, and the voltage of the storage node Q is
pulled to high through the pull-up transistor P1 and write assist
III. REVERSE BIAS CURRENT ELIMINATED, READ-SEPARATED transistor P3. Since the write assist transistor P4 is turned off, it
, AND WRITE-ENHANCED TFET 12T BITCELL is easy to pull the voltage of the storage node QB low. As a
result, this cell structure has a strong write 1 ability. Because of
A. Cell structure
the strong write ability, the period of high WBL/WBLB can be
The structure of the reverse bias current eliminated, very short to ensure that the data of other cells in the same
read-separated, and write-enhanced TFET 12T SRAM bitcell is column with the selected cell remain unchanged. The current
shown in Fig. 2. The proposed structure consists of two flow paths in the write 1 operation are depicted in Fig. 2(a). The
cross-coupled inverters (P1, P2, N1, and N2), and it adopts a principle of writing 0 is similar to that of writing 1. The timing
read-decoupled access buffer (N7 and N8) to decouple the read diagram of various signals in different operating modes is
current path from the storage node, thereby eliminating shown in Fig. 3. The waveforms of Q (0→1) and Q (1→0)
read-disturb, avoiding read reverse bias current and enhancing illustrate the write 1 and write 0 processes, respectively.
the RSNM. This structure also adopts outward direction access 3) Read
transistors (N3, N4, N5 and N6), and the sources of N5 and N6 As shown in Fig. 3, the read bitline (RBL) is pre-charged to
are set to the ground at all times. Thus, this structure can the VDD in advanced in the read operation. Then, the RWL is set
effectively avoid reverse bias current in access transistors. As a to the VDD to turn on N7. If the storage node QB stores “1”, the
result, static power consumption can be reduced and the HSNM read decision transistor N8 is activated, and the RBL is
can be increased. discharged to the ground through N7 and N8 as depicted in Fig.
Single-ended write behavior might affect write delay and 2(b). Otherwise, the RBL maintains its pre-charged potential.
power significantly especially for the two access transistors

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0.8 0.8 Tunneling current Reverse bias current

Q1 QB1 “1”RBLj “0”RBLj+1 “1”RBLj “0”RBLj+1
0.6 0.6 RWLi
QB Q QB Q “1”
0.4
Voltage (V)

WBLB 0.4 WBLB

Voltage (V)
QB1 Tij QB2 Ti(j+1)
0.2 0.2 “1” Tij Ni(j+1)
QB1 QB2
QB1 Q1 “1” Nij Ti(j+1)
0 0 RWLi
“0”
-0.2 -0.2 RWLi+1
“0”
-0.4 -0.4
QB3 T(i+1)j QB4 T(i+1)(j+1)
0.4 0.6 0.8 1 0.4 0.6 0.8 1 N(i+1)j N(i+1)(j+1)
(a) Time (ns) (b) Time (ns) QB3 T(i+1)j QB4
T(i+1)(j+1)
RWLi+1
Fig. 4. Waveforms of the half-selected cells in the same column with the “1”
selected cell considering process variation. (a) Q1=1 and QB1=0, and (b) Q1=0 Cj Cj+1 Cj Cj+1
(a) (b)
and QB1=1.
10-4
1T 1T

Read Power (W)

C. Analysis of the half-selected issue and reverse bias current 3

Read Delay (ns)

2T 2T
When the selected cell performs a write operation, the 10-5
2
waveforms of the half-selected cells with the same column of
the selected cell are shown in Fig. 4. Fig. 4(a) shows the 1 10-6
situation when the storage nodes of half-selected cells (Q1 and
QB1) store “1” and “0”, respectively. Fig. 4(b) shows the
0 10-7
situation when the storage nodes of half-selected cells store “0” 0.3 0.4 0.5 0.6 0.3 0.4 0.5 0.6
(c) VDD (d) VDD
and “1”, respectively. It shows that when the selected cell
Fig. 5. Reverse bias current (a) in the 7T SRAM array, (b) in the proposed 12T
performs a write operation, as long as the period of the low SRAM array, (c) The read delay and (d) read power of the 1T and 2T read
level of WBL and WBLB is not long, it can ensure that the data structures.
of other cells in the same column are not changed.
The half-selected issue may also bring about the reverse bias and with the increase of voltage, this phenomenon becomes
current issue. For clarity, only the read part of the 7T SRAM more obvious.
array, 1T, is shown in Fig. 5(a). The upper left corner in Fig. 5(a)
is assumed to be the selected cell for the read operation. In the IV. PERFORMANCE EVALUATION
read operation, the read bit line (RBLj) is pre-charged to the
A. Write performance
VDD and the read word line (RWLi) is driven to ground, while
all other RWLs are set to VDD. If the storage node QB stores “1”, The write static noise margin (WSNM) of the proposed 12T
the RBLj is discharged through Tij, as indicated with the red SRAM, the combinational access SRAM (10T) [21], and the 7T
arrow in Fig. 5(a). At this time, the read access transistors of SRAM [20] are shown in Fig. 6(a) and (b). To achieve an
half-selected cells have reverse bias current, which will charge acceptable WSNM, the transistor size of the combinational
the RBLj, as indicated with the blue arrow in Fig. 5(a). If the access SRAM should be large enough. The proposed 12T
array contains more cells, the reverse bias current has a stronger SRAM and the 7T SRAM are at minimum size. For the 7T
impact on the read delay and power consumption. SRAM, the access transistor must drive the internal node Q to
The read part of the proposed 12T SRAM array, 2T, is shown the ground and flip the stored value without differential
in Fig. 5(b). The upper left corner is assumed to be the selected assistance from the access transistor, thus decreasing the write
cell. In the read operation, RBLj is pre-charged to VDD and ability of the 7T SRAM. At a supply voltage of 0.6 V, the
RWLi is set to VDD, thus the read pass transistor (Nij) is WSNM of the 7T SRAM is 106 mV. For the proposed 12T
activated. If the storage node QB stores “1”, then the read SRAM, when writing 1, the voltage of the QB is pulled low by
decision transistor (Tij) is activated. RBLj is discharged through the access transistors N4 and N6. Since the write assist
Nij and Tij to complete the reading operation, as indicated with transistor P4 is turned off, the voltage of the storage node QB is
the red arrow in Fig. 5(b). For half-selected cells, as the RWLi+1 hardly affected by noise, and thus it has a stronger WSNM. At a
and RBLj+1 are set to ground, and the source potential of the supply voltage of 0.6 V, the WSNM of the proposed 12T
n-TFET read access transistor is lower than the drain, this SRAM cell is 248 mV which is more than twice that of the 7T
structure can completely avoid reverse bias current in the read, SRAM. For the combinational access SRAM, the storage node
and thus can effectively reduce the read power consumption QB discharges to the ground through a series of two TFETs.
and read delay. Thus, it is more difficult to pull the voltage of the storage node
The read delay and read power of the 1T and 2T read path QB low. As shown in Fig. 6(b), at a supply voltage of 0.6 V, the
structures are shown in Fig. 5(c) and (d), which are obtained in WSNM of the combinational access SRAM is 158 mV when
an array with 256 rows. As shown in Fig. 5(c), Since the reverse the access transistors size and the pull-down transistors size
bias current is not obvious at low voltage (0.3V), the read delay ratio reaches 4. The write static noise margin of the 12T SRAM
of 2T is 28% lower than that of 1T. As the voltage increases, the is 60% larger than that of the combinational access SRAM with
reverse bias current increases, the read delay of 2T is 44% a large size ratio. Therefore, the proposed 12T SRAM has
lower than that of 1T at a supply voltage of 0.6 V. As shown in obvious advantages in terms of WSNM compared with the 7T
Fig. 5(d), the read power consumption of the 2T is lower than SRAM and the combinational access SRAM.
that of the 1T because of the reverse bias current of the 1T, Due to the write assist transistors N3 and N4, the write power
consumption of the proposed 12T SRAM is significantly

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0.6 0.6
V DD = 0.6V
200 198 The 7T SRAM
A B 180mVVDD =0.6V 10-5 The 7T SRAM

4 orders of magnitude down

248mV Combinational access SRAM
181 The proposed. 12T SRAM Combinational access SRAM
The proposed 12T 10-6 The proposed 12 The proposed 12T SRAM

Write Power (W)

158

95% down
TFET SRAM 0.5 10-6

WSNM (mV)
0.4 Combinational 150 T SRAM

Static Power (W)

access SRAM 122 186mV
QB (V)

158mV 100 0.4 Combinational 10-7

The 7T TFET
SRAM 10-7 access SRAM

QB (V)
0.2 106mV
50 47 0.3 10-8
12
0.2
144mV
0 0 10-8 10-9
0.1 0.2 0.3 0.4 0.5 0.6 1 2 3 4 5 6 0.3 0.4 0.5 0.6 The 7 T SRAM
(a) Q (V) (b) WAT/WPDT (VDD=0.6V) (c) VDD (V)
0.1 10-10
300 300 150 μ=0.2480
μ=0.1052 μ=0.1586
σ=0.00014
250 σ=0.0075 250 σ=0.0057 0
0 0.1 0.2 0.3 0.4 0.5 0.6 10-11 0.3 0.4 0.5 0.6
200 200 100
#Samples

#Samples
(a) (b)
#Samples

Q (V) VDD (V)

150 150
Fig. 7. (a) The hold static noise margin (HSNM) and (b) the static power
100 100 50
consumption of the 7T SRAM, the combinational access SRAM, and the
50 50
proposed 12T SRAM.
0 0 0 300 300 250
0.08 0.09 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2478 0.248 0.2482 μ=0.1454 μ=0.1860 μ=0.1800
WSNM (V) WSNM (V) (f) WSNM (V) 250 σ=0.0028 σ=0.0031 σ=0.0040
(d) (e) 250
200

Fig. 6. (a) The write static noise margin (WSNM) of the proposed 12T SRAM

#Samples
200 200

#Samples
150

#Samples
(minimum size), the combinational access SRAM, and the 7T SRAM 150 150

(minimum size), (b) WSNM of the combinational access SRAM (size ratio = [1, 100 100
100

6]), (c) the write power consumption of the 7T SRAM, the combinational 50 50
50

access SRAM, and the proposed 12T SRAM, WSNM histogram plots of (d) the 0 0 0
0.136 0.140 0.144 0.148 0.152 0.180 0.185 0.190 0.195 0.200 0.170 0.175 0.180 0.185 0.190 0.195
7T SRAM, (e) the combination access SRAM, and (f) the proposed 12T (a)
RSNM (V)
(b) (c)
RSNM (V) RSNM (V)
SRAM. Fig. 8. RSNM histogram plots of (a) the 7T SRAM, (b) the combination access
SRAM, and (c) the proposed 12T SRAM.
reduced compared with that of the combinational access SRAM.
As depicted in Fig. 6(c), at a supply voltage of 0.6 V, write transistor, the static power consumption of the 7T SRAM is
power consumption of the proposed 12T SRAM is reduced by increased. At a supply voltage of 0.6 V, the static power
95% compared with that of the combinational access SRAM consumption of the proposed 12T SRAM is 4 orders of
(10T). This clearly shows the promising of the proposed 12T magnitude lower than that of the 7T SRAM. Since the
SRAM for future memory-dominated low-power applications. combinational access SRAM and the proposed 12T SRAM do
There are two sources of variations including local variation not have reverse bias current in the hold state, static power of
or mismatch and global variation. These variations have been them is basically the same.
modeled as a ΔVth of the transistors. Assuming the threshold
variations have a Gaussian distribution with a standard C. Read performance
deviation of 20mV [27, 28], 2000 times Monte Carlo Assuming the threshold variations have a Gaussian
simulations in Fig. 6 (d), (e) and (f) show that the proposed 12T distribution with a standard deviation of 20mV, 2000 times
TFET SRAM cell has higher write stability under the threshold Monte Carlo simulations in Fig. 8 show that the RSNM of the
variations. proposed SRAM is improved by 24% compared with that of the
7T SRAM, and the RSNMs of the proposed 12T SRAM and the
B. Hold performance combination access SRAM are similar. As shown in Table 1,
The HSNMs of the 7T SRAM, the combinational access Large (H, R, W) means that the reverse bias current is larger
SRAM, and the proposed 12T SRAM, are shown in Fig. 7(a), during the hold, read and write. Small (H, R, W) means that the
represented by blue, black and red lines, respectively. The 7T reverse bias current is small. No means there is no reverse bias
SRAM uses an outward access transistor. If the BL and BLB of current during the hold, read and write. The proposed structure
7T are set to the 0, almost all bit lines need to be charged and completely avoids the reverse bias current, so the static power
discharged before and after the write operation. Therefore, the consumption decreases and the H/RSNM increases. 6T SRAM
BL and BLB are set to the VDD in the hold state. If the storage with GND lowering and raising achieves acceptable
node Q stores “0”, there is a reverse bias current from the bit performance at the cost of using multiple power supplies.
line to Q. For this reason, the voltage of Q will be charged from Besides, half-selected cells in 6T SRAM have large reverse
point A to point B, as shown in Fig. 7(a). So, the HSNM of the bias current in write mode.
7T SRAM decreases. At a supply voltage of 0.6 V, the HSNM
of the 7T SRAM is 144 mV. The proposed 12T SRAM uses D. Layout
outward access transistors and the sources of N5 and N6 are set Fig. 9(a) and (b) shows the schematic of the 7T bitcell and
to the ground in the hold mode. Therefore, the reverse bias the combinational access bitcell. Fig. 9(c), (d), and (e) are the
current of the structure can be effectively avoided. At a supply layout of the 7T bitcell, the combinational access bitcell, and
voltage of 0.6 V, the HSNM is 180 mV, which is 25% higher the proposed 12T bitcell under the 65nm process design rule,
than that of the 7T SRAM. Since the combinational access respectively. Note that the source and the drain of TFETs can
SRAM and the proposed 12T SRAM do not have a reverse bias not be shared, even they are on the same net. The area of the
current in the hold state, their HSNMs are basically the same. proposed 12T bitcell is 92% larger than that of the 7T bitcell.
The static power consumption of the 7T SRAM, the However, it is 6% smaller than the area of the combinational
combinational access SRAM, and the proposed 12T SRAM are access bitcell. That’s because the WSNM of combinational
shown in Fig. 7(b). As the 7T SRAM has a reverse bias current access bitcell is only 12mV (at VDD=0.6V) when access
from the bit line to the storage node through the access transistors are at the minimum size, and access transistors need
to be large to achieve acceptable performance.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2020.3011950, IEEE
Transactions on Circuits and Systems II: Express Briefs
> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 5

TABLE I [7] S. Strangio et al., "Benchmarks of a III-V TFET technology platform

PERFORMANCE OF DIFFERENT SRAM against the 10-nm CMOS FinFET technology node considering basic
SRAM cell Reverse bias current Static Power RSNM WSNM HSNM Multiple arithmetic circuits," Solid-State Electronics, vol. 128, pp. 37-42, 2017.
(VDD =0.6V) （W） (mV) (mV) (mV) power
The proposed 12T SRAM cell No 2.3×10-10 180 248 180 No
[8] Z. Wang et al., "Ultra-Low Power Hybrid TFET-MOSFET
7T TFET SRAM [20] Large (H,R,W) 10-6 144 106 144 No Topologies for Standard Logic Cells with Improved Comprehensive
-6
9T TFET SRAM [15] Large (H,R,W) 3×10 133 248 133 No Performance," IEEE International Symposium on Circuits and Systems
6T TFET SRAM with -10
GND lowering RA [17] Small (R), Large (W) 1.6×10 194 215 186 Yes (ISCAS), Sapporo, Japan, 2019, pp. 1-5.
6T SRAM with outward [9] R. Saha, K. Vanlalawmpuia, B. Bhowmick, S. Baishya, "Deep insight
Small (H), Large (R,W) 8.7×10-9 146 106 186 Yes
access transistors [18] into DC, RF/analog, and digital inverter performance due to variation
The combinational -10
access SRAM [21]
No 2×10 186 158 186 No in straggle parameter for gate modulated TFET", Materials Science in
Semiconductor Processing, vol 91, 2019, PP.102-107.
WL WL
S S S
https://doi.org/10.1016/j.mssp.2018.11.011.
P1 P2 P1 P2 P2 N2 N5
[10] F. Settino et al., "Understanding the Potential and Limitations of
BL Q BLB Q D D D D Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits," in
N3 QB N4
BL N3 N4 BLB
QB N6
P1 N4 IEEE Transactions on Electron Devices, vol. 64, no. 6, pp. 2736-2743,
N5
N1 N2
RBL
N1 N2 RWL
S S S June 2017.
N5 [11] B. Sedighi, X. S. Hu, H. Liu, J. J. Nahas, M. Niemier, "Analog Circuit
P+ N+ Ploy Metal M2
N7
N8
Design Using Tunnel-FETs," in IEEE Transactions on Circuits and
(a ) RWL (b) RBL Systems I: Regular Papers, vol. 62, no. 1, pp. 39-48, Jan. 2015.
4.8 um
[12] L. Barboni, M. Siniscalchi and B. Sensale-Rodriguez, "TFET-Based
S S S S D D S S S S D Circuit Design Using the Transconductance Generation Efficiency gm/
N7 P2 N2 N3 N5 N5 N3 N8 P2 N2 P4 Id Method," in IEEE Journal of the Electron Devices Society, vol. 3, no.

D D D D S S D D
D D D D S S D D
N8 N1 P1 N4 N6 P3 N1 P1
S S S S D D S S
(d)
Fig. 9. Schematics of (a) the 7T bitcell and (b) the combinational access bitcell,
and layout of (c) the 7T bitcell, (d) the combinational access bitcell, and (e) the
proposed 12T bitcell.
V. CONCLUSION
In this study, a 12T SRAM cell is proposed to solve the
problems caused by the reverse bias current. By avoiding the
reverse bias current, the 12T SRAM shows a better HSNM,
indicating that it is a promising candidate for ultra-low power
applications. By adopting a write assist circuit, the proposed
12T SRAM cell has a better WSNM compared with those of the
7T SRAM cell and the combinational access SRAM cell and
also has a lower write power. Additionally, the proposed 12T
SRAM cell can effectively avoid the half-selected issue and
improve circuit performance by decoupling read. Finally, the
area of the proposed 12T bitcell is 92% larger than that of the
7T bitcell, but is 6% smaller than that of the combinational
access bitcell.
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1549-7747 (c) 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: National Institute of Technology Patna. Downloaded on August 27,2020 at 10:44:16 UTC from IEEE Xplore. Restrictions apply.