ST24E16

ST25E16

16 Kbit Serial I2C EEPROM with Extended Addressing

COMPATIBLE with I2C EXTENDED

ADDRESSING
TWO WIRE SERIAL INTERFACE,
SUPPORTS 400kHz PROTOCOL
1 MILLION ERASE/WRITE CYCLES, OVER
the FULL SUPPLY VOLTAGE RANGE 8 8
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE 1 1
– 4.5V to 5.5V for ST24E16 version PSDIP8 (B) SO8 (M)
– 2.5V to 5.5V for ST25E16 version 0.25mm Frame 150mil Width
WRITE CONTROL FEATURE
BYTE and PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMING CYCLE Figure 1. Logic Diagram
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES

DESCRIPTION VCC
The ST24/25E16 are 16 Kbit electrically erasable
programmable memories (EEPROM), organized
as 8 blocks of 256 x8 bits. It is manufactured in 3
STMicroelectronics’s Hi-Endurance Advanced E0-E2 SDA
CMOS technology which guarantees an endur-
ance of one million erase/write cycles over the full ST24E16
supply voltage range, and a data retention of over SCL ST25E16
40 years. The ST25E16 operates with a power
supply value as low as 2.5V. WC

Table 1. Signal Names

VSS
E0 - E2 Chip Enable Inputs AI01102B

SDA Serial Data Address Input/Output

SCL Serial Clock
WC Write Control
VCC Supply Voltage
VSS Ground

February 1999 1/16

ST24E16, ST25E16

Figure 2A. DIP Pin Connections Figure 2B. SO Pin Connections

ST24E16 ST24E16
ST25E16 ST25E16

E0 1 8 VCC E0 1 8 VCC
E1 2 7 WC E1 2 7 WC
E2 3 6 SCL E2 3 6 SCL
VSS 4 5 SDA VSS 4 5 SDA
AI01103B AI01104C

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit

TA Ambient Operating Temperature –40 to 125 °C

TSTG Storage Temperature –65 to 150 °C

TLEAD Lead Temperature, Soldering (SO8) 40 sec 215

°C
(PSDIP8) 10 sec 260

VIO Input or Output Voltages –0.6 to 6.5 V

VCC Supply Voltage –0.3 to 6.5 V

Electrostatic Discharge Voltage (Human Body model) (2) 4000 V

VESD
(3)
Electrostatic Discharge Voltage (Machine model) 500 V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and
other relevant quality documents.
2. 100pF through 1500Ω; MIL-STD-883C, 3015.7
3. 200pF through 0Ω; EIAJ IC-121 (condition C)

DESCRIPTION (cont’d) the I2C bus definition. The ST24/25E16 behave as

Both Plastic Dual-in-Line and Plastic Small Outline
packages are available.
Each memory is compatible with the I2C extended
addressing standard, two wire serial interface
which uses a bi-directional data bus and serial
clock. The ST24/25E16 carry a built-in 4 bit, unique
device identification code (1010) corresponding to
slave devices in the I2C protocol with all memory
operations synchronized by the serial clock. Read
and write operations are initiated by a START
condition generated by the bus master. The START
condition is followed by a stream of 4 bits (identifi-
cation code 1010), 3 bit Chip Enable input to form
a 7 bit Device Select, plus one read/write bit and
terminated by an acknowledge bit.

2/16

Table 3. Device Select Code
Device Code
Bit b7 b6
Device Select 1 0
Note: The MSB b7 is sent first.
Table 4. Operating Modes
Mode RW bit
Current Address Read ’1’
’0’
Random Address Read
’1’
Sequential Read ’1’
Byte Write ’0’
Page Write ’0’
When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way.
Data transfers are terminated with a STOP condi-
tion. In this way, up to 8 ST24/25E16 may be
connected to the same I2C bus and selected indi-
vidually, allowing a total addressing field of 128
Kbit.
Power On Reset: VCC lock out write protect. In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Untill the VCC
voltage has reached the POR threshold value, the
internal reset is active: all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
SIGNALS DESCRIPTION
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 3)
ST24E16, ST25E16
Chip Enable RW
b5 b4 b3 b2 b1 b0
1 0 E2 E1 E0 RW
Bytes Initial Sequence
1 START, Device Select, RW = ’1’
START, Device Select, RW = ’0’, Address,
1
reSTART, Device Select, RW = ’1’
1 to 2048 As CURRENT or RANDOM Mode
1 START, Device Select, RW = ’0’
16 START, Device Select, RW = ’0’
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to VCC to act as pull up (see Figure 3).
Chip Enable (E0 - E2). These chip enable inputs
are used to set the 3 least significant bits of the 7
bit device select code. They may be driven dynami-
cally or tied to VCC or VSS to establish the device
select code. Note that the VIL and VIH levels for the
inputs are CMOS, not TTL compatible.
Write Control (WC). The Write Control feature
WC is useful to protect the contents of the memory
from any erroneous erase/write cycle. The Write
Control signal is used to enable (WC at VIH) or
disable (WC at VIL) the internal write protection.
The devices with this Write Control feature no
longer supports the multibyte mode of operation.
When unconnected, the WC input is internally read
as VIL (see Table 5).
When WC = ’1’, Device Select and Address bytes
are acknowledged; Data bytes are not acnowl-
edged.
Refer to the AN404 Application Note for more de-
tailed information about Write Control feature.
3/16
ST24E16, ST25E16
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus, fC = 400kHz
20
16
12
RL max (kΩ)
8
4
VCC = 5V
0
25 50 75
CBUS (pF)
DEVICE OPERATION
2 triggers the internal EEPROM write cycle.
I C Bus Background
The ST24/25E16 support the extended addressing
I2C protocol. This protocol defines any device that
sends data onto the bus as a transmitter and any
device that reads the data as a receiver.The device
that controls the data transfer is known as the
master and the other as the slave. The master will
always initiate a data transfer and will provide the
serial clock for synchronisation. The ST24/25E16
are always slave devices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25E16 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24/25E16
and the bus master. A STOP condition at the end
of a Read command forces the standby state. A
4/16
VCC
RL RL
SDA
MASTER CBUS
SCL
CBUS
100
AI01115
STOP condition at the end of a Write command
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successful data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse the receiver pulls the SDA bus low
to acknowledge the receipt of the 8 bits of data.
Data Input. During data input the ST24/25E16
sample the SDA bus signal on the rising edge of
the clock SCL. For correct device operation the
SDA signal must be stable during the clock low to
high transition and the data must change ONLY
when the SCL line is low.
Device Selection. To start communication be-
tween the bus master and the slave ST24/25E16,
the master must initiate a START condition. The 8
bits sent after a START condition are made up of a
device select of 4 bits that identifies the device type,
3 Chip Enable bits and one bit for a READ (RW =
1) or WRITE (RW = 0) operation. There are two
modes both for read and write. These are summa-
rised in Table 4 and described hereafter. A commu-
nication between the master and the slave is ended
with a STOP condition.
 ST24E16, ST25E16

Table 5. Input Parameters (1) (TA = 25 °C, f = 400 kHz )

Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance (SDA) 8 pF
CIN Input Capacitance (other pins) 6 pF
ZWCL WC Input Impedance VIN ≤ 0.3 VCC 5 20 kΩ
ZWCH WC Input Impedance VIN ≥ 0.7 VCC 500 kΩ
Low-pass filter input time constant
tLP 100 ns
(SDA and SCL)
Note: 1. Sampled only, not 100% tested.

Table 6. DC Characteristics
(TA = 0 to 70 ° or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)
Symbol Parameter Test Condition Min Max Unit
Input Leakage Current
ILI 0V ≤ VIN ≤ VCC ±2 µA
(SCL, SDA, E0-E2)
0V ≤ VOUT ≤ VCC
ILO Output Leakage Current ±2 µA
SDA in Hi-Z
Supply Current (ST24 series) fC = 400kHz 2 mA
ICC
(Rise/Fall time < 30ns)
Supply Current (ST25 series) 1 mA
VIN = VSS or VCC,
100 µA
Supply Current (Standby) VCC = 5V
ICC1
(ST24 series)
VIN = VSS or VCC,
300 µA
VCC = 5V, fC = 400kHz
VIN = VSS or VCC,
5 µA
Supply Current (Standby) VCC = 2.5V
ICC2
(ST25 series)
VIN = VSS or VCC,
50 µA
VCC = 2.5V, fC = 400kHz
VIL Input Low Voltage (SCL, SDA) –0.3 0.3 VCC V
VIH Input High Voltage (SCL, SDA) 0.7 VCC VCC + 1 V
VIL Input Low Voltage (E0-E2, WC) –0.3 0.5 V
VIH Input High Voltage (E0-E2, WC) VCC – 0.5 VCC + 1 V
Output Low Voltage (ST24 series) IOL = 3mA, VCC = 5V 0.4 V
VOL
Output Low Voltage (ST25 series) IOL = 2.1mA, VCC = 2.5V 0.4 V

5/16
ST24E16, ST25E16

Table 7. AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)
Symbol Alt Parameter Min Max Unit
tCH1CH2 tR Clock Rise Time 300 ns
tCL1CL2 tF Clock Fall Time 300 ns
(1)
tDH1DH2 tR SDA Rise Time 20 300 ns
(1)
tDL1DL1 tF SDA Fall Time 20 300 ns
tCHDX (2) tSU:STA Clock High to Input Transition 600 ns
tCHCL tHIGH Clock Pulse Width High 600 ns
tDLCL tHD:STA Input Low to Clock Low (START) 600 ns
tCLDX tHD:DAT Clock Low to Input Transition 0 µs
tCLCH tLOW Clock Pulse Width Low 1.3 µs
tDXCX tSU:DAT Input Transition to Clock Transition 100 ns
tCHDH tSU:STO Clock High to Input High (STOP) 600 ns
tDHDL tBUF Input High to Input Low (Bus Free) 1.3 µs
tCLQV (3) tAA Clock Low to Next Data Out Valid 200 1000 ns
tCLQX tDH Data Out Hold Time 200 ns
fC fSCL Clock Frequency 400 kHz
tW tWR Write Time 10 ms
Notes: 1. Sampled only, not 100% tested.
2. For a reSTART condition, or following a write cycle.
3. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.

Table 8. AC Measurement Conditions DEVICE OPERATION (cont’d)

Input Rise and Fall Times ≤ 50ns Memory Addressing. A data byte in the memory
is addressed through 2 bytes of address informa-
Input Pulse Voltages 0.2VCC to 0.8VCC tion. The Most Significant Byte is sent first and the
Least significant Byte is sent after. The Least Sig-
Input and Output Timing Ref.
Voltages
0.3VCC to 0.7VCC nificant Byte addresses a block of 256 bytes, bits
b10,b9,b8 of the Most Significant Byte select one
block among 8 blocks (one block is 256 bytes).
Figure 4. AC Testing Input Output Waveforms
Most Significant Byte
0.8VCC X X X X X b10 b9 b8
0.7VCC
X = Don’t Care.
0.3VCC
0.2VCC
Least Significant Byte
AI00825

b7 b6 b5 b4 b3 b2 b1 b0

6/16
 ST24E16, ST25E16

Figure 5. AC Waveforms

tCHCL tCLCH

SCL

tDLCL tDXCX tCHDH

SDA IN

tCHDX tCLDX tDHDL

START SDA SDA STOP &

CONDITION INPUT CHANGE BUS FREE

SCL

tCLQV tCLQX

SDA OUT DATA VALID

DATA OUTPUT

SCL

tW

SDA IN

tCHDH tCHDX

STOP WRITE CYCLE START

CONDITION CONDITION

AI00795B

7/16
ST24E16, ST25E16

Figure 6. I2C Bus Protocol

SCL

SDA

START SDA SDA STOP

CONDITION INPUT CHANGE CONDITION

SCL 1 2 3 7 8 9

SDA MSB ACK

START
CONDITION

SCL 1 2 3 7 8 9

SDA MSB ACK

STOP
CONDITION

AI00792

Write Operations
Following a START condition the master sends a
device select code with the RW bit reset to ’0’. The
ST24/25E16 acknowledge this and waits for 2
bytes of address. These 2 address bytes (8 bits
each) provide access to any of the 8 blocks of 256
bytes each. Writing in the ST24/25E16 may be
inhibited if input pin WC is taken high.
For the ST24/25E16 versions, any write command
with WC = ’1’ (during a period of time from the
START condition untill the end of the 2 Bytes
Address) will not modify data and will NOT be
acknowledged on data bytes, as in Figure 9.
Byte Write. In the Byte Write mode the master
sends one data byte, which is acknowledged by the
ST24/25E16. The master then terminates the
transfer by generating a STOP condition.
Page Write. The Page Write mode allows up to 16
bytes to be written in a single write cycle, provided
that they are all located in the same row of 16 bytes
in the memory, that is the same Address bits (b10-
b4). The master sends one up to 16 bytes of data,
which are each acknowledged by the ST24/25E16.
After each byte is transfered, the internal byte
address counter (4 Least Significant Bits only) is
incremented. The transfer is terminated by the
master generating a STOP condition. Care must be
taken to avoid address counter ’roll-over’ which

8/16
 ST24E16, ST25E16

could result in data being overwritten. Note that for
any write mode, the generation by the master of the
STOP condition starts the internal memory pro-
gram cycle. All inputs are disabled until the comple-
tion of this cycle and the ST24/25E16 will not
respond to any request.
Minimizing System Delay by Polling On ACK.
During the internal Write cycle, the ST24/25E16
disable itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the Write time (tW) is given in the
AC Characteristics table, this timing value may be
reduced by an ACK polling sequence issued by the
master.
The sequence is:
– Initial condition: a Write is in progress (see Fig-
ure 7).
– Step 1: the Master issues a START condition
followed by a Device Select byte. (1st byte of
the new instruction)
– Step 2: if the ST24/25E16 are internally writ-
ing, no ACK will be returned. The Master goes
back to Step1. If the ST24/25E16 have termi-
nated the internal writing, it will issue an ACK.
The ST24/25E16 are ready to receive the sec-
ond part of the instruction (the first byte of this
instruction was already sent during Step1).

Figure 7. Write Cycle Polling using ACK

WRITE Cycle
in Progress

START Condition

DEVICE SELECT
with RW = 0

NO ACK
Returned

First byte of instruction YES

with RW = 0 already
decoded by ST24xxx

Next
NO Operation is YES
Addressing the
Memory
Send
Byte Address
ReSTART

STOP

Proceed Proceed
WRITE Operation Random Address
READ Operation

AI01099B

9/16
ST24E16, ST25E16

Figure 8. Write Modes Sequence with Write Control = 0

WC

ACK ACK ACK NO ACK

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

START

STOP
R/W

WC

ACK ACK ACK NO ACK

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1 DATA IN 2
START

R/W

WC (cont'd)

NO ACK NO ACK

PAGE WRITE DATA IN N

(cont'd)
STOP

AI01120B

Read Operations Random Address Read. A dummy write is per-

On delivery, the memory content is set at all "1’s"
(or FFh).
Current Address Read. The ST24/25E16 have
an internal 11 bits address counter. Each time a
byte is read, this counter is incremented. For the
Current Address Read mode, following a START
condition, the master sends a Device Select with
the RW bit set to ’1’. The ST24/25E16 acknowledge
this and outputs the byte addressed by the internal
address counter. This counter is then incremented.
The master does NOT acknowledge the byte out-
put, but terminates the transfer with a STOP con-
dition.
formed to load the address into the address
counter, see Figure 10. This is followed by another
START condition from the master and the byte
address repeated with the RW bit set to ’1’. The
ST24/25E16 acknowledge this and outputs the
byte addressed. The master does NOT acknow-
ledge the byte output, but terminates the transfer
with a STOP condition.
Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
ST24/25E16 continue to output the next byte in

10/16
 ST24E16, ST25E16

Figure 9. Write Modes Sequence with Write Control = 1

WC

ACK ACK ACK ACK

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

START

STOP
R/W

WC

ACK ACK ACK ACK

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1 DATA IN 2
START

R/W

WC (cont'd)

ACK ACK

PAGE WRITE DATA IN N

(cont'd)
STOP

AI01106B

sequence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
ically incremented after each byte output. After a
count of the last memory address, the address
counter will ’roll-over’ and the memory will continue
to output data.
Acknowledge in Read Mode. In all read modes
the ST24/25E16 wait for an acknowledge during
the 9th bit time. If the master does not pull the SDA
line low during this time, the ST24/25E16 terminate
the data transfer and switch to a standby state.

11/16
ST24E16, ST25E16

Figure 10. Read Modes Sequence

ACK NO ACK
CURRENT
ADDRESS DEV SEL DATA OUT
READ START

STOP
R/W

ACK ACK ACK ACK NO ACK

RANDOM
ADDRESS DEV SEL * BYTE ADDR BYTE ADDR DEV SEL * DATA OUT
READ
START

START

STOP
R/W R/W

ACK ACK ACK NO ACK

SEQUENTIAL
CURRENT DEV SEL DATA OUT 1 DATA OUT N
READ
START

STOP
R/W

ACK ACK ACK ACK ACK

SEQUENTIAL
RANDOM DEV SEL * BYTE ADDR BYTE ADDR DEV SEL * DATA OUT 1
READ
START

START

R/W R/W

ACK NO ACK

DATA OUT N
STOP

AI01105C

Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 4th byte) must be identical.

12/16
 ST24E16, ST25E16

ORDERING INFORMATION SCHEME

Example: ST24E16 M 1 TR

Operating Voltage Range Package Temperature Range Option

24 4.5V to 5.5V E Extended B PSDIP8 1 0 to 70 °C TR Tape & Reel
Addressing 0.25mm Frame Packing
25 2.5V to 5.5V 6 –40 to 85 °C
M SO8
150mil Width 3 (1) –40 to 125 °C

Note: 1. Temperature range on special request only.

Devices are shipped from the factory with the memory content set at all "1’s" (FFh).

For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect
of this device, please contact the STMicroelectronics Sales Office nearest to you.

13/16
ST24E16, ST25E16

PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

mm inches
Symb
Typ Min Max Typ Min Max
A 3.90 5.90 0.154 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.130 0.209
B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065
C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390
E 7.62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264
e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB – 10.00 – 0.394
L 3.00 3.80 0.118 0.150
N 8 8

A2 A

A1 L
B e1 C
B1 eA
D eB

E1 E

1
PSDIP-a

Drawing is not to scale.

14/16
 ST24E16, ST25E16

SO8 - 8 lead Plastic Small Outline, 150 mils body width

mm inches
Symb
Typ Min Max Typ Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α 0° 8° 0° 8°
N 8 8
CP 0.10 0.004

h x 45˚

A
C
B
e CP

E H
1

A1 α L

SO-a

Drawing is not to scale.

15/16
ST24E16, ST25E16

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

© 1999 STMicroelectronics - All Rights Reserved
All other names are the property of their respective owners

Purchase of I2C Components by STMicroelectronics, conveys a license under the Philips

I2C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.

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