Lecture 1,2,3,4,5,6,7,8

VI
Vishwakarma Institute of Technology
ROBOTICS
Computational Devices
VI To Compute = To Calculate
Essential Features of a computing device –
1) Input data
2) Processing units
3) Output i.e. Answer
Additional Features –
1) Storage of the data and output
2) To retrieve the data and output when required
3) Print / Display / Transfer the output
4) Make changes in the process
Role of Flip-flops
VI • Storage and Retrieval of the Data.
• Flip-flop is the basic unit which can do this.
• Thus called as basic building block of memory.
• A flip-flop has two stable states, thus, called as a

bistable multivibrator.
• Flip-flops and Latches are used as data storage
elements.
• A Flip-flop is a device which can store a single
bit (binary digit) of data.
• Many Flip-flops together form the memory of the
computing device.
Microprocessor
VI
A microprocessor is an electronic device that is
used by a computer. It is a central processing unit
on a single integrated circuit chip containing

millions of very small components including
transistors, resistors, and diodes that work
together.
It has no specific task given for which it is
designed. Thus, it can be programmed as per the
need.
VI • Non-volatile memory (ROM)
• Volatile memory (RAM)
• Clock
• I/O control unit etc.
Microprocessor has Microcontroller has

only the CPU in it the CPU along with
and these features these features
are to be added embedded inside in a
from outside single chip.
Microprocessor Microcontroller
As all the memory, I/O are As all the memory, I/O are
added from outside, size of present internally, size of the
the circuit is large. circuit is small.
As all the devices are As most of the devices are in-
external, each instruction has built, most of the operations
external operation, thus are internal, thus faster
slower process. process.
High power consumption Low power consumption
High cost Low cost
Non specific, Generalized Dedicated applications such

applications such as as Washing machines,
Personal Computers Automobiles, Music systems
etc.
Difficulty in writing program Easier to write program
28/06/2014 6
History of Micro Processors contd….
VI
History of Micro Processors contd….
VI Name of Year of Clock speed No. of Instructions
Process Invention transistors per second
or
Intel core2 duo, 1.2 GHz to 291 000 000 64 KB of
Core 2 core2 3 GHz L1 cache

quad, per core
etc.
4 MB of
L2 cache
i3, i5, 2007, 2009, 2.2GHz – 1.75 Billion
i7 2010 3.3GHz, 2.1 Billion
2.4GHz –
3.6GHz,
2.93GHz –
3.33GHz
Embedded System Features
VI 1) Combination of Hardware and Software –
2) There is a specific task given –
3) There is a dialogue between the h/w and s/w –
4) It can be a small part of a bigger system –

5) Specific program instructions are written in the
ROM called as firmware, thus can not be used
in any other system –
6) Examples – Washing machines, Mobile phones,
Microwave ovens, Automobiles, Video devices,
Video games, Music systems, Cameras,
Medical instruments, Defence weapons …..
Embedded System Features
VI 7) Requires less power –
8) Highly stable system –
9) Highly reliable –
10) Highly efficient –

11) Minimal user interface –
12) Time specific –
13) Task specific –
14) Mass produced thus cheap –
15) A little development in the system will make
earlier version obsolete –
16) User friendly –
Block Diagram of a Basic
Microcomputer
VI
How does a Microprocessor Work?

The microprocessor follows a sequence: Fetch, Decode, and then Execute.
Initially, the instructions are stored in the memory in a sequential order. The
microprocessor fetches those instructions from the memory, then decodes it
and executes those instructions till STOP instruction is reached. Later, it sends
the result in binary to the output port. Between these processes, the register
stores the temporarily data and ALU performs the computing functions.
VI
Lecture 2
VI
Classification of Embedded Systems
VI
Small scale embedded system – Uses an 8 bit

microcontroller, very few hardware components and a small
power source.
Medium scale embedded systems – Uses a 16 bit or 32 bit
microcontroller, h/w and s/w are complicated. Uses RTOS,
Simulator, Debugger and some special purpose tools for the
design. e.g. Home appliances, security systems etc.
VI
Sophisticated embedded system – Uses huge h/w and s/w

and is very complex. Costly systems. Used for high end
applications. Many subsystems are required to be designed
to build the complete system. Dedicated special purpose
Development tools are required.
e.g. Washing machines, Mobile phones, Automobiles,
Medical instruments, Defence weapons etc.
VI Stand alone embedded systems – Least complicated type
of embedded system. Do not require support from any
computer. Works of its own independently. i/p can be analog
or digital. e.g. Calculator, Digital wrist watch etc.
Real time embedded systems – These are functions of time.

Work in definite time interval. Further types are Soft time E.S.
(Microwave oven, Washing machine) and Hard time E.S.
(Missiles, Robotics, Space operations)
Networked embedded systems – Connected to a network
like LAN, WAN, Internet etc. e.g. ATM, Card swipe machine,
Home security system etc.
Mobile embedded systems – Portable E.S. like Cell phones,
Digital Data devices etc.
VI
Lecture 3
Microprocessor and Microcontroller
VI
Microcontroller
VI • It’s like a small computer on a single IC.
• It contains a processor core, ROM, RAM and I/
O pins.
• it has all the components needed in its single

chip, it does not need any external circuits to do
its task so microcontrollers are heavily used in
embedded systems.
• examples 8051, AVR, PIC series of
microcontrollers.
Microprocessor
VI
• Microprocessor has only a CPU inside them in one or
few Integrated Circuits.
• They are dependent on external circuits of
peripherals to work.
• Microprocessors are not made for specific task but they
are required where tasks are complex and tricky like
development of software’s, games and other
applications that require high memory and where input
and output are not defined.
• examples of microprocessor are Pentium, I3, and I5 etc.

Key Difference Between Controller & Processo
VI • Microcontrollers have RAM, ROM, EEPROM embedded in it while we
have to use external circuits in case of microprocessors.
• As all the peripheral of microcontroller are on single chip it is compact

while microprocessor is bulky.
• Microcontrollers are cheaper microprocessors are high cost because

of the high number of external components required for such systems.
• Processing speed of microcontrollers is about 8 MHz to 50 MHz ,

microprocessors is above 1 GHz so it works much faster than
microcontrollers.
• Power consumption in Microcontroller is less, Microprocessors power

consumption is High.
• Microcontrollers are compact small product and Application ,

Microprocessors are bulky so they are preferred for larger applications
Key Difference Between Controller & Processor
VI
• Tasks performed by microcontrollers are limited and
generally less complex, microprocessors are software
development, Game development, website, documents
making etc. which are generally more complex

so require more memory and speed so that’s why
external ROM, RAM are used with it.
• Microcontrollers are based on Harvard architecture

where program memory and data memory are separate
while microprocessors are based on von Neumann
model where program and data are stored in same
memory module.
RISC vs. CISC
VI RISC CISC
Lesser no of Instructions Greater no of Instructions
Instruction pipelining and increased Generally no Instruction pipelining

execution speed.
Orthogonal Instruction set (Allows each Non-orthogonal instruction set ( All

Instruction on operate on any register and Instructions are not allowed to operate on
use any addressing mode) any register and use any addressing mode.
it is instruction-specific)
Operations are performed on registers only, Operations are performed on registers or
the only memory operations are load and memory depending on the instruction
store.
A large number of registers are available Limited number of general purpose
registers
Programmers needs to write more code to Instructions are like macros In C language.
execute a task since the instructions are A programmer can archive the desired
simpler ones. functionality with a single instruction which
in turn provides the effect of using more
simpler single instructions in RISC
Single fixed length instructions Variable length instructions

VI
Lecture 4
Memory
VI •Memory is an important part of an embedded system. The memory
used in embedded system can be either Program Storage Memory
(ROM) or Data memory (RAM) .
•Certain Embedded processors/controllers contain built in program

memory and data memory and this memory is known as on-chip
memory .
•Certain Embedded processors/controllers do not contain sufficient

memory inside the chip and requires external memory called off-chip
memory or external memory.
Memory – Program Storage Memory
VI •Stores the program instructions.
•Retains its contents even after the power to it is turned off. It is

generally known as Non volatile storage memory.
•Depending on the fabrication, erasing and programming techniques

they are classified into.
Masked ROM (MROM):
•One-time programmable memory.
VI
•Uses hardwired technology for storing data.
•The device is factory programmed by masking and metallization process
according to the data provided by the end user.
•The primary advantage of MROM is low cost for high volume production.
MROM is the least expensive type of solid state memory.
•Different mechanisms are used for the masking process of the ROM, like
1.Creation of an enhancement or depletion mode transistor through
channel implant
2.By creating the memory cell either using a standard transistor or a high
threshold transistor.
3.In the high threshold mode, the supply voltage required to turn ON the
transistor is above the normal ROM IC operating voltage.
4.This ensures that the transistor is always off and the memory cell
stores always logic 0.
Masked ROM (MROM):
VI •The limitation with MROM based firmware storage is the inability to modify
the device firmware against firmware upgrades.
•The MROM is permanent in bit storage, it is not possible to alter the bit
information
Programmable Read Only Memory (PROM) / (OTP)
•It is not pre-programmed by the manufacturer
VI
•The end user is responsible for Programming these devices.

•PROM/OTP hasnichrome orpolysilicon wires arranged in a matrix,
these wires can be functionally viewed as fuses.

•It is programmed by a PROM programmer which selectively burns
the fuses according to the bit pattern to be stored.

•Fuses which are not blown/burned represents a logic “1” where as
fuses which are blown/burned represents a logic “0”.The default state
is logic “1”.

•OTP is widely used for commercial production of embedded systems
whose proto-typed versions are proven and the code is finalized.
•It is a low cost solution for commercial production.

•OTPs cannot be reprogrammed
Erasable Programmable Read Only Memory (EPROM)
•Erasable Programmable Read Only (EPROM) memory gives the
VI flexibility to re-program the same chip.
•During development phase , code is subject to continuous
changes and using an OTP is not economical.
•EPROM stores the bit information by charging the floating gate
of an FET
•Bit information is stored by using an EPROM Programmer,
which applies high voltage to charge the floating gate
•EPROM contains a quartz crystal window for erasing the stored
information. If the window is exposed to Ultra violet rays for a
fixed duration, the entire memory will be erased

•Even though the EPROM chip is flexible in terms of re-
programmability, it needs to be taken out of the circuit board
and needs to be put in a UV eraser device for 20 to 30 minutes
Electrically Erasable Programmable Read Only Memory
(EEPROM):
VI • Erasable Programmable Read Only (EPROM) memory
gives the flexibility to re-program the same chip using
electrical signals

• The information contained in the EEPROM memory can

be altered by using electrical signals at the register/Byte
level
They can be erased and reprogrammed within the circuit

• These chips include a chip erase mode and in this
mode they can be erased in a few milliseconds.
• It provides greater flexibility for system design

• The only limitation is their capacity is limited when
compared with the standard ROM (A few kilobytes).
Program Storage Memory – FLASH
•FLASH memory is a variation of EEPROM technology.
VI
•FALSH is the latest ROM technology and is the most popular ROM
technology used in today’s embedded designs.

•It combines the re-programmability of EEPROM and the high

capacity of standard ROMs.
•FLASH memory is organized as sectors (blocks) or pages.

•FLASH memory stores information in an array of floating gate
MOSFET transistors.

•The erasing of memory can be done at sector level or page level
without affecting the other sectors or pages.
•Each sector/page should be erased before re-programming.

•The typical erasable capacity of FLASH is of the order of a few
1000 cycles.
Read-Write Memory/Random Access Memory (RAM)
VI •RAM is the data memory or working memory of the controller/

processor.
•RAM is volatile, meaning when the power is turned off, all the
contents are destroyed.
•RAM is a direct access memory, meaning we can access the

desired memory location directly without the need for traversing
through the entire memory locations to reach the desired memory
position (i.e. Random Access of memory location).
Static RAM (SRAM)
VI •Static RAM stores data in the form of Voltage.
•They are made up of flip-flops
•In typical implementation, an SRAM cell (bit) is realized using 6 transistors
(or 6 MOSFETs).
Four of the transistors are used for building the latch (flip-
flop) part of the memory cell and 2 for controlling the access.
•Static RAM is the fastest form of RAM available.
•SRAM is fast in operation due to its resistive networking and switching
capabilities
Dynamic RAM (DRAM)
VI •Dynamic RAM stores data in the form of charge. They are made up of MOS
transistor gates .
•The advantages of DRAM are its high density and low cost compared to
SRAM .
•The disadvantage is that since the information is stored as charge it gets
leaked off with time and to prevent this they need to be refreshed periodically .
•Special circuits called DRAM controllers are used for the refreshing operation.
The refresh operation is done periodically in milliseconds interval .
SRAM Vs DRAM
VI
SRAM Cell DRAM Cell
Made up of 6 CMOS transistors Made up of a MOSFET and a

(MOSFET) capacitor
Doesn’t Require refreshing Requires refreshing
Low capacity (Less dense) High Capacity (Highly dense)
More expensive Less Expensive
Fast in operation. Typical access Slow in operation due to refresh
time
requirements. Typical access
is 10ns time is
60ns.
Write operation is faster than
read operation.
VI
Lecture 5,6
VI
Vishwakarma Institute of Technology RAM
VI
Vishwakarma Institute of Technology ROM
Non Volatile RAM (NVRAM):
VI • Random access memory with battery backup

• It contains Static RAM based memory and a minute
battery for providing supply to the memory in the
absence of external power supply

• The memory and battery are packed together in a single
package
• NVRAM is used for the non volatile storage of results of
operations or for setting up of flags etc.
• The life span of NVRAM is expected to be around 10
years.
• DS1744 from Maxim/Dallas is an example for 32KB
VI
Vishwakarma Institute of Technology Von Neumann architecture
Three basic units
VI •The Central Processing Unit (CPU)
•The Main Memory Unit
•The Input/Output Device

Control Unit –A control unit (CU) handles all processor control signals. It
directs all input and output flow, fetches code for instructions and controlling
how data moves around the system.
Arithmetic and Logic Unit (ALU) –The arithmetic logic unit is that part of the
CPU that handles all the calculations the CPU may need, e.g. Addition,
Subtraction, Comparisons. It performs Logical Operations, Bit Shifting
Operations, and Arithmetic Operation.

Basic CPU structure, illustrating ALU
VI
Main Memory Unit (Registers)
VI Accumulator: Stores the results of calculations made by ALU.
Program Counter (PC): Keeps track of the memory location of the

next instructions to be dealt with. The PC then passes this next
address to Memory Address Register (MAR).
Memory Address Register (MAR): It stores the memory locations of

instructions that need to be fetched from memory or stored into
memory.
Memory Data Register (MDR): It stores instructions fetched from

memory or any data that is to be transferred to, and stored in,
memory.
Current Instruction Register (CIR): It stores the most recently

fetched instructions while it is waiting to be coded and executed.
Instruction Buffer Register (IBR): The instruction that is not to be

executed immediately is placed in the instruction buffer register IBR.
VI Input/Output Devices – Program or data is read into main memory
from the input device or secondary storage under the control of CPU
Output devices are used to output the information
input instruction.
from a computer. If some results are evaluated by computer and it is
stored in the computer, then with the help of output devices, we can
present it to the user.
Buses – Data is transmitted from one part of a computer to another,

connecting all major internal components to the CPU and memory,
by the means of Buses. Types:
Data Bus: It carries data among the memory unit, the I/O devices,
and the processor.
Address Bus: It carries the address of data (not the actual data)
between memory and processor.
Control Bus: It carries control commands from the CPU (and

status signals from other devices) in order to control and
coordinate all the activities within the computer.
Architecture
VI Harvard Architecture Von-Neumann
Architecture
Separate buses for Single shared for
Instruction and Data Instruction and data
fetching fetching
Easier to pipeline so high Low performance
performance compared to Harvard
architecture
Comparatively high cost Cheaper
Since data memory and Since data memory and

program memory are program memory are
stored physically in stored physically in the
different locations no same chip chances for
changes for accidental accidental corruption of
corruption of program program memory.
Computer Organization | RISC and CISC
VI Reduced instruction set computing (RISC) –
The main idea behind is to make hardware simpler by
using an instruction set composed of a few basic steps
for loading, evaluating and storing operations just like a
load command will load data, store command will store

the data.
Complex instruction set computing (CISC) –
The main idea is to make hardware complex as a single
instruction will do all loading, evaluating and storing
operations just like a multiplication command will do
stuff like loading data, evaluating and storing it.
Both approaches try to increase the CPU performance

VI RISC: In RISC machine, cycle is already defined i.e one,
so it fetches the instruction quickly
CISC: CISC instruction set multiple machine cycle is
present that's why it takes more time to execute.
Characteristic of RISC –
Simpler instruction, hence simple instruction decoding.
Instruction come under size of one word. ( 1 word = 16
bits)
Instruction take single clock cycle to get executed.
More number of general purpose register.
Simple Addressing Modes.
Less Data types.
Pipelining can be achieved , because it uses Harvard
architecture
VI Characteristic of CISC –
Complex instruction, hence complex instruction

decoding.
Instruction are larger than one word size.

Instruction may take more than single clock cycle to
get executed.
Less number of general purpose register as operation
get performed in memory itself.
Complex Addressing Modes.
More Data types.
VI Example – Suppose we have to add two 8-bit number:
CISC approach: There will be a single command or
instruction for this like ADD which will perform the task.
RISC approach: Here programmer will write first load
command to load data in registers then it will use

suitable operator and then it will store result in desired
location.
So, add operation is divided into parts i.e. load, operate,
store due to which RISC programs are longer and require
more memory to get stored but require less transistors
due to less complex command.
VI
RISC vs. CISC
VI RISC CISC
Lesser no of Instructions Greater no of Instructions
Instruction pipelining and increased Generally no Instruction pipelining

execution speed.
A instruction execute in single clock cycle Instruction take more than one clock cycle
RISC needs more RAM whereas CISC has an emphasis on smaller

code size and uses less RAM
A large number of registers are available Limited number of general purpose

registers ( for specific purpose )
Programmers needs to write more code to Instructions are like macros In C language.
execute a task since the instructions are A programmer can archive the desired
simpler ones. functionality with a single instruction which
Code size is large in turn provides the effect of using more
simpler single instructions in RISC.
Code size is small
Single fixed length instructions Variable length instructions
With Harvard Architecture Can be Harvard or Von-Neumann

MICROCONTROLLER 8051 ARCHITECTURE
VI
VI
Vishwakarma Institute of Technology Microcontroller 8051
Pin Description
VI Pin No. Description
Pins 1-8 PORT 1 - Each of these pins can be configured as an input

or an output.
Pin 9 RESET - A logic one on this pin disables the microcontroller

and clears the contents of most registers. In other words,
the positive voltage on this pin resets the microcontroller.
By applying logic zero to this pin, the program starts
execution from the beginning.
Pins10-1 PORT 3 - Similar to port 1, each of these pins can serve as
7 general input or output. Besides, all of them have
alternative functions .
Pin 10 RXD - Serial asynchronous communication input or Serial
synchronous communication output.
Pin 11 TXD - Serial asynchronous communication output or Serial

synchronous communication clock output.
Pin Description
Pin 12 INT0 - External Interrupt 0 input
Pin 13 INT1 - External Interrupt 1 input
Pin 14 T0 - Counter 0 clock input

Pin 15 T1 - Counter 1 clock input
Pin 16 WR - Write to external (additional) RAM
Pin 17 RD - Read from external RAM
Pin 18, XTAL2, XTAL1 - Internal oscillator input and output. A
19 quartz crystal which specifies operating frequency is usually
connected to these pins.
Pin 20 GND - Ground.
Pin Port 2 - If there is no intention to use external memory then
21-28 these port pins are configured as general inputs/outputs. In
case external memory is used, the higher address byte, i.e.
addresses A8-A15 will appear on this port.
Pin Description
Pin 29 PSEN - If external ROM is used for storing program then a

logic zero (0) appears on it every time the microcontroller
reads a byte from memory.
Pin 30 ALE - Prior to reading from external memory, the

microcontroller puts the lower address byte (A0-A7) on P0
and activates the ALE output.
Pin 31 EA - By applying logic zero to this pin, P2 and P3 are used

for data and address transmission with no regard to
whether there is internal memory or not.
Pin 32-39 PORT 0 - Similar to P2, if external memory is not used,

these pins can be used as general inputs/outputs.
Pin 40 VCC - +5V power supply.

I/O Port Pins
VI
The four 8-bit I/O ports P0, P1, P2 and P3 each
uses 8 pins.
All the ports upon RESET are configured as output,
ready to be used as input ports by the external

device
Port 0
VI
Port 0 is also designated as AD0-
AD7.
 When connecting an 8051 to an

external memory, port 0 provides both
address and data.
 The 8051 multiplexes address and
data through port 0 to save pins.
 ALE indicates if P0 has address or
data. When ALE=0, it provides data
D0-D7
 When ALE=1, it has address A0-A7
Port 1 and Port 2
VI In 8051-based systems with no external
memory connection:
Both P1 and P2 are used as simple I/O.
In 8051-based systems with external
memory connections:
Port 2 must be used along with P0 to
provide the 16-bit address for the external
memory.
P0 provides the lower 8 bits via A0 – A7.
 P2 is used for the upper 8 bits of the 16-
bit address, designated as A8 – A15, and it
cannot be used for I/O
Port 3
VI Port 3 can be used as input or output.
 Port 3 has the additional function of
providing some extremely important
signals
Features of 8051 Microcontroller
VI • 8 - bit CPU with registers A and B
• 16 bit program counter and data pointer
• 8 Bit Program Status Word (PSW)
• 8 Bit Stack Pointer
• 4K bytes of internal program memory (code memory)

[ROM]
• 128 bytes of internal data memory [RAM]
• 32 bidirectional I/O lines arranged as four 8-bit ports P0 –
P3
• Two 16 Bit Timer/Counter :T0, T1
• Full Duplex serial data receiver/transmitter
• Control registers: TCON, TMOD, SCON, PCON, IP and IE
• Two external and 3 internal interrupt sources
• On chip oscillator and clock circuit
• 64 K bytes of external program memory address space
VI
Vishwakarma Institute of Technology Programming Model of 8051
VI
Figure (a): Crystal Oscillator

Continued…..
• The clock frequency f1 establishes the smallest interval
of time within the microcontroller, called the pulse time
P.
• The smallest interval of time to accomplish any simple
instruction, or part of a complex instruction is called as
the machine cycle.
• The machine cycle is made up of six states.
• A state is the basic time interval for discrete operations
of the microcontroller such as fetching an opcode byte,
decoding opcode, executing an opcode, or writing a
data byte.
• The oscillator pulses define each state.
Continued…..
• Program instruction may require one, two or four

machine cycles to be executed, depending on the type of
the instruction.
• Instruction are fetched and executed, by the
microcontroller automatically, beginning with the
instruction located at ROM memory address 0000h at
the time the microcontroller is first reset.
• We can calculate the time any particular instruction will
take to be executed as follows.
• Where, C is the number of cycles for a particular

instruction.
Program Counter and Data Pointer
• 8051 contains two 16 bit registers: the program counter
(PC) and the data pointer (DPTR).
Program Counter (PC):
• The program counter points to the address of the next
instruction to be executed.
• When the 8051 is initialized PC always starts at 0000h
and is incremented each time an instruction is
executed.
• As the CPU fetches the opcode from the program ROM,
the program counter is incremented to point to the next
instruction.
• The program counter in 8051 is 16 bits wide.
• This means that 8051 can access program addresses
0000h to FFFFh, a total of 64K bytes of code.
Continued…..
Data Pointer (DPTR):
• Data Pointer is a 16-bit register which is the only user-
accessible.
• DPTR, as the name suggests, is used to point to data.
• It is used by a number of commands which allow the
8051 to access external memory.
• The DPTR register is made up of two 8-bit registers
called as DPH and DPL.
• DPH (data pointer high-byte) and DPL (data pointer
lower-byte) are used to access memory addresses for
internal and external code access and external data
access.
Memory Organization of 8051
• The 8051 microcontroller has 128 bytes of Internal
RAM and 4kB of on chip ROM .
• The RAM is also known as Data memory and the ROM
is known as program memory.
• The program memory is also known as Code memory .
• The Code memory holds the actual 8051 program that
is to be executed.
• In 8051 this memory is limited to 64K .
• Code memory may be found on-chip, as ROM or
EPROM.
• It may also be stored completely off-chip in an external
ROM or EPROM.
• The 8051 has only 128 bytes of Internal RAM but it
supports 64kB of external RAM.
• As the name suggests, external RAM is any random
access memory which is off-chip.
Internal RAM OF 8051
• Internal RAM of 8051 is lso called ason-chip RAM.
• It is the fastest RAM available, and it is also the most flexible in
terms of reading, writing, and modifying it’s contents.
• Internal RAM is volatile, that means when the 8051 is reset this
memory is cleared.
• The 128 bytes of internal RAM is organized as below.
1. Four register banks (Bank0,Bank1, Bank2 and Bank3) each of 8-
bits (total 32 bytes).
The default bank register is Bank0. The remaining Banks are
selected with the help of RS0 and RS1 bits of PSW Register.
The address of these register banks is from 00h to 1Fh.
2. 16 bytes of bit addressable area from 20h to 2Fh and
3. 80 bytes of general purpose area (Scratch pad memory) from
30h to 7Fh as shown in the diagram below.
This area is also utilized by the microcontroller as a storage area
for the operating stack.
Continued…..
Internal ROM (On–chip ROM)
• The 8051 microcontroller has 4kB of on chip ROM but it can be

extended up to 64kB.
• This ROM is also called program memory or code memory.
• The CODE segment is accessed using the program counter (PC)
to fetch the opcode and by DPTR to fetch the data.
• The external ROM is accessed when the EA(active low) pin is
connected to ground or the contents of program counter
exceeds 0FFFh.
• When the Internal ROM address is exceeded the 8051
automatically fetches the code bytes from the external program
memory.
Continued…..
Special Function Registers (SFRs)
Register A/Accumulator
The Accumulator (sometimes referred to as

Register A also) holds the result of most of
arithmetic and logic operations.
Register B
The major purpose of this register is in executing
multiplication and division. The 8051 micro
controller has a single instruction for
multiplication (MUL) and division (DIV).
Ex: MUL A,B – When this instruction is executed,
data inside A and data inside B is multiplied and
answer is stored in A.
Note: For MUL and DIV instructions, it is necessary
that the two operands must be in A and B.
Special Function Registers (SFRs)
• In 8051 microcontroller there are certain registers which use
the RAM addresses from 80h to FFh and they are meant for
certain specific operations.
• These registers are called Special function registers (SFRs).
• Some of these registers are bit addressable also.
• The list of SFRs and their functional names are given below.
• In these SFRs some of them are related to I/O ports (P0,P1,P2
and P3) and some of them are meant for control operations
(TCON,SCON, PCON..) and remaining are the auxillary SFRs, in
the sense that they don't directly configure the 8051.
Continued…..
Continued…..
Flags and Program Status Word (PSW)
• Flags are 1-bit registers provided to store the results of certain

program instructions.
• Other instructions can test the conditions of the flags and make
decision based on the status of the flags.
• In order to conveniently address, the flags are grouped inside
the Program Status Word (PSW) and the Power Control (PCON)
registers.
Continued…..
Program Status Word (PSW):
• The Program Status Word (PSW) contains status bits that
reflect the current CPU state
• The 8051 has a 8-bit PSW register which is also known as
Flag register.
• In the 8-bit PSW register only 6-bits are used by 8051.
• The two unused bits are user definable bits.
• In the 6-bits four of them are conditional flags.
• They are Carry –CY, Auxiliary Carry-AC, Parity-P, and
Overflow-OV.
• They indicate some conditions that result after an
instruction is executed.
• The bits PSW3 and PSW4 are denoted as RS0 and RS1 and
these bits are used to select the bank registers of the RAM
location.
Continued…..
• The meaning of various bits of PSW register is shown below.

Continued…..
• Carry flag: used in arithmetic, logic and Boolean

operations.
• Auxiliary flag : used in BCD arithmetic.
• Overflow flag : used in arithmetic operations
• Flag0(f0) : general purpose user flag
• --- : may be used as general purpose flag.
• Parity: set to 1 if A has odd number of 1’s, otherwise
reset.
Continued…..
• The selection of the register Banks and their addresses are

given below.
Example
 Show the status of the CY, AC and P flag after the addition
of 38H and 2FH in the following instructions.
MOV A, #38H
ADD A, #2FH ;after the addition A=67H, CY=0
Solution:
38 00111000
+ 2F 00101111
67 01100111
CY = 0 since there is no carry beyond the D7 bit
AC = 1 since there is a carry from the D3 to the D4 bi
P = 1 since the accumulator has an odd number of 1s (it has
five 1s)
Example
Show the status of the CY, AC and P flag after the addition
of 9CH and 64H in the following instructions.
MOV A, #9CH
ADD A, #64H ;after the addition A=00H, CY=1
Solution:
9C 10011100
+ 64 01100100
100 00000000
CY = 1 since there is a carry beyond the D7 bit
AC = 1 since there is a carry from the D3 to the D4 bi
P = 0 since the accumulator has an even number of 1s (it has
zero 1s)
Stack Pointer (SP)
• The 8-bit Stack Pointer (SP) register is used to hold an internal RAM
address that is called the ‘top of the stack’.
• The address held in the SP register is the location in the internal
RAM where the last byte of data was stored by the stack operation.
• When data is to be placed on the stack the SP increments before
storing the data on the stack.
• This is done by the instruction PUSH.
• As the data is retrieved from the stack the SP is decremented to
point to the next available byte of the stored data.
• This is done by the instruction POP.
• Since the SP is only 8-bit wide it is incremented or decremented by
two.
• SP is modified directly by the 8051 by six instructions: PUSH, POP,
ACALL, LCALL, RET, and RETI.
Timer/Counter
VI A timer is a specialized type of clock which is used to measure time
intervals. A timer that counts from zero upwards for measuring time
elapsed is often called a stopwatch. It is a device that counts down from
a specified time interval and used to generate a time delay, for example,
an hourglass is a timer.
A counter is a device that stores (and sometimes displays) the number
of times a particular event or process occurred, with respect to a clock
signal. It is used to count the events happening outside the
microcontroller. In electronics, counters can be implemented quite easily
using register-type circuits such as a flip-flop.
Difference between a Timer and a Counter
VI Timer Counter
The register incremented for The register is incremented

every machine cycle. considering 1 to 0 transition
at its corresponding to an
external input pin (T0, T1).
Maximum count rate is 1/12 Maximum count rate is 1/24
of the oscillator frequency. of the oscillator frequency.
A timer uses the frequency A counter uses an external

of the internal clock, and signal to count pulses.
generates delay.
Timers of 8051 and their Associated Registers
VI The 8051 has two timers, Timer 0 and Timer 1. They can be used as
timers or as event counters. Both Timer 0 and Timer 1 are 16-bit wide.
Since the 8051 follows an 8-bit architecture, each 16 bit is accessed as
two separate registers of low-byte and high-byte.
Timer 0 Register
The 16-bit register of Timer 0 is accessed as low- and high-byte. The

low-byte register is called TL0 (Timer 0 low byte) and the high-byte
register is called TH0 (Timer 0 high byte). These registers can be
accessed like any other register. For example, the instruction MOV TL0,
#4H moves the value into the low-byte of Timer #0.
VI Timer 1 Register
The 16-bit register of Timer 1 is accessed as low- and high-byte. The

low-byte register is called TL1 (Timer 1 low byte) and the high-byte
register is called TH1 (Timer 1 high byte). These registers can be

accessed like any other register. For example, the instruction MOV TL1,
#4H moves the value into the low-byte of Timer 1.
VI TMOD (Timer Mode) Register
Both Timer 0 and Timer 1 use the same register to set the various
timer operation modes. It is an 8-bit register in which the lower 4 bits
are set aside for Timer 0 and the upper four bits for Timers. In each
case, the lower 2 bits are used to set the timer mode in advance and
the upper 2 bits are used to specify the location.
Gate − When set, the timer only runs

while INT(0,1) is high.
C/T − Counter/Timer select bit.
M1 − Mode bit 1.
M0 − Mode bit 0.
VI GATE
Every timer has a means of starting and stopping. Some timers do this
by software, some by hardware, and some have both software and
hardware controls. 8051 timers have both software and hardware

controls. The start and stop of a timer is controlled by software using
the instruction SETB TR1 and CLR TR1 for timer 1, and SETB
TR0 and CLR TR0 for timer 0.
The SETB instruction is used to start it and it is stopped by the CLR
instruction. These instructions start and stop the timers as long as
GATE = 0 in the TMOD register. Timers can be started and stopped by
an external source by making GATE = 1 in the TMOD register.
VI C/T (CLOCK / TIMER)
This bit in the TMOD register is used to decide whether a timer is used
as a delay generator or an event manager. If C/T = 0, it is used as a
timer for timer delay generation. The clock source to create the time
delay is the crystal frequency of the 8051. If C/T = 0, the crystal
frequency attached to the 8051 also decides the speed at which the
8051 timer ticks at a regular interval.
Timer frequency is always 1/12th of the frequency of the crystal
attached to the 8051. Although various 8051 based systems have an
XTAL frequency of 10 MHz to 40 MHz, we normally work with the
XTAL frequency of 11.0592 MHz. It is because the baud rate for serial
communication of the 8051.XTAL = 11.0592 allows the 8051 system
to communicate with the PC with no errors.
VI
M1 M2 Mode
0 0 13-bit timer mode.
0 1 16-bit timer mode.

1 0 8-bit auto reload
mode.
1 1 Spilt mode.
VI Mode 0 (13-Bit Timer Mode)
Both Timer 1 and Timer 0 in Mode 0 operate as 8-bit counters (with a

divide-by-32 pre scaler). Timer register is configured as a 13-bit
register consisting of all the 8 bits of TH1 and the lower 5 bits of TL1.
The upper 3 bits of TL1 are indeterminate and should be ignored.

Setting the run flag (TR1) does not clear the register. The timer
interrupt flag TF1 is set when the count rolls over from all 1s to all 0s.
Mode 0 operation is the same for Timer 0 as it is for Timer 1.
Mode 1 (16-Bit Timer Mode)
Timer mode "1" is a 16-bit timer and is a commonly used mode. It

functions in the same way as 13-bit mode except that all 16 bits are
used. TLx is incremented starting from 0 to a maximum 255. Once
the value 255 is reached, TLx resets to 0 and then THx is incremented
by 1. As being a full 16-bit timer, the timer may contain up to 65536
distinct values and it will overflow back to 0 after 65,536 machine
cycles.
Mode 2 (8 Bit Auto Reload)
VI
Both the timer registers are configured as 8-bit counters (TL1 and TL0)
with automatic reload. Overflow from TL1 (TL0) sets TF1 (TF0) and also
reloads TL1 (TL0) with the contents of Th1 (TH0), which is preset by
software. The reload leaves TH1 (TH0) unchanged.
The benefit of auto-reload mode is that you can have the timer to always
contain a value from 200 to 255. If you use mode 0 or 1, you would have
to check in the code to see the overflow and, in that case, reset the
timer to 200. In this case, precious instructions check the value and/or
get reloaded. In mode 2, the microcontroller takes care of this. Once you
have configured a timer in mode 2, you don't have to worry about
checking to see if the timer has overflowed, nor do you have to worry
about resetting the value because the microcontroller hardware will do
it all for you. The auto-reload mode is used for establishing a common
baud rate.
VI Mode 3 (Split Timer Mode)
Timer mode "3" is known as split-timer mode. When Timer 0 is placed

in mode 3, it becomes two separate 8-bit timers. Timer 0 is TL0 and
Timer 1 is TH0. Both the timers count from 0 to 255 and in case of
overflow, reset back to 0. All the bits that are of Timer 1 will now be
tied to TH0.
When Timer 0 is in split mode, the real Timer 1 (i.e. TH1 and TL1) can
be set in modes 0, 1 or 2, but it cannot be started/stopped as the bits
that do that are now linked to TH0. The real timer 1 will be
incremented with every machine cycle.
VI Initializing a Timer
Decide the timer mode. Consider a 16-bit timer that runs continuously,
and is independent of any external pins.
Initialize the TMOD SFR. Use the lowest 4 bits of TMOD and consider
Timer 0. Keep the two bits, GATE 0 and C/T 0, as 0, since we want the
timer to be independent of the external pins. As 16-bit mode is timer

mode 1, clear T0M1 and set T0M0. Effectively, the only bit to turn on is
bit 0 of TMOD. Now execute the following instruction −
MOV TMOD,#01h
Now, Timer 0 is in 16-bit timer mode, but the timer is not running. To
start the timer in running mode, set the TR0 bit by executing the
following instruction −
SETB TR0
Now, Timer 0 will immediately start counting, being incremented once

every machine cycle.
VI Reading a Timer
A 16-bit timer can be read in two ways. Either read the actual value of
the timer as a 16-bit number, or you detect when the timer has
overflowed.
Detecting Timer Overflow
When a timer overflows from its highest value to 0, the

microcontroller automatically sets the TFx bit in the TCON register. So
instead of checking the exact value of the timer, the TFx bit can be
checked. If TF0 is set, then Timer 0 has overflowed; if TF1 is set, then
Timer 1 has overflowed.
VI 1) What is 8051 Microcontroller ?
2) What are registers in Microcontroller ?
3) Interrupts available in 8051 Microcontroller?
4) What is stack pointer in 8051 Microcontroller?

5) Explain architecture of 8051 Microcontroller?
6) What is Address Bus, Data Bus and Control Bus in
Microprocessor 8051 ?
7) List some 8051 Microcontroller applications in
embedded systems ?
8) List some features of 8051 Microcontroller.

Lecture 1,2,3,4,5,6,7,8

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Lecture 1,2,3,4,5,6,7,8

Uploaded by

Copyright:

Available Formats

VI

Vishwakarma Institute of Technology

• A ﬂip-ﬂop has two stable states, thus, called as a

on a single integrated circuit chip containing

• I/O control unit etc.

Microprocessor has Microcontroller has

High cost Low cost

Non speciﬁc, Generalized Dedicated applications such

Core 2 core2 3 GHz L1 cache

4) It can be a small part of a bigger system –

10) Highly eﬃcient –

How does a Microprocessor Work?

Small scale embedded system – Uses an 8 bit

Sophisticated embedded system – Uses huge h/w and s/w

Real time embedded systems – These are functions of time.

• it has all the components needed in its single

• examples of microprocessor are Pentium, I3, and I5 etc.

• As all the peripheral of microcontroller are on single chip it is compact

while microprocessor is bulky.

• Microcontrollers are cheaper microprocessors are high cost because

• Processing speed of microcontrollers is about 8 MHz to 50 MHz ,

• Power consumption in Microcontroller is less, Microprocessors power

• Microcontrollers are compact small product and Application ,

making etc. which are generally more complex

• Microcontrollers are based on Harvard architecture

Instruction pipelining and increased Generally no Instruction pipelining

Orthogonal Instruction set (Allows each Non-orthogonal instruction set ( All

Single ﬁxed length instructions Variable length instructions

•Certain Embedded processors/controllers contain built in program

•Certain Embedded processors/controllers do not contain suﬃcient

•Retains its contents even after the power to it is turned off. It is

•Depending on the fabrication, erasing and programming techniques

these wires can be functionally viewed as fuses.

•It is a low cost solution for commercial production.

• The information contained in the EEPROM memory can

• It provides greater ﬂexibility for system design

•It combines the re-programmability of EEPROM and the high

•Each sector/page should be erased before re-programming.

VI •RAM is the data memory or working memory of the controller/

contents are destroyed.

•RAM is a direct access memory, meaning we can access the

Made up of 6 CMOS transistors Made up of a MOSFET and a

VI • Random access memory with battery backup

absence of external power supply

•The Main Memory Unit

•The Input/Output Device

how data moves around the system.

Subtraction, Comparisons. It performs Logical Operations, Bit Shifting

Operations, and Arithmetic Operation.

Program Counter (PC): Keeps track of the memory location of the

address to Memory Address Register (MAR).

Memory Address Register (MAR): It stores the memory locations of

Memory Data Register (MDR): It stores instructions fetched from

Current Instruction Register (CIR): It stores the most recently

Instruction Buffer Register (IBR): The instruction that is not to be

present it to the user.

Buses – Data is transmitted from one part of a computer to another,

Control Bus: It carries control commands from the CPU (and

Since data memory and Since data memory and

load command will load data, store command will store

Both approaches try to increase the CPU performance

Complex instruction, hence complex instruction