Robust and area-efficient nLDMOS-SCR 1 mm in size but the channel width of each side of the square drain is

with waffle layout structure for high-voltage 15 mm. Thus the total effective channel width of the waffle nLDMOS-
SCR is 4 × 15 × 1 mm ¼ 60 mm, whereas for the stripe nLDMOS-
ESD protection SCR, the channel width of each finger is 25 mm. Higher current hand-
ling capability can be achieved with multiple fingers. Two and four
J. Zheng, Y. Han, H. Wong, B. Song, S. Dong, F. Ma and
fingers represent, respectively, equivalent channel widths of 50 and
L. Zhong
100 mm.
A novel waffle-type nLDMOS-SCR ESD clamp with compact source
and drain for high-voltage ESD protection is proposed and realised P+
compact
using the 0.35 mm, 30/5 V bipolar-CMOS-DMOS (BCD) process. S/B
N+
With this new structure, a high ESD failure current of 4.4 A was length = 2 mm
achieved with a total channel width of only 60 mm. Considering the poly
area efficiency, the waffle-type structure provides more than 30%
higher current handling capability than the conventional ones. oxide
Because of its better robustness and area efficiency, the waffle-type anode anode
structure should be a promising layout for high-voltage ESD protection P-body
applications. A A¢
HV N-W

Introduction: Laterally-diffused metal-oxide-semiconductor (LDMOS) P-well

power transistor arrays are widely used as output drivers in high-
voltage (HV) circuits such as power management applications, light- P-well
emitting diode (LED) and liquid-crystal display (LCD) driver circuits
[1, 2]. To achieve a high-voltage operation and a high current driven
capability, the sizes of LDMOS transistors, typically with widths over
a
10000 mm, are much larger than those of other CMOS devices.
However, these LDMOS-based driver circuits are still vulnerable to
ESD stresses, which are often attributed to the inhomogeneous trigger-
ing of the parasitic bipolar junction transitor (BJT) and base push-out
effect [3]. The designs of LDMOS-based ESD clamps, as well as the
compact
self-protection scheme of an LDMOS output driver are still challenging S/B
issues [4].
A¢
A promising technique to sidestep these weaknesses is to use an A
anode
embedded sillicon controlled rectifier (SCR) in the LDMOS structure
(LDMOS-SCR) [5]. The LDMOS-SCR goes into the SCR mode
under a high voltage or a large current condition. The traditional
layout employs the stripe style. In this Letter, a novel waffle layout node
LDMOS-SCR structure is proposed and the performance is verified
p-well
with a 0.35 mm 30/5 V BCD process. We found that the device with
this structure has better robustness and consumes less silicon area and b
thus has high practical values.
Fig. 2 Layout diagram of nLDMOS-SCR with compact source/bulk based
on conventional stripe structure (Fig. 2a) and newly proposed waffle struc-
Device design: The schematic cross-sectional view of the LDMOS- ture (Fig. 2b)
SCR is shown in Fig. 1, which consists of an SCR composed by two
parasitic transistors N1 (NPN) and P1 (PNP). The starting materials Experimental results: A Barth 4002 TLP testing system with a rise time
were p-type bulk wafers without any buried layer. To reduce the of 10 ns and a pulse width of 100 ns were used to measure the snapback
surface electric field, the LDMOS was built in an HV N-well. To characteristics of the devices. Drain leakage current was measured at a
increase the breakdown voltage (BV further), both ends of the stripe DC bias of 30 V after each TLP stress. The device failure criterion is
were pocketed with a the P-body. Note that the dopant concentration set at a leakage current reaching 1 mA.
of the P-well is much lower than that of the P-body so that the BV of The TLP current-voltage (I-V ) characteristics of the two types of SCR
the devices was increased from 27 to 40 V which is larger than the clamps after ESD zapping are shown in Fig. 3. Both clamps have similar
safe operation voltage, i.e. 1.2 × VDD or 36 V in the present case. trigger voltages of about 48 V. It is because, as expected, the geometric
parameters D1 and D2, which govern the trigger characteristics, are the
same.
ground gate D1
D2 drain

A A’
leakage current at 30V, A
P+ N+ P+ N+
10–10 10–9 10–8 10–7 10–6 10–5 10–4 10–3
P-body P1 NDD 80
normalised TLP current, mA/mm

N1 parasitic SCR
waffle nLDMOS-SCR
HV N-well 60 with width = 15 × 4 mm
stripe nLDMOS-SCR
with width = 25 × 2 mm
stripe nLDMOS-SCR
P-sub 40 with width = 25 × 4 mm

Fig. 1 Schematic cross-sectional view of nLDMOS-SCR

20
A – A ′ line indicates the corresponding portion in stripe and waffle layout as
shown in Fig. 2
0
0 10 20 30 40 50
Fig. 2a depicts the top view of the conventional LDMOS-SCR in voltage, V
stripe layout with a compact source/bulk. The gate of the nLDMOS-
SCR is grounded to keep the device in the ‘off’ state. Fig. 2b shows Fig. 3 Comparison of 100 ns TLP current-voltage characteristics of two
the proposed waffle layout. The source and body are placed along the types of ESD clamps based on SCR-embedded LDMOS
four sides of the square drain which distribute the ESD current dischar-
ging in four paths. Note that the waffle layout leading to the four nodes at As shown in Table 1, for the stripe-type LDMOS-SCR device, It2
the corners are also internally-grounded. For the waffle nLDMOS-SCR increases from 2.8 to 4.39 A when the finger number increases from 2
proposed in this Letter, the unit cell of the square drain is only 1 mm × to 4. From an area efficiency point of view, the effective current is

ELECTRONICS LETTERS 6th December 2012 Vol. 48 No. 25

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actually decreased for the larger number of fingers. As listed in Table 1,
by normalising the failure current with total finger width, i.e. It2/W, the
normalised failure current, Ifail , reduces from 56.1 to 43.90 mA/mm.
This suggests that there are some non-uniform ESD currents conducting
between the fingers which makes the effective current lower, whereas for
the waffle-type LDMOS-SCR, Ifail increases to 73.30 mA/mm, which is
about 30% higher than the best of the stripe ones. The lower Ifail in the
stripe-type device is possibly due to the high electric field near the ends
of the stripe active region. It may cause some non-uniform current con-
duction between the fingers. Where the waffle-type structure has four
almost identical current conduction paths, the uniformity of current con-
duction is maintained. In addition, the waffle-type structure also pro-
vides better heat dissipation capacity since it has a relatively larger
effective area than the two-finger stripe.
Table 1: Comparison of area efficiency for stripe- and waffle-type
nLDMOS-SCR
Type of (W )/L It2/area
nLDMOS-SCR (mm/mm) It2 (A) Area (mm2) (mA/mm2)
Stripe (25 × 2)/0.6 2.80 35 × 12.8 6.25
Stripe (25 × 4)/0.6 4.39 35 × 23.6 5.31
Waffle (15 × 4)/0.6 4.40 23 × 23.0 8.32
Table 1 summaries the area-normalised failure current (It2/area) of
the stripe- and waffle-type ESD clamps based on the LDMOS-SCR.
The proposed waffle layout device shows a normalised failure current
of 8.32 mA/mm2, which is, respectively, 33.1 and 56.7% higher than
the two-finger and the four-finger conventional stripe-type LDMOS-
SCR. The proposed waffle structure is more robust and area efficient.
Conclusion: Based on a 0.35 mm, 30/5V BCD process, a novel waffle-
type LDMOS-SCR ESD clamp was fabricated. Compared to the tra-
ditional stripe-type layout, the proposed device structure shows a
higher current limit of 4.4 A with a total layout width of 60 mm and
an area of 23 × 23 mm2. Considering the normalised-failure current,
ELECTRONICS LETTERS 6th December 2012 Vol. 48 No. 25
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the new layout structure increases the current capability by more than
30% when compared with the conventional stripe structure. The high
robustness, high breakdown voltage, and low leakage current character-
istics, as well as the high area utilisation efficiency, make the waffle
layout structure more attractive as a technological option for high-
voltage ESD protection applications.
Acknowledgment: The authors thank the National Science &
Technology Major Project funding scheme of China (2009ZX01033-
001-003) for support.
# The Institution of Engineering and Technology 2012
9 October 2012
doi: 10.1049/el.2012.3548
One or more of the Figures in this Letter are available in colour online.
J. Zheng, Y. Han, H. Wong, B. Song, S. Dong, F. Ma and L. Zhong
(ESD Lab, Department of ISEE, Zhejiang University, Hangzhou
310027, People’s Republic of China)
E-mail: hany@zju.edu.cn
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