ESD Design Considerations for Ultra-Low Power Crystal

Oscillators in Automotive Products

Stefan Dannenberger (1), Danielle Griffith (2), Oddgeir Fikstvedt (1)

(1) Texas Instruments Norway, Pb 264 Skoyen, 0213 Oslo, Norway
tel.: +47 2336 9826, fax: +47 2336 9801, e-mail: s.dannenberger@ti.com
(2) Texas Instruments Inc., 12500 TI Boulevard, Dallas, TX 75243 USA

Abstract – Ultra-low power crystal oscillators are sensitive to resistive and capacitive loads at the input. That
imposes challenges to the design of the oscillator and its electro-static discharge (ESD) protection circuit. In this
paper, protection strategies for automotive products are described while keeping an ultra-low power profile of the
oscillator circuit.

I. Introduction design goal is to reduce the series resistance in the

Power consumption is highly important for
applications where a lifetime of more than 10 years on
a coin cell battery is desired. Often, trade-offs have to
be made between performance and ultra-low power
consumption. A crystal oscillator circuit is used in
wireless microcontrollers (MCUs) to generate a
reference clock for the radio’s frequency synthesizer to
ensure data transmission and reception occurs in the
correct frequency bands. Due to the high quality factor
of the crystal, usually >30,000, the oscillator’s startup
time is relatively long; increasing the power overhead
in duty-cycled protocols commonly used in battery
powered wireless systems. Startup time can be reduced
by increasing the oscillator’s power consumption.
There is intuitively an optimum bias oscillator point
where the best choice for oscillator startup time and
steady state power consumption allows the total system
average power consumption to be minimized.
However, power consumption is not the only important
parameter. The crystal oscillator’s phase noise and
clock stability strongly impact the radio’s frequency
synthesizer’s performance and a certain minimum
performance must be achieved to meet the RF standard.
The input stage of a crystal oscillator circuit is
specifically sensitive to capacitive load and series
resistance. To achieve the correct oscillation
frequency, the capacitance presented to the crystal
must be correct. Loading the crystal with additional
series resistance or capacitance requires more current
to be used to maintain the oscillation. Thus, for correct
frequency, the crystal must be loaded with precisely the
right capacitance. For lowest power consumption, the
integrated circuit (IC).
However, ESD performance is often improved by
adding series resistance and protection elements like
diodes. This directly contradicts the performance
design guidelines and makes achieving ultra-low
power performance difficult. Most crystal oscillator
circuit topologies involve connecting the MOSFET
gate to a device pin. Therefore, in general, the
oscillator input stage is more sensitive to ESD
compared to other pins of a device.
In the next section, ESD testing standards are briefly
reviewed. Section III describes test results of the first
revision (Rev 1) of the oscillator. Section IV discusses
design considerations for crystal oscillators while
section V shows measurement results of the improved
ESD protection circuitry.
For the measurements, the oscillator was tested as part
of the device qualification. A passing test result is
therefore a pass on the whole device and not limited to
the oscillator circuitry.
II. ESD Testing Standards
Device-level testing standards for IC qualification are
the Human Body Model (HBM) and the Charge Device
Model (CDM) [1, 2]. The Automotive Electronics
Council (AEC) bases their HBM and CDM device
testing standards on these joint standards (JS) for HBM
and CDM.
HBM is a 2-pin test in which handling of an IC is
tested. Testing specification of HBM in AEC and JS
standard are essentially the same [3]: AEC-Q100-002E
refers to JS-001 in several chapters. This means also

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that test results should not differ much between Table 1: ESD Passing Levels
industrial (JS) and automotive (AEC) ESD stress.
CDM is a discharge test in which the IC is charged
through charging plates and discharged through one pin
at a time. This simulates electro-static discharge in
production lines. For CDM, the major difference
between the automotive and the industrial standard is Test results show high leakage on the oscillator crystal
the minimum of three discharges on each pin [4]. In pins after the circuitry has been stressed with CDM
addition, as shown in Figure 1, the discharge current AEC. Emission microscopy (EMMI) shows hotspots in
during automotive (AEC) CDM stress is reported to be the oscillator input stage (Figure 2) which directly
roughly 30% higher than for industrial (JS) stress, and connect to the oscillator crystal pins.
the rise time of the discharge pulse is shorter because
of differences in the test setup [5].

Figure 1: First current peak for different standards. Q100 peak is

roughly 30% higher than JEDEC current peak [5]

Both parameters lead to an increased cumulative stress

on each pin and its connected circuitry. A circuit
designed to meet the JS CDM testing standard might Figure 2: Hotspots (red and green) after emission microscopy
therefore not meet the AEC standard due to the (EMMI) analysis in the oscillator input stage of a CDM AEC
cumulative stress. stressed unit

III. Initial Results Taking a more detailed look at the damage, the red
arrows point to small holes in the gate oxide fingers at
Table 1 shows that Rev 1 of the device passes the
the gate-drain overlap of the input NMOS transistor
voltage levels which satisfy the safe manufacturing
(Figure 3).
conditions of 500V HBM [6] and 250V CDM [7] but
fails the standard automotive requirement of 500V for
CDM. This indicates that cumulative stress through
three consecutive strikes impacts the components more
than with a single strike.
Note that Table 1 shows ESD passing levels of a device
which contains Rev 1 of the oscillator IP. In the JS case,
the device was stressed up to 3.5kV HBM, in the AEC
case, the device was only stressed up to 2.5kV HBM.
The devices which were used as shuttle for Rev 1 were
not tested to fail for HBM, but they were tested to fail
for CDM. Therefore, the data in Table 1, does not
indicate that HBM stress is higher for AEC ESD stress
than for JS ESD stress.
Figure 3: Close-up on failure location at the input transistor.
Arrows point to oxide damage

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Failure analysis shows that the oscillator input stage
fails the automotive stress because the drain and the
gate are connected to device package pins without
secondary ESD protection.
IV. Crystal Oscillator Design
Considerations
1. Design Requirements
Figure 4 shows the Pierce crystal oscillator used in a
low power MCU in 65nm CMOS. The crystal is
connected to the SoC through two pins, labeled Q1 and
Q2. A current, Ibias, is mirrored through transistors M2
and M3 to provide the bias current to transistor M1.
The input current Ibias and the size of transistor M2 are
adjustable with switches so that the correct bias current
as a function of supply voltage, temperature, and
process corner can be provided to M1. Transistor M4
is added in the source of M1 and the gate is connected
to the output of a tieoff cell. When the oscillator is
disabled, M4 provides some protection against ESD
events by preventing the gate-source connection of M1
to be connected directly between the two pins Q1 and
ground. Resistor Rfb is large (>100kΩ) and serves to
bias Q1 and Q2 to the same voltage. During normal
operation, approximately sine wave voltages appear on
Q1 and Q2. Because they are approximately 180° out
of phase, they can be applied to the input of a single-
ended to differential buffer to create CLK_OUT, a
digital clock that is used by the rest of the SoC,
including the RF synthesizer. To ensure oscillation at
the desired frequency, a load capacitance CL must be
presented by the circuit that matches the crystal
requirement. Typical values for CL specified by crystals
are 6pF - 9pF. To minimize the need for external
components while still providing a flexible solution
that can support a variety of crystals, CL is implemented
with an on-chip adjustable load capacitor array shown
by C1 and C2 [8]. If C1 and C2 are significantly larger
than the circuit parasitic capacitances, CL is
approximately the series combination of C1 and C2. The
oscillator negative resistance is given by
= (1)
where gm is the transconductance of M1, f is the crystal
resonance frequency, and CL is the effective load
capacitance presented by the circuit. To maintain
oscillation, Rn must be higher than the equivalent series
resistance (ESR) of the crystal [9]. As can be seen by
(1), larger values for CL require higher current in
transistor M1. While disadvantageous for power
consumption, larger CL can provide improved
immunity to environmental changes such as
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temperature and humidity. This can be seen in the
following equation. The loaded oscillation frequency,
fL, is given by
= ∙ 1+ (2)
where fS is the unload crystal resonance frequency, Cm
is the motional capacitance of the crystal, and CO is the
parasitic capacitance of the crystal due to the package
and leads and other shunt capacitance from the PCB.
The crystal is fabricated with fS higher than the desired
frequency such that when the CL matches the specified
value, the correct oscillation frequency is obtained. If
CO, however, is larger or smaller than expected due to
variations in the PCB capacitance or other
environmental changes such as temperature and
humidity, the loaded oscillation frequency can shift.
Many wireless standards require the frequency of a
transmission to be accurate within 20-40 parts-per-
million (ppm), so variations in CO must be small
compared to the value of CL so that the frequency
remains sufficiently accurate.
The time constant of the crystal oscillator startup time
is given by
= (3)
In low power duty cycled systems with short data
packets, the crystal oscillator startup time can
contribute significantly to the average power
consumption. From (1), it can be seen that increasing
the transconductance, and therefore power
consumption, of the oscillator, the magnitude of Rn can
be increased which can shorten the startup time. In low
power products, minimizing the power consumption is
desired. Therefore, an amplitude control loop is
implemented (not shown in Figure 3 for simplicity) that
adjusts the bias current, Ibias, and mirror ratio through
transistor M2 to optimize the negative resistance to the
correct value for best startup time and steady state
power consumption regardless of the ESR or CL of the
crystal that is used.
ESD protection is used as a part of the pad and IO
structure to protect against device damage. However,
any capacitance or resistance added from the ESD
protection device can have negative impact on the
oscillator performance, in terms of startup time,
frequency transmission accuracy, and steady state
power consumption. Parasitic capacitance will increase
the effective CL seen by the crystal which will shift the
frequency as described in (2). This can be compensated
by reducing the capacitance from C1 and C2 switched
in by Vtrim[5:0]. However, if any series resistance were
added to the HBM clamps which provide ESD
protection in Figure 4, it would directly degrade the
negative resistance, and increase the current required to
sustain an oscillation
_ = + (4)
For example, a crystal with an ESR of 50Ω requires Rn
of -150Ω to -250Ω for reliable startup and correct
oscillation. If it is desired that the amplitude control
loop adjusts gm such that Rn=-150Ω during steady state
operation, and a series resistance in the ESD protection
of 150Ω is added, the transconductance must be
increased until the actual Rn=-300Ω causing a
significant and undesired increase in power
consumption.
Figure 4: Pierce crystal oscillator with adjustable on-chip load
capacitors, amplitude control, and ESD protection.
2. Split ESD Protection
The negative impact on oscillator performance from
adding ESD protection can be avoided if a split ESD
protection implementation is chosen. Figure 5 shows
the negative resistance vs. oscillator bias current from
an AC simulation performed using Cadence’s Spectre
simulator for a 48MHz crystal oscillator, including
parasitic components extracted from the IC layout. The
different curves are for three different ESD
implementations. The first implementation labeled
“only HBM” corresponds to the circuit in Figure 3.
The second, “combined HBM+CDM” is a commonly
used configuration in SoCs where the HBM clamp in
Figure 3 is expanded to also include a series resistor of
100Ω and rail clamps, all directly on nodes Q1 and Q2.
This is the architecture often used with the ESD
structure combined in the IO cell. The third
implementation, labeled “split HBM+CDM”, is shown
in Figure 5 and corresponds to a custom design. Here,
the series resistor Resd and rail clamps that make up the
CDM protection have moved to the other side of switch
and capacitor C1, and now connect directly to the gate
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of M1. It can be seen that -Rn for the oscillator with
HBM ESD protection is nearly the same as when a split
HBM+CDM protection scheme is used. On the other
hand, negative resistance is significantly degraded if a
combined ESD protection structure is used in the
pad/IO.
To illustrate the impact of device performance, assume
the crystal has an ESR of 30Ω. The negative resistance
should then be ~100 Ω for steady state operation. For
an HBM+CDM ESD structure combined in the pad/IO
cell, this requires a bias current in the oscillator of
>500μA. On the other hand, if the split HBM+CDM
structure is used, the same ESD protection can be
achieved while using less than 200μA bias current.
Both the steady state power consumption and startup
time are impacted by this ESD choice, so it has a
significant impact on the battery lifetime of SoC.
Figure 5: Impact of protection circuit placement on negative
resistance and current consumption. Scheme “only HBM” and
“split HBM+CDM” have clearly same good negative resistance.
The implementation of the split ESD protection scheme
is shown in Figure 6. The following ESD protection
circuitry has been added compared to Figure 3:
• The diode size of the primary ESD protection on
Q1 and Q2 was doubled. This adds a little extra
capacitance, which can be compensated by
reducing the default value of Vtrim[5:0].
• A CDM clamp close to the gate of M1 was added
consisting of a 100Ω resistor and dual diodes with
diode perimeter of 40μm.
• Transistor M1 was put in an isolated PWELL
(Deep N-well was available). This will make the
source voltage of M1 to follow the gate of M1
 during an ESD event, reducing the stress-voltage
over the gate oxide of M1.
• CDM clamps were added to the clock buffer with
a 200Ω series resistance. The clock buffer is a
high gain differential-to-single-ended amplifier
with high input impedance, so the addition of a
200Ω series resistance does not impact the phase
noise of the CLK_OUT signal.
HBM clamps, 2x
VDD
Q2 CDM clamp M2
crystal
Rfb
VDD VDD
Resd
Q1 Vtrim[5:0]
C1[5:0]
tie
high
VDD
2·Resd
VDD
2·Resd
CDM clamps
Figure 6: Crystal oscillator with ESD protection split so that it
does not significantly impact negative resistance.
If the capacitance on the gate of M1 is small compared
to the capacitance on node Q1, which consists of C1,
PCB and pad capacitance, and parasitics from the ESD
diodes, the impact of adding Resd on the negative
resistance and required oscillator power consumption
is limited [10]. To help to minimize the capacitance on
the gate of M1, the inputs to the clock buffer, its
associated CDM clamps, and other amplitude sensing
circuitry (not shown) are taken from nodes Q1 and Q2
rather than the gate of M1. Also, the diodes connected
the gate of M1 are sized carefully so as to not add
significant capacitance. With these precautions, the
addition of Resd and protection diodes has a negligible
impact on negative resistance (shown in Figure 4),
power consumption, and oscillator startup time. In this
instance, designing a custom ESD structure, rather than
using a standard combined HBM+CDM in the IO cell,
allows improved ESD performance without an increase
in oscillator, and therefore SoC, power consumption.
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V. Measurement Results
Rev 1 implemented the “only HBM” scheme shown in
Figure 4 while the updated revision (Rev 2)
implements the “split HBM+CDM” scheme shown in
Figure 6. Rev 2 of the oscillator is ESD tested and the
results are shown in Table 2 together with the results
from Rev 1. Again, HBM is not tested to fail while
CDM was tested to fail.
The JS results essentially do not differ between the
VDD revisions. The maximum stress voltage levels differ
between the two revisions, but both revisions pass their
M3 maximum tested voltage.
For automotive (AEC) ESD testing, HBM levels are
not impacted by the changed protection scheme and
Vtrim[5:0] Ibias they are similar to the industrial numbers.
M1
The device passes now up to 700V CDM which is
C2[5:0] double ESD robustness compared to Rev 1. The results
satisfy now the 500V CDM standard level with good
M4 margin. The oscillator input stage withstands even
higher voltage levels because the failing pins at 700V
are not related to the crystal oscillator.
Table 2: ESD Measurement Results
CLK_OUT
Buffer
65nm CMOS
The oscillator circuitry still satisfies its ultra-low power
consumption requirements with the improved ESD
protection scheme.
Conclusion
The objective of this work is to show differences in
ESD testing standards and their impact on integrated
circuits. It is possible to improve the ESD robustness
of critical oscillator circuits in wireless MCUs by
splitting ESD protection circuits and placing protection
elements carefully in the design rather than using
standard HBM+CDM protection devices combined
together in the IO cell. Then, an ultra-low power profile
can be maintained and automotive ESD robustness
requirements can be achieved without significant
changes to the oscillator circuit design.
Acknowledgements
We would like to thank Texas Instruments’ Advanced
Technology Development team for their valuable
support in the design process as well as the test and
reliability teams for their lab support.
 References [6] JEDEC, “Recommended ESD Target Level for
HBM/MM Qualification (JEP155B)”, 2018
[1] ESDA/JEDEC, “Joint Standard for Electrostatic
[7] JEDEC, “Recommended ESD-CDM Target
Discharge Sensitivity Testing Human Body
Levels (JEP157)”, 2009
Model (HBM) – Device Level (JS-001-2014)”,
2014 [8] D. Griffith, et. al, “A 37µW dual-mode crystal
oscillator for single-crystal radios,” 2015 ISSCC
[2] ESDA/JEDEC, “Joint Standard for Electrostatic
pp. 104-105.
Discharge Sensitivity Testing Charge Device
Model (CDM) – Device Level (JS-002-2014)”, [9] E. Vittoz, et. al, “High-Performance Crystal
2015 Oscillator Circuits: Theory and Application,”
IEEE JSSC, vol. 23, no. 3, pp. 774–783, Mar. 1988
[3] Automotive Electronics Council, “Human Body
Model Electrostatic Discharge Test (AEC-Q100- [10] K. B. Östman, et al., “Analysis and Design of
002-Rev-E), 2013 ESD Protection for Robust Low-Power Pierce
Crystal Oscillator Startup,” 2018 IEEE NORCAS,
[4] Automotive Electronics Council, “Charge Device
pp. 1-4
Model (CDM) Electrostatic Discharge Test
(AEC-Q100-011-Rev-C1)”, 2013
[5] M. Polewski, et al., “Comparison of JEDEC and
Q100 standard and new ESD-CDM calibration
issue”, AEC Reliability Workshop, 2008

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