Tlv915X 4.5-Mhz, Rail-To-Rail Input/Output, Low Offset Voltage, Low Noise Op Amp

TLV9151, TLV9152, TLV9154
www.ti.com TLV9151,
SBOS986C – OCTOBER TLV9152,
2019 – REVISED TLV9154
DECEMBER 2020
SBOS986C – OCTOBER 2019 – REVISED DECEMBER 2020
TLV915x 4.5-MHz, Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise Op Amp
1 Features 3 Description
• Low offset voltage: ±125 µV The TLV915x family (TLV9151, TLV9152, and
• Low offset voltage drift: ±0.3 µV/°C TLV9154) is a family of 16-V, general purpose
• Low noise: 10.5 nV/√ Hz at 1 kHz operational amplifiers. These devices offer
• High common-mode rejection: 120 dB exceptional DC precision and AC performance,
including rail-to-rail output, low offset (±125 µV, typ),
• Low bias current: ±10 pA
low offset drift (±0.3 µV/°C, typ), and 4.5-MHz
• Rail-to-rail input and output bandwidth.
• Wide bandwidth: 4.5-MHz GBW
• High slew rate: 20 V/µs Convenient features such as wide differential input-
voltage range, high output current (±75 mA), high
• Low quiescent current: 560 µA per amplifier
slew rate (20 V/μs), and low noise (10.5 nV/√ Hz)
• Wide supply: ±1.35 V to ±8 V, 2.7 V to 16 V make the TLV915x a robust, low-noise operational
• Robust EMIRR performance: EMI/RFI filters on amplifier for industrial applications.
input pins
• Differential and common-mode input voltage range The TLV915x family of op amps is available in
to supply rail standard packages and is specified from –40°C to
125°C.
• Industry standard packages:
– Single in SOT-23-5, SC70-5, and SOT553 Device Information
– Dual in SOIC-8, SOT-23-8, TSSOP-8, PART NUMBER (1) PACKAGE BODY SIZE (NOM)
VSSOP-8, WSON-8, and X2QFN-10 SOT-23 (5) 2.90 mm × 1.60 mm
– Quad in SOIC-14, TSSOP-14, WQFN-14, and SOT-23 (6) 2.90 mm × 1.60 mm
TLV9151
WQFN-16 SC70 (5) 2.00 mm × 1.25 mm
2 Applications SOT-553 (5)(2) 1.60 mm × 1.20 mm

SOIC (8) 4.90 mm × 3.90 mm
• Professional microphones & wireless systems
SOT-23 (8) 2.90 mm × 1.60 mm
• Multiplexed data-acquisition systems
TSSOP (8) 3.00 mm × 4.40 mm
• Test and measurement equipment
TLV9152 VSSOP (8) 3.00 mm × 3.00 mm
• Factory automation & control
VSSOP (10)(2) 3.00 mm × 3.00 mm
• High-side and low-side current sensing
WSON (8) 2.00 mm × 2.00 mm
X2QFN (10) 1.50 mm × 1.50 mm
SOIC (14) 8.65 mm × 3.90 mm
TSSOP (14) 5.00 mm × 4.40 mm
TLV9154
WQFN (16)(2) 3.00 mm × 3.00 mm
X2QFN (14) 2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at

the end of the data sheet.
(2) This package is preview only.
TLV915x in a Single-Pole, Low-Pass Filter
An©IMPORTANT
Copyright NOTICEIncorporated
2020 Texas Instruments at the end of this data sheet addresses availability, warranty, changes, use in safety-critical
Submit Document applications,
Feedback 1
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA. Product Folder Links: TLV9151 TLV9152 TLV9154
TLV9151, TLV9152, TLV9154
SBOS986C – OCTOBER 2019 – REVISED DECEMBER 2020 www.ti.com
Table of Contents
1 Features............................................................................1 8 Application and Implementation.................................. 33
2 Applications..................................................................... 1 8.1 Application Information............................................. 33
3 Description.......................................................................1 8.2 Typical Applications.................................................. 33
4 Revision History.............................................................. 2 9 Power Supply Recommendations................................35
5 Pin Configuration and Functions...................................4 10 Layout...........................................................................35
6 Specifications................................................................ 11 10.1 Layout Guidelines................................................... 35
6.1 Absolute Maximum Ratings ..................................... 11 10.2 Layout Example...................................................... 36
6.2 ESD Ratings .............................................................11 11 Device and Documentation Support..........................37
6.3 Recommended Operating Conditions ...................... 11 11.1 Device Support........................................................37
6.4 Thermal Information for Single Channel .................. 11 11.2 Documentation Support.......................................... 37
6.5 Thermal Information for Dual Channel .....................12 11.3 Related Links.......................................................... 37
6.6 Thermal Information for Quad Channel ................... 12 11.4 Receiving Notification of Documentation Updates.. 37
6.7 Electrical Characteristics ..........................................13 11.5 Support Resources................................................. 37
6.8 Typical Characteristics.............................................. 17 11.6 Trademarks............................................................. 38
7 Detailed Description......................................................24 11.7 Electrostatic Discharge Caution.............................. 38
7.1 Overview................................................................... 24 11.8 Glossary.................................................................. 38
7.2 Functional Block Diagram......................................... 24 12 Mechanical, Packaging, and Orderable
7.3 Feature Description...................................................25 Information.................................................................... 39
7.4 Device Functional Modes..........................................32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2020) to Revision C (December 2020) Page
• Updated the numbering format for tables, figures and cross-references throughout the document ..................1
• Changed SOT-23 (5) package status on Device Information from Preview to Active ....................................... 1
• Changed SC70 (5) package status on Device Information from Preview to Active ...........................................1
• Changed VSSOP (8) package status on Device Information from Preview to Active ....................................... 1
• Changed SOIC (14) package status on Device Information from Preview to Active ......................................... 1
• Changed TSSOP (14) package status on Device Information from Preview to Active ......................................1
• Changed X2QFN (14) package status on Device Information from Preview to Active ......................................1
• Removed preview notation on SOT-23-5 (DBV), SC70-5 (DCK) SOT-23-6 (DBV), and SOT-23-8 (DDF)
packages in Pin Configurations and Functions ..................................................................................................4
• Removed preview notation on SOIC-14 (D) package in Pin Configurations and Functions ..............................4
• Removed preview notation on TSSOP-14 (PW) package in Pin Configurations and Functions ....................... 4
• Removed preview notation on X2QFN-14 (RUC) package in Pin Configurations and Functions ..................... 4
Changes from Revision A (March 2020) to Revision B (May 2020) Page

• Changed X2QFN (10) package status on Device Information from Preview to Active ......................................1
• Removed preview notation on X2QFN (RUG) package in Pin Configurations and Functions .......................... 4
• Added VIH and VIL in Recommended Operating Conditions section.................................................................11
• Added SHUTDOWN in Electrical Characteristics table.....................................................................................11
Changes from Revision * (October 2019) to Revision A (March 2020) Page

• Changed document status from Advance Information to Production Data ........................................................1
• Changed SOIC (8) package status on Device Information from Preview to Active ........................................... 1
• Changed TSSOP (8) package status on Device Information from Preview to Active ........................................1
2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TLV9151 TLV9152 TLV9154

TLV9151, TLV9152, TLV9154
www.ti.com SBOS986C – OCTOBER 2019 – REVISED DECEMBER 2020
• Changed WSON (8) package status on Device Information from Preview to Active .........................................1
• Removed preview notation on SOIC-8 (D), TSSOP-8 (PW), and WSON-8 (DSG) packages in Pin
Configurations and Functions ............................................................................................................................ 4
• Added Typical Characteristics section in Specifications section.......................................................................17
Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3

TLV9151, TLV9152, TLV9154
5 Pin Configuration and Functions
OUT 1 5 V+ IN+ 1 5 V+
V± 2 V± 2
IN+ 3 4 IN± IN± 3 4 OUT
Not to scale Not to scale
A. DRL package is preview only. Figure 5-2. TLV9151 DCK 5-Pin SC70 and SOT-553
Figure 5-1. TLV9151 DBV and DRL Package(1) 5-Pin Top View
SOT-23 Top View
Table 5-1. Pin Functions: TLV9151

PIN
I/O DESCRIPTION
NAME DBV, DRL DCK
+IN 3 1 I Noninverting input
–IN 4 3 I Inverting input
OUT 1 4 O Output
V+ 5 5 — Positive (highest) power supply
V– 2 2 — Negative (lowest) power supply

TLV9151, TLV9152, TLV9154
OUT 1 6 V+
V± 2 5 NC
+IN 3 4 ±IN
Not to scale
A. DRL package is preview only.
Figure 5-3. TLV9151S DBV and DRL Package(1) 6-Pin SOT-23 and SOT-563 Top View
Table 5-2. Pin Functions: TLV9151S

PIN
I/O DESCRIPTION
NAME DBV, DRL
+IN 3 I Noninverting input
–IN 4 I Inverting input
OUT 1 O Output
SHDN 5 I Shutdown (active low) logic input
V+ 6 — Positive (highest) power supply
V– 2 — Negative (lowest) power supply

TLV9151, TLV9152, TLV9154
OUT1 1 8 V+
OUT1 1 8 V+
IN1± 2 7 OUT2
IN1± 2 7 OUT2
Thermal
IN1+ 3 6 IN2±
Pad
IN1+ 3 6 IN2±
V± 4 5 IN2+
V± 4 5 IN2+
Not to scale
Not to scale
A. DGK package is preview only.
Figure 5-4. TLV9152 D, DDF, DGK, and PW A. Connect thermal pad to V–. See Packages with and Exposed
Package(1) 8-Pin SOIC, SOT-23-8, TSSOP, and Thermal Pad section for more information.
VSSOP Top View Figure 5-5. TLV9152 DSG Package(1) 8-Pin WSON
With Exposed Thermal Pad Top View

PIN
SOIC, SOT-23-8, I/O DESCRIPTION
NAME TSSOP, VSSOP,
WSON
+IN A 3 I Noninverting input, channel A
+IN B 5 I Noninverting input, channel B
–IN A 2 I Inverting input, channel A
–IN B 6 I Inverting input, channel B
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
V+ 8 — Positive (highest) power supply
V– 4 — Negative (lowest) power supply

TLV9151, TLV9152, TLV9154
IN1+
OUT1 1 10 V+
IN1± 2 9 OUT2
V± 1 9 IN1±
IN1+ 3 8 IN2±
10
V± 4 7 IN2+
SHDN1 2 8 OUT1
SHDN1 5 6 SHDN2
Not to scale SHDN2 3 7 V+
A. Package is preview only.
5
Figure 5-6. TLV9152S DGS Package(1) 10-Pin
IN2+ 4 6 OUT2
VSSOP Top View
Not to scale
IN2±
Figure 5-7. TLV9152S RUG Package 10-Pin X2QFN
Top View

PIN
I/O DESCRIPTION
NAME VSSOP X2QFN
+IN A 3 10 I Noninverting input, channel A
+IN B 7 4 I Noninverting input, channel B
–IN A 2 9 I Inverting input, channel A
–IN B 8 5 I Inverting input, channel B
OUT A 1 8 O Output, channel A
OUT B 9 6 O Output, channel B
Shutdown, channel 1: low = amplifier enabled, high = amplifier
SHDN1 5 2 I
disabled. See Shutdown section for more information.
Shutdown, channel 2: low = amplifier enabled, high = amplifier
SHDN2 6 3 I
disabled. See Shutdown section for more information.
V+ 10 7 — Positive (highest) power supply
V– 4 1 — Negative (lowest) power supply

TLV9151, TLV9152, TLV9154
OUT1
OUT4
IN1±
IN4±
OUT1 1 14 OUT4
IN1± 2 13 IN4±
IN1+ 3 12 IN4+
16
15
14
13
V+ 4 11 V± IN1+ 1 12 IN4+
IN2+ 5 10 IN3+ V+ 2 11 V±
Thermal
IN2± 6 9 IN3± IN2+ 3 Pad 10 IN3+
OUT2 7 8 OUT3 IN2± 4 9 IN3±
8
Not to scale
Figure 5-8. TLV9154 D and PW Package 14-Pin
OUT2
NC
NC
OUT3
SOIC and TSSOP Top View Not to scale
A. Connect thermal pad to V–. See Packages with and Exposed

Thermal Pad section for more information.
B. Package is preview only.
Figure 5-9. TLV9154 RTE Package(1)(2) 16-Pin
WQFN With Exposed Thermal Pad Top View
OUT1
OUT4
IN1± 1 12 IN4±
14
13
IN1+ 2 11 IN4+
V+ 3 10 V±
IN2+ 4 9 IN3+
6
IN2± 5 8 IN3±
OUT2
OUT3
Not to scale
Figure 5-10. TLV9154 RUC Package 14-Pin X2QFN With Exposed Thermal Pad Top View

PIN
SOIC, I/O DESCRIPTION
NAME WQFN X2QFN
TSSOP
IN1+ 3 1 2 I Noninverting input, channel 1
IN1– 2 16 1 I Inverting input, channel 1

TLV9151, TLV9152, TLV9154
Table 5-5. Pin Functions: TLV9154 (continued)

PIN
SOIC, I/O DESCRIPTION
NAME WQFN X2QFN
TSSOP
NC — 6, 7 — — Do not connect
OUT1 1 15 14 O Output, channel 1
V+ 4 2 3 — Positive (highest) power supply
V– 11 11 10 — Negative (lowest) power supply

TLV9151, TLV9152, TLV9154
OUT1
OUT4
IN1±
IN4±
16
15
14
13
IN1+ 1 12 IN4+
V+ 2 11 V±
Thermal
IN2+ 3 Pad 10 IN3+
IN2± 4 9 IN3±
8
OUT2
SHDN12
SHDN34
OUT3
Not to scale
A. Package is preview only.
Figure 5-11. TLV9154S RTE Package(1) 16-Pin WQFN With Exposed Thermal Pad Top View

PIN
I/O DESCRIPTION
NAME RTE
IN1+ 1 I Noninverting input, channel 1
IN1– 16 I Inverting input, channel 1
OUT1 15 O Output, channel 1
SHDN12 6 I Shutdown (active low), channel 1 & 2, logic input
SHDN34 7 I Shutdown (active low), channel 3 & 4, logic input
VCC+ 2 — Positive (highest) power supply
VCC– 11 — Negative (lowest) power supply

TLV9151, TLV9152, TLV9154
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage, VS = (V+) – (V–) 0 20 V
Common-mode voltage (3) (V–) – 0.5 (V+) + 0.5 V
Signal input pins Differential voltage (3) VS + 0.2 V
Current (3) –10 10 mA
Output short-circuit (2) Continuous
Operating ambient temperature, TA –55 150 °C
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Short-circuit to ground, one amplifier per package.
(3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN MAX UNIT
VS Supply voltage, (V+) – (V–) 2.7 16 V
VI Input voltage range (V–) – 0.1 (V+) + 0.1 V
VIH High level input voltage at shutdown pin (amplifier enabled) 1.1 (V+) V
VIL Low level input voltage at shutdown pin (amplifier disabled) (V–) 0.2 V
TA Specified temperature –40 125 °C
6.4 Thermal Information for Single Channel

TLV9151, TLV9151S
DBV DCK DRL (2)
THERMAL METRIC (1) UNIT
(SOT-23) (SC70) (SOT-553)
5 PINS 6 PINS 5 PINS 5 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 185.7 167.8 202.6 TBD TBD °C/W
RθJC(top) Junction-to-case (top) thermal resistance 108.2 107.9 101.5 TBD TBD °C/W
RθJB Junction-to-board thermal resistance 54.5 49.7 47.8 TBD TBD °C/W
ψJT Junction-to-top characterization parameter 31.2 33.9 18.8 TBD TBD °C/W
Junction-to-board characterization
ψJB 54.2 49.5 47.4 TBD TBD °C/W
parameter

TLV9151, TLV9152, TLV9154
6.4 Thermal Information for Single Channel (continued)

TLV9151, TLV9151S
DBV DCK DRL (2)
(SOT-23) (SC70) (SOT-553)
5 PINS 6 PINS 5 PINS 5 PINS 6 PINS
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A TBD TBD °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) This package option is preview for TLV9151.
6.5 Thermal Information for Dual Channel

TLV9152, TLV9152S
D DDF DGK (2) DGS (2) DSG PW RUG
(SOIC) (SOT-23-8) (VSSOP) (VSSOP) (WSON) (TSSOP) (X2QFN)
8 PINS 8 PINS 8 PINS 10 PINS 8 PINS 8 PINS 10 PINS
Junction-to-ambient
RθJA 138.7 143.5 176.5 TBD 77.6 185.1 142.3 °C/W
thermal resistance
Rθ Junction-to-case (top)
78.7 79.9 68.1 TBD 93.7 74.0 53.5 °C/W
JC(top) thermal resistance
Junction-to-board
RθJB 82.2 61.6 98.2 TBD 43.9 115.7 68.5 °C/W
thermal resistance
Junction-to-top
ψJT characterization 27.8 5.7 12.0 TBD 4.4 12.3 1.0 °C/W
parameter
Junction-to-board
ψJB characterization 81.4 61.3 96.7 TBD 43.9 114.0 68.4 °C/W
parameter
Junction-to-case
Rθ
(bottom) thermal N/A N/A N/A TBD 19.0 N/A N/A °C/W
JC(bot)
resistance
report, SPRA953.
6.6 Thermal Information for Quad Channel

TLV9154, TLV9154S
D PW RTE (2) RUC
(SOIC) (TSSOP) (WQFN) (WQFN)
14 PINS 14 PINS 16 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 101.4 131.4 TBD 125.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 57.6 51.8 TBD 39.8 °C/W
RθJB Junction-to-board thermal resistance 57.3 75.8 TBD 68.0 °C/W
ψJT Junction-to-top characterization parameter 18.5 7.9 TBD 0.8 °C/W
Junction-to-board characterization
ψJB 56.9 74.8 TBD 67.8 °C/W
parameter
Junction-to-case (bottom) thermal
RθJC(bot) N/A N/A TBD N/A °C/W
resistance
report, SPRA953.

TLV9151, TLV9152, TLV9154
6.7 Electrical Characteristics

For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO UT
= VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
TLV9151, TLV9152 ±125 ±750

VCM = V– TA = –40°C to 125°C ±780
VOS Input offset voltage µV
TLV9154 ±125 ±830
VCM = V– TA = –40°C to 125°C ±880
Input offset voltage
dVOS/dT TA = –40°C to 125°C ±0.3 µV/℃
drift
Input offset voltage VCM = V–, VS = 4 V to 16 V ±0.3 ±1

PSRR TA = –40°C to 125°C μV/V
versus power supply VCM = V–, VS = 2.7 V to 16 V(2) ±1 ±5
Channel separation f = 0 Hz 5 µV/V
INPUT BIAS CURRENT
IB Input bias current ±10 pA
IOS Input offset current ±10 pA
NOISE
1.8 μVPP
EN Input voltage noise f = 0.1 Hz to 10 Hz
0.3 µVRMS
Input voltage noise f = 1 kHz 10.8

eN nV/√Hz
density f = 10 kHz 9.4
iN Input current noise f = 1 kHz 2 fA/√Hz
INPUT VOLTAGE RANGE
Common-mode (V–) – (V+) +
VCM V
voltage range 0.1 0.1
VS = 16 V, (V–) – 0.1 V < VCM <
109 130
(V+) – 2 V (Main input pair)
VS = 4 V, (V–) – 0.1 V < VCM <
84 100
(V+) – 2 V (Main input pair)
Common-mode
CMRR VS = 2.7 V, (V–) – 0.1 V < VCM < TA = –40°C to 125°C dB
rejection ratio 75 95
(V+) – 2 V (Main input pair)(2)
VS = 2.7 V to 16 V, (V+) – 1 V <
VCM < (V+) + 0.1 V (Aux input 85
pair)
INPUT CAPACITANCE
ZID Differential 100 || 3 MΩ || pF
ZICM Common-mode 6 || 1 TΩ || pF

TLV9151, TLV9152, TLV9154
6.7 Electrical Characteristics (continued)

OPEN-LOOP GAIN
VS = 16 V, VCM = V– 120 145
(V–) + 0.1 V < VO < (V+) – 0.1
V TA = –40°C to 125°C 142
VS = 4 V, VCM = V– 104 130

Open-loop voltage
AOL (V–) + 0.1 V < VO < (V+) – 0.1 dB
gain TA = –40°C to 125°C 125
V
VS = 2.7 V, VCM = V– 101 120
(V–) + 0.1 V < VO < (V+) – 0.1
V(2) TA = –40°C to 125°C 118
FREQUENCY RESPONSE
Gain-bandwidth
GBW 4.5 MHz
product
SR Slew rate VS = 16 V, G = +1, CL = 20 pF 21 V/μs
To 0.01%, VS = 16 V, VSTEP = 10 V , G = +1, CL = 20 pF 2.5
To 0.01%, VS = 16 V, VSTEP = 2 V , G = +1, CL = 20 pF 1.5
tS Settling time μs
To 0.1%, VS = 16 V, VSTEP = 10 V , G = +1, CL = 20 pF 2
To 0.1%, VS = 16 V, VSTEP = 2 V , G = +1, CL = 20 pF 1
Phase margin G = +1, RL = 10 kΩ 60 °
Overload recovery
VIN × gain > VS 400 ns
time
Total harmonic 0.00021
THD+N VS = 16 V, VO = 3 VRMS, G = 1, f = 1 kHz
distortion + noise %
OUTPUT
VS = 16 V, RL = no
5 10
load(2)
VS = 16 V, RL = 10 kΩ 50 55
Voltage output swing Positive and negative rail VS = 16 V, RL = 2 kΩ 200 250

mV
from rail headroom VS = 2.7 V, RL = no
1 6
load(2)
VS = 2.7 V, RL = 10 kΩ 5 12
VS = 2.7 V, RL = 2 kΩ 25 40
ISC Short-circuit current ±75 mA
CLOAD Capacitive load drive 1000 pF
Open-loop output
ZO f = 1 MHz, IO = 0 A 525 Ω
impedance
POWER SUPPLY
Quiescent current per 560 685

IQ IO = 0 A µA
amplifier TA = –40°C to 125°C 750

TLV9151, TLV9152, TLV9154
6.7 Electrical Characteristics (continued)

SHUTDOWN
Quiescent current per
IQSD VS = 2.7 V to 40 V, all amplifiers disabled, SHDN = V– 30 45 µA
amplifier
Output impedance
ZSHDN VS = 2.7 V to 40 V, amplifier disabled 10 || 2 GΩ || pF
during shutdown
Logic high threshold
(V–) +
VIH voltage (amplifier V
1.1
enabled)
Logic low threshold
(V–) +
VIL voltage (amplifier V
0.2
disabled)
Amplifier enable
tON G = +1, VCM = V-, VO = 0.1 × VS/2 8 µs
time (1)
Amplifier disable time
tOFF (1) VCM = V-, VO = VS/2 3 µs
SHDN pin input bias VS = 2.7 V to 40 V, (V+) ≥ SHDN ≥ (V–) + 0.9 V 500
nA
current (per pin) VS = 2.7 V to 40 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V 150
(1) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
(2) Specified by characterization only.

TLV9151, TLV9152, TLV9154
Table 6-1. Table of Graphs

DESCRIPTION FIGURE
Offset Voltage Production Distribution Figure 6-1
Offset Voltage Drift Distribution Figure 6-2
Offset Voltage vs Temperature Figure 6-3, Figure 6-4
Offset Voltage vs Common-Mode Voltage Figure 6-5, Figure 6-6, Figure 6-7, Figure 6-8
Offset Voltage vs Power Supply Figure 6-9
Open-Loop Gain and Phase vs Frequency Figure 6-10
Closed-Loop Gain and Phase vs Frequency Figure 6-11
Input Bias Current vs Common-Mode Voltage Figure 6-12
Input Bias Current vs Temperature Figure 6-13
Output Voltage Swing vs Output Current Figure 6-14, Figure 6-15,
CMRR and PSRR vs Frequency Figure 6-16
CMRR vs Temperature Figure 6-17
PSRR vs Temperature Figure 6-18
0.1-Hz to 10-Hz Noise Figure 6-19
Input Voltage Noise Spectral Density vs Frequency Figure 6-20
THD+N Ratio vs Frequency Figure 6-21
THD+N vs Output Amplitude Figure 6-22
Quiescent Current vs Supply Voltage Figure 6-23
Quiescent Current vs Temperature Figure 6-24
Open Loop Voltage Gain vs Temperature Figure 6-25
Open Loop Output Impedance vs Frequency Figure 6-26
Small Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 6-27, Figure 6-28
Phase Margin vs Capacitive Load Figure 6-29
No Phase Reversal Figure 6-30
Positive Overload Recovery Figure 6-31
Negative Overload Recovery Figure 6-32
Small-Signal Step Response (100 mV) Figure 6-33, Figure 6-34
Large-Signal Step Response Figure 6-35, Figure 6-36, Figure 6-37
Short-Circuit Current vs Temperature Figure 6-38
Maximum Output Voltage vs Frequency Figure 6-39
Channel Separation vs Frequency Figure 6-40
EMIRR vs Frequency Figure 6-41

TLV9151, TLV9152, TLV9154
6.8 Typical Characteristics

at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
33 50
30
27 40
24
Population (%)
Population (%)
21
30
18
15
20
12
9
10
6
3
0 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0
-600
-480
-360
-240
-120
120
240
360
480
Offset Voltage (µV) 600 D001 Offset Voltage Drift (µV/C) D002
Distribution from 15462 amplifiers, TA = 25°C Distribution from 60 amplifiers
Figure 6-1. Offset Voltage Production Distribution Figure 6-2. Offset Voltage Drift Distribution
900 400
700 300
500
200
Offset Voltage (µV)
300
100
100
0
-100
-100
-300
-500 -200
-700 -300
-900 -400
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) D004 Temperature (°C) D003
VCM = V+ VCM = V–
Figure 6-3. Offset Voltage vs Temperature Figure 6-4. Offset Voltage vs Temperature
800 800
600 600
400 400
200 200
0 0
-200 -200
-400 -400
-600 -600
-800 -800
-8 -6 -4 -2 0 2 4 6 8 4 4.5 5 5.5 6 6.5 7 7.5 8
VCM D005
VCM D005
TA = 25°C TA = 25°C
Figure 6-5. Offset Voltage vs Common-Mode Voltage Figure 6-6. Offset Voltage vs Common-Mode Voltage (Transition
Region)

TLV9151, TLV9152, TLV9154
6.8 Typical Characteristics (continued)

800 800
600 600
400 400

200 200
0 0
-200 -200
-400 -400
-600 -600
-800 -800
-8 -6 -4 -2 0 2 4 6 8 -8 -6 -4 -2 0 2 4 6 8
VCM D006
VCM D007
TA = 125°C TA = –40°C
Figure 6-7. Offset Voltage vs Common-Mode Voltage Figure 6-8. Offset Voltage vs Common-Mode Voltage
600 100 200
90 Gain (dB) 175
500 Phase ( )
400 80 150
300 70 125
200 60 100
Gain (dB)
Phase ( )
50 75
100
40 50
0
30 25
-100
20 0
-200
10 -25
-300
0 -50
-400 -10 -75
-500 -20 -100
-600 100 1k 10k 100k 1M 10M
2 4 6 8 10 12 14 16 18 Frequency (Hz) C002
Supply Voltage (V) D008
CL = 20 pF
Figure 6-9. Offset Voltage vs Power Supply
Figure 6-10. Open-Loop Gain and Phase vs Frequency
80 6
G= 1
70 G=1 4.5
Input Bias and Offset Current (pA)
60 G = 10
G = 100 3
Closed-Loop Gain (dB)
50 G = 1000
1.5
40
0
30
-1.5
20
-3
10
-4.5
0 IB
-6 IB+
-10
IOS
-20 -7.5
100 1k 10k 100k 1M 10M -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
Frequency (Hz) Common Mode Voltage (V) D010
C001
Figure 6-11. Closed-Loop Gain vs Frequency Figure 6-12. Input Bias Current vs Common-Mode Voltage

TLV9151, TLV9152, TLV9154

150 V+
IB
125 V+ 1V
IB+
Input Bias and Offset Current (pA)
100 IOS V+ 2V
V+ 3V
Output Voltage (V)

75
50 V+ 4V
V+ 5V
25
V+ 6V
0
V+ 7V
-25
V+ 8V -40°C
-50
V+ 9V 25°C
-75 125°C
V+ 10 V
-100 0 10 20 30 40 50 60 70 80 90 100
-40 -20 0 20 40 60 80 100 120 140 Output Current (mA) D012
Temperature (°C) D011
Figure 6-14. Output Voltage Swing vs Output Current (Sourcing)
Figure 6-13. Input Bias Current vs Temperature
V +8V 135
-40°C CMRR
V +7V 25°C 120 PSRR+
125°C PSRR
V +6V 105
CMRR and PSRR (dB)
Output Voltage (V)
V +5V 90
V +4V 75
V +3V
60
45
V +2V
30
V +1V
15
V
0 10 20 30 40 50 60 70 80 90 100 0
Output Current (mA) D012 100 1k 10k 100k 1M 10M
Frequency (Hz)
Figure 6-15. Output Voltage Swing vs Output Current (Sinking) C003
Figure 6-16. CMRR and PSRR vs Frequency

135 170
130
Common-Mode Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
165
125
120
160
115
PMOS (VCM V+ 1.5 V)
110 NMOS (VCM V+ 1.5 V) 155
105
100 150
95
145
90
85 140
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) D015 Temperature (°C) D016
f = 0 Hz f = 0 Hz
Figure 6-17. CMRR vs Temperature (dB) Figure 6-18. PSRR vs Temperature (dB)

TLV9151, TLV9152, TLV9154

Input Voltage Noise Spectral Density (nV/ Hz)

1 200
0.8
100
0.6
0.4
Amplitude (uV)
0.2
0
10
-0.2
-0.4
-0.6
-0.8
-1 1
Time (1s/div) 1 10 100 1k 10k 100k
Frequency (Hz) C017
C019
Figure 6-19. 0.1-Hz to 10-Hz Noise Figure 6-20. Input Voltage Noise Spectral Density vs Frequency
-32 -20
RL = 10 k
-40 -30
RL = 2 k
-48 RL = 604 -40
RL = 128
-56 -50
THD+N (dB)
THD+N (dB)
-64 -60
-72 -70
-80
-80
-90
-88
RL = 10 k
-100 RL = 2 k
-96
-110 RL = 604
-104 RL = 128
-120
-112 1m 10m 100m 1 10
100 1k 10k Amplitude (Vrms) C023
Frequency (Hz) C012
BW = 80 kHz, f = 1 kHz
BW = 80 kHz, VOUT = 1 VRMS
Figure 6-22. THD+N vs Output Amplitude
Figure 6-21. THD+N Ratio vs Frequency
580 700
570 675
560 650
Quiescent current (µA)
Quiescent current (µA)
550 625
540 600
530 575
520 550
510 525
500 500
490 475
480 450
2 4 6 8 10 12 14 16 18 -40 -20 0 20 40 60 80 100 120 140
Supply Voltage (V) D021
VCM = V– Figure 6-24. Quiescent Current vs Temperature
Figure 6-23. Quiescent Current vs Supply Voltage

TLV9151, TLV9152, TLV9154

140 700
VS = 4 V
650
Open-loop output impedance (ohms)

VS = 16 V
Open Loop Voltage Gain (dB)
135 600
550
130 500
450
400
125
350
300
120
250
200
115
-40 -20 0 20 40 60 80 100 120 140 150
Temperature (°C) 100 1k 10k 100k 1M 10M
D023
Frequency (Hz) C013
Figure 6-25. Open-Loop Voltage Gain vs Temperature (dB)
Figure 6-26. Open-Loop Output Impedance vs Frequency
60 80
70
50
60
40
Overshoot (%)
Overshoot (%)
50
30 40
30
20
RISO = 0 , Positive Overshoot 20 RISO = 0 , Positive Overshoot
10 RISO = 0 , Negative Overshoot RISO = 0 , Negative Overshoot
RISO = 50 , Positive Overshoot 10 RISO = 50 , Positive Overshoot
RISO = 50 , Negative Overshoot RISO = 50 , Negative Overshoot
0 0
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF) C007
Cap Load (pF) C008
G = –1, 10-mV output step G = 1, 10-mV output step
Figure 6-27. Small-Signal Overshoot vs Capacitive Load Figure 6-28. Small-Signal Overshoot vs Capacitive Load
60
Input
Output
50
Phase Margin (Degree)
Amplitude (2V/div)
40
30
20
10
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Time (20us/div)
Cap Load (pF) C009 C016
Figure 6-29. Phase Margin vs Capacitive Load VIN = ±8 V; VS = VOUT = ±17 V
Figure 6-30. No Phase Reversal

TLV9151, TLV9152, TLV9154

Input Input
Output Output
Voltage (5V/div)
Voltage (5V/div)
Time (100ns/div) Time (100ns/div)
C018 C018
G = –10 G = –10
Figure 6-31. Positive Overload Recovery Figure 6-32. Negative Overload Recovery
Input
Output
Amplitude (5mV/div)
Amplitude (5mV/div)
Input
Output
Time (300ns/div) Time (1µs/div)

C010 C011
CL = 20 pF, G = 1, 20-mV step response CL = 20 pF, G = 1, 20-mV step response
Figure 6-33. Small-Signal Step Response, Rising Figure 6-34. Small-Signal Step Response, Falling
Input
Output
Amplitude (2V/div)
Amplitude (2V/div)
Input
Output
Time (300ns/div) Time (300ns/div)

C005 C005
CL = 20 pF, G = 1 CL = 20 pF, G = 1
Figure 6-35. Large-Signal Step Response (Rising) Figure 6-36. Large-Signal Step Response (Falling)

TLV9151, TLV9152, TLV9154

100
Large Signal Step Response (2V/div)
80
60
Input
Output Current (mA)

Output 40
20
Sourcing
0 Sinking
-20
-40
-60
-80
-100
Time (2µs/div) -40 -20 0 20 40 60 80 100 120 140
C021
CL = 20 pF, G = –1 Figure 6-38. Short-Circuit Current vs Temperature
Figure 6-37. Large-Signal Step Response

20 -50
VS = 15 V
18 VS = 2.7 V -60
16
Maximum Output Swing (V)
Channel Seperation (dB)
-70
14
-80
12
10 -90
8 -100
6
-110
4
-120
2
0 -130
1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz) C014
C020
Figure 6-39. Maximum Output Voltage vs Frequency Figure 6-40. Channel Separation vs Frequency
110
100
90
Gain(dB)
80
70
60
50
40
1M 10M 100M 1G
Frequency (Hz) C004
Figure 6-41. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency

TLV9151, TLV9152, TLV9154
7 Detailed Description
7.1 Overview
The TLV915x family (TLV9151, TLV9152, and TLV9154) is a family of 16-V general purpose operational
amplifiers.
These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset
(±125 µV, typ), low offset drift (±0.3 µV/°C, typ), and 4.5-MHz bandwidth.
Wide differential and common-mode input-voltage range, high output current (±80 mA), high slew rate (21 V/µs),
low power operation (560 µA, typ) and shutdown functionality make the TLV915x a robust, high-speed, high-
performance operational amplifier for industrial applications.
7.2 Functional Block Diagram

TLV9151, TLV9152, TLV9154
7.3 Feature Description

7.3.1 EMI Rejection
The TLV915x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV915x benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure
7-1 shows the results of this testing on the TLV915x. Table 7-1 shows the EMIRR IN+ values for the TLV915x at
particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational
Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op
amps and is available for download from www.ti.com.
100
90
80
EMIRR (dB)
70
60
50
40
30
1M 10M 100M 1G
Frequency (Hz) C004
Figure 7-1. EMIRR Testing
Table 7-1. TLV9151 EMIRR IN+ for Frequencies of Interest

FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
400 MHz 59.5 dB
applications
Global system for mobile communications (GSM) applications, radio communication, navigation,
900 MHz 68.9 dB
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 77.8 dB
802.11b, 802.11g, 802.11n, Bluetooth®,
mobile personal communications, industrial, scientific and
2.4 GHz 78.0 dB
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 88.8 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
5 GHz 87.6 dB
operation, C-band (4 GHz to 8 GHz)

TLV9151, TLV9152, TLV9154
7.3.2 Thermal Protection

The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the TLV915x is 150°C.
Exceeding this temperature causes damage to the device. The TLV915x has a thermal protection feature that
reduces damage from self heating. The protection works by monitoring the temperature of the device and turning
off the op amp output drive for temperatures above 170°C. Figure 7-2 shows an application example for the
TLV9151 that has significant self heating because of its power dissipation (0.81 W). Thermal calculations
indicate that for an ambient temperature of 65°C, the device junction temperature must reach 177°C. The actual
device, however, turns off the output drive to recover towards a safe junction temperature. Figure 7-2 shows how
the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output
is 3 V. When self heating causes the device junction temperature to increase above the internal limit, the thermal
protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL. If
the condition that caused excessive power dissipation is not removed, the amplifier will oscillate between a
shutdown and enabled state until the output fault is corrected.
Normal
VOUT
3V
Operation
16 V TA = 100°C
PD = 0.39W
JA = 138.7°C/W 0V Output
TJ = 138.7°C/W × 0.39W + 100°C High-Z
TJ = 154.1°C (expected)
150°C
TLV9151
Temperature 140ºC
IOUT = 30 mA +
RL 3V
+ VIN 100 –
– 3V
Figure 7-2. Thermal Protection
7.3.3 Capacitive Load and Stability

The TLV915x features a resistive output stage capable of driving moderate capacitive loads, and by leveraging
an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing the gain
enhances the ability of the amplifier to drive greater capacitive loads; see Figure 7-3 and Figure 7-4. The
particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when
establishing whether an amplifier will be stable in operation.
55 33
50 30
45 27
40 24
Overshoot (%)
Overshoot (%)
35 21
30 18
25 15
20 12
RISO = 0 :, Positive Overshoot RISO = 0 :, Positive Overshoot
15 RISO = 0 :, Negative Overshoot 9 RISO = 0 :, Negative Overshoot
10 RISO = 50 :, Positive Overshoot 6 RISO = 50 :, Positive Overshoot
RISO = 50 :, Negative Overshoot RISO = 50 :, Negative Overshoot
5 3
0 40 80 120 160 200 240 280 320 360 0 40 80 120 160 200 240 280 320 360
Cap Load (pF) C008
Cap Load (pF) C007
Figure 7-3. Small-Signal Overshoot vs Capacitive Figure 7-4. Small-Signal Overshoot vs Capacitive
Load (10-mV Output Step, G = 1) Load (10-mV Output Step, G = –1)
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small
resistor, RISO, in series with the output, as shown in Figure 7-5. This resistor significantly reduces ringing and
maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the

TLV9151, TLV9152, TLV9154
capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing
the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low
output levels. A high capacitive load drive makes the TLV915x well suited for applications such as reference
buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-5 uses an isolation resistor,
RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase
margin.
+Vs
Vout
Riso
+
+ Cload
Vin -Vs
±
Figure 7-5. Extending Capacitive Load Drive With the TLV9151

TLV9151, TLV9152, TLV9154
7.3.4 Common-Mode Voltage Range

The TLV915x is a 16-V, rail-to-rail input operational amplifier with an input common-mode range that extends 200
mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel and P-
channel differential input pairs, as shown in Figure 7-6. The N-channel pair is active for input voltages close to
the positive rail, typically (V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active for inputs
from 100 mV below the negative supply to approximately (V+) – 2 V. There is a small transition region, typically
(V+) – 2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with process
variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance may be
degraded compared to operation outside this region.
Figure 6-5 shows this transition region for a typical device in terms of input voltage offset in more detail.
For more information on common-mode voltage range and PMOS/NMOS pair interaction, see Op Amps With
Complementary-Pair Input Stages application note.
V+
IN-
PMOS
PMOS
NMOS
IN+
NMOS
V-
Figure 7-6. Rail-to-Rail Input Stage
7.3.5 Phase Reversal Protection

The TLV915x family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in non-inverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The TLV915x is a rail-to-rail input op amp; therefore, the common-mode range can
extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into
the appropriate rail. This performance is shown in Figure 7-7. For more information on phase reversal, see Op
Amps With Complementary-Pair Input Stages application note.
Input
Output
Amplitude (2V/div)
Time (20us/div)
C016
Figure 7-7. No Phase Reversal

TLV9151, TLV9152, TLV9154
7.3.6 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage
breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to
the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them
from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 7-8 shows an illustration of the ESD circuits contained in the TLV915x (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or
the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
TVS
RF
+
–
+VS
VDD
TLV915x
R1 100
IN–
–
RS IN+ 100
+
Power Supply RL
ID ESD Cell
+
VIN
–
VSS
+
–
–VS
TVS
Figure 7-8. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit
(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.

TLV9151, TLV9152, TLV9154
7.3.7 Overload Recovery

Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the TLV915x is approximately 500 ns.
7.3.8 Typical Specifications and Distributions
Designers often have questions about a typical specification of an amplifier in order to design a more robust
circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an
amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These
deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage this
information to guardband their system, even when there is not a minimum or maximum specification in the
Electrical Characteristics table.
0.00002% 0.00312% 0.13185% 2.145% 13.59% 34.13% 34.13% 13.59% 2.145% 0.13185% 0.00312% 0.00002%
1 1 1 1 1 1 1 1 1 1 1 1
-61 -51 -41 -31 -21 -1 +1 +21 +31 +41 +51 +61
Figure 7-9. Ideal Gaussian Distribution
Figure 7-9 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ, or
sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution,
approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or
one sigma, of the mean (from µ – σ to µ + σ).
Depending on the specification, values listed in the typical column of the Electrical Characteristics table are
represented in different ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for
example, like gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification
naturally has a mean near zero (like input offset voltage), then the typical value is equal to the mean plus one
standard deviation (µ + σ) in order to most accurately represent the typical value.
You can use this chart to calculate approximate probability of a specification in a unit; for example, for TLV915x,
the typical input voltage offset is 125 µV, so 68.2% of all TLV915x devices are expected to have an offset from –

TLV9151, TLV9152, TLV9154
125 µV to 125 µV. At 4 σ (±500 µV), 99.9937% of the distribution has an offset voltage less than ±500 µV, which
means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units.
Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits
will be removed from production material. For example, the TLV915x family has a maximum offset voltage of 675
µV at 25°C, and even though this corresponds to about 5 σ (≈1 in 1.7 million units), which is extremely unlikely,
TI assures that any unit with larger offset than 675 µV will be removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guardband for your application, and design worst-case conditions using this value. For example, the 6-
σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an
option as a wide guardband to design a system around. In this case, the TLV915x family does not have a
maximum or minimum for offset voltage drift, but based on Figure 6-2 and the typical value of 0.3 µV/°C in the
Electrical Characteristics table, it can be calculated that the 6 σ value for offset voltage drift is about 1.8 µV/°C.
When designing for worst-case system conditions, this value can be used to estimate the worst possible offset
across temperature without having an actual minimum or maximum value.
However, process variation and adjustments over time can shift typical means and standard deviations, and
unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a
device. This information should be used only to estimate the performance of a device.
7.3.9 Packages With an Exposed Thermal Pad
The TLV915x family is available in packages such as the WSON-8 (DSG) and WQFN-16 (RTE) which feature an
exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically conductive
compound. For this reason, when using a package with an exposed thermal pad, the thermal pad must either be
connected to V– or left floating. Attaching the thermal pad to a potential other than V– is not allowed, and
performance of the device is not assured when doing so.
7.3.10 Shutdown
The TLV915xS devices feature one or more shutdown pins (SHDN) that disable the op amp, placing it into a low-
power standby mode. In this mode, the op amp typically consumes about 20 µA. The SHDN pins are active high,
meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic high.
The SHDN pins are referenced to the negative supply rail of the op amp. The threshold of the shutdown feature
lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been
included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.4 V. A valid logic high is defined as a voltage between V– + 1.2 V and V– + 20 V. The
shutdown pin circuitry includes a pull-down resistor, which will inherently pull the voltage of the pin to the
negative supply rail if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or
driven to a valid logic low. To disable the amplifier, the SHDN pins must be driven to a valid logic high. The
maximum voltage allowed at the SHDN pins is V– + 20 V. Exceeding this voltage level will damage the device.
The SHDN pins are high-impedance CMOS inputs. Channels of single and dual op amp packages are
independently controlled, and channels of quad op amp packages are controlled in pairs. For battery-operated
applications, this feature may be used to greatly reduce the average current and extend battery life. The typical
enable time out of shutdown is 30 µs; disable time is 3 µs. When disabled, the output assumes a high-
impedance state. This architecture allows the TLV915xS family to operate as a gated amplifier, multiplexer, or
programmable-gain amplifier. Shutdown time (tOFF) depends on loading conditions and increases as load
resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to
midsupply (VS / 2) is required. If using the TLV915xS without a load, the resulting turnoff time significantly
increases.

TLV9151, TLV9152, TLV9154
7.4 Device Functional Modes

The TLV915x has a single functional mode and is operational when the power-supply voltage is greater than 2.7
V (±1.35 V). The maximum power supply voltage for the TLV915x is 16 V (±8 V).
The TLV915xS devices feature a shutdown pin, which can be used to place the op amp into a low-power mode.
See Shutdown section for more information.

TLV9151, TLV9152, TLV9154
8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information

The TLV915x family offers excellent DC precision and DC performance. These devices operate up to 16-V
supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 4.5-MHz
bandwidth and high output drive. These features make the TLV915x a robust, high-performance operational
amplifier for high-voltage industrial applications.
8.2 Typical Applications
8.2.1 Low-Side Current Measurement
Figure 8-1 shows the TLV9151 configured in a low-side current sensing application. For a full analysis of the
circuit shown in Figure 8-1 including theory, calculations, simulations, and measured data, see TI Precision
Design TIPD129, 0-A to 1-A Single-Supply Low-Side Current-Sensing Solution.
VCC
LOAD 12 V
+ TLV9151
VOUT
–
RSHUNT
ILOAD 100 m
LM7705
RF
360 k
RG 7.5 k
Figure 8-1. TLV9151 in a Low-Side, Current-Sensing Application
8.2.1.1 Design Requirements

The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 4.9 V
• Maximum shunt voltage: 100 mV

TLV9151, TLV9152, TLV9154
8.2.1.2 Detailed Design Procedure

The transfer function of the circuit in Figure 8-1 is given in Equation 1.
VOUT ILOAD u RSHUNT u Gain (1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2.
VSHUNT _ MAX 100mV

RSHUNT 100m:
ILOAD _ MAX 1A (2)
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the TLV9151 to produce an output voltage of 0 V to 4.9 V. The gain needed by the TLV9151 to
produce the necessary output voltage is calculated using Equation 3.
VOUT _ MAX VOUT _ MIN

Gain
VIN _ MAX VIN _ MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
is used to size the resistors, RF and RG, to set the gain of the TLV9151 to 49 V/V.
RF
Gain 1
RG (4)
Choosing R F as 360 kΩ, R G is calculated to be 7.5 kΩ. R F and R G were chosen as 360 kΩ and 7.5 kΩ because
they are standard value resistors that create a 49:1 ratio. Other resistors that create a 49:1 ratio can also be
used. Figure 8-2 shows the measured transfer function of the circuit shown in Figure 8-1.
8.2.1.3 Application Curves
5
3
Output (V)
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
ILOAD (A)
Figure 8-2. Low-Side, Current-Sense, Transfer Function

TLV9151, TLV9152, TLV9154
9 Power Supply Recommendations

The TLV915x is specified for operation from 2.7 V to 16 V (±1.35 V to ±8 V); many specifications apply from –
40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 16 V can permanently damage the device; see the Absolute Maximum
Ratings.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 10-2, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

TLV9151, TLV9152, TLV9154
10.2 Layout Example
VIN +
RG VOUT
RF
Figure 10-1. Schematic Representation

Place components close
Run the input traces to device and to each VS+
as far away from other to reduce parasitic
the supply lines errors
as possible RF
NC NC
Use a low-ESR,
RG
ceramic bypass
GND ±IN V+ capacitor
VIN +IN OUTPUT
V± NC GND
VS± GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 10-2. Operational Amplifier Board Layout for Noninverting Configuration

TLV9151, TLV9152, TLV9154
11 Device and Documentation Support

11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs

The TLV915x is featured in several TI Precision Designs, available online at http://www.ti.com/ww/en/analog/
precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications
experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout,
bill of materials, and measured performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
Texas Instruments, Analog Engineer's Circuit Cookbook: Amplifiers.
Texas Instruments, AN31 amplifier circuit collection.
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 11-1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
TLV9152 Click here Click here Click here Click here Click here
11.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

TLV9151, TLV9152, TLV9154
11.6 Trademarks
TINA-TI™ are trademarks of Texas Instruments, Inc and DesignSoft, Inc.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
All trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

TLV9151, TLV9152, TLV9154
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated

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TLV9151, TLV9152, TLV9154

2 Applications SOT-553 (5)(2) 1.60 mm × 1.20 mm

(1) For all available packages, see the orderable addendum at

TLV915x in a Single-Pole, Low-Pass Filter

Changes from Revision A (March 2020) to Revision B (May 2020) Page

Changes from Revision * (October 2019) to Revision A (March 2020) Page

2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

Product Folder Links: TLV9151 TLV9152 TLV9154

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3

5 Pin Configuration and Functions

IN+ 3 4 IN± IN± 3 4 OUT

Not to scale Not to scale

Table 5-1. Pin Functions: TLV9151

4 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

Product Folder Links: TLV9151 TLV9152 TLV9154

Table 5-2. Pin Functions: TLV9151S

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 5

Table 5-3. Pin Functions: TLV9152

6 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

Product Folder Links: TLV9151 TLV9152 TLV9154

Not to scale SHDN2 3 7 V+

A. Package is preview only.

Table 5-4. Pin Functions: TLV9152S

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 7

OUT2 7 8 OUT3 IN2± 4 9 IN3±

Figure 5-8. TLV9154 D and PW Package 14-Pin

A. Connect thermal pad to V–. See Packages with and Exposed

Table 5-5. Pin Functions: TLV9154

8 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

Product Folder Links: TLV9151 TLV9152 TLV9154

Table 5-5. Pin Functions: TLV9154 (continued)

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 9

A. Package is preview only.

Table 5-6. Pin Functions: TLV9154S

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Product Folder Links: TLV9151 TLV9152 TLV9154

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information for Single Channel

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 11

6.4 Thermal Information for Single Channel (continued)

6.5 Thermal Information for Dual Channel

6.6 Thermal Information for Quad Channel

12 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

Product Folder Links: TLV9151 TLV9152 TLV9154

6.7 Electrical Characteristics

TLV9151, TLV9152 ±125 ±750

Input offset voltage VCM = V–, VS = 4 V to 16 V ±0.3 ±1

Input voltage noise f = 1 kHz 10.8

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 13

6.7 Electrical Characteristics (continued)

VS = 4 V, VCM = V– 104 130

Voltage output swing Positive and negative rail VS = 16 V, RL = 2 kΩ 200 250

Quiescent current per 560 685

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Product Folder Links: TLV9151 TLV9152 TLV9154

6.7 Electrical Characteristics (continued)

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