FABRICATION AND ELECTRICAL MEASUREMENTS OF

MIS BASED MEMORY DEVICES

ABSTRACT- We have used the Tin(Sn) as a
catalyst to form the Si nanostructures as a storage
medium or as a floating gate in the MIS memory
device. This paper discusses the fabrication of
MIS device, a Metal-Insulator-Semiconductor
structured device, where we are using
Aluminium(Al) as metal, a p-type semiconductor
and SiO2 native oxide layer as tunnelling layer
insulator (1-2nm) and Si3N4 as blocking layer
insulator and the growth of nanostructures in the
MIS device using Vapour-Liquid-Solid growth
method in the PECVD chamber. The electrical
characteristics like current-voltage measurements
and capacitance-voltage measurements are
calculated for two MIS devices, one with the
nanostructures and the other without
nanostructures to compare and find whether the
device can store charge and based on
capacitance-voltage measurements, charge-
frequency measurements. The retention time is
measured for 100 seconds and 1000 seconds is
measured using capacitance-time graph.
layer, as shown in fig.1 [2]. As the tunnelling
layer is too narrow approximately 1-2nm, the
excited charges tunnel through the tunnelling
layer and get trapped. The trapped charges can
be manipulated into data. Hence, an MIS
component can be transformed into a memory
device [3]. This device can be faster when the
p-type semiconductors are used, where the
electrons are minority carriers and also
depends upon the size of the floating gate,
when the nanostructures are introduced as a
floating gate, the MIS device can perform
faster and in present technology, the size is
reduced by the reducing the gap between
source and drain of the MIS structure [4]. In
the present, the size is reduced to 1nm using
3D-technology [5].

INTRODUCTION:

It is noticed that, in recent decades, there is a

rapid increase in the use of memory devices is
increased exponentially. The three main
objectives, which are considered while
purchasing a memory device is, whether the
device is fast, small and whether it can store
more data or not? The size, speed and storage
capacity is depended upon each Metal-
Insulator-Semiconductor(MIS) component in
the storage device, in current technology [1].
The MIS device works on the principle when Figure 1: Schematic diagram of MIS Structure
the MIS device is supplied with a voltage with Si- Nanostructures.
when the positive voltage to the top contact,
EXPERIMENTAL SECTION:
the negative minority charges excite and forms
a layer down the insulating layer. Hence, when Fabrication of MIS Memory Device:
a metal is introduced as floating gate into the
insulating layer near to the semiconductor, it Step 1: A p-type semiconductor substrate is
divides the insulating layer into two, one is the cleaved and cleaned with acetone, methanol,
tunnelling layer, and the other is blocking IPA and DI water with ultrasonic bath twice in
each for five minutes and using N 2 gun remove
the DI water molecules and further dried in a
furnace at 300oC in an N2 atmosphere for
5minutes.

Step 2: Aluminium(Al) is deposited on the

unpolished side of thickness 100-150nm under
a vacuum of 10-7mbar in a thermal evaporator,
Edwards-AUTO360. The Al deposited p-Si
substrate is annealed to diffuse the Al into the
p-Si at 500oC for 15 minutes in N2 atmosphere
in a furnace, to form an ohmic contact.

Step 3: Tin(Sn) is preferred as the best catalyst
to form a floating gate [6]. So, Sn is deposited
on the polished side of the mass thickness of
3nm as a catalyst layer under a vacuum of 10 -
7 Step 6: A top layer of Al has deposited again
mbar in a thermal evaporator Edwards-
AUTO360, on the native-oxide layer of SiO 2
formed on the polished p-Si, which acts as a
tunnelling layer, which is formed
approximately 1-2nm.
Step 4: Then, followed by the growth of Si
nanostructures (a floating gate), as shown in
fig 2. SEM image, using the VLS(Vapour-
Liquid-Solid) growth process in Plasma
Enhanced Chemical Vapour
Deposition(PECVD) chamber, with
parameters silane(Si3H4) flowrate at 20sccm,
H2 flowrate at 100sccm, when the temperature
is set at 400oC and pressure at 0.666mbar, with
RF power 11mW/cm2, for 120seconds. Where,
the silane vapour is diffused with liquid Sn and
forms a solid wire like nanostructures having a
catalyst Sn head at the top, which are known
as nanostructures are formed.
Step 5: Then, the deposition of Silicon
Nitride(Si3N4) layer and top layer contact of
Al, using the PECVD chamber, with the
parameters set to silane flowrate at 20sccm,
Ammonia flowrate at 40sccm, N 2 flowrate at
100sccm, when the temperature is set at 300oC
and pressure at 0.466mbar, with RF Power
11mW/cm2., for 20 minutes. A reference
device is also made similarly, but without
nanostructures.
Figure 2: SEM image of the growth of Si
nanostructures with Sn metal catalyst as head,
using VLS method.
with the thermal evaporator with similar
environmental conditions, as a top node end.
Step 7: Then, Al foil is attached to the bottom
Al ohmic contact, using a conductive
silver(Ag) paste.
Then, the Current-Voltage(I-V) measurements
are calculated using HP4140B pico-ammeter.
When the leakage current is found to be below
10nA, for the fixed voltage of -30V to 30V,
the Capacitance-Voltage(C-V) measurements
are computed using LCR bridge HP4192A
impedance analyser for the same fixed voltage.
Later, Capacitance-Time(C-T) for a bit-
0(Erase Voltage) and bit-1(Write voltage), by
sending the AC voltage of 10Volts.
The measurements are carried out, kept inside
a shielded Faraday cage to avoid
electromagnetic(e-m) interference and light, as
the p-Si substrate is photosensitive.
RESULTS AND DISCUSSION:
If the leakage current is below 10nA, then
these MIS structures are capable of storing the
charge(data). Otherwise, if the current leakage
is more than 10nA, these devices are unable to
Graph 1: Current-Voltage(I-V) graph of the
two MIS devices, one with nanostructures and
other without nanostructures.
store the charge(data) [7]. From graph 1, both
the devices are found having the leakage
current reached a maximum of 1.2nA, which is
below 10nA, this explains that the minority
charge carriers are not able to tunnel entirely
through the insulator. So, these devices can
store the charge(data) in the floating gate.
Graph 2: Capacitance-Voltage (C-V) graph of
the two MIS devices, showing the difference
between the MIS with nanostructures (green)
and the MIS without nanostructures (red).
The C-V measurements are depicted between
the reference MIS device, which is produced
without nanostructures layer and the actual
MIS device, which is produced with the
nanostructures. From graph 2, It is found that
the actual device (green), is charged with a
voltage of -30V to +30V and then discharged
from +30V to -30V shows a wide
area(hysteresis) of capacitance is captured,
compared to the reference MIS device (green).
This small area is captured in the reference
device, is negligible. However, this hysteresis
area shows that the insulator layer is thick or
high in quality of insulator. By this, we can
conclude that the C-V behaviour shows there
an electronic charge captured in the insulating
layer. So, it can be called a memory device.
From graph 2, it also depicts that both devices
have three stages formed, the accumulation
region, the depletion region and the inversion
region, which shows the characteristics of the
MIS devices.
Graph 3: Capacitance-Voltage(C-V) graph of
MIS device with frequencies of 100kHz,
200kHz, 400kHz, 600kHz, 800kHz, and
1000kHz.
From graph 3, the Accumulation, Depletion,
and inversion regions of the MIS device is
observed for all the frequencies. Also, for
lower frequency, the accumulation capacitance
and the inversion capacitance is higher
compared to the higher frequency [8].
Using the C-V data, the charge is calculated.
By using the below fundamental formulae,
Charge(c) = Capacitance(F) X Voltage(V) [9]
So, the integrals of each C-V data is taken for
different frequencies and plotted charge versus
frequency in graph 4. From graph 4, it is
observed that, as the frequency increases, the
area(hysteresis) decreases non-linear because
the lower frequencies travel more distance
compared to the higher frequencies. As the
lower frequencies travel deep, the higher the
trapped charges in the floating gate can be
found [10].
Graph 4: Charge- Frequency graph for MIS
memory device, shows a non-linear decrease
in charge with the increase in frequency.
Graph 5: Retention Graph for the MIS
memory Device, where the 100s data is
overlapped by the 1000s data.
The graph 5, shows the retention time for the
MIS memory device so that the reliability of
the memory device can be determined. The
retention time of 100s and 1000s is calculated
for the MIS memory device, and from the
graph 5, the retention time is stable from 0s to
100s, where the difference between the two
states is 1pF as shown in graph 6. So, the
procedure continued till 1000s. There was no
instability in the plotted graph; the difference
was still 1pF at 1000s. Then, after 1000s the
process was terminated and determined that
the manufactured MIS memory device is
stable for 1000s.
Graph 6: Bit – 1 and Bit – 0 for the retention
time of 100s and 1000s is plotted in
Capacitance versus Time graph.
To write the data or also known as at Bit – 1 is
obtained by applying +10V, and to erase the
data or Bit – 0 is obtained by applying -10V.
To read the written value, 5V for 10 3 pulses
were applied.
CONCLUSION:
In this paper, from the above results, it can be
determined that the leakage current is less than
10nA so that the MIS device can be said to be
able to work as a memory device. From the C-
V plots, it can be concluded that the MIS has a
hysteresis area compared to the reference
device, which determines the MIS structure is
a memory device and also shows that as the
lower frequency is introduced to the device,
the higher the trapped charges can be found.
Moreover, from C-T graphs, the reliability of
the MIS memory device is found, that is more
than 1000s.
FUTURE SCOPE:
The present and future of the storage depends
totally upon the MIS Memory devices. By
manupulating the Quantum theory, the
MISFET’s can be reduced to minimum. The
present least gate length is in atom level [11].
 [9] E. Chan, K. Garikipati and R. Dutton,
"Characterization of contact electromechanics
through capacitance-voltage measurements
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