No.

2D730-154E

3.3 IM PWB

(1) Functions

This PWB is used to record ultrasound images and performs loop playback or frame advance
playback of such recorded images on the monitor of the main unit. This PWB is optional.

(2) Details of each section

(a) IIR section

Performs IIR frame correlation when data is written (recorded) into RAM consisting of
image memory. The IIR correlation circuit is used to pass through the ROM into which
correlation coefficients are written. Correlation uses data from the ADC and the
previous frame data. This function can specify the same coefficient as that for frame
correlation of FM from DIGITAL by the host.

(b) Memory main unit

This is a recording memory composed of dynamic RAM. The memory capacity is

32 MB. Writing is always performed when the DSC is in real-time mode. The number
of images that can be recorded changes within the range from min. 32 frames to max.
128 frames according to the combination of the transducer, the LOW DENSITY/HIGH
DENSITY setting, and the HIGH FRAME ON/OFF setting.

(c) LIP section

Performs smoothing of data by interpolating data in the direction of the depth of

sampling data.

(d) Sampling controller section

Generates signals for memory address count timing and memory write control timing
with respect to the sampling endpoint, sampling speed, combination focus point, etc.
specified by the host.

(e) Mode, frame number control section

Preserves each of the recording, frame advance playback, loop playback, and CPU
access modes specified by the host and generates the frame numbers from them. It
also generates control signals for each section.

(f) Memory cycle generator section

Generates control signals to be given to memory chip or memory address generating

section according to the control timing generated by the sampling controller. It also
generates the timing signal for memory fresh.

(g) Memory address generating section

Generates the corresponding physical address in memory to be accessed using the

sampling address, raster position, and frame number during recording and playback.
Also generates the multiplexed address information required for the memory chip.

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(h) Host interface section

Serves as the interface through which the control register and status reading register
are accessed from the host CPU. The data bus width must be 16 bits and the address
must be composed of 16 lines. Address decoding is performed inside the image
memory board.

(i) Control register section

Consists of registers which store the IIR and LIP utilization patterns specified by the
control host.

(3) IM block diagram

from to
"DIGITAL" "DIGITAL"
8 F/F 8 F/F 6 8 B/W MEMORY 8 8 F/F

IIR LIP
ADCCK
6 DRAM
synchronization Read timing
16Mbit *2 synchronization
(ADCCK 15 MHz)
Write timing
synchronization

Data BUF
CPU
ACCESS Address
CONT BUF

RAS, CAS, address

From the RPG OE,WE

HOST REG SMPL MEMORY ADDR

IF CONT CYCLE Sampling MAX 10 bits
HOST GEN GEN Raster MAX 8 bits
BUS Frame MAX 6 bits

MODE
FRAME
NUMBER
CONTROL

REG Sampling controller

Including Combination Focus processing

Control register

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