2017 11 th International Conference on Intelligent Systems and Control (ISCO)
Design of a High Gain, Temperature Compensated
Biomedical Instrumentation Amplifier for EEG
Applications
Aditi Jain
Department of Electrical and Electronics
Birla Institute of Technology and Science, Pilani
Pilani, India
flO 12031 @pilani.bits-pilani.ac.in
Abstract- This paper proposes a high gain, low power
instrumentation amplifier (IA) for EEG signal processing. A
three opamp instrumentation amplifier has been designed by
using sub-threshold three-stage op-amps with PMOS input.
NMOS transistors operating in the triode region have been used
to replace the passive resistors of IA. This eliminates the
problems of mismatch, temperature dependency and large area
consumption, at the same time taking advantage of the high
CMRR and DC offset cancellation properties of conventional IA.
A BGR circuitry with temperature coefficient of 420 ppm/oC is
used to bias the opamp. The instrumentation amplifier is
simulated in Cadence Virtuoso 180nm CMOS technology by
using a supply voltage of IV. It achieves a Gain of 96.4dB,
Bandwidth of 400 KHz, input-referred noise voltage of 610nV//""
Hz, CMRR in the range of 60dB and power consumption about
53.7/lW.
Keywords- Instrumentation amplifier, sub-threshold, triode
region, BGR, opamp
I. INTRODUCTION
EEG (electroencephalography) refers to the recording of the
electrical signals of the brain in order to provide reliable
electrophysiological information, used to diagnose disorders
such as epilepsy and coma. However, capturing these signals
is extremely difficult and inconvenient due to multiple
reasons. First of all , they are very faint and can be easily
drowned. These signals are 0.1 to 100uV in amplitude and
span a bandwidth of 0.IHz-100Hz. Hence, it needs to be
amplified several thousand times before it can be captured.
Also, present long-time continuous monitoring of the patients
connected to a bulky instrument is very discomforting. Since
we are interested in monitoring the brain signals, discomforts
distorting the pathological characteristics of the measured
EEG signal are highly unacceptable and may result into
incorrect diagnosis [I]. Hence, bio-medical electronics is
developing rapidly with improvements in VLSI techniques
facilitating the search for high gain, low power miniaturized
EEG signal acquisition system. The front end of analog
biomedical signal processing is shown in Fig.l.
978-1-5090-2717-0/171$31 .00 ©2017 IEEE
Kavindra Kandpal
Department of Electrical and Electronics
Birla Institute of Technology and Science, Pilani
Pilani, India
kavindra.kandpal@pilani.bits-pilani.ac.in
Low Pass
Analog-
Filter
Electrodes Amplifier (Anti- to-Digital
Conveltor
aliasing)
Figure I: Biomedical Analog Signal Processing Front-end
A general EEG-based Brain Computer Interface (BCI)
involves recognizing and analyzing a set of patterns from EEG
signals in the following five steps: acquisition of the signal,
signal pre-processing, feature extraction, classification and
control interface [2]. First, the differential signal is acquired
with a pair of electrodes from the head surface and amplified
by a pre-amplifier that provides gain without introducing any
significant noise. This is processed by a low-pass filter which
further amplifies the signal and is used for anti-aliasing
(AAF). The output is then digitized through an Analog to
Digital Convertor (ADC).
The contact electrodes used to extract biological signals create
differential dc offset voltage. This DC offset is usually 20-50
mY, which is approximately 500 times bigger than the signal
[3]. Given the low amplitude of the signal, it forms a
significant part of the incoming signal. Coupling due to 60Hz
interference signal from the supply mains is another problem.
Further, signals in low frequency ranges such as these are
affected by flicker noise of the MOSFETs. Hence, acquisition
of such weak signals requires suitable amplification along
with rejection of noise. The three opamps instrumentation
amplifier (IA) is commonly used front end on bio-signal
processing module due to its low DC offset and
high gain, common-mode rejection ratio (CMRR) , and input
impedances. It suppresses the unwanted noise and the
common mode signals that affect the original signal and also
provides proper amplification to the input signal.
There is an increasing demand for low power dissipation in
bio-potential recording devices for longer battery life and
enhanced continuous monitoring. Amplifier is the most power
consuming building block of the analog frontend. Hence, the
design approach where transistors are designed to operate in
sub-threshold region of operation is suitable for low power
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designs. The same approach has been employed in the drain-source resistance r d are given by
proposed design . aID ID
Section II describes the proposed opamp along with its band- (2)
gill = avGS = mVTH
gap reference circuitry. Section III describes the design of an
Instrumentation Amplifier. Experimental results and
discussions of the design are given in section IV. Finally rd
= [ aID ]-1 = mVTH (3)
conclusion is presented in Section V. avDS ADID

where AD is the channel length modulation coefficient.

II. CIRCUIT DESIGN
The overall open loop DC gain of the op-amp is given by
A. Proposed Three- Stage CMOS Operational Amplifier
The designed opamp consists of three stages i.e. two stage of
Miller-compensated opamp with a common drain amplifier at
the output for lower output resistance. The first stage operates where g mi and rai are transconductance and drain-source
in the sub-threshold region, while the second and third stages resistance, respectively [5].
work in saturation region. The op-amp has been shown in The table I shows calculated value of aspect ratios of various
Fig.2. The input stage comprises of a differential pair of transistors.
PMOS transistors M2 and M3 and a current mirror load of
NMOS transistors MO & M4. Use of PMOS transistors in the

VillAS 1 ..-j V81AS2 ~

IN 1 ..-jr-.-----' lN2 ..-j

.46

Q - - - - + - - - - - 1.. 0UT
Rl

Figure 2: Proposed Three stage CMOS Operational Amplifier

input stage is an obvious choice to minimize the flicker noise,
since the flicker constants hold the relation Kvp« K VN • The TABLE I. TRANSISTOR SIZING OF OP-AMP
NMOS transistor M4 forms a current sink for proper biasing
of the circuit. The second stage comprises of PMOS transistor TRANSISTORS ASPECT RATIO (W/L)
Ml & NMOS transistor M6. The output stage has NMOS M7 MO 5.5ullu
in common drain configuration. A series connection of C 1 and Ml 1.5ul7u
RO form the Miller' s compensation to ensure closed-loop M2 lOOul2u
stability of the amplifier. In sub-threshold region, the drain M3 lOOul2u
current of an n-channel MOSFET is given by equation below M4 lOOu/2u
[4] M5 5.5ullu
w --
~- ~ ~ -- ~-~ w -- M6 O.3u/20u
I = - I e III VT (1 - e v, ) "" I = - I e (1) m Vr M7 900u/O.3u
d L 0 d L 0

B. Band-gap Reference Circuit

where W IL is the aspect ratio of the transistor, VTH is transistor
A modified version of the work presented in [6] is proposed in
threshold voltage, VGS and VDS are gate-to-source and drain-to-
Fig. 3. It is a low supply and temperature independent a
source voltages respectively, VT is the thermal voltage, and m
reference voltage of 510 mV at supply voltage of 1 V using
and 10 are process parameters.
subthreshold region of MOSFETs. The first part is made of
Calculating further from (1) , the transconductance g m and transistors MO, MI, M6, M7 and resistor RO. This represents

293
 The differential gain of the circuit is given below,
V OIlI = (1 + 2.R1 ). R 3 (7)
V2 -~ RG R2
Typically in the lA, first stage is used to amplify the input
signal and the common mode signal is transferred unaltered to
the inputs of the 2nd stage. Second stage is a unity gain stage
used as a difference amplifier. Despite being suitable for
biomedical applications, an LA. suffers from several
drawbacks. The CMRR of this topology depends on the
matching of the resistors. Accurate design of passive
resistance is not a reliable method. Slightest mismatch can
0" result into the degradation of the amplifier parameters. Their
Figure 3: Band Gap Reference Circuit
high dependency on temperature and large area consumed
the PT AT (Proportional to Absolute Temperature) part of the
further imposes serious implications. Also, it is not very
reference circuit. The second part, representing the CTAT
efficient in low noise and low power applications.
(Complementary to Absolute Temperature), includes M2, M3 ,
In order to address all the above mentioned drawbacks,
M8 , M9 and resistor Rland last part is composed of transistors
NMOS transistor operating in triode mode is used to replace
M4, M5 and resistor R2 to generate the reference voltage Vrej.
the passive resistance of LA [8] . This makes it an active LA.
The average temperature coefficient a is calculated according
The resistance can be calculated using the equation below,
to
L
= .
a_ -1- a
- - * 106ppm 10C
r DS (8)
VreJ (5) K ,W,(VGS - VTH )
v'-e/ aT
The average supply dependency coefficient P is calculated Fig.5. shows the plot of r DS vs vDs for VGS equal to 0.8 and 1V .
according to

f3 = 1 aV . f
_ _re_J *10 6 ppm l V (6)
200~---,---------------,

175

v" eJ aVDD 150

125
III. PROPOSED INSTRUMENTATION AMPLIFIER M 100

The bio-potential amplifier should be designed to have the '"~ 75.0

following characteristics [7] : 50.0

• High input impedance 25 .0

• High CMRR
•
•
High gain
Low noise response ~~
-25.0-!--_ _. - ._ _. -_ _- . -_ _-.--_ _..-I
o .2 .4 .6 .. 1.0

• Low power dissipation

Figure 5: Resistance vs drain-to-source voltage
The conventional design of instrumentation amplifier is
shown in the Fig. 4.
Fig.6 shows the circuit design of an instrumentation amplifier
with all the resistances realized through NMOS transistors
working in triode region. The transistors MO to M7 are NMOS
transistors biased in triode mode using DC voltages V BIAS I.
V BIAS 2, V BIAS3, V BIAS4 and V BlASS whose values are calculated
using Eq. 8. The gain can be adjusted by tuning the bias
voltages in triode region. For the given design, we have set
Rl = lOO Kn, Rg= 10 n , R3 = 1 Kn, R2= 1 Kn. Gain,
according to (7) is 86db.

294
 ~ ~
'" . - _ _S - - -I--, ~ ",.
- ~.--<;J- LLJ '
--.;,;:
. V8 S3
~
..
VBJAS 4

~
•
VPLUS

gnd

r--f~~
~1~~-- ~
~
l'
. .

o cp=1 81il ~ VBIAS2

I
M1 . I VBIASl

Figure 6: Implemented Instrumentation Amplifier

IV, SIMULATION RESULTS
the noise is 6lOnV/f Hz , Fig,9 shows an input common mode
The proposed active instrumentation amplifier has been range (ICMR) of 400 - 700 mV,
simulated for a differential input of 50~V at 50Hz, Fig,7
shows that the design achieves an overall gain of 96.4 dB with 70~---------------,

a phase margin of 57°, It was observed that for the resistance 60

values as mentioned in Section III, the achieved gain was

71dB, against the theoretical value of 86dB, Therefore, gain
can be adjusted by changing the resistor ratios of the IA

AC Response
O(8 1.HHz, 61O.7nVjsqn(Hz))
100~ dBI o(ilFt'lnet073")I~ liN 1")) I
0(1025mHz, 9641dB)
500 ~ I -10~~;----r;-"~r;----r;,.........-r:-"""""7'""""'-::~"-:-........J
M (4003kHz, l497mdB) 10- 1 100 10 1 4 10 2 103 10 10 5 10 6 10 7 10 8
':/1'; R<::Rltl_h I <;1 d" ...Vk,.,,.,/I_h\ freQ (Hz)

"
,,·5 0.0
> Figure 8: Input referred noise for a three-stage op-amp
· 100
- 150 DC Response

1
-250ool~fsffifglli~iPe'ff~rnft6m1iiFfiiNfiTL=====~
0 P h aSe D eg O nWrap pe d(ilF~ InelOI3")/VFt'IINl")) I I
- I,~ fVPLUS") - VS, lOUr)

1.25,--- - - - - - - - - - - - - - - ,

_~_.M 2l677kHz, -12l0deg)

10

Ml(7 9.5mV, 7195mV)

> 75
2
>
j -- - - ----:;7"'" (400.2rnV, 400.2rnY)
- 4001~""r"';""'r'::""'rc:"""C":"""i""",,,",,'r'""""""'''''r'",,,",,'''''''-"'''''I'''''''~~
10-5W410-310-210-1 100 101 10 2 10l 104 10 5 106 107 10 8 10 9 1010 25
I a' "o .. ~, I _,Od <On on freq (Hz)
o.o+:==.-~-.-.-,-~-_,_~--,,___--~
0.0 .25 .5 .75 10
Figure 7: AC Gain and Phase for a three-stage op-amp i ..... ~ <> ... ~" I ..,c-A <> ... ~" de (V)

Moreover, the IA achieves a CMRR of 60 dB , PSRR of Figure 9: ICMR for a three-stage op-amp
153,71dB and power consumption of 53,72 ~W at a I-V
supply using TSMC 180nm CMOS technology, Table II shows the simulation results of the proposed
Fig,8 shows, the input-referred noise for the range of operational amplifier. Besides this, the comparisons of the
frequency, It's obvious that the low frequency region is proposed instrumentation amplifier with previous works,
dominated by flicker noise however, the high frequency region referred as [8], [9] and [10], are also provided, on the basis of
Le, more than 10 7 Hz is dominated by thermal noise, At 81 Hz gain, power dissipation, input referred noise and other

295
parameters. The design clearly shows an effective increment circuit has been designed to realize bias voltage independent
in gain and decrease in the power dissipation, as proposed. of temperature and supply voltage.

TABLE II. SIMULATION RESULTS AND REFERENCES

COMP ARISON WITH PREVIOUS WORKS [1] Waterhouse, E. "New horizons in ambulatory EEG monitoring." IEEE
Eng. Med. BioI. Mag 22.3 (2003): 74-80.
[2] Hassani, Kaveh, and Won-Sook Lee. "An experimental study on semi-
This [8] [9] [10] invasive acupuncture-based EEG signal acquisition. " Brain-Computer
work Interface (BCI), 201S 3rd International Winter Conference on. IEEE,
Supply voltage 1 >1 2.5 1.2 201S.
[3] Abdullah, Reza Muhatmnad. A High CMRR Instrumentation Amplifier
CMOS 180nm 500nm 500nm 180nm
for Biopotential Signal Acquisition. Diss. Texas A&M University, 2011.
Technology [4] Magnelii, Luca, et al. "Design of a 7S-nW, O.S-Y subthreshold
Gain(dB) 96.41 45 19.9 40.08 complementary metal-oxide-semiconductor operational amplifier."
Phase 57 - - - International Journal of Circuit Theory and Applications 42.9 (2014):
margin(degrees) 967-977.
[S] Behzad Razavi, "Design of Analog CMOS Integrated Circuits",
CMRR(dB) 60 75 >110 >60 McGraw-Hili.
PSRR(dB) 153.71 - > 102 >60 [6] Huang, Po-Asuan, Aongchin Lin, and Yen-Tai Lin. "A simple
subthreshold CMOS voltage reference circuit with channel-length
Slew rate (V/~S) 0.001 - - modulation compensation." Circuits and Systems II: Express Briefs,
IEEE Transactions on S3 .9 (2006): 882-88S.
ICMR 400- - - -
[7] Coulon, Jesse. A Low Power Low Noise Instrumentation Amplifier For
725mV ECG Recording Applications. Diss. Texas A&M University, 2012.
[8] Goswami, Manish, and Smriti Khanna. "DC suppressed high gain active
Input DC offset 6.3uV 1.28uV 0.16mV - CMOS instrwnentation amplifier for biomedical application. " Emerging
Input referred 610 22 175 54 Trends in Electtical and Computer Technology (lCETECT), 2011
International Conference on. IEEE, 2011.
noise [9] Yen, Chih-Jen, Wen-Yaw Chung, and Mely Chen Chi. "Micro-power
(nV/sqrt(Hz» low-offset instrumentation amplifier IC design for biomedical system
Power 53 .72 280 - 1320 applications." Circuits and Systems 1: Regular Papers, IEEE
dissipation(~ W) Transactions on SI.4 (2004): 691-699.
[10] Lyu, Yu-Jyun, et al. "CMOS analog /i'ont end for ECG measurement
system." Intelligent Signal Processing and Communications Systems
(ISPACS), 2012 International Symposium on. IEEE, 2012.
Fig. 10 shows the dependency of the designed BGR circuit
with respect to temperature and supply voltage, respectively.
The calculated coefficient according to (5) is 420ppml°C.
Similarly the BGR has a supply voltage dependency of
25.5ppmlV.

DC Response
iii
- /netS

535 ~

505 +---~-~~~~-~-~-~~-~----I
-50 -25 o 25 50
~~ terno CO

Figure 10: Vbias vs Temperature for Band-gap Reference

circuit

V. CONCLUSION
Design of a Temperature Compensated Biomedical
Instrumentation Amplifier for EEG Applications is presented.
The simulation result shows the proposed instrumentation
amplifier offers high gain with low power consumption, as
compared to previous designs. Further, the band-gap reference

296