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Unit 3 MCQ MP PDF
Unit 3 MCQ MP PDF
Unit 3 MCQ MP PDF
(1/2/3...)
((QUESTION)) For a single task in protected mode, the 80386 can address---
memory the virtual memory of Virtual memory
((OPTION_A)) 32 GB
((OPTION_B)) 64 MB
((OPTION_C)) 32 TB
((OPTION_D)) 64 TB
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_C c
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_C d
HOICE))
(A/B/C/D)
((EXPLANATI The User/Supervisor (U/S) bit and Read/Write (R/W) bit are used
ON)) to provide protection
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) PG
((OPTION_B)) ET
((OPTION_C)) PE
((OPTION_D)) NT
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) DPL
((OPTION_B)) CPL
((OPTION_C)) RPL
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI)
) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) 1
((OPTION_B)) 2
((OPTION_C)) 3
((OPTION_D)) 4
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) 1
((OPTION_B)) 3
((OPTION_C)) 2
((OPTION_D)) 0
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) 1
((OPTION_B)) 0
((OPTION_C)) 3
((OPTION_D)) 2
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI)
) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The unit that provides a four level protection mechanism, for system‟s
code and data against application program is
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI)
) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI)
) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_CHO D
ICE)) (A/B/C/D)
((EXPLANATIOPT
IONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_CH B
OICE)) A/B/C/D)
((EXPLANATIO
N)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) HOLD
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The data segments defined in GDT (global descriptor table) and the LDT
(local descriptor table) can be accessed by a task with
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) A task with privilege level 0, does not refer to all the lower level privilege
descriptors in
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The selector RPL that uses a less trusted privilege than the current
privilege level for further use is known as
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) A CALL instruction can reference only a code segment descriptor with
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The RPL of a selector that referred to the code descriptor must have
a)
b) c) d)
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The instruction that refers to only code segment descriptors with DPL
equal to or less than the task CPL is
((OPTION_A)) CALL
((OPTION_B)) IRET
((OPTION_C)) ESC
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The mechanism to provide protection, that is accomplished with the help
of read/write privileges is
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) If CPL is not of the required privilege level, then the instructions that get
affected is
((OPTION_A)) IRET
((OPTION_B)) POPF
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) If CPL is greater than zero, then the instruction that remains unaffected is
((OPTION_A)) IRET
((OPTION_B)) POPF
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The condition, “CPL not equals to zero” satisfies, when executing the
instruction
((OPTION_A)) LIDT
((OPTION_B)) LGDT
((OPTION_C)) LTR
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) CPL = 0
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The instruction that reads the segment limit into the register, if privilege
rules and descriptor type allow is
((OPTION_A)) VERW
((OPTION_B)) APRL
((OPTION_C)) LSL
((OPTION_D)) LAR
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The instruction that adjusts the RPL (Requested Privilege Level) of the
selector, to the numeric maximum of current selector RPL value is
((OPTION_A)) LAR
((OPTION_B)) VERR
((OPTION_C)) LSL
((OPTION_D)) APRL
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The selector RPL that uses a less trusted privilege than the current
privilege level for further use is known as
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) CLTS
((OPTION_B)) TEST
((OPTION_C)) HLT
((OPTION_D)) LLDT
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) LMSW
((OPTION_B)) TEST
((OPTION_C)) AND
((OPTION_D)) STD
((CORRECT_C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) AAA
((OPTION_B)) OR
((OPTION_C)) CLD
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS))
(1/2/3...)
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS))
(1/2/3...)
((QUESTION)) What is the significance of setting R/W field of PTE in protected mode?
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) PL0
((OPTION_B)) PL1
((OPTION_C)) PL2
((OPTION_D)) PL3
((CORRECT_C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) What condition must be satisfied for successful control transfer using Call
Gate mechanism?
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) For instruction HLT to be executed what must be the value of CPL?
((OPTION_A)) 0
((OPTION_B)) 1
((OPTION_C)) 2
((OPTION_D)) 3
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((QUESTION))
((OPTION_A))
((OPTION_B))
((OPTION_C))
((OPTION_D))
((CORRECT_C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) The on chip protection hardware performs which checks of the following
(1/2/3...) ?
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS))
(1/2/3...)
((OPTION_A)) 0
((OPTION_B)) 1
((OPTION_C)) 2
((OPTION_D)) 3
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Custom routines to support special purpose system operations like Device
Drivers are executed at Privilege level ----
((OPTION_A)) 0
((OPTION_B)) 1
((OPTION_C)) 2
((OPTION_D)) 3
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((OPTION_D)) B AND C
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS))
(1/2/3...)
((CORRECT_C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((CORRECT_C D
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) Type field of Call gate indicates value - -------------
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) 8
((OPTION_B)) 16
((OPTION_C)) 32
((OPTION_D)) 48
((CORRECT_C B
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((OPTION_A)) 8
((OPTION_B)) 16
((OPTION_C)) 32
((OPTION_D)) 48
((CORRECT_C C
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) WC field of call gate is used to push ------- on destination privilege level
stack .
((CORRECT_C A
HOICE))
(A/B/C/D)
((EXPLANATI
ON))
(OPTIONAL)
(MARKS)) 1
(1/2/3...)
((QUESTION)) The task state segment descriptor for the designated task is
checked for its ----- and --------
((CORRECT_CH C
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) Normal
((OPTION_B)) Currently
((OPTION_C)) ( Multiple
((OPTION_D)) ( Single
((CORRECT_CH B
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((OPTION_A)) 16 bit
((OPTION_B)) 20 bit
((OPTION_C)) 24 bit
((OPTION_D)) 32 bit
((CORRECT_CH A
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) 64 bytes
((OPTION_C)) 4 KB
((OPTION_D)) 64 KB
((CORRECT_CH B
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) Real
((OPTION_B)) Protected
((OPTION_C)) Virtual
((OPTION_D)) V86
((CORRECT_CH A
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) How task switching can be obtained in 80386?
((CORRECT_CH D
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) RET
((OPTION_B)) IRET
((OPTION_C)) JMP
((OPTION_D)) CALL
((CORRECT_CH B
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((OPTION_B)) Exception
((CORRECT_CH D
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_B)) TSS
((OPTION_D)) TR
((CORRECT_CH B
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_CH C
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) TSS
((OPTION_B)) TR
((CORRECT_CH D
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) Interrupts
((OPTION_B)) Exceptions
((OPTION_C)) A&B
((CORRECT_CH C
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_CH A
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((OPTION_A)) 80 bytes
((CORRECT_CH B
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) 80 bytes
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) 64 KB
((OPTION_B)) 1MB
((OPTION_C)) 4GB
((OPTION_D)) 64 TB
((CORRECT_CH C
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) Base
((OPTION_B)) Limit
((CORRECT_CH D
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) TR
((OPTION_B)) TP
((OPTION_C)) TSSD
((CORRECT_CH A
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which field in TSS holds the 16-bit offset of the beginning of I/O
permission bit map
((OPTION_C)) CR 3
((OPTION_D)) EIP
((CORRECT_CH A
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((CORRECT_CH D
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) Flags
((OPTION_B)) EIP
((CORRECT_CH C
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_B)) PDBR
((OPTION_C)) T-bit
((CORRECT_CH D
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_C)) A&B
((CORRECT_CH C
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((OPTION_A)) GDT
((OPTION_B)) LDT
((OPTION_C)) A or B
((OPTION_D)) A
((CORRECT_CH
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_CH A
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_CH D
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_C)) Sequential
((CORRECT_CH D
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_CH D
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((CORRECT_CH C
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) Processor selects task gate descriptor only when the maximum of
selectors ............and the ...............of procedure is less than or equal to
the ..........of the descriptor
((OPTION_A)) DPL,RPL,CPL
((OPTION_B)) CPL,DPL,RPL
((OPTION_C)) RPL,CPL,DPL
((OPTION_D)) CPL,RPL,DPL
((CORRECT_CH C
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) Processor selects task gate descriptor only when the maximum of
selectors RPL and the CPL of procedure are................. to the DPL of the
descriptor
((OPTION_A)) less than or equal
((OPTION_C)) Same
((CORRECT_CH A
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) When task gate is used, the DPL of target ..............is not used for privilege
checking
((OPTION_B)) TR
((OPTION_C)) TSS
((OPTION_D)) Stack
((CORRECT_CH A
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) During task switching without task gate which of the checks are
performed
((CORRECT_CH D
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) The DPL of the new TSS descriptor is not used for privilege checking
,when ...........is used for task switch
((CORRECT_CH A
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((OPTION_D)) Both A or B
((CORRECT_CH C
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((CORRECT_CH C
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) During task switching without task gate which of the checks are
performed
((OPTION_A)) instruction check
((CORRECT_CH B
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) DPL of the task gate is compared with ......... and ..........of the gate
selector
((OPTION_A)) CPL,RPL
((OPTION_B)) DPL,RPL
((OPTION_C)) DPL,CPL
((CORRECT_CH A
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) NT
((OPTION_B)) G
((OPTION_C)) TS
((OPTION_D)) B
((CORRECT_CH A
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((OPTION_A)) A long jump or call instruction contains a selector which refers to a TSS
descriptor
((CORRECT_CH D
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_CH B
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((CORRECT_CH C
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((CORRECT_CH A
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_CH B
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) The parent task and child tasks are indicated by which fields of the TSS?
((CORRECT_CH A
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS))
(1/2/3...)
((OPTION_D)) (d)JBE
((CORRECT_CH B
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
2
((QUESTION)) What condition is needed to permit the current task to switch to the new
task?
((OPTION_A)) (a) Task Gate DPL >= max(CPL, RPL)
((CORRECT_CH A
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_CH B
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_CH A
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((CORRECT_CH D
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((OPTION_A)) CR0
((OPTION_B)) CR1
((OPTION_C)) CR2
((OPTION_D)) CR3
((CORRECT_CH D
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((QUESTION)) Which descriptor table base address is present in task state segment?
((OPTION_A)) GDT
((OPTION_B)) IDT
((OPTION_C)) LDT
((CORRECT_CH C
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 1
(1/2/3...)
((CORRECT_CH B
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) . What is the size of segment limit in task state segment descriptor?
((CORRECT_CH C
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) . Which instruction is used to load the new TSS selector to the task
register?
((OPTION_A)) STR
((OPTION_B)) STD
((OPTION_C)) CLD
((OPTION_D)) LTR
((CORRECT_CH D
OICE))
(A/B/C/D)
((EXPLANATION
)) (OPTIONAL)
((MARKS)) 2
(1/2/3...)
((QUESTION)) Which instruction is used to read the visible portion of the task
register into memory or general-purpose register?
((OPTION_A)) LTR
((OPTION_B)) STR
((OPTION_C)) STD
((OPTION_D)) CLD
((CORRECT_CH B
OICE))
(A/B/C/D)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) LOOP
((OPTION_B)) XLAT
((OPTION_C)) TEST
((OPTION_D)) LTR
((CORRECT_CH D
OICE))
(A/B/C/D)
((MARKS)) 1
(1/2/3...)
((QUESTION)) What must be the CPL at the time of execution of LTR instruction?
((OPTION_A)) 0
((OPTION_B)) 1
((OPTION_C)) 2
((OPTION_D)) 3
((CORRECT_CH A
OICE))
(A/B/C/D)
((MARKS)) 1
(1/2/3...)
((OPTION_A)) AAA
((OPTION_B)) LTR
((OPTION_C)) STD
((OPTION_D)) CLD
((CORRECT_CH B
OICE))
(A/B/C/D)
((MARKS))
(1/2/3...)
((OPTION_A)) STR
((OPTION_B)) HLT
((OPTION_C)) OUT
((OPTION_D)) LTR
((CORRECT_CH C
OICE))
(A/B/C/D)
((MARKS)) 1
(1/2/3...)
((CORRECT_CH D
OICE))
(A/B/C/D)
((MARKS)) 1
(1/2/3...)
((CORRECT_CH D
OICE))
(A/B/C/D)
((MARKS)) 1
(1/2/3...)
((CORRECT_CH A
OICE))
(A/B/C/D)
((MARKS)) 1
(1/2/3...)
((CORRECT_CH C
OICE))
(A/B/C/D)
((MARKS)) 1
(1/2/3...)
((CORRECT_CH A
OICE))
(A/B/C/D)