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    MTVD Iii

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    MTVD Iii

    Uploaded by

    Ms. Bhavini Kumawat
    6 views4 pages

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    MTVD III

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    6 views4 pages

    MTVD Iii

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    Ms. Bhavini Kumawat

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    MTESRO138/1 ‘Total No. of Printed Pages: 02 ‘Total No, of Questions : 08 Roll No. MTES-301 M-Tech. (Third Semester) Examination -December,2013 SOFTWARE ENGINEERING (EMBEDDED SYSTEM) ‘Time: Three Hours Maximum Marks : 70, (Minimum Pass Marks:28) Note: Attempt any five quest marks. All questions carry equal Q.1 (@) Explainindetail Sytem Development LifeCyles? () List five desirable characteristics of « good Software Requirement Specification (SRS) document? Q2 (@) Whatdoyoureanby the tem Software Engineering? Destibe ‘the evolving role ofsoftware? What are its tributes? (©) Explain:he types of situations where iterative enancement model might ead to difficulties. Compre iterive enhancement ‘model and evolutionary development mode! ? Q3 (a) Compare waterfall model and the spiral model, How docs project risk factor affects the spiral model of software development? MTESM013/9/1 ® Pro. Mvpno13/1 ‘Total No. of Printed Pages: 02 ‘Total No. of Questions : 05, Roll Ne MTVD-301 MTech. (Third Semester) Examination December, 2013, ‘TESTING OF VLSICIRCUITS (VLSIDESIGN) ‘Time: Thr Hours Maximum Marks :70 (Minimum Pass Mas :28) Note: Attempt two pars from each question. Allparts ofa question should be atempted together and strietly in sequence.All questions ‘cary equal marks. Q.1 @)Whatdoyou understand by testing? Explain the importance of ‘estingin VLSTsystem. (©) Discus diferent ypesoffinisin VLSI during ibsiation snd packaging. (©) Explain IC production est press and burn-in-boar 2.2 (@) _Dilferentate between fault and bridging faults. How will you tect bridging fault fom the iets (©) Explain structural, combinational pseudo exhaustive and full exhaustive tesing (©) Whatissimuaion? Explain pari and detective ft sition Mrvpn2013 I i) PTO. 4 Qs a6 qr as © @ o ® © ® © © @ © Explain Re-engineering? How do you decide fora project to beRe-engnered ? \Whatisrisk Ist economical to do sk management? Whatis itsefecton overall costo project? Define the term Reverse Engineering? Explain the different sstvites undertaken dering Reverse Engineering? \Whatis design? Discuss the objectives of software dsign- Aiferenateberseen conceptual design and technical design? What isthe diffrence between flowchart and structure char? "Explain he state of desion Alo explaintopdownandbotom, updesign Explain Black Box testing, What are the various methods of Black Box testing? Explain the terms quality, quality contro, quali assurance and costof quality? Explain decision table based testing, Write a procedure to find ‘maximum of tree numbers and develop decision able for this procedure? Explain Debugging techniques andthe approaches induction approach and deduction approach? Explain Planning Whatarethe dimensions of panning? Differentiate betwsenthe folowing @ Dstasnd information @__ Dataprocessing and Information processing GH _MISand Computer System S20133/. @ ae © | © ase ® © as@ © o ‘Whats the need for fault model? Explain transistor eve fat ‘mode and gate level fault model. DiseussIDDQ testing withimportance in VLSI desion Discuss ATPG fora sequential digital circuit, aking suitable example, ‘Explain path sensitization method anditslimitaions. Diseusstime frame expansion method fortesing of sequential iris, Discuss the following pps testing: © Stored pater tesing @ Random patiem esting GH Alpcitimictesing Write shore noon: @ FAM () SOPRAS ] Furwetesting Explain PODEM and D algorithm with suitable example, List various method for delay Ful testing Elaborate any one ‘ofthem giving suitable example, MTVDn0131 @ MTVbTESA01392, Total No.of Printed Pages: 03 “Total No.of Questions: 08 Roll No. MTVD/MTES-3021 M-Tech, (Third Semester) Examination - December, 201 (COMPUTER ARCHITECTURE AND PARALLEL PROCESSING (COMMON FOR VLSI DESIGN AND EMBEDDED SYSTEM) Note : ae © a2@ ° aw © “Time Three Hours Maximum Marks :70 (Minimum Pass Maks :28) Attempt any five ques marks. questions carry equal Whats Pale Computing? Explain VonNeumann Computer Architcture and Flynn's Classical Taxonomy with dggrams’? Differentiate Shared Memory: Distibuted Memory and Hybrid Distibuted-Shared Memory’? Explain the meckanism ofsuper scalar and vector processors withexarmple? Fstblish trade-off between the sped up and performance Explain the Open Sytem Interconnection (OSI Architecture inde with proper diagram? Explain Transmission Control Proto Iatemet Protocol (1CP {Pn detail with suitable diagram? MIVDMTESROIN82 (1) ase © as @ O) 26 @) ) ‘The Cycles Per instruction (CPD and Instructions Per Cycle (APC) are popular metrics used to deseribe computer Performance. What isthe meaning of PI an IPC? A given rogram consists of 120 insretons tht loops 40 times, when exeute, © the system takes 16,000 clock eyces to complete the rogram, whatarethe CPL and IPC values ofthe system? (i) Ifthe system clock operates at Gate, clculte the ‘ime taken to complete he program, ‘There isanumber of levels a computer, ftom the wer level down o the transistor level (Describe different levels ina computersytem between ‘wer programs and transistor level by using diagram, (1) Define the Following tems 1) Responsetime D Thowghpa i) CPU time x) Elapsed time Explain Parallel algorithm forbubble sort. How isashared memory bus used for rads and writes of data shared beeen threads safely and correctly? ‘An un-pipelined processor ha an instruction cycle time of 25ns. MIVDMTESROIN2 (2) a7@ » 8 a 2 a8 @ c) 4) Whatis the eyele time ofa processor with $ evenly

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