RESEARCH PAPERS

ENERGY AWARE MULTIPROCESSOR ARCHITECTURE

CONFIGURATION: DQN APPROACH

By

NAJAR YOUSRA * SAMIR BEN AHMED **

* Department of Science Computer School (ISI), Tunis in Tunisia.
** University of Science and Technology (FST), Tunis in Tunisia.

Date Received: 16/12/2019 Date Revised: 07/01/2020 Date Accepted: 27/02/2020

ABSTRACT
This research investigates a new Deep Q-Network (DQN) based approach to manage Dynamic Voltage Frequency
Scaling (DVFS) on a multiprocessor architecture, such that it would guarantee the balance between energy
consumption minimization and application feasibility. This paper also addresses software periodic real time applications
with time constraints. The proposed DQN formulation operates in two steps: on offline and on online configuration. It
calculates the optimal number of activated homogenous cores and their frequency and reconfigures the platform with
these parameters. We perform an experimental investigation on different parameters in a simulation environment
executing periodic tasks that are generated randomly with different system charge. The results suggest that the
proposed method reduces energy upto CC-EDF and Static-EDF and guarantees schedulability test when compared to
state of the art feedback that addresses the same applications.
Keywords: Deep Q-Network (DQN), Energy Optimization, Multiprocessor Architecture, Periodic Tasks, System Schedulability.

INTRODUCTION respect to a significant issue. Therefore, the chosen

Power consumption is one of the most challenging issues
in the design of modern real-time systems. The most
important component consuming energy is the processor
(ul Islam & Lin, 2015). Multi-core processors are single
integrated circuits with two or more processor cores
attached together, shows high performance at low
energy. Dynamic Voltage and Frequency Scaling (DVFS) is
a well-known method for reducing power consumption in
modern real time applications (Fakhfakh, 2016). Dynamic
power is consumed by the major parts of the system due
to the switching operation of the Complementary Metal
Oxide Semiconductor (CMOS) circuits (Charr et al., 2014).
DVFS has been easily implemented in real-time system
under timing constraints, where tasks can be executed
with lower CPU frequency. Hence, it will reduce power
dissipation especially when the energy leakage is not
important. However, this, significantly affects real-time
application performance, because lower CPU frequency
increases tasks execution time making time contrasts
scaling factor must give a best possible trade-off between
energy reduction and time performance. The main
challenge is to guarantee that the deadlines will not be
violated when the frequency is reduced to decrease
e n e r g y c o n s u m p t i o n. B e s i d e s, m u l t i p r o c e s s o r
architectures are becoming one of the most used
solutions in order to meet the growing computational
requirements of modern applications. Hardware
configuration, in this work, concerns design parameters:
number of cores and their frequencies. Hence, we
treated this issue as a multiple criteria multiple objective
decision making problem.
Different algorithms based on heuristics and intelligent
approaches tries to calculate the scaling factor. In fact,
these algorithms are tightly-coupled with operating
system's task management services, since the dynamic
selection of DVFS must be coupled with task computation
time (Henkel & Parameswaran, 2007). Intelligent DVFS
approaches are essentially based on tree decision

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method, neural networks, deep learning (Fettes et al.,
2018; Zhang et al., 2017), and fuzzy logic (Yousra & Samir,
2019).
Recently, Reinforcement Learning (RL) methods have
been applied for energy optimization. Without relaying on
an explicit model, RL stills a promising approach that
exploits data collected at runtime to learn the optimal
decision (Gupta et al., 2019). Different RL algorithms were
applied in decision making. The most used is Q-learning
due to its simplicity and its strong convergence properties,
especially in games decision making. Although its
efficiency, this algorithm applied in modern System on
Chips (SoCs), needs a large memory requirement for Q-
table memorization. Thus, Deep Q-Learning (DQL)
algorithm is applied for a large variety of problems.
1. Objectives and Contributions
The major contributions of this paper are as follows,
The DQN approach is presented, which can dynamically
control both the frequency and the number of activated
cores. Then, reward function and parameters are discussed
for effective training of the DQN. We present
comprehensive experimental evaluations of periodic tasks
in Intel X86 and ARM Cortex A8 using a real time simulator.
Our approach is compared with CC-EDF and Static-EDF.
This paper describes the contribution of the approach into
three main parts: the first part is about the state-of-art
dynamic frequency scaling in the multiprocessing
architecture and its use of reinforcement learning in this
domain, the second part is dedicated to the proposed
DQN approach. Finally the simulations on generated
periodic sets with different system charges are detailed to
evaluate the approach performance.
2. Related Works
Many RL schemes have been developed and tested for
reconfiguration of multiprocessor architectures and
Multiprocessor System on Chips (MPSoCs). In fact, Gupta
et al. (2019) have presented an approach that uses
standard benchmarks on real platforms that do not make
any assumptions on the underlying workloads. It controls
four parameters (the number of little and big cores and
their frequencies) simultaneously. Also, we are designing a
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new type of reward function to handle multiple processing
elements and configuration knobs.
Molnos et al. (2016) investigates the use of Q-learning in
managing DVFS to minimize energy consumption. This
paper addresses the problem of determining the clock
frequency of a System-on-a-Chip (SoC) that executes
applications with throughput constraints. The solution is a
novel Q-learning based manager. They evaluated the
controller on test board embedding and ARM host
processor and a SoC with 16 processors elements and
dynamic frequency scaling. All timing- related numbers,
i.e., throughput, are realistic and include overheads.
Fettes et al. (2018) proposed LEAD-RL uses recent RL
techniques state of-the-art such as Deep Q Networks
(DQNs) to select the V/F mode that maximizes an
expected long-term reward capturing a desired energy
vs. throughput tradeoff. This creates a model that
prioritizes actions leading to maximal energy savings with
minimal throughput loss. It was realized by considering all
possible voltage level selections for the next time window.
ul Islam et al. (2015,2018) proposed a Q learning
algorithm that selects the best DVFS architecture from
(CC, DRA , LA). The research referenced in Zhang et al.
(2018) proposed a double deep Q-learning model to
reduce the energy consumption for the systems in edge
computing devices. It targets randomly generated
periodic real- time tasks. And it controls only the frequency
of a single resource, i.e., one variable. The same other in
Zhang et al. (2017) proposed Deep Q-Learning Model for
the Energy Efficient Scheduling in Real-time Systems
(DQLEES) by combining a stacked auto-encoder and a Q-
learning model.
The stacked auto-encoder is substituted for a Q-function
to learn the Q-value of each DVFS technology for any
system state, that is described by the dynamic stack and
system utilization.
This paper (Chen et al., 2018) is an extension of a
lightweight learning-based DVFS technique for single-
core and multi-core embedded systems. This technique
was implemented and evaluated on the Linux operating
system running on an Intel PXA27x embedded platform
(Intel, Santa Clara, CA, USA) and NVIDIA Tegra K1 multi-
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core platforms (NVIDIA, Santa Clara, CA, USA). For the
experiments, several benchmarks with different behaviors
were selected from MiBench and ParMiBench to
demonstrate the performance of the proposed scheme.
Real energy data were collected using a high-
performance Data Acquisition Instrument (DAQ).
According to the experimental results, the proposed
learning-directed DVFS technique can achieve an energy
savings rate upto 42%.
3. Context of the Research
Since DVFS lowers core frequency, execution time of a
program running over that scaled down processor may
increase, especially if the program is compute bound.
The frequency reduction process can be expressed by
the scaling factor S, which is the ratio between the highest
available frequency (fmax) for the CPU and the new
frequency (fnew) applied to the CPU, as in Equation 1.
S=fmax /fnew
3.1 Energy Model
The hardware platform consists of mmax homogenous
processors. Energy consumption of single processor is
given by formula Equation 2. Many searches divide the
power consumed by a processor into two power metrics:
static power and dynamic power (Rauber et al., 2014;
Rountree et al., 2007; Cochran et al., 2011; Da Rosa et al.,
2012; Parain et al., 2001). The first one is consumed as
long as the computing unit is on; the latter is consumed
only during computation times.
E=∫0tmax P(t).dt with P = Pdyn+Pstatic
The dynamic power Pdyn is related to the switching activity
a, load capacitance CL, the supply voltage V, and
operational frequency f, as shown in Equation 3.
2
Pdyn=a.CL.V .f
For earlier processors, static power was considered to be
negligible,
Pstatic = V. N. Kdesign. lleak
where,
N - Number of transistor
kdesign - Design dependent parameter
lleak - Technology dependent parameter
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The dynamic power is reduced by a factor of S, when
reducing the frequency of a processor by a factor S. The
energy consumption is measured in Joule, and can be
calculated by multiplying the power consumption,
measured in watts,and the execution time of the program
as follows:
Energy=Power x Time
3.2 Periodic Task Model Schedulability
In this paper, we assume a periodic task model in which
each task Γi is defined by (ri1, WCETi, AETi,Ti, Di): ri: release
time, Ti : period, Di : deadline and computation time that
could be WCETi (Worst Case Computation Time) or AETi
(Actual Execution Time). Furthermore, we focus our
attention on the implicit deadline task system (Ci<Ti=Di).
As in classical treatments of the real-time scheduling
problem, the relative deadline is assumed to be equal to
period, so a task must complete its execution before its
(1) next release. Given that, the worst case computation time
is supposed to be the time needed for the task to
complete its charge at maximum operating frequency, a
real time scheduler allocates processor time to the task in
such a way that it respect its deadline. In this section, we try
to establish a relationship between operating frequency
and system schedulability. A system is schedulable when
all its tasks respect their deadlines under designed
architecture and the specific real-time scheduler. Many
schedulability tests were associated with several
schedulers, such as global Earliest Deadline First (EDF). For
a set of n periodic tasks, we assume that the platform is
(2)
composed of m identical processors and that Un is system
utilization, system schedulability is assured if this is
sufficient and necessary condition is satisfied (Nayet &
Grajar, 2006; Baker & Cirinei, 2006; Li et al., 2015).
(3)
Un =∑ni=1C∕T
i m/S
i £ (5)
4. The proposed Approach: DQN-EDF
We utilize the DQN as an optimization method that aimed
(4)
at minimizing the energy consumption of the architecture
and guaranting the objectives of the research. There are
two main objectives in this case: to minimize energy
consumption and to guarantee system schedulability
under global EDF. Total system charge and initial
3
 RESEARCH PAPERS
frequency are approach criterion. In fact, mathematical
relation between system charge and the frequency
makes it a decision-making with interdependent multiple
criteria. Decision- making with interdependent multiple
criteria is surprisingly a difficult task. If we have clear
conflicting objectives, there is normally no optimal
solution, which would simultaneously satisfies all the
criteria. In fact, in this case, minimizing the CPU speed
reduces the energy (realizes first objective) but rises the
computation time and system load (contraries second
objective). The main idea of the proposed architecture is
to take advantage of reinforcement learning to avoid the
establishment of a model describing the exact relations
between input and output parameters.
Figure 1 is an illustration of the proposed approach, which
is based on a decision support system. It is a closed loop
that configures the multiprocessor architecture with the
couple (f,m). Two phases have been proposed: off-line
configuration and on-line configuration. The environment
which gives states is the simulator, and the agent that
provides actions is the DQN agent.
4.1 Deep Q-Learning Scheme
The agent reads the states from environment (the
platform) and takes actions, such as choosing the
operating frequency. The aim of the agent is to learn a
policy of maximizes a cost function such as energy per
joule. Figure 2 is an illustration of DQN approach.
The policy takes the state and counts the Q-value of each
Figure 1. Proposed Approach for Offline/Online Configuration
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Figure 2. Proposed DQN
possible action (9 actions). Then the action with maximum
Q-value is applied by the agent to the architecture. After
each action, we have a new state and a reward from the
environment. The reward rn is then used to improve the
policy of the agent. The epsilon-greedy policy is used to
explore the rewards due to all future actions (Gupta et al.,
2019). The policy is modeled for the deep Q-learning
where Q- values are a function of state S, action a and
neural network weights. At each interval, the policy
chooses the action that leads to the maximum Q-value
and the update is done through Equation 6.
(6)
In this equation, a is the learning rate and γ is the discount
factor. Table 1 gives the parameters of DQN. The number
of episodes are fixed in 1001.
Epsilon and epsilon decay are used by the epsilon-
greedy policy. It fixes the dilemma between exploration
and exploitation.
We propose a reward scheme that assigns the maximum
reward value when the Un/m is inferior to 1 and the
normalized energy is inferior to 0.2. When the charge per
processor is superior to 1, the reward is zero. Experience
buffer stores the most recent current action, current state,
next state, and reward. Then, a minibatch is sampled
uniformly from the experience buffer (its size is given in
Table 2).
5. Simulations and Results
Our experiments are executed in multiprocessor
scheduling simulator that we develop with python. The
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Bach size 32 Intel x 86

Learning rate 0.01 Parameter Value
¡ 0.95 Processor types Intel 86
Epsilon 1.0 Number of cores [1..16]
Epsilon_decay 0.995 Processing frequency [16 20 25 33] MHZ

Table 1. Training Parameters Operating voltage [2.0 2.2 2.4 2.7] V

Dynamic Energy Cons. [13.1 15.4 18.7 22.9] nJ
Reward Function
If (Un /m>1) then Reward=-20 Table 5. Intel X86 Characteristics
else
if (En <0.2) then Reward = 5
multiprocessor architecture parameters.
end
As indicated in the last paragraph, periodic application is
if (En>0.2) and (En<0.6) then Reward =3
else Reward=2 end composed of tasks characteristics; period/deadline (T, P),
end
Worst-Case Execution Times (WCET), Actual Execution Time
Table 2. Reward Function (AET), and Release time (r). Architecture parameters

DQN approach is developed using modules; Keras and concern especially, the number of processors, operating

Tensor flow dedicated to artificial intelligence.
The target architectures are multiprocessor systems
composed of identical processors supporting DVFS
techniques especially; Intel 486 GX and ARM Cortex A8.
Tables 4 and 5 gives the power consumption of processors
points, dynamic and static energy. Outputs are simulation
of scheduled tasks with global EDF/Global RM, application
schedulability analysis, number of missed deadline and
energy consumption.
Figure 3 is the class diagram illustration. It is centered on the

for all possible operating points. main class “model” that is composed of four classes;
“monitor”, “RTOS”, “CPU”, and “Task”.
The scheduler is global EDF, which is dynamic priority based
scheduling. The periodic tasks adopted to evaluate the The simulator integrates intelligent module that decides two

approach are illustrated in Tables 3 and 6. parameters; the number of activated processors and the
execution frequency. This decision system is composed of a
We developed a real time simulator IntSimRT using python,
previous research algorithm based on fuzzy logic. It
to evaluate the performance of DVFS techniques on
implements the agent described bellow. The DQN
multiprocessor architecture. The inputs of the simulator are;
approach is realized using Tensor flow and Keras modules,
the periodic application parameters and the
which are widely used in artificial intelligence.
Tasks WCETi Ti=Di ri AETi
The simulator in command line takes the tasks and
T1(new_frame) 1 19 0 1
T2(Nal_Dispatch) 2 5 0 1 architecture characteristics as input parameters, illustrated
T3(Slice1_processing) 38 66 0 21 in Figure 4. Then it generates scheduling application under
T4(Slice2_processing) 38 66 1 21
global-EDF as illustrated in Figure 5. It also calculates the
T5(Slice3_processing) 38 66 2 21
T6(Slice4_processing) 38 66 3 21
processor energy consumption of the periodic
T7(Rebuild_frame) 2 66 66 1 application as presented in Equation 2.
Table 3. Tasks of the H264 Video Decoder

ARM Cortex A8
Parameter Value

Number of cores [1..16]

Processing fr [125, 250, 500, 520, 720]MHz
Operating voltage [0975, 1.05, 1.2, 1.27, 1.35]V
Pd [57, 130, 303, 348, 550] mW
Pidle [4, 7, 16, 18, 28] mW

Table 4. ARM A8 Characteristics Figure 3. Class Diagram of the Simulator

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Figure 4. Simulation Parameters and Results

Figure 7. Normalized Energy Consumption / System Charge for

Video Decoder H264 – ARM Cortex A8 fr = (125,250,500,720) MHZ

When we choose an application from those in Table 6, we

calculate its utilization charge and its normalized energy
estimation under maximum frequency and one active
processor, which is considered as state 0 = [U0, En0].
The offline configuration using the DQN algorithm
Figure 5. Tasks and CPU Execution without DVFS
Techniques (m=2 and Ci=AET) exposed below begins with training phase that takes
5.1 Offline Configuration some minutes, which is tolerable in offline mode. Figure 8
indicates the mean time consumed for training of
The conception of the reward function is based on the
different task sets with different charge (Table 7). The
energy consumed by cores while executing the periodic
number of tasks and the system charge does not affect
application depends on the number of active cores and
the training time since, it depends on the number of
their speed. We could notice from Figure 6 that rising the
episodes fixed in the training parameters.
number of active cores increases the energy
consumption. On the other hand, scaling down their In the first episodes, the agent acts randomly and the loss
speed decreases the energy and rises the system charge
as shown in Figure 7.
The offline configuration is realized before runtime. In this
part, we train the DQN network with the parameters fixed in
the Table 1.

Figure 8. Consumed Time While Training

Task Sets Number of Tasks Usys Random Generation Method

Set 1 3 1.83 Rand fix sum
Set 2 10 2.97 Rand fix sum
Set 3 30 4.77 Rand fix sum
Set 4 100 14.77 Rand fix sum
Figure 6. Processor Energy Consumption for Different
Processor Number-Video Decoder H264-Intel x86 Table 6. Periodic Application

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Intel X86 Set1 Set2 Set3 Set4

Configuration (33MHz,2) (33MHz,4) (20MHz,7) (33MHz,16)

Schedulability Yes Yes Yes

no
(U=0.92) (U=0.7) (U=0.76)

Estimated Energy (MJ) 846.33 MJ 6622.67MJ 11130.11MJ 245218 MJ

Table 7. Offline DQN Configuration Results

function (illustrated in Figure 9) takes huge values before

stabilization in the end. In fact, the agent while learning from
the rewards of its random acts, adjusts weights to attempt
the desired policy.
Results are efficient since they respect constraints which Figure 11. Energy Consumption for Video Decoder H264-ARM

are; the deadline guarantee of all tasks, the execution time
raised by the scale factor must inferior to its period and the
energy minimization.
As shown in Figure 10, the proposed configuration for the
h264 decoder simulated with ARM A8 architecture is (m=2,
fr=720 MHz), which estimated energy of 101300.n11 MJ
and system charge Un=0.93.
5.2 Online Configuration
The trained model allows the agent to make decision in
online mode. Since, tasks execute their AET time the
dynamic slacks are used to configure the architecture.
The agent is called when a task is terminated. Figure 11 is
an illustration of the energy consumed with the DQN-EDF
Figure 9. Loss Values of Offline Configuration for
H264 Decoder - ARM Cortex A8
Figure 10. The Simulator Response for Video Decoder
H264- Intel X86
and with CC-EDF.
Conclusion
With relentless technology scaling and mass integration of
transistors into a single chip, exponentially increased
power consumption and severely degraded reliability
have become first class design design issues in modern
computing systems. In this paper, we study the energy
minimization and the schedulability problem of periodic
tasks in multiprocessor architecture. We proposed a deep
reinforcement learning approach for dynamic resource
management of multiprocessor architecture.
Although the DQN agent is model free, it guarantees a
balance between the minimization of consumed energy
and the schedulability of periodic application. Applied to
different periodic applications generated randomly, the
approach proposed efficient configuration in offline and
online mode. Compared to well-known DVFS techniques
based on EDF such as static-EDF, CC-EDF, and DSR, the
agent saved energy and guarantees theschedulability.
These results were achieved by the development of a new
reward function specific to guarantee the constraints of
the issue. The advantage of this new approach is that, we
do not need an exhaustive model to make the optimal
decision. Besides, it is a generic agent that could easily be
modified to configure memory cache size and
associativity. In fact, the power module is responsible for
estimating the consumed energy should just be extended.
We proposed a model that calculates the frequency of
processors and the number of activated processors. This
achieves good results for different applications.

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ABOUT THE AUTHORS

Najar Yousra is currently working as an Assistant Professor in the Department of Science Computer School (ISI) of Tunis in Tunisia.
She received degrees in Computer Science. Her research fields are Fuzzy Logic, Deep Learning, Decision Making, and Real Time
Systems.

Samir Ben Ahmed is currently working as a Professor in University of Science and Technology (FST) of Tunis in Tunisia. From 1996 to
1999, he was the Director of Electrical Engineering department of ENIT. From 1999 to 2001, he was the Director of the Computer
Science department at the Faculty of Sciences of Tunis. From 2001 to 2005, he was the Founding Director of the Higher Institute of
Computer Science. From 2005 to 2011, he was the Director of National Institute of Applied Sciences and Technology of Tunis.
Since 2012, he has been responsible for the Commission of Doctoral Theses in Computer Science - Faculty of Sciences of Tunis.

i-manager’s Journal on Embedded Systems, Vol. 8 l

No. 1 l
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