High-Efficiency 255 W ATX Power Supply Reference Design

TND359/D
Rev 0, Jan-09
High-Efficiency
255 W ATX Power Supply
Reference Design
Documentation Package
1
© 2009 ON Semiconductor
Disclaimer: ON Semiconductor is providing this reference design documentation

package “AS IS” and the recipient assumes all risk associated with the use and/or
commercialization of this design package. No licenses to ON Semiconductor’s or any
third party’s Intellectual Property is conveyed by the transfer of this documentation.
This reference design documentation package is provided only to assist the customers
in evaluation and feasibility assessment of the reference design. The design intent is
to demonstrate that efficiencies beyond 85% are achievable cost effectively utilizing
ON Semiconductor provided ICs and discrete components in conjunction with other
inexpensive components. It is expected that users may make further refinements to
meet specific performance goals.
2
Table of Contents
1. Overview................................................................................................... 4
2. Specifications .......................................................................................... 5
3. Architecture Overview............................................................................. 7
3.1 Primary Side: PFC Stage................................................................................. 7
3.2 Primary Side: Half bridge resonant LLC Converter.......................................... 7
3.3 Secondary Side: Synchronous Rectification .................................................... 7
3.4 Secondary Side: DC-DC Conversion Stage .................................................... 8
3.5 Secondary Side: Monitoring and Supervisory Stage........................................ 8
3.6 Standby Power ................................................................................................ 8
4. Performance Results ..................................................................................9
4.1 Total Efficiency ............................................................................................................9
4.2 Power Factor ...............................................................................................................9
4.3 Standby Power ..........................................................................................................10
4.4 Input Current..............................................................................................................10
4.5 Inrush Current............................................................................................................10
4.6 Output Transient Response (Dynamic Loading) ........................................................11
4.7 Overshoot at Turn-On/Turn-Off..................................................................................11
4.8 Output Ripple / Noise.................................................................................................13
4.9 Hold-up Time .............................................................................................................20
4.10 Timing / Housekeeping / Control..............................................................................21
4.11 Output Protection.....................................................................................................23
5. Evaluation Guidelines ..............................................................................26
6. Schematics................................................................................................28
7. Parts List ...................................................................................................29
8. Resources/Contact Information ..............................................................36
9. Appendix ...................................................................................................36
3
1. Overview
ON Semiconductor was the first semiconductor company to provide an 80 PLUS-certified open
reference design for an ATX power supply in 2005. A second generation 80 PLUS-certified open
reference design with improved efficiency was then introduced in 2007. ON Semiconductor is now
introducing its third generation 80 PLUS-certified open reference design with a drastic efficiency
improvement. This is a 255 W multi-output power supply for the ATX form factor. Achieving a
maximum efficiency of 90% at 50% load, and at 230 and 240 Vac, this third generation reference
design achieves >88% efficiency at 50% load, and 100 and 115 Vac. All efficiency measurements
were obtained at the end of a 41 cm (16 in.) cable, ensuring the design can be used ‘as is’ in all
standard desktop PC configurations.
This reference document provides the details behind this third generation design. The design manual
provides a detailed view of the performance achieved with this design in terms of efficiency,
performance, thermals and other key parameters. In addition, a detailed list of the bill-of-materials
(BOM) is also provided. ON Semiconductor will also be able to provide technical support to help our
customers design and manufacture a similar ATX power supply customized to meet their specific
requirements.
The results achieved in this third generation design were possible due to the use of advanced new
components from ON Semiconductor. These new ICs not only speeded up the overall development
cycle for this new design, but also helped achieve the high efficiencies while at the same time keeping
a check on the overall cost.
This third generation design consists of a single PCB designed to fit into the standard ATX enclosure
along with a fan. Figure 1 below presents the overall architecture employed in this design. Detailed
schematics are included later in this design manual.
Figure 1: Reference Design Architecture Simplified Block Diagram
4
As seen in figure 1, the first stage, active Power Factor Correction (PFC) stage, is built around ON
Semiconductor’s Continuous Conduction Mode (CCM) PFC controller, NCP1654. The NCP1654
provides an integrated, robust and cost-effective PFC solution. The second stage features a resonant
half-bridge LLC topology using ON Semiconductor’s controller, NCP1396. This topology ensures
maximum efficiency and minimizes EMI. The NCP1027, standby controller, is used to generate the 5
V standby output. The NCP1027 is an optimized integrated circuit for the ATX power supply and
incorporates a high-voltage MOSFET.
On the secondary side, this architecture uses a synchronous rectification scheme built around ON
Semiconductor’s NCP4302 controller in order to generate a 12 V output. Finally, two identical DC-DC
controllers are used to down-convert the 12 V into +5 V, +3.3 V and -12 V. The DC-DC controller is
the NCP1587, a low voltage synchronous buck controller in a very small surface mount 8-pin package.
Each DC-DC controller drives two NTD4809 (30 V, 58 A, single N-channel power MOSFET) in a
synchronous rectification scheme.
With the introduction of this third generation, high-efficiency ATX Power Supply, ON Semiconductor
has shown that with judicious choice of design tradeoffs, optimum performance is achieved at
minimum cost.
2. Specifications
The design closely follows the ATX12V version 2.2 power supply guidelines and specifications
available from www.formfactors.org, unless otherwise noted. This 255 W reference design exceeds
the 80 PLUS Silver (www.80plus.org), ENERGY STAR® 5.0 (www.energystar.gov), and Climate
Savers Computing Initiative (CSCI) Step 3 (www.climatesaverscomputing.org) efficiency targets for
desktop PC multi-output power supplies. Table 1 hereafter shows a summary of the efficiency targets
from these different organizations.
20% of 50% of 100% of

Levels Specification rated rated rated Compliance
Multi-Output ATX Power Supplies
output output output

ENERGY STAR rev. 4.0
• Multiple-Output
&
• Non-Redundant 80% 80% 80%
CSCI step #1
• PFC 0.9 at 100% efficiency efficiency efficiency
of rated output
Effective date: July 2007
ENERGY STAR rev. 5.0

• Multiple-Output
(Effective date: July 2009)
• Non-Redundant 82% 85% 82%
&
• PFC 0.9 at 50% efficiency efficiency efficiency
CSCI step #2
of rated output
(June 2008 thru July 2009)
• Multiple-Output
• Non-Redundant 85% 88% 85% CSCI step #3
• PFC 0.9 at 50% efficiency efficiency efficiency (July 2009 thru June 2010)
of rated output
• Multiple-Output
• Non-Redundant 87% 90% 87% CSCI step #4
• PFC 0.9 at 50% efficiency efficiency efficiency (July 2010 thru June 2011)
of rated output
Table 1: Summary of Efficiency Targets
5
Key specifications for this reference design are included in Table below.
Input DC Output Current

Output
Voltage Min Full Load Max
Voltage Frequency
(Vdc) DC Current DC Current DC Current
(Vac) (HZ)
(A) (A) (A)
Min. 90 47 +12 VA 0 9.50 13.0
100 50 +12 VB 0 5.12 7.0
115 60 +5 V 0.3 9.44 15.0
Typ.
230 50 +3.3 V 0.3 5.03 8.0
240 50 -12 V 0 0.32 0.4
Max. 264 63 +5 VSB 0 2.39 3.0
Output Power
Output Full Load
Voltage DC Current Full Load
(Vdc) (A) Output Power Notes
(W)
+12 VA 9.50 114.0 Peak +12 VAdc output current up to 14 A.
Peak +12 VBdc output current to be 8 A.
The maximum combined load on the +12 VAdc
+12 VB 5.12 61.4
and +12 VBdc outputs shall not exceed 220 W.
+5 V 9.44 47.2 The maximum continuous combined load on
the +5Vdc and +3.3 Vdc outputs shall not
+3.3 V 5.03 16.6
exceed 80 W.
-12 V 0.32 3.8
+5 VSB 2.39 11.95
Full Load Total
Output Power =
255 W
Output Output Voltage Regulation (V) Tolerance Output Ripple

Voltage (%) / Noise
Min. Typ. Max.
(Vdc) (mVpp)
+12 VA +11.4 +12 +12.6 ±5 120
+12 VB +11.4 +12 +12.6 ±5 120
+5 V +4.75 +5 +5.25 ±5 70
+3.3 V +3.14 +3.3 +3.47 ±5 50
-12 V -10.8 -12 -13.2 ±10 250
+5 VSB +4.75 +5 +5.25 ±5 100
Table 2: Target Specifications
Target specifications for other key parameters of the reference design include:
Efficiency: Minimum efficiency of 85% at 20% and at 100% of rated output power, and 88% at 50%
of rated output power as defined by the 80 PLUS requirements.
Power Factor: Power factor of 0.9 or greater at 100 % load.
Input Voltage: Universal Mains: 90 Vac to 265 Vac, frequency: 47 to 63 Hz.
Safety Features: As per the ATX12V version 2.2 power supply guidelines, this design includes
safety features such as OVP, UVP, and OCP.
6
3. Architecture Overview
The architecture selected is designed around a succession of conversion stages as illustrated in
Figure 1. The first stage is a universal input, active power factor boost stage delivering a constant
output voltage of 385 V to the second stage, the half bridge resonant LLC converter. On the
secondary side, this architecture uses a synchronous rectification scheme built around ON
Semiconductor’s NCP4302 controller in order to generate a +12 V output. Finally, the +12 V is down-
converted +5 V, +3.3 V and -12 V by a DC-DC conversion stage, built around two identical DC-DC
controllers. In addition, a small integrated flyback converter delivers 12 W of standby power to another
isolated 5 V rail. All the different voltage rails are monitored by a dedicated supervisory controller.
ON Semiconductor has developed multiple power management controllers and MOSFET devices in
support of the ATX program. Web-downloadable data sheets, design tools and technical resources
are available to assist design optimization. The semiconductor components, supporting the ATX
Generation 3 platform, are the NCP1654 PFC controller, the NCP1396 half-bridge resonant LLC
controller, the NCP4302 synchronous rectification, the NCP1027 standby controller, the NCP1587 DC-
DC controller with synchronous rectification, and the NTD4809 single N-channel power MOSFET
driven by the NCP1587, in synchronous rectification.
3.1 Primary Side: PFC Stage

There are a variety of PFC topologies available. These include discontinuous conduction mode
(DCM), critical conduction mode (CRM) and continuous conduction mode (CCM). At this power level,
CCM is the preferred choice and the NCP1654 will implement an IEC61000-3-2 compliant, fixed
frequency, peak current mode or average current mode PFC boost converter with very few external
components.
3.2 Primary Side: Half bridge resonant LLC Converter

The heart of the half-bridge resonant LLC converter stage is the NCP1396 resonant mode controller.
Thanks to its proprietary high-voltage technology, this controller includes a bootstrapped MOSFET
driver for half-bridge applications accepting bulk voltages up to 600 V. Protections featuring various
reaction times, e.g. immediate shutdown or timer-based event, brown-out, broken optocoupler
detection etc., contribute to a safer converter design, without engendering additional circuitry
complexity. An adjustable dead-time also helps lower the shoot-through current contribution as the
switching frequency increases. More information about LLC structure can be found in the ON
Semiconductor application note AND8311/D (Understanding the LLC Structure in Resonant
Applications).
3.3 Secondary Side: Synchronous Rectification

The 12 V output generated by the half-bridge resonant LLC converter is rectified using a proprietary
synchronous rectification scheme built around two NCP4302 and two external single N-channel
MOSFETs.
7
3.4 Secondary Side: DC-DC Conversion Stage
Two identical DC-DC controllers are used to down-convert the 12 V into +5 V and +3.3 V. The DC-DC
controller is the NCP1587, a low voltage synchronous buck controller in a very small surface mount 8-
pin package. The NCP1587 is a low cost PWM controllers designed to operate from a 5 V or 12 V
supply. This device is capable of producing an output voltage as low as 0.8 V. The NCP1587 provides
a 1 A gate driver design and an internally set 275 kHz (NCP1587) oscillator. Other efficiency
enhancing features of the gate driver include adaptive non overlap circuitry. The NCP1587 also
incorporates an externally compensated error amplifier and a capacitor programmable soft start
function. Protection features include programmable short circuit protection and under voltage lockout.
Each DC-DC controller drives two NTD4809 (30 V, 58 A, single N-channel power MOSFET) in a
synchronous rectification scheme.
The -12 V is generated from the +5 V using a small discrete-based converter.
3.5 Secondary Side: Monitoring and Supervisory Stage

The four dc outputs +5 V, +3.3 V, +12 VA and +12 VB are monitored by a dedicated monitoring
controller which also provides over-current protection, over-voltage protection, under-voltage
protection and generates the Power Good logic signal.
3.6 Standby Power

The NCP1027 integrates a fixed frequency current mode controller and a 700 volt MOSFET. The
NCP1027 is an ideal part to implement a flyback topology delivering 15 W to an isolated 5 V output.
At light loads the IC will operate in skip cycle mode, thereby reducing its switching losses and
delivering high efficiency throughout the load range.
8
4. Performance Results
Measurements are done at three loading conditions, the load being expressed as a % of the rated
output power, i.e. at 20%, 50% and at 100% of rated output power.
Measurements are also done at four AC line voltages, at 100 Vac, 115 Vac, 230 Vac and 240 Vac, at
50 Hz, 60 Hz and 63 Hz.
All measurements are taken at the end of the 41 cm-long (16 inches) cable.
The converter efficiency is measured according to the loading conditions detailed in Table 3:
Load as % of rated Output Current (A)

output power +12VA +12VB +5V +3.3V -12V +5VSB
20% 1.90 1.02 1.89 1.01 0.06 0.48
50% 4.75 2.56 4.72 2.52 0.16 1.20
100% 9.50 5.12 9.44 5.03 0.32 2.39
Max. 13.0 7.0 15.0 8.0 0.4 3.0
Table 3: Load Matrix for Efficiency Measurements
4.1 Total Efficiency

Total Efficiency (%)
AC Input 20% Load 50% Load 100% Load
100 VAC / 50 HZ 85.9% 88.3% 85.9%
115 VAC / 60 HZ 86.3% 88.8% 86.8%
230 VAC / 50 HZ 86.5% 90.1% 88.7%
240 VAC / 63 HZ 86.5% 90.1% 88.8%
Table 4: Efficiency Results
The converter achieves over 85% efficiency with room to spare over all load conditions. All
measurements are done at the end of the power cable.
4.2 Power Factor

The power factor exceeds 0.9 over all operating conditions as shown in Table .
Power Factor
Specification
AC Input 20% Load 50% Load 100% Load
100 VAC / 50 HZ 0.96 0.983 0.987
PF > 0.90 @100%
115 VAC / 60 HZ 0.945 0.978 0.986
& 50% of rated
230 VAC / 50 HZ 0.714 0.912 0.966
output power
240 VAC / 63 HZ 0.689 0.902 0.962
Table 5: Power Factor vs Load as % of Rated Output Power
9
4.3 Standby Power
Output Input
AC Input Current on Power Specification
+5VSB (A) (W)
100 VAC / 50 HZ 0.147 0.36 < 1W
115 VAC / 60 HZ 0.171 0.31 • U.S. Department of Energy, FEMP (Federal Energy
230 VAC / 50 HZ 0.244 0.55 Management Program):
http://www1.eere.energy.gov/femp/procurement/index.html
240 VAC / 63 HZ 0.312 0.57 • Executive Order 13221 of July 31, 2001:
http://www1.eere.energy.gov/femp/pdfs/eo13221.pdf
Table 6: Standby Power vs AC Line Voltage
4.4 Input Current

Measurement (A)
AC Input Specification
20% Load 50% Load 100% Load
90 VAC / 47 HZ 0.673 1.609 3.245
100 VAC / 50 HZ 0.614 1.458 2.952
115 VAC / 63 HZ 0.544 1.271 2.549 90V (max 3.6A)
180 VAC / 50 HZ 0.363 0.799 1.573 180V (max.1.8A)
230 VAC / 53 HZ 0.355 0.667 1.266 @ 100% load
240 VAC / 60 HZ 0.353 0.646 1.217
264 VAC / 63 HZ 0.339 0.597 1.092
Table 7: Input Current vs Load and AC Line Voltage
4.5 Inrush Current

Parameter Description Min. Typ. Max. Units
Initial In-rush Current 55 A (Peak)
Secondary In-rush Current 35 A (Peak)
Table 8: Inrush Current Specification
Output
AC Input Measurement (A) Specification
Load
100% Initial In-rush Current 9.9
90 VAC/47 HZ
Load Secondary In-rush Current 8.0
120 VAC/63 HZ Initial In-rush Current < 55 A
100% Initial In-rush Current 25.4 Secondary In-rush Current < 35 A
220 VAC/50 HZ
264 VAC/63 HZ
Table 9: Inrush Current vs AC Line Voltage
10
4.6 Output Transient Response (Dynamic Loading)
Output Transient starting Load T1 / T2 (0.1 A/µsec), T1 / T2 (1 ms)
Load (A) Voltage Max. (V)
DC Output
Min. Load Step Max. Overshoot Undershoot
+12 VA 0.5 6.5 6.5 0.6 0.6
+12 VB 0.5 3.5 3.5 0.6 0.6
+5 V 0.3 5 10 0.25 0.25
+3.3 V 0.3 2.66 5.34 0.17 0.17
-12 V 0 0.17 0.33 0.6 0.6
+5 VSB 0 1.33 2.67 0.25 0.25
Table 10: Output Transient Response (Dynamic Loading)
4.7 Overshoot at Turn-On/Turn-Off

Min. – Load Load Step –
DC Output Specification Unit
Step Max.
+12VA 0.34 N/A 1.2
+12VB 0.38 N/A 1.2
+5V 0.21 0.23 0.5
VP-P
+3.3V 0.15 0.17 0.33
-12V 0.18 0.20 -1.2
+5VSB 0.21 0.20 0.5
Table 11: Overshoot at Turn-On/Turn-Off
Measured and Calculated Data at 115V / 60HZ

DC Output Min. – Load Step Load Step – Max.
+12 VA N/A
+12 VB N/A
11
+5 V
+3.3 V
-12 V
+5 VSB
Figure 2: Dynamic Load Test Waveforms
12
4.8 Output Ripple / Noise
The ripple voltage of each output is measured at no load and at the maximum load for each output.,
and at the four different line voltages. The output ripple is measured across 10 μF/MLC parallel 1000
μF low ESR/ESL termination capacitors. Figure 3 through 6 show the output voltage ripple
measurements. All outputs meet the voltage ripple requirements.
Output Ripple / Noise

DC Output No Load (A) Full Load (A)
Max (mVp-p)
+12 VA 0 9.50 120
+12 VB 0 5.12 120
+5 V 0 9.44 70
+3.3 V 0 5.03 50
-12 V 0 0.32 250
+5 VSB 0 2.39 100
Table 12: Output Ripple / Noise Specification
4.8.1 100 VAC / 50 HZ - Ripple / Noise Test Waveform
No Load Full Load
+12 VA
No Load Full Load
+12 VB
13
No Load Full Load
+5 V
No Load Full Load
+3.3 V
No Load Full Load
-12 V
No Load Full Load
+5 VsB
Figure 3: 100 VAC / 50 HZ - Ripple / Noise Test Waveform
14
No Load Full Load
+12 VA
No Load Full Load
+12 VB
No Load Full Load
+5 V
No Load Full Load
+3.3 V
15
No Load Full Load
-12 V
No Load Full Load
+5 VSB
16
No Load Full Load
+12 VA
No Load Full Load
+12 VB
No Load Full Load
+5 V
No Load Full Load
+3.3 V
17
No Load Full Load
-12 V
No Load Full Load
+5 VSB
18
No Load Full Load
+12 VA
No Load Full Load
+12 VB
No Load Full Load
+5 V
No Load Full Load
+3.3 V
19
No Load Full Load
-12 V
No Load Full Load
+5 VSB
4.9 Hold-up Time

The required holdup time at 50% load is 16 ms. Holdup time is measured from the moment the AC
power is removed to when the PWR_OK signal goes low. Figure 7 shows the holdup time at 50%
load, and at 115 Vac and 230 Vac. Channel 4 is the AC power and Channel 1 is the PWR_OK signal.
Dropout Loading Measurement

AC Input Specification
Condition (msec)
115 VAC / 60 HZ 50% Load 22
> 16 ms
230 VAC / 50 HZ 50% Load 23
Table 13: Hold-up Time Specification
20
115 VAC 60HZ - 50% Load 230 VAC / 50 HZ - 50% Load
Figure 7: Hold-up Time
4.10 Timing / Housekeeping / Control

4.10.1 AC On / Off Control
AC On / Off Test Parameter Description

Main Outputs Rise Time 2 ms < T2 < 20 ms
POK delay 100 ms < T3 < 500 ms
Power down warning 1 ms < T4
Hold-up time T6 > 16 ms
PS_ON Timing (on) T7 < 1000 ms
Main Outputs Rise Time 2 ms < T2 < 20 ms
Figure 8: AC On / Off Control
21
4.10.2 PS_ON On / Off Control
PS_ON On / Off Test Parameter Description

Rise Time 2 ms < T2 < 20 ms
POK delay 100 ms < T3 < 500 ms
Power down warning 1 ms < T4
PS_ON Timing (off) T8 < 60 ms
PS_ON Timing (on) T9 < 350 ms
-12VDC Rise Time 0.1 ms < T10 < 20 ms
Figure 9: PS_ON On / Off Control
4.10.3 Logic Timings

Measurements
Parameter DC
Description Min. Max. Units
Description Output
AC IN PS_ON
Delay from Standby within regulation to DC outputs turn
T1 5 300 N/A 148 N/A
on
+12V 2.8 4.2
+5V 2.6 2.4
T2 Standby, +3.3VDC, +5VDC,and 12VDC output rise time 2 20
+3.3V 2.8 2.2
+5Vsb 14 N/A
+12V 250 256
Delay from output voltages within regulation limits to
T3 100 500 +5V 244 250
POK asserted at turn on
+3.3V 244 252
+12V 1.6 28.4
Delay from POK deasserted to output voltages (3.3V, +5V 4.8 30
T4 1
5V, 12V, -12V) dropping out of regulation limits +3.3V 6.8 32.4
-12V 6 12
+12V 608 ms
Delay from DC output deasserted to Standby out of
T5 5 +5V 600
regulation at turn off.
+3.3V 600
T6 Delay from loss of AC to desertions of PWOK. 16 N/A 604
+12V 143
T7 PS_ON Timing (on) 1000 +5V 178
+3.3V 179
+12V 65.6
T8 PS_ON Timing (off) 60 +5V 67.2
+3.3V 69.2
+12V 80.8
T9 Delay from PS-ON reasserted to output turn on 350 +5V 86.8
+3.3V 86.8
T10 -12VDC output rise time 0.1 20 -12V 1.822 1.239
Table 14: Logic Timings
22
4.10.4 PWR_OK
CONTROL AND LOGIC SIGNALS RIPPLE/NOISE
PWR_OK
Measurement Max. Unit
Full Load
35 400 mVP-P
Table 15: PWR_OK Timings
4.10.5 PS_ON
CONTROL AND LOGIC SIGNALS RIPPLE/NOISE
PS_ON
Measurement Max. Unit
Full Load
30 400 mVP-P
Table 16: PS_ON Timings
4.11 Output Protection

4.11.1 Output Over-Voltage Protection
Specification Measurements
DC Output
Min. (V) Max. (V) (V)
+12 VA / B 13.5 15
+5 V 5.6 7 6.36
+3.3 V 3.76 4.3 4.2
-12 V -13.5 -15
+5 VSB 5.6 7
Table 17: Output Over-Voltage Protection
4.11.2 Output Under-Voltage Protection

+12VA +12 VB
+5 V +3.3 V
Figure 10: 115 VAC / 60 HZ DC Output Under-Voltage Protection @ Full Load
23
4.11.3 Short Circuit Protection
+12 VA +12 VB
+5 V +3.3 V
+5 VSB
Figure 11: 115 VAC / 60 HZ DC Output Short circuit protection @ Full Load
24
4.11.3 Over-Current Protection
Over Current Protection Measurements
DC Output
Min. (A) Max. (A) (A)
+12 VA 15 21 (< 240 VAC) 19.6
+12 VB 8.5 11.5 (< 240 VAC) 10.0
+5 V 18 24 20.5
+3.3 V 10 13 10.9
-12 V N/A N/A N/A
+5 VSB 3 6 6.0
Table 18: Over-Current Protection
+12 VA +12 VB
+5 V +3.3 V
+5VSB
Figure 12: DC Output Short circuit protection @ Full Load
25
5. Evaluation Guidelines
Evaluation of the reference design should be attempted only by persons who are intimately familiar
with power conversion circuitry. Lethal mains referenced voltages and high dc voltages are present
within the primary section of the ATX circuitry. All testing should be done using a mains high-isolation
transformer to power the demonstration unit so that appropriate test equipment probing will not affect
or potentially damage the test equipment or the ATX circuitry. The evaluation engineer should also
avoid connecting the ground terminal of oscilloscope probes or other test probes to floating or
switching nodes (e.g. the source of the active clamp MOSFET). It is not recommended to touch heat
sinks, on which primary active components are mounted, to avoid the possibility of receiving RF burns
or shocks. High impedance, low capacitance test probes should be used where appropriate for
minimal interaction with the circuits under investigation.
As with all sensitive switchmode circuitry, the power supply under test should be switched off from the
ac mains whenever the test probes are connected and/or disconnected.
The evaluating engineer should also be aware of the idiosyncrasies of constant current type electronic
loads when powering up the ATX demonstration unit. If the loads are adjusted to be close to the ATX’s
maximum rated output power, the unit could shut down at turn on due to the instantaneous
overloading effect of the constant current loads. As a consequence, electronic loads should be set to
constant resistance mode or rheostats should be used for loads. The other alternative is to start the
supply at light to medium load and then increase the constant current electronic loads to the desired
level.
The board is designed to fit in a traditional ATX enclosure as shown in Figure .
26
Figure 13: ON Semiconductor’s 255 W Reference Design for ATX Power Supplies
27
6. Schematics
The power supply is implemented using a single sided PCB board. Added flexibility is provided by
using daughter cards for the PFC (NCP1654) circuit and the NCP1396 resonant mode controller. The
individual PCB board schematics are shown in figure 14.
28
ACL
To +5Vsb system D1 R133

ACN STTH310(UF5407G) R13 10- 2W IC14 10K
R132 104 IS12A/B VS12A
LF1 LF3 Q3 1 SYNC/CS VCC8 0.002
SW1 F1 5A/250V BD1 LQA08TC600 HV+
2.2-
0-1 Switch CX3 0.8*25t 3mH 0.8*25 3mH 10A600V L2 STP12NM50 A 2 TRIG GATE 7
RS12A-1 Peak 14A
L
CON1 L3 D2
0.33 3A1000V T1 C132 RS12A C144
1
0.1*50t 680uH E
2 N T1/P1 3 CATH GND 6 +12VA R146
CX2 0.002 A
1M(1/4W)
TO220 EE35 A
1 MOV R1 0.47 120uH R6 R7 D3 R10 0.1*50 33t
1,2 4 REF Dlyadj 5 E 22-
CX1
VS12B
1n/50V
N.C.
3.96 471K 4 2 1.8M(1%) TO220 NCP4302 L6 0.8uH T1(1/3) R147 D78
3.3M 10K RS12B Peak 8A
1uF Ls=80uH 12,13,14 +12VB 1K
7.5B
0.1*80 2T
C130561 C136 C137 C138 C139 0.002
Lm=620uH R130 C140
2200uF/16V
2200uF/16V
2200uF/16V
2200uF/16V
C146 R134
2200uF/16V
R8 C2
220uF/16V
2
3
3 1.8M(1%) 10-(2W) 6.2K
Q1
3
2
1
D D77 D
1 4 220uF/450V TO220 R135 RS12B-1 F
AC INLET CY1 CY2 C1 C6
Q4 R12 5,6 D70 R148
CORE CY3 CY4 SPP15N60C3 T1/P2 0.002
N.C.
AC IN 472 472 474 R9 STP12NM50 3.3K 1K 7.5B
RH16*17*9 472 472 (EE35) F C145
24K
AC IN 85-264V 474 R5 0-(1%) MBR60L45CTG R149
C4-1 B
223/630V
GND WIRE 2t 10K TO220 GND B
C4
10,11 D72 L9
STP80NF55
R3 R11 D4 TO220 1n/50V 22-
10K Q30 0.8uH
333/630V
CY5 0.1-3Ws
nc. R3-1 R137 1N4148
80A55V 10-
0.5- 1W
R138
STP80NF55
R12A
4 2 1 24K 10-
Q31 D73
C5 R142
TO220
R52 3.6K(1%) 80A55V 1K
220P 8,9 1N4148
R51 R53 D71
3.3M IC1 C52
1 8 10-(1206) R57 0.1uF T1/P3
5 2T MBR60L45CTG
2 7 23.2K R55
C56 D5 1K C131 R140
3 6
47uF/25V R13110-(2W) 561 10K R143 68K R144
4 5 C141 18K(1%)
R56 4148 IC15 104
R141 IC16 223
+12V
C50 R54 C53 12K 1 SYNC/CS VCC8 AZ431 R145 R303
NCP1654 C55 2.2-
R55 C54 2.2uF B 2 TRIG GATE 7 4.7K(1%) 15-
0.47uF C134
1nF
47K
82.5K 220nF TM2 D120
UF 1A600V
D20 3 CATH GND 6 CON3 +
65Khz HV T204K 6.2B
R56 C60 FAN
IC23 4 REF Dlyadj 5 1
30K 47uF/25V 2 A 12V
NCP4302
6 J9 R68 7
18-(1206)
2.54 -
33- 10- 6 817
R65
C57 1uF
16 Q11
R77 33- IC2 NCP1396A C61 104
Q20 FAN Control
2SC4672 MMBT2222
jump 1 Css VBOOT 16 R300 R301 Q21
R57 30K
CTL1 10K 1K
SSS8050(TO92)
Q10 C64 2 FMAX MVPP 15
R75 NC R76 10uF/25V R71 10- D24 D121
NC 1.8K
3 CTMR HB 14
R69 1K D25
R58 15K 6.2B C262
4 RT NC. 13
R59 6.8K R70 R72 1N4148 1N4148 100/25V
C Q12 5 BO VCC 12 R302
C
1K
10K
D26 D27 6 FB MLOW 11
Q5 10K
NC 7 DT GND 10 C62 R74
NC D23 GND
R60 R67 MMBT2907 3.3K
MMBT2907 8 FF SF 9
8.2K(1%) 3.6B IC3 683
3,14 C58 R61 SO16 10K -12V/0.32A
R62 R63 D21
4.7uF/50V
R66 AZ431
150K
R64 R216
10K C59 1.1K(1%) 5.1K 1N4148 D22
PFC OK
2K
VCC1 222 7.5B R73 C63 18K

VCC1
1N4744
L11
AZ431
Jump 1.1K 103
D110
C209-1 224(1812)
IC20
15 Q13 C143 Be core
Q14 D102 SR24E
R78 R79 220uF/25V
NC NC 10K 2SA1797 L9
IS12A/B
IS12V
L10
D28 R80 IC20 PGO PS_ON C230
3uH C200 C209 1.5uH
PS_ON
R269 330- 5VSB
PGO
10K 11 D100 224(1812) D101 C142
NC +5Vsb NC. SR24E 330uF/25V
R206
10 C201 NC.
220uF/25V ES1D C204
817 IS12A IS12B
HV+ IS12B VS12B VS12BVS12A VS12A 104 Q32
+5Vsb IS12A P5-6 P5-5 R212 10- VS5
HV+ P4-1 P4-1 P4-3 P4-2
VCC1
+5Vsb C202 100P NTD4809N IS5 IS5 VS5
IC18 10t RS5-1
D29 PGI P5-2 N2
Vcc 5
1 BST 2 TG 75K
R258 200-
DPAK NC.
R257100-
R259 47-
R260 47-
IS5 IS33 VS33 VS5
R202 C203 D112 4148 +5V
R81 IC21 817 R253 RS5
R261 47-
4148 +5Vsb IS5 IS33 R263 C251
R89 8 R250 Q16 1K Comp. Phase 8
499K(1%) R252 470- 2K 1K L7 6.8uH C216 NC.
3 Gnd
4.7K 1K 474 563 Q33
R82 R85 R87 22K 9 R255 R256 R262 RS5
R86
470- 240- 47-
6 FB 4 BG
R21310- 104
499K(1%) 470K C220 NCP1587 NTD4809N 1uH
10K C250104
12 R84 IC5 IC5 MMBT2222 Q17 2200uF/16V R203 +5V/9.44A
R88100- 4148 DPAK
MMBT2222
1K D113 C206 330uF/10V C208 47.2W

LM393(1/2) C252 27K R205
R83 104 C207
PPTC(NSMD100)
R251 R204 NC. 2200uF/10V Add
6.8K(1%) C65 C66 IC4 4.7k 5.11K C205 2200uF/10V
LM393(1/2)
104 105 C253104 NC.
AZ431 C67
SOT23 105
C254 TM1
104
T10K
OPT.
C255 C258 12
IC17 GND
GND D103 ES1D
VS12A C210A
B
C256 104 104 8
VS12B OTP
9 R264 220uF/25V
C210 NC. C213 Q34 +5V/+3.3V Max.80W B
TO D-D 104 14 2.2K C232
IS12A/B VS5 104 R21410-
FPBO 13 2 C261
IS12A/B VS33 GND C211 100P NTD4809N NC. IS33 VS33
R265 IC19 L8 6.8uH
C257104 104 1K IS33 VS33
Vcc 5
7 6 1 BST 2 TG
P5-3 IS12B RI D1064148 DPAK
D105 R208 C212 Q35 L13 +3.3V
FPBO 5
IS12A PGO
16 RS33
Comp. Phase 8
11 1 1K 563 C217 0.002 3uH
3 Gnd
4148 IS33 PGI
10
IS5 PSONB
4 6 FB 4 BG R215 10-
D104 104
R254 15 3 NCP1587 NTD4809N
VCC FPOB
R209 +3.3V/5.03A
47- PS223 16.6W
4148 C259 C260 4148
104 R268 D107
R211 DPAK C215 C218 C219
10/50V 16K
62K R210 NC. 2200uF/10V
R267 R266 5.11K C214
2200uF/10V 2200uF/10V
1K 10K NC.
GND
DC-DC Stage (CTL2)

P5-1
HV-B+
HV-B+
P5-4
ACL T2
D122 EE25
ACL VCC1 10-(2W)C110 102
1N4006 D48 L5
R111
D51 D50 P1 +5Vsb/2.39A
ACN D123 UF4007 55t
ES1D P6KE200 DR6*8
ACN C105 VCC1 D52 MBR20L45CT
R99 220uF/25V R105
1N4006 R103 L=0.9mH
2.2M S1 C108 C109
0- 3.3K(1206) 5t 2200uF/10V 1000uF/10V D54
C103 C104 100- D49 1N4734A 1W
A 5.32-5.88V A
10uF/25V 100uF/35V GND
C100 R106 LL4148
P2
IC10
22uF400V R100 19t
1 VCC GND 8 IC12 R110100-
2.2M
817(1/2)
2 Ramp Comp. R108

OPP 7 R150
10K(1%)
2008.12.10
3 Brown-Out
1K C107
4 FB Drain 5
NCP1027 684
R101 R102 C102 IC11 R109
C101
103
27K 78.7K IC12
817(1/2) 104
CY6
AZ431
10K(1%)
ON SEMICONDUCTOR.
Title
POWER SUPPLY ATX 255W >85%
222 Size Number Revision
A1 ON -Semi ATX255W V8
Date: 11-Dec-2008 Sheet of D
File: D:\WORK\layout\MAINSTAY_F.K.ddb Drawn By:
D70,D71,C133,C135,R4,R134,R135,R139
Figure 14: Schematics

7. Parts List
The bill of materials (BOM) for the design is provided in this section. To reflect the schematics shown
in the previous section, the BOM have also been broken into different sections and provided in
separate tables – Table 19 through 22.
It should be noted that a number of components used during the development cycle were based on
availability. As a result, further cost reductions and better inventory management can be achieved by
component standardization, i.e. the unique part numbers can be SIGNIFICANTLY reduced by
standardization and re-use of component values and case sizes. This will result in a lower cost BOM
and better inventory management.
QTY SYMBOL DESCRIPTION VENDOR VENDOR P/N

MAIN BOARD (PFC Stage, Synchronous Rectification Output Stage)
1 HS1 HEAT SINK 93*60*4 AL4.0t Taizhi
1 BD1 DIO.BRI 10A 600V / TS10P05G PANJIT
1 D2 DIO.NR LQA08TC600 8A 600V TO-220AC QSPEED
1 Q1 FET.NCH SPP15N60C3 TO220 INFINEON
2 Q3, Q4 FET.NCH STP12NM50 TO-220 ST
1 SCREW(BD1) SCREW PAN-HEAD M3*10 LONGFEI
4 SCREW(D2, Q1, Q3, Q4) SCREW PAN-HEAD M3*6 LONGFEI
4 SL(D2, Q1, Q3, Q4) SLTO-220 13*19*0.3mm JUNHO
4 B(D2, Q1, Q3, Q4) BUSHING TO-220 JUNHO
1 HS2 HEAT SINK 93*60*4 AL4.0t Taizhi
2 Q30, Q31 STP80NF55-06 80A55V TO220 ST
1 D52, MBR20L45CT 20A 45V TO-220 ON
2 D70, D71 MBR60L45CTG 60A 45V TO-220 ON
SCREW(D52, Q32, Q31,
5 SCREW PAN-HEAD M3*6 LONGFEI
Q70, Q71)
SL(Q30, Q31, D70, D71,
5 SLTO-220 13*19*0.3mm JUNHO
D52)
B(Q30, Q31, D70, D71,
5 BUSHING TO-220 JUNHO
D52)
1 R3 RES.WW. 0.1R 3WS NKNP Synton-Tech
1 R13 RES.MO. 10- 2W Synton-Tech
3 R130, R131, R111 RES.CR. 10- 2WS Synton-Tech
1 D48 P6KE200A DO-15 PANJIT
1 D50 UF4007 DO-41 PANJIT
1 D1 STTH310 3A 1000V / UF5407G DII
1 C109 CAP.ELE 1000uF 10V 10*16KY SU'SCON
1 R1 RES.CR. 1M 1/4W
3 RS12A, RS12A-1, RS12B COPPER 0.002-
1 F1 MST 5A/250V CONQUER
(ASC-2203V-
2 LF1.LF3 0.8*25t L=3mH+30% L=2.5mm MEIHUA
GH)25T
1 L2 POT3319 0.1Φ*50t*61t L=0.68uH MEIHUA
1 L3 T80-26+UL L=120uH±20% MEIHUA
1 L5 DR6*8 L=3.6uH MEIHUA
2 L6, L9 R8*20+UL L=0.8uH 2.4Φ*5.5t J.X.E. J-YH-R8*20-789
29
1 T1 YC3501 L=0.63mH Ls=80uH MEIHUA
1 T2 EE25 MEIHUA
1 MOV TVR10471KSY TKS
1 IC10 NCP1027P065G DIP-8 ON
4 IC23, IC12, IC20, IC21 PHOTO PC817B DIP-4P SHARP
1 D54 1N4734A 1W 5.32-5.88V
2 D122, D123 1N4006
1 C4-1 CAP.PEI 0.022uF 630V
1 C4 CAP.PEI 0.033uF 630V PAC R75PI2330JEMEJ
2 C1, C6 CAP.MEF 0.47uF 400V P=10 UTX
1 CX3 CAP.MPP 0.33uF 275vac p=15 UTX
1 CX2 CAP.MPP 0.47uf 275V HQX P=15 UTX
1 C100 CAP.ELE 22uF 450V 8*11 SU'SCON
1 C55 CAP.ELE 2.2uF 50V 5*11
1 C2 CAP.ELE 220uf 450V NDB
1 C56 CAP.ELE 47uF 25V 5*11 NDB
1 C105 CAP.ELE 220uF 25V 6.3*11 NDB
1 C103 CAP.ELE 10uF 50V 5*11 NDB
1 C104 CAP.ELE 100uF 35V 6*11 NDB
C136, C137, C138, C139,
5 CAP.ELE 2200uF 16V 10*25 KZE NDB
C140
1 C108 CAP.ELE 2200uF 10V 10*16 NDB
1 C110 CAP.CER 1000PF 1KV Y5P P=5 SEC 2Y5P102K102C56E
2 C130, C131 CAP.CER 560PF 1KV Y5P SEC
1 C146 CAP.ELE 220uF 16V 6.3*11
2 CY3, CY4 CAP.CER 4700PF Y2 SEC
1 CY6 CAP.CER 2200PF Y1 SEC
3 J4, J5, J6 JUMP 0.8Φ P=12.5mm
3 J7, J19, J22 JUMP 0.8Φ P=20mm
J1, J2, J3, J8, J11, J15,
8 JUMP 0.8Φ P=10mm
J18, J24
1 J23 JUMP 0.8Φ P=5mm
1 MB CONNECT MB CONNECT 24-PORT EVERBIZ
1 CPU CONNECT CPU CONNECT 4-PORT(2*2) EVERBIZ
3 P3, P4, P5 SATA+SATA CONNECT EVERBIZ
2 P6, P7 SATA CONNECT EVERBIZ
2 P8, P9 FDD CONNECT 4-PORT EVERBIZ
2 HS3, HS4 HEAT SINK 28*38*5 CU1.2t Taizhi
1 CON1 WAFER 3.96(3-1)PIN 180° SUNDA
J10, J12, J13, J14, J16, R9,
8 RES.SMD 0- 5% 0805
J20, R105
1 J9 RES.SMD 33- 5% 0805
1 J21 RES.SMD 0- 5% 1206
1 R3-1 RES.SMD 0.5- 1% 2512
5 R5, R10, R11, R133, R140 RES.SMD 10K 5% 0805
2 R7, R8 RES.SMD 1.8M 5% 0805
2 R12, R12A RES.SMD 24K 5% 0805
30
1 R54 RES.SMD 47K 1% 0805
1 R55 RES.SMD 82.5K 1% 0805
1 R56 RES.SMD 12K 5% 0805
1 R57 RES.SMD 23.2K 5% 0805
2 R51, R6 RES.SMD 3.3M 5% 0805
1 R52 RES.SMD 3.6K 1% 0805
2 R81, R82 RES.SMD 499K 1% 0805
1 R83 RES.SMD 6.8K 1% 0805
2 R99, R100 RES.SMD 2.2M 5% 0805
1 R101 RES.SMD 27K 5% 0805
1 R102 RES.SMD 78.7K 1% 0805
1 R103 RES.SMD 3.3K 5% 1206
R142, R147, R148, R250,
6 RES.SMD 1K 5% 0805
R253, R150
2 R108, R109 RES.SMD 10K 1% 0805
1 R110 RES.SMD 100- 5% 0805
2 R132, R141 RES.SMD 2.2- 5% 0805
1 R134 RES.SMD 6.2K 5% 0805
1 R135 RES.SMD 3.3K 5% 0805
2 R137, R138 RES.SMD 10- 5% 0805
1 R53 RES.SMD 10- 5% 1206
1 R143 RES.SMD 68K 5% 0805
1 R144 RES.SMD 18K 1% 0805
1 R145 RES.SMD 4.7K 1% 0805
2 R146, R149 RES.SMD 22- 5% 0805
1 R251 RES.SMD 4.7K 5% 0805
1 R252 RES.SMD 470- 5% 0805
1 R269 RES.SMD 330- 5% 0805
1 C5 CAP.MON 220P 50V 0805 X7R
1 C50 CAP.MON 0.47uF 50V X7R 0805
2 C101, C102 CAP.MON 0.01uF 50V X7R 0805
2 C107, C54 CAP.MON 0.22uF 50V X7R 0805
3 C53, C144, C145 CAP.MON 1000PF 50V X7R 0805
3 C134, C132, C52 CAP.MON 0.1uF 50V X7R 0805
1 C141 CAP.MON 0.022uF 50V X7R 0805
1 D51 ES1D 1A 200V SMA TSC
4 D5, D72, D73, D49 DIO.NR LL4148 TSC
2 D77, D78 DIO.ZEN RLZ7.5B ROHM
2 Q16, Q17 MMBT2222 SOT23
1 IC1 NCP1654A 65Khz SO-8 ON
2 IC11, IC16 TL431 ON
2 IC14, IC15 NCP4302 SO-8 ON
1 PCB CEM-1 1oz 1.6t 145*108.5 NO.SPB011V5
Table 19: Main Board (PFC Stage, Synchronous Rectification Output Stage)
31
DC-DC Converter Stage, Supervisory Stage (referred to as CTL2 in schematics of figure 14)
1 C220 CAP.ELE 2200uF 16V 10*25 NDB
1 L11 BEAD RH035100ST-A8
1 RS33 COPPER 0.002- Tzai Yuan
1 C208 CAP.ELE PSC 680uF 10V 10*11.5 NDB
C206, C207, C215, C218,
5 CAP.ELE 2200uF 16V 10*25 NDB
C219
1 C260 CAP.ELE 10uF 50V 5*11 KY NDB
1 C142 CAP.ELE 330uF 25V 8*15 KY NDB
1 C143, C200, C200A CAP.ELE 220uF 25V KY 6.3*11 NDB
1 C209 CAP.PEI 0.47uF 100V P=10 欣統
1 C262 CAP.ELE 100uF 25V 6.3*11 NDB
1 D110 1N4744
1 Q21 S8050L-C EBC TO92 UTC
1 L7 HKH080 L=6.8uH
1 L8 HKH080 L=6.8uH MEIHUA HKH-080CE/034
1 L9 DR6*8 L=3.6uH MEIHUA
2 L10, L13 R6*20+UL L=3.0uH±20% 1.2Φ*11.5t MEIHUA R6*20-0003
1 RS5 R8*20+UL L=1uH±20%
1 TM1 T10K TKS TTC05103KSY
1 TM2 T204K TKS TTC05204KSY
1 HS7 HEAT SINK 25.5*12.5 Cu1.2t Taizhi
2 HS8, HS9 HEAT SINK 40.5*12.5 Cu1.2t Taizhi
1 CON3 WAFER P=2.5*2 90° SUNDA
1 P4(CTL3-PCB) Pin Header 3pin 90° P=2.54mm SUNDA
1 P5(CTL3-PCB) Pin Header 6pin 90° P=2.54mm SUNDA
1 PPTC Fuse 1A 1206 CONQUER nSMD100
3 R266, R300, R302 RES.SMD 10K 5% 0805
1 R203 RES.SMD 27K 1% 0805
2 R204, R210 RES.SMD 5.11K 1% 0805
4 R212, R214, R213, R215 RES.SMD 10- 5% 0805
1 R206 RES.SMD 75K 5% 1206
1 R216 RES.SMD 18K 5% 1206
1 R209 RES.SMD 16K 1% 0805
R254, R259, R260, R261,
5 RES.SMD 47- 5% 0805
R262
1 R255 RES.SMD 470- 1% 0805
1 R256 RES.SMD 240- 1% 0805
1 R257 RES.SMD 100- 1% 0805
1 R258 RES.SMD 200- 1% 0805
1 R263 RES.SMD 2K 5% 0805
1 R264 RES.SMD 2.2K 5% 0805
R265, R267, R301, R202,
5 RES.SMD 1K 5% 0805
R208
1 R268 RES.SMD 62K 1% 0805
1 R303 RES.SMD 15- 5% 0805
2 C209, C209-1 CAP.MON 0.22uF 50V X7R 1812
C204, C213, C216, C217,
C250, C252, C253, C254,
14 CAP.MON 0.1uF 50V X7R 0805
C255, C256, C257, C258,
C259, C261
2 C202, C211 CAP.MON 100P 50V X7R 0805
2 C203, C212 CAP.MON 0.056uF 50V X7R 0805
32
1 C251 CAP.MON 0.47uF 16V X7R 0805
2 D100, D103 ES1D 1A 200V SMA TSC
2 D101, D102 DIO.SB SR24 2A 40V SMA PANJIT
D104, D105, D112, D113,
6 DIO.ZEN LL4148 TSC
D106, D107
2 D120, D121 DIO.ZEN RLZ6.2B ROHM
1 Q20 MMBT2222 SOT23
4 Q32, Q33, Q34, Q35 NTD4809N-D 58A 30V DPAK ON
1 IC17 PS223 SOP-16 SITI
2 IC18, IC19 NCP1587 SO-8 ON
1 IC20 TL431 ON
1 PCB FR4 1oz 1.6t 62*83.5 NO.PB011V5-CTL3
Table 20: DC-DC Converter Stage, Supervisory Stage (referred to as CTL2 in schematics of
figure 14)
33
P/N QTY SYMBOL DESCRIPTION VENDOR VENDOR P/N
HB Resonant LLC-Stage (referred to as CTL1 in schematics of figure 14 )
1 C58 CAP.ELE 4.7uF 50V KMG 5*11 NDB
1 C60 CAP.ELE 47/25V KMG 5*11 NDB
1 C64 CAP.ELE. 10uF 25V NDB
1 P2 (CTL2-PCB) Pin Header 3pin 90° P=2.54mm SUNDA
1 P3 (CTL2-PCB) Pin Header 13pin 90° P=2.54mm SUNDA
1 HS 25*16*8
1 PCB HOLD RCC-5 KANGYANG
4 R55, R69, R70, R84 RES.SMD 1K 5% 0805
2 R56, R57 RES.SMD 30K 5% 0805
1 R58 RES.SMD 15K 5% 0805
1 R59 RES.SMD 6.8K 5% 0805
1 R60 RES.SMD 8.2K 1% 0805
1 R61 RES.SMD 150K 5% 0805
1 R62 RES.SMD 2K 5% 0805
2 R64, R73 RES.SMD 1.1K 1% 0805
R63, R67, R72, R79, R80,
6 RES.SMD 10K 5% 0805
R86
1 R65 RES.SMD 18- 5% 1206
1 R66 RES.SMD 5.1K 5% 0805
2 R68, R71 RES.SMD 10- 5% 0805
1 R74 RES.SMD 3.3K 5% 0805
1 R76 RES.SMD 1.8K 5% 0805
1 R77 RES.SMD 33- 5% 0805
1 R88 RES.SMD 100- 5% 0805
1 R85 RES.SMD 470K 5% 0805
1 R87 RES.SMD 22K 5% 0805
1 R89 RES.SMD 4.7K 5% 0805
1 C59 CAP.MON 2200PF 50V X7R 0805
2 C61, C65 CAP.MON 0.1uF 50V X7R 0805
1 C62 CAP.MON 0.068uF 50V X7R 0805
1 C63 CAP.MON 0.01uF 50V X7R 0805
3 C66, C67, C57 CAP.MON 1uF 25V X7R 0805
1 D20 UF 1A600V / US1J PANJIT
4 D21, D24, D25, D29 DIO.ZEN. LL4148 TSC
1 D22 DIO.ZEN. RLZ7.5B ROHM
1 D23 DIO.ZEN. RLZ3.6B ROHM
2 Q5, Q12 MMBT2907 PANJIT
1 Q11 2SC4672 ROHM
1 Q14 2SA1797 ROHM
1 IC2 NCP1396A SO-16 ON
2 IC3, IC4 TL431 ON
1 IC5 LM393 SO-8 ON LM393D
1 PCB FR4 1oz 1.6t 44*56 NO.SPB011V4-CTL2
Table 21: HB Resonant LLC-Stage (referred to as CTL1 in schematics of figure 14)
34
Mechanical and Miscellaneous Items
1 SW1 0-1 4P 10A Look SW SWEETA SS21-BBIWG-R
1 SW-INLET UL1015#18 L=115mm CHARNG MIN
1 SW-INLET UL1015#16 L=60mm White CHARNG MIN
1 SW-INLET UL1015#16 L=60mm Black CHARNG MIN
1 INLET(G)-GND UL1015#18 L=125mm CHARNG MIN
1 CORE(INLET-GND) RH16*9*17
1 DTOD-BOARD
1 FAN 80*80*25mm 12V SUNON
2 CY1, CY2 CAP.CER 4700PF Y2 SEC
1 CX1 CAP.MPP 1uF 275VAC HQX P=22.5 UTX
1 AC INLET 10A/15A 250V SWEETA SC-9-1
1 CASE CASE 150.2*140*84mm
1 CASE CASE 140*148.2*85.5mm
1 MYLAR MYLAR FILM 165*110*0.35mm JUNHO
2 SCREW(AC INLET) SCREW F3*10 ISO(BLACK) LONGFEI
4 SCREW(CASE) SCREW F3*6 ISO(BLACK) LONGFEI
1 SCREW(INLET-GND)) SCREW F3*5 ISO(BLACK) LONGFEI
4 SCREW(S1~S4) SCREW MAIN BOARD M3*4 ISO LONGFEI
4 SCREW(FAN) SCREW I5*10 TAP (BLACK) LONGFEI
1 SCREW(GND) SCREW K/NUT 8#32T LONGFEI
1 FAN GUARD 80*80mm COLOR-GOLD PRO-CROWN
1 SANP BUSHING NB-27A KANGYANG
Table 22: Mechanical and Miscellaneous Items
35
8. Resources/Contact Information
Data sheets, applications information and samples for the ON Semiconductor components are
available at www.onsemi.com. Links to the datasheets of the main components used in this design are
included in the Appendix.
Authors of this document are: Edward Weng, Patrick Wang, Roman Stuler, and Laurent Jenck.
9. Appendix
Link to ON Semiconductor’s web site:
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Additional collateral from ON Semiconductor:

NCP1654 Continuous conduction mode PFC NCP1027 High voltage integrated switcher
controller NTD4809 Single N-Channel MOSFET 30 V, 58 A
NCP1396 Resonant mode controller with high MBR20L45 20 A, 45 V dual schottky rectifier
voltage drivers
NCP4302 Synchronous rectification controller
NCP1587 Low voltage synchronous buck
controller
36
AND8311/D
Understanding the LLC

Structure in Resonant
Applications
Prepared By: Christophe Basso http://onsemi.com
ON Semiconductor
The resonant LLC topology, member of the Series understand the resonant structure alone, object of the present
Resonant Converters (SRC) begins to be widely used in application note.
consumer applications such as LCD TVs or plasma display
panels. In these applications, a high level of safety and The LLC converter
reliability is required to avoid catastrophic failures once The LLC converter implies the series association of two
products are shipped and operated in the consumer field. To inductors (LL) and one capacitor (C). Figure 1 shows a
face these new challenges, ON Semiconductor has recently simplified representation of the resonant circuit where:
released to new controllers, the NCP1395 (low-voltage) and Ls is the series inductor
the NCP1396 (high-voltage) dedicated to driving resonant Lm is the magnetizing inductor
power supplies, usually of LLC type. However, before Cs represents the series capacitor
rushing to design a converter of this type, it is important to
ÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏ Vbulk
ÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ
Vbulk
ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏ
0
QA
HB
N:1 D1
Vout
ÎÎÎÎÎÎÎÎÎÎ QB +
Lm
Rload
Cout
ÎÎÎÎÎÎÎÎÎ
CS D2
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Figure 1. The LLC Topology Uses a Half-Bridge Configuration to Drive the Resonant Circuit
© Semiconductor Components Industries, LLC, 2008 1 Publication Order Number:

January, 2008 - Rev. 0 AND8311/D
AND8311/D
The operating principle is rather simple: a constant 50% associated with leaky transformers (radiated noise) has to be
duty-cycle switching pattern drives QA - QB gates and a kept in mind when selecting the final configuration.
high-voltage square wave appears on node HB. By When studying the resonant converter, it is convenient to
adjusting the switching frequency, the controller can control reduce the architecture to a passive element arrangement
the power flow depending on the output demand. As a such as presented on Figure 2. The high-voltage square
transformer is needed for isolation purposes, its magnetizing signal is replaced by its fundamental content thanks to the
inductance plays the role of the second inductor Lm. The first harmonic approximation (the so-called FHA in the
series inductor, Ls, can either be a separated element or literature): because we operate a tuned LC filter, all
physically lump into the transformer. In this case, a harmonics can be considered as rejected and only the
voluntary degradation of both primary and secondary fundamental passes through. Of course, this statement holds
coupling naturally increases the leakage inductance which as long the controller drives the resonating work in the
can act as the series element. There are pros and cons to vicinity of its resonant frequency. Figure 2 offers such a
include the leakage element in the transformer. The cost and simplified representation of the resonant cell, actually
the absence of saturation play in favor of the integration but pointing out a series impedance (Ls and Cs) with a parallel
the difficulty to keep a precise value from lots to lots impedance (Lm and the reflected load).
Figure 2. The Impedance Representation Makes the LCC Operation Easier to Understand
Depending on the loading, the network resonant frequency • RL = ∞, light or no load condition, Lm appears in series
varies between two different values: with Ls and the whole network resonates to
• RL = 0, short-circuit, Lm disappears and Zseries 1
becomes a short. The series resonant point for Zseries is F min +
thus 2p ǸǒLS ) LmǓCS (eq. 2)
F max + F S +
1 • 0 < RL < ∞, the resonance which combines Lm and Ls ,
(eq. 1)
2p ǸL SC S shifts depending on the total quality coefficient.
At Fsw = FS, Zseries becomes a short and the ac transfer

function drops to 1 or 0 dB.
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AND8311/D
Lm = 600 mH
24.0 LS = 100 mH
Vout = 24 V Pout = 10 W, Q = 60
CS = 33 nF
N=8
Pout = 50 W, Q = 13
12.0
Pout = 100 W, Q = 6.7
V out(s)
20log 10 dB Pout = 200 W, Q = 3
V in(s)
0
Pout = 300 W, Q = 2
-12.0
-24.0
10k 20k FREQUENCY (Hz) 50k 200k

1 1
F min + F max + F S
2p ǸL S ) Lm)CS 2p ǸLSC S
Figure 3. The AC Response of Figure 2 Circuit with Various Load Conditions
This is actually what Figure 3 plots suggest by showing the ac transfer function of Figure 2 as the load changes.
If we now study the impedance seen from the half-bridge node, we have an expression showing a series association of
inductors and a capacitor. Sticking to Figure 2 sketch and writing the impedance seen between ground and Node 3, we have:
Z in + Z L ) Z C ) Z L ŦR ac (eq. 3)
S S in
ƪ Ǔƫ
2
ǒ
4 2
(wL m) R ac 2 1 R ac2
Z in + ) wL S * ) wL m (eq. 4)
ǒR ac
2 wC S R ac 2 ) w2L m 2
2 ) w 2L m Ǔ
2
In the low frequency portion, the terms associated with inductors are of less importance and Cs dominates. The impedance
is thus capacitive. As the frequency increases, the inductive portion starts to kick-in and the impedance goes up. This is what
Figure 4 describes. As one can see, all the curves go through point A whose value is independent from the resistive loading.
For the sake of a friendly exercise, we can solve Equation 4 with two different Rac values and find the frequency at which input
impedances equal. We obtain:
wA + ǸL Cm S ) 2L SC S
2
(eq. 5)
If we substitute this value into Equation 4, the impedance at point A is:

Lm
2L
L Sw S
S
ZA +
Ǹ
(eq. 6)
Lm
)1
2L
S
If we define the ratio R by Lm/Ls, we can re-arrange equation 6:
ZA +
Ǹ2(R ) 2)
R
Ǹ LS
CS
+
R
Ǹ2(R ) 2)
ZO (eq. 7)
Where Z0 represents the characteristic impedance of the series resonant network. Using the numerical values noted in the
graphs, we obtain a frequency of 43.8 kHz and an impedance of 38.3 dBW (82.6 W).
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AND8311/D
5
1
2
3
4
62.0
Inductive Region
Capacitive Region Pout = 300 W, Q = 2

50.0
38.0
Pout = 100 W, Q = 6.7 A
Pout = 50 W, Q = 13
26.0 Pout = 200 W, Q = 3
Lm = 600 mH
dBW LS = 100 mH
Pout = 10 W, Q = 60 Vout = 24 V
14.0
CS = 33 nF
N=8
10k 20k FREQUENCY (Hz) 50k 200k

1
F min
2p ǸL S ) L in)C S
Figure 4. Impedance Plots at Various Power Levels
If we now observe the resonant current waveforms in a LLC body diode turns on first. Observing figure 3, the output
converter working below or above the series resonance Fs , level goes down as the frequency increases.
we have different types of operation: Most of the LLC converters operate in the inductive region
• Capacitive mode: in this mode, where the current leads for the second bullet reason. Also, given the feedback
the voltage, the bridge MOSFETs operate in zero polarity, if by mistake the closed-loop LLC enters the left
current switching (ZCS). ZCS means that power side of the resonance, the control law reverses and a power
MOSFETs are turned-off at zero current. Back to figure runaway obviously occurs. It is thus extremely important to
3, we can see that the output level goes up as the clamp down the lower frequency excursion in fault
frequency increases. condition or during the startup sequence to avoid falling on
• Inductive mode: in this mode, the current lags the the other slope of the characteristics.
voltage and the power switches are turned-on at zero The inductive region can be split into two other regions,
volt (ZVS), virtually eliminating all capacitive losses. depending where you operate compared to the resonant
This operating way implies that a certain delay exists series frequency Fs, as defined by Equation 1. Figure 5
before operating the concerned MOSFET so that its represents the classical set of curves often found in the
dedicated literature:
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AND8311/D
Region 2
4.00
Q = 10
Region 1
3.00
Q=5
2.00
Q=2
Q=1
1.00
1
2
3
4
5
0
Q = 0.5
Region 3
200m 600m 1.00 1.40 1.80

Vf/FS (V)
F sw < F s F sw = F s F sw > F s
Figure 5. Typical Transmittance Curves with Various Loading Conditions, Highlighting Three Distinct Regions
Region 3 is the capacitive mode where you do not want to 1 1

F max + F S + +
2p ǸL SC S Ǹ116m
operate since ZVS is a wanted feature for the power 6.28 28n
switches. In regions 1 and 2, you still have ZVS on the power
MOSFET's and the output diodes are operated in Zero + 88.3kHz
Current Switching (ZCS), cancelling all associated losses at 1
F min +
2p Ǹ(L S ) L m)C S
turn-off. Before discussing the benefits of a particular
solution, let us have a look at the various operating phases
the LLC converter is made of. 1
+ + 33kHz
6.28 Ǹ(116m ) 700m) 28n
Operating Waveforms Below the Series Resonance,
Fsw < Fs Fsw = 70 kHz at full load and nominal input voltage.
For this example, we have selected a set of elements which The converter delivers 24 V@10 A from a 380 Vdc input
operate the converter below the series resonance defined by source and a simulation has been performed using the above
Equation 1. The following value have been used: values. Figure 6 shows the main waveforms obtained from
Lm = 700 mH the simulator. Let us study the switching events step by step
Ls = 116 mH to learn about the LLC behavior in this region.
Cs = 28 nF
N=8
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5
AND8311/D
14.0
V V
GS,lower GS,upper
vgsl, vgsu in volts

10.0 23
Q is on Q is off
plot1
6.00 B B
Q is off DT Q is on
A A
2.00 Gate voltages
22
-2.00
V
4.00 400 HB
Resonant currents
ils, ilmag in amperes
vbridge in volts
2.00 300
I
mag
plot2
0 200
25
26
-2.00 100
I
L
-4.00 0 I =I 24
L mag
30.0
id(d3a), idiode in amperes
I
d,peak
20.0 I I
d2 d1
I
plot3
out
10.0
28
0 27
-10.0 Diode current

478u 482u 486u 490u 494u
time in seconds
Figure 6. Waveforms Obtained for a Converter Operated Below the Series Resonant Frequency
QA is off, QB is on, D2 is conducting : resonates to Fs as Lm is shorted. Figure 7 depicts the

The low-side MOSFET QB imposes a 0 V potential on the situation during this period of time.
half-bridge node and the current circulates from its drain to
source (first quadrant). The upper parasitic capacitor CossA QA is off, QB is on, D2 turns off:
is fully charged to the input voltage Vbulk since the HB node As the network current IL resonates in a sinusoidal
is grounded by QB. The secondary diode D2 is conducting manner, its amplitude peaks and then starts to dip towards 0.
and imposes a voltage reflection -NVout over the When it reaches a level equal to that of the magnetizing
magnetizing inductor Lm. Its current linearly decreases with current, no current circulates in the transformer anymore: D2
a slope of -NVout/Lin. As this inductor is dynamically blocks and the voltage reflection over Lm disappears. The
shorted by the voltage reflection, it does not participate to magnetizing inductor now comes back in series with Ls and
the on-going resonance between Ls and Cs which deliver the Cs and changes the resonant frequency from Fs to Fmin: the
output energy (the input source is out of the picture). The LLC converter is really a multi-resonant structure and the
current flowing into the transformer primary side (given its plateau - actually a small arch of a lower sinewave
theoretical representation, Lm associated to a perfect oscillation - in the current as it appears on figure 6 testifies
transformer) is the main current IL minus the magnetizing for it. Both diodes are now blocked and this moment lasts
current Imag. D1 is blocked and undergoes twice the output until QB opens. Figure 8 represents the circuit during this
voltage given the transformer coupling. The circuit time. As one can see, the output capacitor alone supplies the
energy to the load.
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AND8311/D
Vbulk Vbulk
QA Vbulk QA
CossA CossA
LS IL-Imag LS IL-Imag
Iout Vout Vout
N:1 D1 N:1 D1
Imag Iout Imag

VLm Vout VLm
IL IL
Lm + Lm +
QB QB
Vout
Imag
Imag
IL-Imag D2 Iout IL-Imag D2
IL CS IL CS
IL
IL IL
Figure 7. QA is Off, QB is On and Diode D2 Conducts Figure 8. QA is Off, QB is On and Diode D2 Blocked.
Current. Lm is Off the Picture as it is Dynamically Lm Comes Back Again in the Resonating Network
Shorted by the Output Voltage Reflection. and Changes the Resonant Frequency to Fmin.
QA is off, QB is Off, Both Secondary Diodes are reversing (Figure 9). At this moment, when the HB node
Blocked reaches Vbulk + Vf, the body-diode of QA conducts and
Both transistors are now open, this is the dead-time period ensures energy re-cycling through the input source
(DT on Figure 6). The dead-time is placed here to avoid (Figure 10). You understand that this dead-time period must
cross-conduction between both MOSFETs but also to favor last a time long enough to allow for the complete discharge
Zero Voltage Switching as we will see in a moment. Because of CossA before re-activating QA so that its body-diode
the current was circulating from drain to source in QB, the turns on first. If not, hard switching occurs and efficiency
circuit no longer sees an ohmic path when this transistor suffers.
opens. The current strives to find a way through the parasitic As currents are oscillating, a time is reached where IL and
drain-source capacitors Coss of both QA and QB: CossB starts Imag are no longer equal (end of the plateau) and a current
to charge (it was previously discharged by QB being on) and circulates again in the primary side. D1 starts to conduct and
given the rise of VHB towards the high voltage rail, CossA NVout appears across Lm :the resonant frequency goes back
sees its terminals voltage going down to zero and then from Fs to Fmin. Figure 10 describes this moment.
Vbulk Vbulk
The Voltage is Falling
CossA
QA Reaches (Vin + Vf) when
The Voltage is Rising
QA Body-Diode Conducts
Iout Vout QA Vout
LS N:1 D1 LS N:1 D1
Vf
IL IL
Imag VLm Imag VLm
Lm + Lm +
QB
CossB QB
CossB
Imag Imag
IL-Imag D2 D2
CS CS
IL IL
Figure 9. QA is Off, QB is Off. The Current Finds a Figure 10. QA and QB are Still Off. The Current Finds
Circulating Path Through Both Transistors Coss, a Circulating Path through the Upper-side Body
Both Secondary-Side Diodes are Off. Diode. D1 Starts Conducting at the End of the
Plateau when IL 0 Imag.
QA is on, QB is off, D1 is on can therefore safely turn it on and benefit from Zero Voltage
Now that QA body-diode is conducting, we have a Conditions. As we have a sinusoidal waveform in the
negligible voltage across its drain and source terminals: we network, the resonating current reaches zero and reverses.
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AND8311/D
Lm is still dynamically shorted as D1 is conducting. The Figure 6. At this point, no current circulates in the
energy is delivered by the source to the output load. This is transformer and D1 naturally blocks. As explained before,
illustrated by Figure 11. the magnetizing inductor re-appears in the circuit since the
output voltage reflection is gone. The resonant frequency
QA is on, QB is off, D1 turns off changes from Fmin to Fs and the energy to the load is
The current IL is moving down and reaches the delivered by the output capacitor alone. Figure 12 shows the
magnetizing current level, we are the second plateau on circuit state during this event.
Vbulk Vbulk
QA QA
+ IL-Imag N:1 Vout + Vout
D1 LS N:1
LS
IL IL
Imag Imag
VLm Vout VLm
Lm + Lm +
QB
CossB Vout
QB
CossB
Imag Imag
IL-Imag
D2
CS CS
IL IL
Figure 11. The Current is Now Flowing from the Figure 12. As Both Diodes are Off, the Network
Source to the Output Via the Upper-Side Includes the Magnetizing Inductance which
Transistor QA. Changes the Resonant Frequency.
QA is of, QB is off, both secondary diodes are blocked towards ground. The drain falls down in a resonating
At a certain time, both transistors block and only their manner, involving both Coss in parallel and the equivalent
drain-source capacitors remain in the circuit. The current inductor made of Ls + Lm. Figure 13 represents the circuit
keeps circulating in the same direction but CossA starts to during this event.
charge: the voltage on the HB node drops and CossB depletes
Vbulk Vbulk
CossA CossA
QA QA
The Voltage is Falling
+ Vout + Vout
LS N:1 D1 LS N:1 D1
IL IL
Imag VLm Imag VLm
Lm + Lm +
QB
CossB QB
Imag Imag
D2 D2
CS CS
IL IL
Figure 13. The Current is Still Flowing through the Figure 14. When the Voltage on the Node HB
Source and Contributes to Discharge CossB. Swings Below Ground, QB Body-Diode Conducts.
The bridge voltage further dips and becomes negative is not playing any role here. The controller now activates QB
until the body-diode of QB conducts. This is what Figure 14 in ZVS and the transistor conducts in its 3rd quadrant for a
suggests. At the end of the plateau, where IL = Imag, D2 will few moments, until the current reaches zero and swings
start conducting, reflecting -NVout over the primary negative: we are back at the beginning of the first phase.
inductance. The energy comes from Cs and Ls, as the source
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AND8311/D
Zero Voltage Switching

Figure 15 zooms on these ZVS events and show the turns-on at a Vf across its drain-source terminals but the
various signals in play. The MOSFET current starts to be current is still negative: we are in the 3rd quadrant
negative before the appearance of its gate-source bias: this conduction. Finally, the current becomes positive and flows
is the body-diode conduction period. Then the MOSFET from drain to source, back to the 1st quadrant.
400 V GS,lower 8
V HB
200
Vbridge (V)
I D,lower
0 6
2
Body 1st
-200
diode quadrant
3rd
-400 Q B quadrant
7
400 V GS,upper
9
V HB
200 I D,upper
Vbridge (V)
Body -200 1st

Diode quadrant
-400 3rd
Q A
quadrant
485u 488u 491u 494u 497u
TIME (s)
Figure 15. Simulation Results Zooming on the MOSFET Variables
ZVS A
V bridge
V gsB
V gsA
I L(t) ZVS B
Figure 16. Measured Signals on a Demonstration Board Showing the ZVS Operation on QA.
The selection of a controller where the dead-time is Zero Current Switching

adjustable therefore represents an important selection By the term ZCS, we assume a natural blocking event
argument to fine tune the behavior and ensure a minimum when the current in the semiconductor is zero. When
conduction period of both body-diodes. operating the LLC converter below Fs, as it is the case in this
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AND8311/D
example, both secondary-side diodes are operated in ZCS. resonating current IL. This is the plateau on figure 6.
The current in the concerned diode (D1 or D2) naturally Observing the diode current in this particular mode gives
reaches 0 when the magnetizing current Imag equals the main smooth signals as shown on Figure 17.
I
d
48.0 22.0 4.00
I -I
L mag
Diode blocks
24.0 11.0 2.00
here as I =0
d
idiodein amperes
iprim in amperes
vdiodein volts
Plot1
0 0 0 12
10
Both diodes
are blocked.
11
-24.0 -11.0 -2.00
The other diode
conducts, V = -2 V
-48.0 -22.0 -4.00 R out
484u 487u 490u 493u 495u

TIME (s)
Figure 17. The Secondary-Side Diodes are Naturally Blocked When the Primary Current Vanishes to Zero
Startup sequence and short-circuit differentiating the voltage across the capacitor Cs and
During startup or short-circuit, the magnetizing inductor routing the resulting voltage to a fast latch input. Figure 19
is shorted and the resonant frequency becomes Fs. Because shows this solution where the component values must be
we designed the LLC converter to operate at a frequency adjusted to avoid false triggering in normal operating
lower than Fs, the operating fault mode (lack of feedback) of transients.
the controller naturally lies below Fs. In other words, if the Reference [1] has experimented a solution where the
LLC converter quickly starts-up, without soft-start at all, resonating capacitor is split in two values - Cs/2 - and two
the controller will quickly sweep from a high frequency high voltage diodes clamp the voltage excursion between
value down to the minimum authorized in case of fault. The ground and the bulk rail. As the voltage across the capacitor
current in the network can therefore peak to a high value (at is limited, the resonant current is also clamped. The solution
resonance, the LC impedance is only limited by ohmic appears in Figure 20. There are several drawbacks
losses) and destroy the power MOSFETs instantaneously. associated to the usage of this diode arrangement such as a
Figure 18a shows an oscilloscope shot captured on a LLC variable clamping level in relationship to the high-voltage
circuit started with a short soft-start period (≈20 ms): the rail. However, experience shows that this simple circuit
current peaks to 6 A. Increasing the soft-start period to a few brings an efficient protection to the converter experiencing
hundred of milliseconds clearly helps to smooth the peak a short-circuit. The diodes must be of fast types, MUR260
and keep it below 4 A. can be selected for this purpose.
Short-circuit protection is more difficult to achieve given
the resonating nature of the circuit. Some solutions exist like
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AND8311/D
Imax = 6.2 A
Imax = 3.8 A
Css = 1 μF IL(t) Css = 10 μF IL(t)
a b
Figure 18. The LLC converter peaks to a high current if started too quickly. Increasing the soft-start sequence
naturally calms down the current excursion.
Vbulk
QA
LS N:1 D1
Vout
QB Lm
+
Rload
R15 C8 Cout
10k 100p D2
To Latch
Open
C4 R16 D2 R14 CS
10n 1k 1N4937 10k
Figure 19. Differentiating the Voltage Across the Resonant Capacitor Gives an Indication of the Current Flowing
Through it
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AND8311/D
Vbulk
QA
CS/2
LS N:1 D1
Vout
QB Lm
+
Rload
Cout
D2
CS/2
Figure 20. To Keep the Voltage Excursion on the Resonant Capacitor within Safe Limits, a Diode Network Forbids
any Lethal Runaways
Operating Waveforms Above the Series Resonance, secondary diode is always conducting. In other
Fsw > Fs words, a single resonance occurs in this mode at
For this example, we have selected a set of elements which full power, implying Ls and Cs only. Lm is out of
operate the converter above the series resonance defined by the picture as long as the converter operates in
equation 1. The following values have been used: continuous conduction mode (full load operation).
Lm = 1.2 mH 2. Observing Figure 21, we can see that the main
Ls = 200 mH resonant current IL changes from a sinusoidal
Cs = 44 nF waveshape to a straight line, implying a change in
N=6 the operating mode. This change occurs when a
1 1 voltage discontinuity appears across Ls terminals.
F max + F S + + This discontinuity comes from the delay between
2p ǸL SC S 6.28 Ǹ200m 44n the bridge signal VHB and the reflected voltage
+ 53.7kHz polarity across the magnetizing inductor Lm.
Figure 22 zooms on this particular moment where
1
F min + we can see that the bridge voltage goes down to
2p Ǹ(L S ) L m)C S zero via the body-diode activation of QB, but
1 because there is still current flowing in the
+ + 20kHz
6.28 Ǹ(200m ) 1.2m) 44n
transformer primary side (IL is different than Imag),
one of the secondary diode is still conducting,
Fsw = 70 kHz at full load and nominal input voltage. imposing a constant reflected output voltage
The converter still delivers 24 V@10 A from a 380 Vdc across Lm. The voltage across Ls is up by one step
input source and a simulation has been conducted using the which starts to reset it towards zero. This is the
above values. Figure 21 shows the main waveforms beginning of the linear segment, if we consider the
obtained from the simulator. There are several differences voltage across Ls almost constant. When IL
between this operating mode and the previous one: reaches the magnetizing current Imag, the
1. In the previous mode, the magnetizing inductance conducting diode blocks and the primary current
was released at a point where both secondary-side transitions to the second diode which now
diodes were blocked (IL = Imag). The resonant conducts. The voltage polarity across Lm reverses
frequency was therefore moved from Fs to Fmin and the resonant current goes back to its sinusoidal
during a certain time (the plateau on Figure 6). shape. The next segment occurs when QB opens
When operated above the series frequency Fs, the and the bridge voltage jumps to Vin via QA
magnetizing inductance is always shorted by the body-diode. This segment lasts until IL reaches
reflected voltage NVout or -NVout as one of the Imag again.
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AND8311/D
14.0 V GS,lower V GS,upper
vgsl,vgsuin volts
10.0 5
Q B is off
Plot1
Q B is on
6.00
DT
Q A is off Q A is on
2.00
6
-2.00 Gate voltages
4.00 400
ils,i(lmag)in amperes
Resonant currents
vbridge in volts
2.00 300 V HB
I mag
Plot2
0 200 9
-2.00 100 IL
8
-4.00 0 7
id(d3a),id(d3b)in amperes
35.0
Diode current
25.0 I d,peak
I d2 I d1
11
Plot3
15.0 I out
5.00
10
-5.00
473u 477u 481u 485u 490u

time in seconds
Figure 21. Figure 6 Waveforms Updated with a Converter now Operating Above the Series-Resonant Frequency
Fs
8.00 200 400 VL mag 15

vbridge in volts
ils in amperes
vprim in volts
4.00 100 300 ZVS

14
Plot2
0 0 200
IL s
-4.00 -100 100
V HB 19
0 S [( V
Lmag+ VC s ) L s
-8.00 -200
ZVS S [ ( V L + V bulk) L s
mag
14.0
vgsl,vgsuin volts
17
10.0
V GS,upper V GS,lower V GS,upper
Plot1
6.00
2.00
16
-2.00
800 + VC s
vls,vcapresoin volts
VL
mag
400 VC s
Plot3
0 21
7
-400 VL s
VL + V in
mag
-800
484u 487u 490u 494u 497u

time in seconds
Figure 22. The Voltage Discontinuity Across Ls Induces a Linear Segment in the Resonant Waveform
1. The diode are still operated in ZCS despite a (the segment on IL(t)) which smoothly leads the
switching frequency above Fs. This is thanks to the concerned diode to a blocking state. Figure 23
linear reset taking place on the resonant current illustrates this fact.
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13
AND8311/D
I
d
4.00 20.0 40.0
I -I
L mag
2.00 10.0 20.0
S [ (V L + VC s) L s 2
mag
idiodein amperes
iprimin amperes
vdiodein volts
Plot1
0 0 0 1
-2.00 -10.0 -20.0
-4.00 -20.0 -40.0 The other diode
conducts, V = -2 V
R out
3
481u 484u 487u 490u 493u
time in seconds
Figure 23. A Zoom on the Switching Diodes Reveal a ZCS Operation for Fsw greater than Fs
Operating Waveforms at the Series Resonance, Fsw = 1

F min +
2p Ǹ(L S ) L m)C S
Fs
For this final example, we have selected a set of elements
which operate the converter at the series resonance defined 1
+ + 28.2kHz
by Equation 1. The following values have been used: 6.28 Ǹ(277m ) 1.6m) 44n
Lm = 1.6 mH
Fsw = 73 kHz at full load and nominal input voltage.
Ls = 277 mH
When operated at the tank resonant frequency, the main
Cs = 17 nF
current IL(t) is sinusoidal as confirmed by Figure 24.
N=8
1 1
F max + F S + +
2p ǸL SC S 6.28 Ǹ277m 17n
+ 73.4kHz
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14
AND8311/D
16.0
Gate voltages
vgsu, vgsl in volts

12.0
V V 15
plot3
GS,upper GS,lower
8.00
Q is off Q is on
B B
4.00 DT
Q is on Q is off
A A
0 14
400 4.00
16
ils, i(lmag) in amperes
vbridge in volts
300 2.00
I
mag 17
plot1
200 0 20
I
100 -2.00 L I =I
I =I L mag
L mag V
HB
0 -4.00 Resonant currents
id(d3a), id(d3b) in amperes
20.0 I
d,peak
I I
d1 d2
10.0
I
plot2
out 19
0 18
-10.0
-20.0 Diode current

677u 681u 685u 688u 692u
time in seconds
Figure 24. At the Resonant Frequency, the Main Current is Sinusoidal. Also, There is no Deadtime Between the
Secondary-Side Diode Conduction Periods.
In this mode, the EMI signature is excellent as the 2I d.peak

I dc + (eq. 9)
distortion is least compared to the other modes. The p
secondary-side currents are at the boundary between the
segment-like shape and the dead-time period, as We can then evaluate the ac current flowing into the output
respectively observed for Fsw > Fs and Fsw < Fs. As we capacitor applying the following equation:
observed before, the diode block when the resonant current
equal the magnetizing current Imag. I Cou.RMS + ǸI2RMS * I2dc + Ǹ I2
peak
2
*
4I 2
d.peak
p2
(eq. 10)
[ 0.3I d.peak
Operating the LLC at the series resonant frequency offers
another advantage. Back to Figure 3, we can see a point In the simulated example, if we have a diode peak current of
where all curves cross. This point, for which Vout/Vin = 1, is 15.7 A at steady-state, the RMS current flowing in the
reached at the series resonance. When operated at this capacitor is therefore 4.7 A. If we simulate a similar
particular position, the LLC resonant network transfer converter in a 100 kHz 2-switch forward configuration, the
function becomes insensitive to load variations. This RMS current in the output capacitor reduces down to 0.5
characteristics is sometimes exploited when a LLC Arms. That is one of the major disadvantage of the resonant
converter is designed to operate at a fixed switching operation. The switching losses are almost removed,
frequency locked to Fs and the feedback loop drives the allowing high-frequency operation, but conduction losses
output voltage of a pre-converter. increase significantly.
The RMS current in the output capacitor is also at its
lowest value as no discontinuity, or deadtime, exists as Conclusion
shown on figure 6 for Fsw < Fs. We can quickly derive its This quick study of the LLC converter explores the
value in presence of sinusoidal signals: various operating modes of the power supply, mainly
dictated by the switching frequency value in relationship to
I d.peak
I d.RMS + (eq. 8) the series resonant frequency Fs. Most of LLC designs are
Ǹ2 operated at the series resonance in full load and nominal
input voltage conditions. The controller allows operation
The total dc current contributed by both diodes in the output
below Fs during an input voltage drop and lets the frequency
current delivered by the converter. This dc current can be
exceed Fs in light load conditions. Despite sinusoidal
linked to the equivalent full-wave rectification and equals:
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15
AND8311/D
currents, care must be taken in the selection of the output 2. Bo Yang, “Topology Investigation for Front-End
capacitor given the high ac ripple. Compared to dc-dc Power Conversion for Distributed Power
buck-derived applications, this is the penalty to pay with System”, Virginia Tech Dissertation, 2003”
LLC converters, however, largely compensated by the http://scholar.lib.vt.edu/theses/available/etd-09152
reduction in switching losses on both the primary transistors 003-180228/unrestricted/
(ZVS) and the secondary-side diodes (ZCS).
References:
1. Bo Yang, Fred C. Lee, Matthew Concannon, Over
Current Protection Methods for LLC Resonant
Converter, IEEE Conference 2003
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16
Power Supply Design Seminar
Designing an LLC Resonant

Half-Bridge Power Converter
Topic Category:
Design Reviews – Functional Circuit Blocks
Reproduced from
2010 Texas Instruments Power Supply Design Seminar
SEM1900, Topic 3
TI Literature Number: SLUP263
© 2010, 2011 Texas Instruments Incorporated
Power Seminar topics and online power-

training modules are available at:
power.ti.com/seminars

Designing an LLC Resonant
Half-Bridge Power Converter
Hong Huang
AbstrAct
While half-bridge power stages have commonly been used for isolated, medium-power applications,
converters with high-voltage inputs are often designed with resonant switching to achieve higher efficiency,
an improvement that comes with added complexity but that nevertheless offers several performance
benefits. This topic provides detailed information on designing a resonant half-bridge converter that uses
two inductors (LL) and a capacitor (C), known as an LLC configuration. This topic also introduces a
unique analysis tool called first harmonic approximation (FHA) for controlling frequency modulation.
FHA is used to define circuit parameters and predict performance, which is then verified through
comprehensive laboratory measurements.
Topic 3
IntroductIon A. Brief Review of Resonant Converters
There are many resonant-converter topologies,
Higher efficiency, higher power density, and
and they all operate in essentially the same way: A
higher component density have become common
square pulse of voltage or current generated by the
in power-supply designs and their applications.
power switches is applied to a resonant circuit.
Resonant power converters—especially those with
Energy circulates in the resonant circuit, and some
an LLC half-bridge configuration—are receiving
or all of it is then tapped off to supply the output.
renewed interest because of this trend and the
More detailed descriptions and discussions can be
potential of these converters to achieve both higher
found in this topic’s references.
switching frequencies and lower switching losses.
Among resonant converters, two basic types
However, designing such converters presents many
are the series resonant converter (SRC), shown in
challenges, among them the fact that the LLC
Fig. 1a, and the parallel resonant converter (PRC),
resonant half-bridge converter performs power
shown in Fig. 1b. Both of these converters regulate
conversion with frequency modulation instead of
their output voltage by changing the frequency of
pulse-width modulation, requiring a different
the driving voltage such that the impedance of the
design approach.
resonant circuit changes. The input voltage is split
This topic presents a design procedure for the
between this impedance and the load. Since the
LLC resonant half-bridge converter, beginning
SRC works as a voltage divider between the input
with a brief review of basic resonant-converter
and the load, the DC gain of an SRC is always
operation and a description of the energy-transfer
function as an essential requirement for the design
process. This energy-transfer function, presented Lr Cr Lr
as a voltage ratio or voltage-gain function, is used

along with resonant-circuit parameters to describe
the relationship between input voltage and output RL Cr RL
voltage. Next, a method for determining parameter
values is explained. To demonstrate how a design
is created, a step-by-step example is then presented a. Series resonant b. Parallel resonant
for a converter with 300 W of output power, a 390- converter. converter.
VDC input, and a 12-VDC output. The topic
concludes with the results of bench-tested per- Fig. 1. Basic resonant-converter configurations.
formance measurements.
3-1
Texas Instruments 1 SLUP263
lower than 1. Under light-load conditions, the Lr Cr1 Lr Cr
impedance of the load is very large compared to
the impedance of the resonant circuit; so it becomes
difficult to regulate the output, since this requires
the frequency to approach infinity as the load
Cr2 RL Lm RL
approaches zero. Even at nominal loads, wide

frequency variation is required to regulate the
output when there is a large input-voltage range. a. LCC configuration. b. LLC configuration.
In the PRC shown in Fig. 1b, the load is Fig. 2. Two types of SPRC.
connected in parallel with the resonant circuit,
inevitability requiring large amounts of circulating
current. This makes it difficult to apply parallel inductance, Lr, and the transformer’s magnetizing
resonant topologies in applications with high inductance, Lm.
power density or large load variations. The LLC resonant converter has many addi-
tional benefits over conventional resonant con-
B. LCC and LLC Resonant Converters verters. For example, it can regulate the output
Topic 3
To solve these limitations, a converter over wide line and load variations with a relatively
combining the series and parallel configurations, small variation of switching frequency, while main-
called a series-parallel resonant converter (SPRC), taining excellent efficiency. It can also achieve zero-
has been proposed. One version of this structure voltage switching (ZVS) over the entire operating
uses one inductor and two capacitors, or an LCC range. Using the LLC resonant configuration in
configuration, as shown in Fig. 2a. Although this an isolated half-bridge topology will be described
combination overcomes the drawbacks of a simple next, followed by the procedure for designing
SRC or PRC by embedding more resonant fre- this topology.
quencies, it requires two independent physical
capacitors that are both large and expensive II. LLc resonAnt
because of the high AC currents. To get similar HALf-brIdge converter
characteristics without changing the physical com- This section describes a typical isolated LLC
ponent count, the SPRC can be altered to use two resonant half-bridge converter; its operation; its
inductors and one capacitor, forming an LLC reso- circuit modeling with simplifications; and the
nant converter (Fig. 2b). An advantage of the LLC relationship between the input and output voltages,
over the LCC topology is that the two physical called the voltage-gain function. This voltage-gain
inductors can often be integrated into one physical function forms the basis for the design procedure
component, including both the series resonant described in this topic.
Texas Instruments 3-2

2 SLUP263
Square-Wave Generator Resonant Circuit Rectifiers for
DC Output Cr Lr
Q1
D1
I m Ios
n:1:1 Vo
Ir
Cr Lr + +
Vin = + Io
Vsq
VDC –
Vsq Vso Lm R´L
+
Ir
Q2 Vso Lm Co RL
–
Vsq Vso
D2
a. Typical configuration. b. Simplified converter circuit.
Fig. 3. LLC resonant half-bridge converter.
A. Configuration together with the losses from the transformer

and output rectifiers.
Topic 3
Fig. 3a shows a typical topology of an LLC
resonant half-bridge converter. This circuit is very 3. On the converter’s secondary side, two diodes
similar to that in Fig. 2b. For convenience, Fig. 2b constitute a full-wave rectifier to convert AC
is copied as Fig. 3b with the series elements input to DC output and supply the load RL. The
interchanged, so that a side-by-side comparison output capacitor smooths the rectified voltage
with Fig. 3a can be made. The converter and current. The rectifier network can be
configuration in Fig. 3a has three main parts: implemented as a full-wave bridge or center-
1. Power switches Q1 and Q2, which are usually tapped configuration, with a capacitive output
MOSFETs, are configured to form a square- filter. The rectifiers can also be implemented
wave generator. This generator produces a with MOSFETs forming synchronous
unipolar square-wave voltage, Vsq, by driving rectification to reduce conduction losses,
switches Q1 and Q2, with alternating 50% especially beneficial in low-voltage and high-
duty cycles for each switch. A small dead time current applications.
is needed between the consecutive transitions,
both to prevent the possibility of cross- B. Operation
conduction and to allow time for ZVS to be This section provides a review of LLC
achieved. resonant-converter operation, starting with series
2. The resonant circuit, also called a resonant resonance.
network, consists of the resonant capacitance, Resonant Frequencies in an SRC
Cr, and two inductances—the series resonant Fundamentally, the resonant network of an
inductance, Lr, and the transformer’s magnet- SRC presents a minimum impedance to the
izing inductance, Lm. The transformer turns sinusoidal current at the resonant frequency,
ratio is n. The resonant network circulates the regardless of the frequency of the square-wave
electric current and, as a result, the energy is voltage applied at the input. This is sometimes
circulated and delivered to the load through the called the resonant circuit’s selective property.
transformer. The transformer’s primary wind- Away from resonance, the circuit presents higher
ing receives a bipolar square-wave voltage, impedance levels. The amount of current, or
Vso. This voltage is transferred to the secondary associated energy, to be circulated and delivered
side, with the transformer providing both to the load is then mainly dependent upon the
electrical isolation and the turns ratio to deliver value of the resonant circuit’s impedance at that
the required voltage level to the output. In Fig. frequency for a given load impedance. As the
3b, the load R′L includes the load RL of Fig. 3a frequency of the square-wave generator is varied,
3-3
the resonant circuit’s impedance varies to control It is apparent from Fig. 3b that f0 as described
that portion of energy delivered to the load. by Equation (1) is always true regardless of the
An SRC has only one resonance, the series load, but fp described by Equation (2) is true only
resonant frequency, denoted as at no load. Later it will be shown that most of the
time an LLC converter is designed to operate in
1
f0 = . (1) the vicinity of f0. For this reason and others yet to
2π L r C r be explained, f0 is a critical factor for the converter’s
The circuit’s frequency at peak resonance, fc0, operation and design.
is always equal to its f0. Because of this, an SRC Operation At, Below, and Above f0
requires a wide frequency variation in order to The operation of an LLC resonant converter
accommodate input and output variations. may be characterized by the relationship of the
fc0 , f0 , and fp in an LLC Circuit switching frequency, denoted as fsw, to the series
However, the LLC circuit is different. After the resonant frequency (f0). Fig. 4 illustrates the
second inductance (Lm) is added, the LLC circuit’s typical waveforms of an LLC resonant converter
frequency at peak resonance (fc0) becomes a function with the switching frequency at, below, or above
Topic 3
of load, moving within the range of fp ≤ fc0 ≤ f0 as the series resonant frequency. The graphs show,
the load changes. f0 is still described by Equation from top to bottom, the Q1 gate (Vg_Q1), the Q2
(1), and the pole frequency is described by gate (Vg_Q2), the switch-node voltage (Vsq), the
resonant circuit’s current (Ir), the magnetizing
1 current (Im), and the secondary-side diode current
fp = . (2)
2π (L r + L m )Cr (Is). Note that the primary-side current is the sum
of the magnetizing current and the secondary-side
At no load, fc0 = fp. As the load increases, fc0 current referred to the primary; but, since the
moves towards f0. At a load short circuit, fc0 = f0. magnetizing current flows only in the primary
Hence, LLC impedance adjustment follows a side, it does not contribute to the power transferred
family of curves with fp ≤ fc0 ≤ f0, unlike that in from the primary-side source to the secondary-
SRC, where a single curve defines fc0 = f0. This side load.
helps to reduce the frequency range required from
an LLC resonant converter but complicates the
circuit analysis.
Vg_Q1 Vg_Q1 Vg_Q1

Vg_Q2 Vg_Q2 Vg_Q2
Vsq Vsq Vsq
0 0 0
Ir
Im Ir Im Ir Im
0 0 0
Is Is Is
D1 D2 D1 D2 D1 D2
0 0 0
t0 t1 t2 t3 t4 t0 t1 t2 t3 t4 t0 t1 t2 t3 t4
time, t time, t time, t
a. At f0 . b. Below f0 . c. Above f0 .
Fig. 4. Operation of LLC resonant converter.

4 SLUP263
Operation at Resonance (Fig. 4a) Operation Above Resonance (Fig. 4c)
In this mode the switching frequency is the In this mode the primary side presents a smaller
same as the series resonant frequency. When circulating current in the resonant circuit. This
switch Q1 turns off, the resonant current falls to reduces conduction loss because the resonant
the value of the magnetizing current, and there is circuit’s current is in continuous-current mode,
no further transfer of power to the secondary side. resulting in less RMS current for the same amount
By delaying the turn-on time of switch Q2, the of load. The rectifier diodes are not softly
circuit achieves primary-side ZVS and obtains a commutated and reverse recovery losses exist, but
soft commutation of the rectifier diodes on the operation above the resonant frequency can still
secondary side. The design conditions for achieving achieve primary ZVS. Operation above the reso-
ZVS will be discussed later. However, it is obvious nant frequency may cause significant frequency
that operation at series resonance produces only a increases under light-load conditions.
single point of operation. To cover both input and The foregoing discussion has shown that the
output variations, the switching frequency will converter can be designed by using either fsw ≥ f0
have to be adjusted away from resonance. or fsw ≤ f0, or by varying fsw on either side around
f0. Further discussion will show that the best
Topic 3
Operation Below Resonance (Fig. 4b) operation exists in the vicinity of the series resonant
Here the resonant current has fallen to the frequency, where the benefits of the LLC converter
value of the magnetizing current before the end of are maximized. This will be the design goal.
the driving pulse width, causing the power transfer
to cease even though the magnetizing current C. Modeling an LLC Half-Bridge Converter
continues. Operation below the series resonant To design a converter for variable-energy
frequency can still achieve primary ZVS and transfer and output-voltage regulation, a voltage-
obtain the soft commutation of the rectifier diodes transfer function is a must. This transfer function,
on the secondary side. The secondary-side diodes which in this topic is also called the input-to-
are in discontinuous current mode and require output voltage gain, is the mathematical relation-
more circulating current in the resonant circuit to ship between the input and output voltages.
deliver the same amount of energy to the load. This section will show how the gain formula is
This additional current results in higher conduction developed and what the characteristics of the
losses in both the primary and the secondary sides. gain are. Later the gain formula obtained will be
However, one characteristic that should be noted used to describe the design procedure for the LLC
is that the primary ZVS may be lost if the switching resonant half-bridge converter.
frequency becomes too low. This will result in
high switching losses and several associated issues.
This will be explained further later.

5 SLUP263
Cr Lr Cr Lr
I m Ios
Ir Ir
+ + + +
Vsq Vso Lm RĹ Vge Lm Re Voe
– –
Im I oe
Vsq Vso
a. Nonlinear nonsinusoidal circuit. b. Linear sinusoidal circuit.

Fig. 5. Model of LLC resonant half-bridge converter.
Traditional Modeling Methods Do Not Work Well The FHA method can be used to develop the
To develop a transfer function, all variables gain, or the input-to-output voltage-transfer
should be defined by equations governed by the function. The first steps in this process are as
Topic 3
LLC converter topology shown in Fig. 5a. These follows:

equations are then solved to get the transfer • Represent the primary-input unipolar square-
function. Conventional methods such as state- wave voltage and current with their fundamental
space averaging have been successfully used in components, ignoring all higher-order
modeling pulse-width-modulated switching harmonics.
converters, but from a practical viewpoint they • Ignore the effect from the output capacitor and
have proved unsuccessful with resonant converters, the transformer’s secondary-side leakage
forcing designers to seek different approaches. inductance.
Modeling with Approximations • Refer the obtained secondary-side variables to
As already mentioned, the LLC converter is the primary side.
operated in the vicinity of series resonance. This • Represent the referred secondary voltage, which
means that the main composite of circulating is the bipolar square-wave voltage (Vso), and the
current in the resonant network is at or close to the referred secondary current with only their
series resonant frequency. This provides a hint that fundamental components, again ignoring all
the circulating current consists mainly of a single higher-order harmonics.
frequency and is a pure sinusoidal current. With these steps accomplished, a circuit model
Although this assumption is not completely of the LLC resonant half-bridge converter in Fig.
accurate, it is close—especially when the square 5a can be obtained (Fig. 5b). In Fig. 5b, Vge is the
wave’s switching cycle corresponds to the series fundamental component of Vsq , and Voe is the fun-
resonant frequency. But what about the errors? damental component of Vso . Thus, the nonlinear
If the square wave is different from the series and nonsinusoidal circuit in Fig. 5a is approxi-
resonance, then in reality more frequency mately transformed into the linear circuit of Fig.
components are included; but an approximation 5b, where the AC resonant circuit is excited by an
using the single fundamental harmonic of the effective sinusoidal input source and drives an
square wave can be made while ignoring all higher- equivalent resistive load. In this circuit model,
order harmonics and setting possible accuracy both input voltage Vge and output voltage Voe are
issues aside for the moment. This is the so-called in sinusoidal form with the same single frequency—
first harmonic approximation (FHA) method, now i.e., the fundamental component of the square-
widely used for resonant-converter design. This wave voltage (Vsq), generated by the switching
method produces acceptable design results as long operation of Q1 and Q2.
as the converter operates at or close to the series This model is called the resonant converter’s
resonance. FHA circuit model. It forms the basis for the
3-6
design example presented in this topic. The which can be simplified as
voltage-transfer function, or the voltage gain, is
ω = ωsw = 2πfsw . (11)
also derived from this model, and the next section
will show how. Before that, however, the electrical The capacitive and inductive reactances of Cr, Lr,
variables and their relationships as used in Fig. 5b and Lm, respectively, are
need to be obtained.
1
X Cr = , X Lr = ωL r , and X Lm = ωL m . (12)
Relationship of Electrical Variables ωC r
On the input side, the fundamental voltage of
The RMS magnetizing current is
the square-wave voltage (Vsq) is
2 Voe 2 2 n × Vo
vge (t) = × VDC × sin(2πfsw t), (3) Im = = × . (13)
π ωL m π ωL m
and its RMS value is The circulating current in the series resonant
circuit is
2
Vge = × VDC . (4)
π I r = I 2m + Ioe
2
. (14)
Topic 3
On the output side, since Vso is approximated as a With the relationships of the electrical variables
square wave, the fundamental voltage is established, the next step is to develop the voltage-
4 gain function.
voe (t) = × n × Vo × sin(2πfsw t − ϕV ), (5)
π
D. Voltage-Gain Function
where φV is the phase angle between Voe and Vge,
Naturally, the relationship between the input
and the RMS output voltage is
voltage and output voltage can be described by
2 2 their ratio or gain:
Voe = × n × Vo . (6)
π n × Vo n × Vo
M g _DC = = (15)
The fundamental component of current corre- Vin / 2 VDC / 2
sponding to Voe and Ioe is
As described earlier, the DC input voltage and
π 1 output voltage are converted into switching mode,
ioe (t) = × × Io × sin(2πfsw t − ϕi ), (7)
2 n and then Equation (15) can be approximated as the
where φi is the phase angle between ioe and voe, ratio of the bipolar square-wave voltage (Vso) to
and the RMS output current is the unipolar square-wave voltage (Vsq):
π 1 Vso
Ioe = × × Io . (8) M g _DC ≈ M g _ sw = (16)
2 2 n Vsq
Then the AC equivalent load resistance, Re, can be The AC voltage ratio, Mg_AC, can be approx-
calculated as imated by using the fundamental components, Vge
and Voe, to respectively replace Vsq and Vso in
Voe 8 × n 2 Vo 8 × n 2 Equation (16):
Re = = 2 × = 2 × RL. (9)
Ioe π Io π
n × Vo
Since the circuit in Fig. 5b is a single-frequency, M g _DC = ≈ M g _ sw
Vin /2
sinusoidal AC circuit, the calculations can be (17)
made in the same way as for all sinusoidal circuits. V V
= so ≈ M g _ AC = oe
The angular frequency is Vsq Vge
ωsw = 2πfsw , (10)

7 SLUP263
To simplify notation, Mg will be used here in Further, to combine two inductances into one, an
place of Mg _AC. From Fig. 5b, the relationship inductance ratio can be defined as
between Voe and Vge can be expressed with the Lm
electrical parameters Lr, Lm, Cr, and Re. Then the Ln = . (21)
input-to-output voltage-gain or voltage-transfer Lr
function becomes The quality factor of the series resonant circuit is
defined as
Voe jX Lm || R e
Mg = = L r /Cr
Vge ( jX Lm || R e ) + j(X Lr − X Cr ) Qe = . (22)
Re
(18)
( jωL m ) || R e Notice that fn, Ln, and Qe are no-unit variables.
= , With the help of these definitions, the voltage-
1
( jωL m ) || R e + jωL r + gain function can then be normalized and
jω C r
expressed as
––
where j = √ –1. L n × f n2
Topic 3
Equation (18) depicts a connection from the Mg = . (23)

input voltage (Vin) to the output voltage (Vo) [(L n + 1) × f n2 − 1] + j[(f n2 − 1) × f n × Qe × L n ]
established in relation to Mg with LLC-circuit
The relationship between input and output voltages
parameters. Although this expression is only
can also be obtained from Equation (23):
approximately correct, in practice it is close
enough to the vicinity of series resonance. 1 V 1 V
Vo = M g × × in = M g (f n , L n ,Qe ) × × DC , (24)
Accepting the approximation as accurate allows n 2 n 2
Equation (19) to be written:
where Vin = VDC.
1 V
Vo = M g × × in . (19)
n 2 Behavior of the Voltage-Gain Function
In other words, output voltage can be determined The voltage-gain function expressed by Equation
after Mg, n, and Vin are known. (23) and the circuit model in Fig. 5b form the basis
for the design method described in this topic;
Normalized Format of Voltage-Gain Function therefore it is necessary to understand how Mg
The voltage-gain function described by behaves as a function of the three factors fn, Ln,
Equation (18) is expressed in a format with and Qe. In the gain function, frequency fn is the
absolute values. It is difficult to give a general control variable. Ln and Qe are dummy variables,
description of design issues with such a format. It since they are fixed after their physical parameters
would be better to express it in a normalized are determined. Mg is adjusted by fn after a design
format. To do this, the series resonant frequency is complete. As such, a good way to explain how
(f0) can be selected as the base for normalization. the gain function behaves is to plot Mg with
Then the normalized frequency is expressed as respect to fn at given conditions from a family of
values for Ln and Qe.
fsw
fn = . (20)
f0

8 SLUP263
2 2
1.8 Q e = 0.1 1.8 Q e = 0.1

Q e = 0.2 Q e = 0.2
Q e = 0.5 Q e = 0.5
1.6 Q e = 0.8 1.6 Q e = 0.8
Qe = 1 Qe = 1
1.4 Qe = 2 1.4 Qe = 2
Qe = 5 Qe = 5
Q e = 0.5
Gain, Mg
Gain, Mg
1.2 Qe = 8 1.2 Qe = 8
Q e = 10 Q e = 10
1 2 = 0 1 2 = 0
0.8 0.8
0.6 Q e = 0.1 0.6 Q e = 0.1
0.4 0.4
0.2 Q e = 0.5 0.2 Q e = 0.5

0 0
0.1 1 Q e = 10 10 0.1 1 Q e = 10 10
Normalized Frequency, fn Normalized Frequency, fn
Topic 3
a. Ln = 1. b. Ln = 5.
2 2
Q e = 0.1 Q e = 0.1
1.8 Q e = 0.2 1.8 Q e = 0.2
Q e = 0.1 Q e = 0.5 Q e = 0.1 Q e = 0.5
1.6 Q e = 0.8 1.6 Q e = 0.8
Qe = 1 Qe = 1
1.4 Qe = 2 1.4 Qe = 2
Qe = 5 Qe = 5
Qe = 8 Qe = 8
Gain, Mg
Gain, Mg
1.2 1.2 Q e = 10
Q e = 10
Q e = 0.5 2 = 0 2 = 0
1 1
Q e = 0.5
0.8 0.8
Q e = 0.1 Q e = 0.1
0.6 0.6
0.4 0.4
Q e = 0.5 Q e = 0.5
0.2 0.2
0 0
0.1 1 Q e = 10 10 0.1 1 Q e = 10 10
Normalized Frequency, fn Normalized Frequency, fn
c. Ln = 10. d. Ln = 20.
Fig. 6. Plots of voltage-gain function (Mg) with different values of Ln.
Figs. 6a to 6d illustrate several possible represent both magnitude and phase angle, but
relationships. Each plot is defined by a fixed value only the magnitude is useful in this case.
for Ln (Ln = 1, 5, 10, or 20) and shows a family of Within a given Ln and Qe, Mg presents a
curves with nine values, from 0.1 to 10, for the convex curve shape in the vicinity of the circuit’s
variable Qe. From these plots, several observations resonant frequency. This is a typical curve that
can be made. shows the shape of the gain from a resonant
The value of Mg is not less than zero. This is converter. The normalized frequency correspond-
obvious since Mg is from the modulus operator, ing to the resonant peak (fn_c0, or fsw = fc0) is
which depicts a complex expression containing moving with respect to a change in load and thus
both real and imaginary numbers. These numbers to a change in Qe for a given Ln.
3-9
Changing Ln and Qe will reshape the Mg curve effect of Lm and shift fc0 towards f0. As a simple
and make it different with respect to fn. As Qe is a illustration, it is helpful to examine two extremes:
function of load described by Equations (9) and 1. If RL is open, then Qe = 0, and fc0 = fp as
(22), Mg presents a family of curves relating described by Equation (2). fc0 sits to the far left
frequency modulation to variations in load. of f0, and the corresponding gain peak is very
Regardless of which combination of Ln and Qe high and can be infinite in theory.
is used, all curves converge and go through the
2. If RL is shorted, then Qe = ∞ and Lm is com-
point of (fn, Mg) = (1, 1). This point is at fn = 1, or pletely bypassed or shorted, making the effect
fsw = f0 from Equation (20). By definition of series
of Lm on the gain disappear. The corresponding
resonance, XLr – XCr = 0 at f0. In other words, the peak gain value from the Lm effect then
voltage drop across Lr and Cr is zero, so that the becomes zero, and fc0 moves all the way to the
input voltage is applied directly to the output load, right, overlapping f0.
resulting in a unity voltage gain of Mg = 1.
Notice that the operating point (fn, Mg) = (1, 1) Therefore, if RL changes from infinite to zero,
is independent of the load; i.e., as long as the gain the resonant peak gain changes from infinite to
(Mg) can be kept as unity, the switching frequency unity, and the corresponding frequency at peak
Topic 3
will be at the series resonant frequency (f0) no resonance (fc0) moves from fp to the series
matter what the load current is. In other words, in resonant frequency (f0).
a design whose operating point is at (fn, Mg) = For a fixed Qe, a decrease in Ln shrinks the
(1, 1) or its vicinity, the frequency variation is curve; the whole curve is squeezed, and fc0 moves
narrowed down to minimal. At (fn, Mg) = (1, 1), towards f0. This results in a better frequency-
the impedance of the series resonant circuit is control band with a higher peak gain. There are
zero, assuming there are no parasitic power losses. two reasons for this. First, as Ln decreases due to
The entire input voltage is then applied to the the decrease in Lm, fp gets closer to f0, which
output load no matter how much the load current squeezes the curves from fp to f0. Second, a
varies. However, away from (fn, Mg) = (1, 1), the decreased Ln increases Lr, resulting in a higher Qe.
impedance of the series resonant circuit becomes A higher Qe shrinks the curve as just described.
nonzero, the voltage gain changes with different At first glance, it appears that any combination
load impedances, and the corresponding operation of Ln and Qe would work for a converter design
becomes load-dependent. and that the design could be made with fn operating
For a fixed Ln, increasing Qe shrinks the curve, on either side of fn = 1. However, as explained in
resulting in a narrower frequency-control band, the following section, there are many more
which is expected since Qe is the quality factor of considerations.
the series resonant circuit. In addition, as the
whole curve shifts lower, the corresponding peak III. desIgn consIderAtIons
value of Mg becomes smaller, and the fn As discussed earlier, fn is the control variable
corresponding to that value moves towards the
in frequency modulation. Therefore the output
right and closer to fn = 1. This frequency shift with
voltage can be regulated by Mg through controlling
increasing Qe is due to an increased load. It is
fn , as indicated by Fig. 6 and Equation (24), which
apparent from reviewing Equations (9) and (22)
can be rearranged as
that an increase in Qe may come from a reduction
in RL, as both Lm and Lr are fixed. For the same 1 V
Vo = M g (f n , L n , Qe ) × × in . (25)
series resonant frequency, Cr is fixed as well. RL is n 2
in parallel with Lm, so reducing RL will reduce the

10 SLUP263
Although this discussion has so far determined 2
that the design should operate in the vicinity of the
series resonance, or near fn = 1, it is recommended
1.8
Qe = 0
that the optimum design be restricted to the area

1.6
Mg_max
described by a1 through a4 in Fig. 7, for reasons to 1.4 a3 a2
be explained.
Gain, Mg
1.2
A. What Does “In the Vicinity” Mean?

a0
1
Mg_min
Obviously, “in the vicinity” is a loose designa- 0.8 a1
Curve 1
tion; but, as stated before in the discussion of the 0.6
a4 Cu (Qe = 0)
FHA concept, if a pure sinusoidal current flowing
rv
e
2
through the resonant circuit is assumed, and if the
0.4 (Q
Cu e =m
rve
circuit is made to operate at the exact location of
3 ax)
0.2 Curv
f0, then the design result is accurate. This can also
e4
0
be verified easily by a bench test or a computer
0.1 fn_min 1 fn_max 10
simulation, but so far there is no verification in Normalized Frequency, fn
Topic 3
theory. A potential insight into such verification
a. In the vicinity of series resonance (near fn = 1).
can be made through Equation (19). Assigning a
value of 1 to Mg in Equation (19) as an indication
of operation at fn = 1 will remove the approxima- 1.6
tions made to Equation (17). A precise relationship

Qe = 0
n x Vo_max
is then achieved between the DC input and DC

Mg_max =
1.4 Vin_min /2
output as described by Equation (15).

a3 a2
A design that operates only at f0 certainly

Gain, Mg
1.2
cannot be made, but when it includes operating

Q e = max
frequencies away from f0, it starts to show errors

a0 n x Vo_min
1 Mg_min =
when compared with bench-test measurements. So
Vin_max /2
the common understanding in an FHA design 0.8 a1
approach is that it can help to create an initial a4

design, with all design variables retaining their 0.6 Qe = 0
clear physical concepts and meanings, which is fn_min

1Q e = max fn_max
important in order for designers to understand the Normalized Frequency, fn
behavior of the LLC converter. However, it should
b. Operation boundary set by a1 through a4.
be expected that some bench testing to optimize
and finalize the design may be necessary. This Fig. 7. Recommended design area.
could be an iterative process, but computer-based
circuit simulation will save iteration cycles. As a
matter of fact, computer simulation plays an voltage variation over a specified range, at a given
important role in LLC-converter design after an output load current.
initial design is made with the FHA approach.
Load regulation is defined as the maximum
B. Basic Design Requirements output-voltage variation caused by a change in
For a typical design of a power-supply load over a stated range, usually from no load to
converter, as is well-known, three basic require- maximum.
ments are almost always considered first—line These two types of regulation are actually achieved
regulation, load regulation, and efficiency. through the voltage-gain adjustment—and in an
LLC converter, the gain adjustment is made
Line regulation is defined as the maximum through frequency modulation. The recommended
output-voltage variation caused by an input- area of operation described in Fig. 7 shows a

11 SLUP263
relatively steep slope for the gain, which can n × Vo _ max
narrow the range of the frequency modulation. As M g _ max = , (28)
Vin _ min /2
such, a design has to make the gain adequately
adjustable in a range that meets the required and
regulating specifications.
Ln
Efficiency is one big benefit of using an LLC Mg _∞ = . (29)
Ln + 1
converter. The converter’s switching losses can be
reduced significantly by ensuring that primary- Mg_∞ is a special value of Mg that presents the
side ZVS is maintained over the whole operating gain value at no load when fn is approaching
range. As will be explained, ZVS cannot be infinity. In other words, at no load, the gain curve
achieved everywhere in the gain-plot area, but (Mg) is approaching an asymptotic horizontal line
keeping the design within the recommended region with its value described by Equation (29), which
will ensure ZVS. can be easily obtained from Equation (23) when
the value of fn approaches infinity.
Line Regulation
Mg_min and Mg_max each form a horizontal
Achieving line regulation for the design of a
Topic 3
line in Fig. 7. For the no-load condition (Io = 0),

power-supply converter can be based on Equation
the quality factor (Qe) equals zero, shown in Fig.
(25) and the recommended design areas in Fig. 7.
7a as Curve 1. Since the gain curves are deter-
A minimum and maximum output voltage, Vo_min
mined by Ln and Qe, and Qe = 0, Ln is the sole
and Vo_max, respectively, will be assumed. To
design factor at this stage. As such, a value for Ln
simplify the discussion, it will also be assumed
needs to be selected that will provide a gain curve
that all parasitic voltage drops—for example, from
that meets the conditions of Equation (26). In
PCB traces, the MOSFET’s Rds_on, the diode’s
other words, the value of Ln needs to make Curve
forward voltage, etc.—are already converted or
1 cross over the two horizontal lines defined by
lumped into a part of the output-voltage range. It
Equations (27) and (28) inside the frequency
will also be assumed that the design requires a
limits. This is depicted in Fig. 7 by design points
maximum switching-frequency range; i.e., that it
a1 and a2.
is limited within fn_min ≤ fn ≤ fn_max. In reality, the
Similarly, if the load condition is not zero (Io >
frequency limits may need adjustment in order to
0), then an appropriate curve can be selected by
adapt the line- and load-regulation requirements,
making Qe correspond to the required maximum
or vice versa.
load and following the same process.
With these conditions and assumptions, to
achieve line regulation (and load regulation as Load Regulation
discussed later), Mg should be designed to meet
Normal Load Operation
the conditions described by Equation (26), which
As illustrated in Fig. 7, the gain presents a
says that all possible Mg values must contain the
family of curves. For a fixed Ln, each value for Qe
value of both Mg _min and Mg _max within the fn
generates a different gain curve. A bigger Qe
limits. For Io = 0,
makes the gain curve shift lower with a lower
{M g M g > M g _ ∞ } ⊃ {M g _ min , M g _ max }, (26a) peak. As such, when load current increases, the
gain curve moves away from its no-load shape
and for Io > 0, (Curve 1) to a lower representation. In Fig. 7,
Curve 2 corresponds to the maximum load current
{M g M g ≥ 0} ⊃ {M g _ min , M g _ max }, (26b) (Qe = max) while still meeting the conditions of
Equation (26) with the same Ln. This yields design
where
points a3 and a4 in the recommended design area.
n × Vo _ min If the load is increased further, Curve 2 will be
M g _ min = , (27) reshaped towards Curve 3. Horizontal line Mg_max
Vin _ max /2
will not be able to cross over with the gain curve,
3-12
so the conditions of Equation (26) cannot be met. that a zero gain transfers a zero percentage of
Output-voltage regulation is then lost. When this input voltage to the load short circuit. In this way,
happens, a design modification will be needed, the converter can be protected from a load short-
such as adjusting Ln or the switching-frequency circuit fault.
limits to reshape the gain curve. However, it is worth noting that the effec-
Since Qe is associated with the load current, it tiveness of such a protection method depends on
is appropriate to extend this discussion to include how quickly the short-circuit signal can be sent to
the possibility of overload and short-circuit the controller to activate the frequency increase. In
conditions. the recommended design area, the gain will
inevitably be forced to the left side of the resonant
Overload Current peak for some time until it eventually reaches
In the example, the recommended design area Curve 4. This could cause several severe issues,
in Fig. 7 includes an overload because Qe_max was including the possibility of a polarity reversal of
defined to include a value for it. As stated earlier, the feedback control. Considering this, an inde-
any further increase in load causes Curve 2 to pendent overcurrent shutdown may be a preferable
move towards Curve 3 or beyond, which places solution. However, if a frequency increase is still
Topic 3
the design outside of the design area and towards preferred, two other possible solutions are recom-
the condition of a short circuit. mended. Either (1) add a separate high-speed
Load Short Circuit control loop to rapidly initiate the frequency shift,
Since a load short circuit causes a potentially or (2) shift the recommended design area to where
excessive amount of current in the converter the minimum switching frequency (fn_min) is never
circuit, it is necessary to examine the gain plot of a less than the series resonant frequency (f0)—i.e.,
load short circuit to know what happens and how to where fn_min ≥ 1.
to deal with it. The corresponding gain plot is Zero-Voltage Switching (ZVS)
shown by Curve 4 in Fig. 7a. fc0 will become f0 A major benefit of the LLC converter topology
when Lm is bypassed by a load short circuit, and is its potential for significantly reduced switching
this defines Curve 4 as the gain shape with a losses, primarily achieved through primary-side
shorted output. ZVS; however, as stated earlier, it is ZVS consid-
Curve 4 provides insight into possible solutions erations that drive the recommended design area
for protecting the LLC converter. One possibility to be only on the right side of the resonant gain
is to increase the switching frequency to reduce curves in Fig. 7. This section discusses how ZVS
the gain. Based on Figs. 6 and 7, if the switching is achieved and why it affects the design area.
frequency is increased to more than two times the
series resonant frequency (f0), the gain will be Achieving ZVS
reduced to below 10%. If the frequency can be To achieve ZVS, a MOSFET is turned on only
pulled up to ten times f0, the gain becomes after its source voltage, Vds, has been reduced to
practically zero. From Equation (25) it can be seen zero by external means. One way of ensuring this

13 SLUP263
is to force a reversal of the current flowing through where the input impedance, Zin (shown in Fig. 9a),
the MOSFET’s body diode while a gate-drive can be inductive, making the circuit’s Ir lag behind
turn-on signal is applied (see Fig. 8). its Vge.
As shown in Fig. 8, when Q1 turns off at t1, Zin can be expressed in its polar form:
the Q2 gate’s turn-on drive signal is not applied
until t2, such that there exists a dead time, tdead, Zin = Zin e jϕz, (30a)
from t1 to t2. During tdead, the current in the reso- where φz is the phase angle between Ir and Vge.
nant circuit (Ir) is diverted from Q1 to Q2, first From Equation (30a), it is apparent that Zin varies
discharging Q2’s drain-to-source capacitance, Cds, in relation to φz (–π/2 ≤ φz ≤ π/2):
to make its voltage zero, and then forward biasing
• When φz > 0, the impedance is inductive.
Q2’s body diode. At t2, conduction through the Q2
• When φz < 0, the impedance is capacitive.
body diode maintains zero Vds_Q2 (ignoring the Q2
body diode’s forward-voltage drop) until the Q2 • When φz = 0, the impedance is resistive.
gate’s turn-on drive signal is applied. So the critical The φz angle is a function of frequency, or
condition is when Q1 turns off. A nonzero current switching frequency in this case. As such, a
(Ir) should still continue in its same direction as frequency boundary formed by the locus of the
Topic 3
when Q1 was on, normally accomplished by exter- resonant peaks corresponds to φz = 0 and is the
nal circuit inductance. And, of course, the same dividing line between the capacitive and inductive
conditions are necessary for a Q1 ZVS turn-on. regions (see Fig. 9b). Therefore, ZVS can be
Since there is inductive impedance, the circuit’s
current lags behind its applied voltage. To achieve + Vr –
ZVS, the designer must determine the conditions Lr
Cr Ir
+ +
Q1 + Vge Lm Re Voe
Vg Vds_Q1 –
–
n:1:1 Im I oe
Ids_Q1 Lr
+
Vin Vsq
– Lm
+ Ir
Q2 Z in
Vg Vds_Q2 Im
a. Input impedance.
Ids_Q2 Cr
a. LLC resonant circuit.

2
Qe = 0 Qe = 0
1.8 Q e = 0.2
Q e = 0.8
1.6 Qe = 1
Vg_Q1 Capacitive Qe = 2
1.4 Region Q e = 10
Q1 Turns Off
Vg_Q2
Gain, Mg
1.2 Inductive
Region
Vsq Q2 Turns On 1
Vds_Q2 = 0 Qe = 0
0.8
0
0.6
Ir Q2: Cds Discharge,
Im Body Diode 0.4
Turns On
0 Q e = 10
0.2
tdead 0
0.1 1 Frequency 10
t0 t1 t2 t3 t4 Boundary
time, t Normalized Frequency, fn
b. ZVS timing waveform. b. Gain regions.
Fig. 8. ZVS operation. Fig. 9. LLC resonant circuit.

14 SLUP263
Vg_Q1
Q1 Turns Off
Vg_Q2
Q1
Cds
Vg n:1:1
Lr Ceq Vsq Q2 Turns On
+ Lm
Vin Vsq
– Ir Vds_Q2 = 0
Q2 + I m_max
Cds Im Vin 0
–
Vg Ir Q2: Cds Discharge,
Cr Im Body Diode
Ceq Turns On
0
Cr
a. LLC resonant circuit showing (Short)
tdead
parasitic capacitance.
b. Equivalent circuit. t0 t1 t2 t3 t4
time, t
c. ZVS timing waveform.

Fig. 10. Obtaining sufficient inductive energy for ZVS.
Topic 3
achieved only when the converter’s input phase Ensuring Sufficient Inductive Energy
angle is greater than zero: To realize sufficient inductive energy for ZVS,
it is necessary to understand how ZVS is achieved
ϕz = ∠( Zin e jϕz ) > 0 (30b) in the inductive region. Fig. 10 can be used to
describe the ZVS mechanism. During the dead-
All resonant peaks corresponding to fc0 are in time interval between t1 and t2 (tdead), the resonant
the capacitive region, although the boundary line circuit’s current (Ir) equals the magnetizing current
is very close to the peaks. To distinguish resonant (Im). Im is by nature sinusoidal. In tdead, Im is
peaks from the gain values on the resonant bound- circulating through the capacitances (Cds) of Q1
ary, the gain values on the frequency boundary are and Q2 before Q2’s body diode begins to conduct.
defined as attainable peak-gain values, denoted as In tdead, the magnetic-field energy associated with
Mg _ap. Practically, though, Mg _ap is usually very Im converts into the electric-field energy of the
close to Mg _peak, where two capacitances; i.e., it charges up the Cds of Q1
M g _ peak = M g (31) and discharges the Cds of Q2 before Q2’s body
f = f c0 diode can turn on. Cr is much larger than Cds × 2,
and fc0 is the frequency when the maximum value so any energy-conversion effect from Cr can be
of Mg is achieved from Equation (18) or (23) ignored. An equivalent circuit in tdead can then be
during a frequency sweep from zero to infinity derived as shown in Fig. 10b. Ceq is used since
with a given Lm, Lr, Cr, and Re. parasitic capacitances exist in addition to Cds × 2.
From Fig. 7, it is clear that the recommended Hence, in order for the body diode of Q2 to be
operating area, a1 through a4, is in the inductive turned on within tdead, the conditions in Equations
region; so the design example should achieve (32a) and (32b) must be met:
ZVS. Although this is true, it is worth pointing out 1 1
that the recommendation is only a condition (L m + L r ) × I 2m _ peak ≥ (2Ceq ) × Vin2 (32a)
2 2
necessary to ensure ZVS. There must also be
sufficient inductive energy for the converter to t dead ≥ 16 × Ceq × fsw × L m (32b)
operate with ZVS.
3-15
Why the Capacitive Region Is Not Used
As already discussed, ZVS cannot be achieved
in the capacitive region; and, without it, switching 1.5
losses become high and the efficiency benefit of

using an LLC converter is lost. Several additional
issues arise if operation is allowed in the capacitive
Gain, Mg
1
region:
With C w
• This region yields hard switching on the primary

side, since ZVS is lost. 0.5 Without C w
• Because of hard switching and a capacitive
current, the primary-side MOSFET’s body diodes fCw
present reverse-recovery losses, and these diodes 0
are usually of a type with slow reverse recovery. 0.1 1 10
The slow reverse recovery may allow severe

Normalized Frequency, fn
shoot-through of the two primary MOSFETs, Fig. 11. Effect of transformer windings’ parasitic
resulting in high current and causing the capacitance (Cw ) on gain function at high
Topic 3
MOSFETs to fail. frequency.

• Even if the MOSFETs can be selected to tolerate
shoot-through current caused by power dissipa-
tion from the reverse recovery, high current spikes may need consideration. As is well-known, the
are still present, leading to high EMI noise. lower the switching frequency is, the bulkier the
• The frequency relationship is reversed, which converter, and the less important switching losses
changes the feedback control to positive. and ZVS efficiency become. Conduction losses
become dominant, making the LLC converter less
C. Selecting Design Parameters fsw, n, Ln, attractive. A higher switching frequency makes the
and Qe benefits of the LLC converter more pronounced,
With a better understanding of the gain behavior, particularly in comparison with hard-switched
it is now possible to move ahead and create the converters. If the switching frequency is very
design. Thus far, all discussion has been based on high, additional factors may have to be considered,
knowing the values of fsw, n, Ln, and Qe and their such as component availability and the associated
potential effect on circuit operation; but, at the additional cost; additional board-layout concerns;
beginning of a design, nothing is known about and additional switching losses despite MOSFET
these variables, so where does the designer start? ZVS, such as magnetic-core losses. Also, the
parasitic capacitance, Cw , of the transformer
Selecting the Switching Frequency (fsw) windings may begin to change the nature of the
Acceptable switching frequency is usually resonant gain curves, as shown in Fig. 11.
defined for particular applications. For example,
most off-line AC/DC applications require a Selecting the Transformer Turns Ratio (n)
switching frequency below 150 kHz for normal As shown in Fig. 7, the gain magnitude in the
operation, and usually between 100 and 150 kHz recommended design area can be greater or smaller
as a rule of thumb. This is usually because con- than unity. This provides flexibility in selecting
duction EMI testing starts at 150 kHz. Maintain- the transformer turns ratio. Initially the gain can
ing the switching frequency below the EMI test’s be set at unity (Mg = 1) for the output voltage at its
lower boundary helps the application to pass the middle value between Vo_min and Vo_max. This
test. Therefore, circuit components corresponding middle value can be called the output voltage’s
to such a frequency range are usually well- nominal value, Vo_nom , although the middle value
developed, more available, and less expensive. may not necessarily always be the nominal value.
If a different frequency range is required for Similarly, the input voltage’s nominal value can be
unique applications, there are several factors that called Vin_nom . Then the transformer turns ratio
3-16
may be initially designed based on Equation (25): 3.0
Vin / 2 Vin _ nom / 2 Ln = 1.5

n = Mg × = (33)
2.8
Ln = 2.0
Vo Vo_ nom
Attainable Peak Gain, Mg_ap

Ln = 3.0
Mg = 1
2.6
Ln = 3.0 Ln = 4.0
2.4 Ln = 5.0
Ln = 6.0
Selecting Ln and Qe 2.2 Ln = 3.5 by
Ln = 8.0
Recall that in order to achieve line and load

Ln = 9.0
Interpolation
regulation across the operation range, the design
2.0 Mg_ap = 1.56
must meet the conditions of Equation (26), which

Qe = 0.45
1.8
defines two horizontal lines crossing over two Ln = 1.5
gain curves within frequency limits. Designing

1.6
Ln = 5
circuit parameters to select Ln and Qe values that 1.4 Mg_ap = 1.2
satisfy Equation (26) will be discussed next.
Qe = 0.5
1.2
How Are the Proper Ln and Qe Selected? 1.0

First, recall the discussion on Fig. 7. The most
0.15 0.35 0.55 0.75 0.95 1.15
Topic 3
critical point for normal operation is the point a3.
Quality Factor, Q e
This point corresponds to Qe_max, determined by a. Peak-gain curves.

the maximum load current. This point should be
designed to avoid operation that would enter the
capacitive region. Since a required maximum gain Attainable Peak Gain, Mg_ap
1.8
(Mg _max) can be determined from Equation (28),

Mg _max can be plotted to the gain curves to obtain 1.6
point a3 by finding the cross point between the Ln = 5

Mg _max line and the gain curves. Because the gain 1.4 Mg_ap = 1.2
curves are dependent on Ln and Qe, several gain

Qe = 0.5
curves may need to be drawn to find a proper point 1.2
a3. This is certainly one way to make the initial

selection of Ln and Qe, but it is a difficult way and
1.0
most likely will require some wild guess.

0.15 0.35 0.55 0.75
A more desirable approach is to create a

Quality Factor, Q e
common tool to represent the gain curves that can

1.4
be shared and reused by different designs. Since

Qe = 0.5
1.2 Ln = 5
the attainable peak gain (Mg _ap) corresponding to Mg_max = 1.2
Qe_max is the highest gain of concern for a design,
1
Gain, Mg
gain-curve plots can be created beforehand to show

0.8
Mg _ap with different values of Ln and Qe . Then Ln 0.6

and Qe can be selected to achieve Mg _ap > Mg_max
based on a common tool—the Mg _ap curves. How
0.4
this method is used will be described after a 0.2
discussion of how the Mg _ap curves are obtained. 0

0.1 1
How Are the Mg _ap Curves Obtained? Normalized Frequency, fn
The created Mg_ap curves are shown in Fig. 12a. b. Obtaining peak-gain curves.
The horizontal axis is Qe and the vertical axis is
Mg _ap with respect to a family of fixed values for Fig. 12. Using peak-gain curves in a design.
Ln. Fig. 12b is used to illustrate how Fig. 12a is
formed.

17 SLUP263
From a plot of gain curves, for example from optimal design. However, LLC converters have
Fig. 6b, which is partially copied to the lower half some things in common that can be used to guide
of Fig. 12b, one attainable peak-gain value, Mg_ap the selection:
= 1.2, can be located at the curve with (Ln, Qe) = • A smaller Ln can make the peak gain higher for a
(5, 0.5). This point can be plotted to Fig. 12a at fixed Qe, keeping the design’s operation out of
(Mg _ap, Qe) = (1.2, 0.5). (Note that Ln = 5 at this the capacitive region. Since Ln is a ratio of the
point.) Because all curves in Fig. 6b have a fixed magnetizing inductance (Lm) to the series reso-
Ln = 5, that figure can be used to repeat the process nant inductance (Lr), a smaller Ln usually results
with different Qe values. Then a peak-gain curve from a smaller Lm, and vice versa. Equation (13)
can be formed as a function of Qe with a fixed Ln indicates that a smaller Lm will introduce higher
= 5, shown in Fig. 12a. The process can be repeated magnetizing current. This can help ZVS but will
for different Ln values of interest, producing the increase conduction losses.
results in Fig. 12a. • A smaller Qe makes the peak gain higher while
associated gain curves have a larger frequency
How Are Mg _ap Curves Used in a Design?
variation for a given gain adjustment. A large Qe
With Mg _max already determined for a partic-
results in a very low peak gain, which may not
Topic 3
ular design from Equation (28), Mg _max can be

meet the design requirements.
plotted as a horizontal line on Fig. 12a. Any Mg_ap
values above this line are greater than Mg_max , so • With these considerations in mind and from
the designed converter should operate in the design practice, a good start is to select a value
inductive region. For example, for Mg_max = 1.2, any for Ln around 5 and for Qe around 0.5 so that the
corresponding gain curves will be neither too
values of Mg _ap can be selected that are greater
than 1.2, as shown in Fig. 12a. Then the selected flat nor too steep.
value meets the maximum-gain requirement. • Reiteration is usually needed after an initial
From the selected Mg _ap value, Ln and Qe values selection.
can then be selected. For example, selecting a
D. Peak-Gain Curves from a Bench Test
value from the curve of Ln = 5 provides the Ln
The attainable peak-gain curves shown in Fig.
value right away. Since a gain value greater than
12a were made from the gain function described
Mg _max needs to be selected, Qe would have to be
by Equation (23), but Equation (23) was developed
less than 0.5, based on Fig. 12a. Similarly, a
with approximations. These approximations allow
smaller Ln provides more gain and Ln can be
errors in the peak-gain curves, causing accuracy
selected by interpolating as shown in Fig. 12a. For
concerns. To test the accuracy, a comparison was
example, if a value of 0.45 is selected for Qe, the
made between the gain function of Equation (23)
corresponding Mg _ap value with Ln = 3.5 would be
and a bench test with a 135-kHz series resonant
1.56 > Mg _max = 1.2, which satisfies the design
frequency. The peak-gain values were found to
requirements.
differ from those shown in Fig. 12a and from the
What Ln and Qe Values Are Best if They Are All gain curves shown in Fig. 6.
Greater than Mg _max?
Different applications may require the selection
of unique values for Ln and Qe to achieve an

18 SLUP263
The comparison results are plotted in Fig. 13a. obvious that this can be done by selecting proper
The solid line shows the result based on Equation values for Ln and Qe. After Ln and Qe are
(23), and the discrete points (t) show the results obtained, the resonant circuit’s parameters (Cr,
from the bench test. This comparison supports the Lr, and Lm) can be calculated based on Equations
argument that the FHA-based gain function of (22), (1), and (21), respectively:
Equation (23), while diverging for frequencies
away from resonance, is accurate enough and 1
Cr = (34)
acceptable in the vicinity of series resonance. 2πfsw R e Qe fsw = f 0
One other interesting observation is that the
peak gain and attainable peak gain from the test
are much larger than those obtained from the
2.0
(65, 1.90)
FHA-based gain function. Certainly this is good
Bench Test
Measurements
for a design, as it yields more design margin (80, 1.58) Plot Based on
before operation enters the capacitive region. From
(60, 1.57) Equation 18
this viewpoint, computer-based circuit simulation

1.4
should be conducted to supplement an FHA design

(55, 1.27) (100, 1.21)
Topic 3
Gain, Mg
if more accuracy is desired prior to hardware
(135, 0.99)
implementation. (170, 0.87)
In practice, to reduce the potential effect of (200, 0.78)
inaccuracy, peak-gain curves may be regenerated

(40, 0.70) (240, 0.72)
0.6
by experiment and/or by computer-based circuit (30, 0.51) (400, 0.56)
simulation to replace the curves from Equation

(23). Fig. 13b shows the peak-gain curves resulting
from the experiment. Compared to Fig. 12a, Fig.
f0 = 135 kHz
0.0
13b presents higher gain values. For example, for 10 100 1000
Ln = 5 and Qe = 0.5, the attainable peak gain from

Frequency, fsw (kHz)
Fig. 13b is Mg_ap = 1.65, versus 1.2 from Fig. 12a. a. Comparison of FHA-based gain function and
bench test.
E. Resonant-Network Design Flow
The design procedure that has been described 3
can be summarized as follows:
• First, terminal voltages Vo_min and Vin_max, used
2.8
in Equation (27), and Vo_max and Vin_min, used in

2.6
Equation (28), must be taken from the converter 2.4 Ln = 1.5
specifications. 2.2
• Second, the transformer turns ratio (n) can be Mg_ap = 1.65
obtained from Equation (33). Then the two hori-
2
Qe = 0.5 Ln = 2.0
zontal lines represented by Mg _min and Mg_max
1.8
can be calculated. From the converter’s load 1.6 Ln = 3.0

specifications, the load current with its 1.4
corresponding resistance (RL ) can be obtained at Ln = 5.0
any specified load condition. Then the AC
1.2
Ln = 9.0
equivalent load resistance (Re ) in the FHA circuit 1
model can be determined from Equation (9).

0.15 0.35 0.55 0.75 0.95 1.15
0.25 0.45 0.65 0.85 1.05 1.25
• Third, two proper gain curves must be found that Quality Factor, Q e
will cross over the two horizontal lines b. Peak-gain curves from test.
represented by Mg _min and Mg _max within
selected or specified frequency limits. It is Fig. 13. Peak-gain curves from experiment.

19 SLUP263
Iv. desIgn exAmpLe
1
Lr = (35)
(2πfsw ) 2 Cr This section will demonstrate step-by-step
fsw = f 0 how to use the described method to design an LLC
resonant half-bridge converter. The design is
Lm = Ln Lr (36) oriented to applications with low output voltage,
The design method can also be summarized such as the ATX12 power supplies used in
with the flowchart shown in Fig. 14. computers and servers, where energy conservation
is important.
Vin
Converter Specifications n
2Vo
3.0
2.8 Ln = 1.5
Topic 3
Ln = 2.0
2.6 Ln = 3.0
Ln = 3.0 Ln = 4.0
2.4 Ln = 5.0 n  Vo_min
Ln = 6.0 M g_min 
Ln = 8.0
2.2 Ln = 3.5 by Ln = 9.0
Interpolation
Vin_max / 2
2.0 Mg_ap = 1.56
Qe = 0.45
1.8
Ln = 1.5
1.6
Ln = 5 n  Vo_max
1.4 Mg_ap = 1.2
Qe = 0.5
M g_max  Magnetizing Inductance
1.2 Vin_min / 2
1.0
0.15 0.35 0.55 0.75 0.95 1.15 L m  Ln  Lr
Quality Factor, Qe
Resonant Inductor
Choose L n and Q e 1
Lr  2
(2fsw)  Cr
Change L n and Q e Resonant Capacitor
Check Mg and fn
Against Graph
No 1
Cr 
1.9 Ln = 3.5 Are Values 2 fsw R eQe
Qe = 0
Within
1.7
fn_min = 0.65 Limits? Yes
1.5 Mg_max Calculate R e
Q e = 0.47 Mg_max = 1.3
Gain, Mg
Mg_min
1.3
fn_max 2 2 V2
1.1
Mg_min = 0.99 fn_min Re  8 ×2n × R L  8 ×2n × o
  Pout
0.9
Q e = 0.52
0.7
fn_max = 1.02
0.5
0 0.5 1 1.5
Fig. 14. Flowchart of resonant-network design.
3-20
The converter’s electrical specifications are as efficiency-boosting features and high-level protec-
follows: tion features that provide a cost-effective solution.
• Input voltage: 375 to 405 VDC The step-by-step design demonstration will focus
• Rated output power: 300 W mainly on the power stage. For those interested in
• Output voltage: 12 VDC how to use and program the UCC25600, please
• Rated output current: 25 A refer to its data sheet (Reference [1]).
• Output-voltage line regulation (Io = 1.0 A): ≤ 1%
B. Design Steps
• Output-voltage load regulation (Vin = 390 V):
≤ 1% 1. Determine Transformer Turns Ratio (n)
• Output-voltage peak-to-peak ripple (Vin = 390 V The transformer turns ratio is determined by
and Io = 25 A): ≤ 120 mV Equation (33):
• Efficiency (Vin = 390 V and Io = 25 A): ≥ 90%
Vin / 2 Vin _ nom / 2
• Switching frequency (normal operation): 70 to n = Mg × =
150 kHz Vo Vo_ nom
Mg = 1
A. Block Diagram of Proposed From the specifications, the nominal values
Topic 3
Converter Circuit for input voltage and output voltage are 390 V and
A block diagram of the proposed circuit is 12 V, respectively, so the turns ratio can be
shown in Fig. 15. For clarity, some auxiliary func- calculated as
tions are not included. For the LLC resonant-mode Vin _ nom /2 (390 V)/2
controller, the UCC25600 can be a good choice. n= = = 16.25 ⇒ 16.
Vo _ nom 12 V
This eight-pin device has built-in, state-of-the-art,
DT1 Q1
Lr T1
Cin
n:1:1 Vo
Ir
Io
Lm
Q2
Co +
Cr RL
ID1 ID2
D1 D2
U1
8 3
GD1 OC Vs
UCC25600 RT1 R o1
5 2
GD 2 RT
U2
7 1
VCC DT
RT2
Cf Rf1
6 4
GND SS
CB R DT R o2
C SS
U3
Fig. 15. Proposed circuit for the design example.

21 SLUP263
2. Determine Mg _min and Mg _max 4. Determine the Equivalent Load Resistance
Mg _min and Mg _max can be determined by using (Re ) in Fig. 5b
Equations (27) and (28), respectively: Re is determined from Equation (9). At full load,
n × (Vo _ min + VF ) 8× n2 Vo 8 ×162 12 V
M g _ min = Re = × = × = 99.7 Ω .
Vin _ max /2 π2 Io π2 25 A
16 × [12 V × (1 − 1%) + 0.7 V] At 110% overload,
= = 0.99
(405 V)/2 8× n2 Vo 8 ×162 12 V
Re = × = × = 90.6 Ω .
n × (Vo _ max + VF + Vloss ) π2 Io π 2 25 A ×110%
M g _ max =
Vin _ min /2
5. Design Resonant Circuit’s Parameters
16 × [12 V × (1 + 1%) + 0.7 V + 1.05 V] The resonant circuit’s parameters are determined
= from Equations (34), (35), and (36). A switching
375/2
frequency of 130 kHz may be selected initially for
Topic 3
= 1.18 the series resonant frequency, and then the resonant

In these calculations, 1% is used to adjust circuit’s parameters can be calculated at full load:
output voltage from the line and load regulation. 1
VF = 0.7 V is assumed for the secondary-side Cr =
2π× Qe × f 0 × R e
diode’s forward-voltage drop. Vloss = 1.05 V is
assumed for the voltage drop due to power losses. 1
If the efficiency is assumed to be 92% (> 90% as =
2π× 0.45 ×130 ×103 Hz × 99.7 Ω
required by the specifications), then 8% of the
total power would be power losses. If all losses are = 27.3 nF ⇒ 12 nF × 2 + 3.3 nF
referred to the output voltage, then 8% loss at 25 A
would drop the output voltage to 1
Lr =
300 W (2π× f 0 ) 2 Cr
× 8%
92%
= 1.05 V. 1
25 A =
This is added to Mg _max to maintain voltage-load (2π×130 ×10 Hz) 2 × 27.3 ×10−9 F
3
regulation. = 54.9 µH ⇒ 60 µH
To keep operation within the inductive region
with an overload-current capability of 110%,
L m = L n × L r = 3.5 × 60 = 210 µH
Mg_max is increased from 1.18 to 1.18 × 110% = 1.30.
3. Select Ln and Qe 6. Verify the Resonant-Circuit Design
From Fig. 12a, if the values Ln = 3.5 and Qe = 0.45 The design parameters are as follows:
are selected, the corresponding Mg _ap = 1.56, • Series resonant frequency:
which is greater than Mg _max = 1.30. A curve for
Ln = 3.5 is not shown in Fig. 12a, but it can be 1
f0 =
obtained by interpolating the curves of Ln = 3 and 2π× L r × Cr
Ln = 4.
1
=
2π× 60 ×10−6 H × 27.3 ×10−9 F
= 124.4 kHz

22 SLUP263
• Inductance ratio:
Ln = 3.5
210 µH
1.9
L
Ln = m = = 3.5
Qe = 0
Lr 60 µH 1.7
fn_min = 0.65
• Quality factor at full load: 1.5 Q e = 0.47 Mg_max = 1.3
Gain, Mg
L r /Cr
Qe =
1.3
Re Mg_min = 0.99
1.1
(60 ×10−6 H) / (27.3 × 10−9 F)

= = 0.47
99.7 Ω
0.9
Q e = 0.52
• Quality factor at 110% overload: 0.7
fn_max = 1.02
L r /Cr
Qe =
0.5
0 0.5 1 1.5
Re
Topic 3
(60 ×10−6 H) / (27.3 ×10

−9
F) Fig. 16. Verification of resonant-circuit design.
= = 0.52
90.6 Ω
Plot the gain curves corresponding to the The resonant circuit’s current (Ir) is determined
design parameters (Fig. 16). The plot shows that from Equation (14):
the initial design meets the requirements of both
Equation (26) and the following frequency I r = I 2m + Ioe
2
= (1.63 A) 2 + (1.91 A) 2 = 2.51 A
specifications:
This is also the transformer’s primary winding
• The frequency at series resonance is f0 = 124.4
current at fsw_min.
kHz.
• The frequency at (Mg _min, fsw_max) is fn_max × f0 8. Determine the Secondary-Side Currents
= 1.02 × 124.4 kHz = 126.9 kHz. The total secondary-side RMS load current is the
• The frequency at (Mg _max, fsw_min) with an overcurrent referred from the primary-side current (Ioe)
load (Qe = 0.52) is fn_min × f0 = 0.65 × 124.4 kHz to the secondary side:
= 80.7 kHz. Ioe _ s = n × Ioe = 16 ×1.91 A = 30.6 A
7. Determine the Primary-Side Currents
Since the transformer’s secondary side has a
The primary-side RMS load current (Ioe) with a
center-tapped configuration, this current is equally
110% overload is determined from Equation (8):
split into two transformer windings on the
π Io 25 A ×110% secondary side. The current of each winding is
Ioe = × = 1.11× = 1.91 A
2 2 n 16 then calculated as
The RMS magnetizing current (Im) at fsw_min = 2 × Ioe _ s 2 × 30.6 A
80.7 kHz is determined from Equation (13): Isw = = = 21.6 A.
2 2
nVo The corresponding half-wave average current is
I m = 0.901×
ωL m
2 × Ioe _ s 2 × 30.6 A
Isav = = = 13.8 A.
16 ×12 V π π
= 0.901×
2π× 80.7 ×103 Hz × 210 ×10−6 H
= 1.63 A

23 SLUP263
9. Selectthe Transformer 1000
The transformer can be built or purchased from a
catalog. The specifications for this example are: 500
12 nF,
• Turns ratio (n): 16

300 V,
AC Voltage, Vin_max (VRMS )

100 kHz
• Primary terminal voltage: 450 VAC

• Primary winding’s rated current, Iwp: 2.6 A
• Secondary terminal voltage: 36 VAC 6.2 nF
• Secondary winding’s rated current, Iws: 21.6 A

100
(center-tapped configuration) 50
• Frequency at no load: 127 kHz 12 nF
• Frequency at full load: 80 kHz 33 nF
• Insulation between primary and secondary sides:
IEC60950 reinforced insulation
10
10. Selectthe Resonant Inductor
10 k 100 k 1M 10 M
The inductor can be built or purchased from a

Frequency, f (Hz)
Topic 3
catalog, with these specifications: Fig. 17. Voltage derating from frequency.
• Series resonant inductance, Lr: 60 μH
• Rated current, ILr: 2.6 A
• Terminal AC voltage: Ir
VCr = X Cr × I r =
VLr = ωL r × I r = 2π× 80.7 ×103 × 60 ×10−6 × 2.6 ω× Cr
= 75.7 V ⇒ 100 V 2.6 A

= = 187.9 V
2π× 80.7 ×10 Hz × 27.3 ×10−9 F
3
• Frequency range: 80 to 127 kHz
11. Select the Resonant Capacitor • RMS voltage:
The resonant capacitor (Cr) must have a low 2
 Vin _ max 
dissipation factor (DF) due to its high-frequency, VCr _ RMS =  2
 + VCr
high-magnitude current. Capacitors such as elec-  2 
trolytic and multilayer X7R ceramic types usually
have high DF and therefore are not preferred. NP0  405 V 
2
2
capacitors can be used due to their low DF, but =   + (187.9 V) = 276.3 V
their capacitance range presents limitations.  2 
Capacitors often used for LLC converters are • Corresponding peak voltage:
made with metalized polypropylene film. These
capacitors present very low DF and are capable of Vin _ max
VCr _ peak = + 2 × VCr
handling high-frequency current. 2
Before a capacitor is selected, its voltage rating
has to be derated with regard to the switching 405 V
= + 2 ×187.9 V = 467.4 V
frequency in use. Fig. 17 shows an example where 2
a 12-nF capacitor rated at 600 VRMS can be used
only up to 300 VRMS with a 100-kHz switching 12. Select the Primary-Side MOSFETs
frequency. Specify the MOSFET parameters required for the
The selected capacitor (Cr) must meet these converter. Each MOSFET sees the input voltage
additional specifications: as its maximum applied voltage:
• Rated current, ICr: 2.6 A VQ1_ peak = VQ2 _ peak = Vin = 405 V ⇒ 500 V
• AC voltage, calculated from the circuit in Fig. 9a:

24 SLUP263
Each MOSFET conducts half of the resonant net- These calculations verify that Equation (32a) is
work’s current in steady state after the resonant true:
capacitor’s voltage has been established. However, 1 1
during the initial start-up and transient, the current (L m + L r ) × I 2m _ peak ≥ (2Ceq ) × Vin2
in each MOSFET can be as high as the resonant 2 2
current (Ir) with a 110% overload: To meet the requirements of Equation (32b), the
IQ1_ RMS = IQ2 _ RMS = I r = 2.51 A dead time should be designed as
MOSFET switching losses are minimized by t dead ≥ 16 × 200 ×10−12 F × 127 ×103 Hz
ZVS; therefore, the MOSFETs’ conduction losses × 210 × 10−6 H = 85.0 × 10−9 s.
may become the main concern for the design. This
suggests that MOSFETs with a low Rds_on should A tdead of 100 ns will meet the requirement.
be used, but with the recognition that there is
14. Select the Rectifier Diodes
usually a trade-off between Rds_on and Cds.
The diodes’ voltage rating is determined as
13. Design for ZVS Vin _ max /2
Topic 3
The converter’s input phase angle must be greater VDB = ×2
n
than zero, as described by Equation (30b). Based
on Step 6, this requirement has been met. (405 V)/2
The conditions under which the converter has = × 2 = 25 V ⇒ 30 V.
16
sufficient inductive energy and sufficient switching
dead time for ZVS are described by Equations The diodes’ current rating is determined as
(32a) and (32b), respectively. To check these 2 × Ioe _ s 2 × 30.6 A
conditions, it can be assumed that Ceq is mainly Isav = = = 13.8 A.
π π
from the MOSFETs’ Cds. For typical 500-V
MOSFETs, Cds is around 200 pF. If it is assumed
15. Select the Type of Output Filter and Specify
that Ceq = 200 pF and that the worst-case minimum
the Capacitors
magnetizing current (Im_min) is
In an LLC converter, the output filter may consist
n × Vo of capacitors alone instead of the LC filter seen in
I m _ min = 0.901× most pulse-width-modulated converters, although
2π× fsw × L m fsw =
127 kHz a small second-stage LC filter can be an option. If
the filter has only capacitors, they should be chosen
16 × 12 V to allow conduction of the rectifier current through
= 0.901×
2π×127 ×103 × 210 ×10−6 all AC components.
The rectifier’s full-wave output current is
= 1.03 A, expressed as
then, to verify Equation (32a), π
I rect = Isw = × Io .
1 2 2
(L + L r ) × I 2m _ peak
2 m Then, for the load current (Io), the capacitor’s RMS
1 current rating at about 100 kHz is calculated as
= (210 ×10−6 H + 60 ×10−6 H) × ( 2 ×1.03 A) 2
2
2
 π  π2
= 286.5 ×10 −6
joules, I Co =  × Io − Io2 = − 1 × Io
2 2  8
and
= 0.482 × Io = 0.482 × 25 A = 12.1 A.
1
(2Ceq ) × Vin2 = 200 ×10−12 F × (405 V) 2
2 Usually a single capacitor will not allow such a high
= 32.8 ×10−6 joules. RMS current, so several capacitors connected in

25 SLUP263
parallel are often used and may offer a lower pro- along with the FHA method. Using the two
file. Aluminum solid capacitors with conductive- methods together is effective and provides a good
polymer technology have a high current rating and balance. The FHA method is very effective for
a low equivalent series resistance (ESR), making initiating a design because it provides a functional
them a good choice. connection between a frequency-modulated
The ripple voltage is a function of the amount switching-mode converter and established sinu-
of AC current that flows in and out of the capacitors soidal AC circuit design and analysis, giving
with each switching cycle, multiplied by the designers insight into the converter’s operation.
capacitors’ ESR. Since all electric current, includ- Computer-based circuit simulation, on the other
ing the load’s DC current, can be assumed to flow hand, compensates the FHA method with accurate
in and out of the filter capacitors, this is a very design values. The combined design approach can
good estimate of the ripple voltage. To meet the significantly reduce the number of design itera-
specification for a 120-mV ripple voltage, the max- tions, shortening the time from starting a design to
imum ESR should be realizing its final product.
Vo _ pk-pk Vo _ pk-pk vI. concLusIon
ESR max = =
Topic 3
I rect _ peak  π 
 4 × Io  × 2 This topic has presented comprehensive
  considerations for designing an isolated LLC
0.12 V resonant half-bridge converter. It has been shown
= = 3.05 mΩ. that the FHA method is especially effective for
π
× 25 A initiating a new design of this type. A step-by-step
2
design example has also been presented to
Any capacitance value can be used as long as demonstrate how to use this method.
combined capacitors meet the following speci-
fications: vII. AcknowLedgments
• Voltage rating: 16 V The author would like to express sincere grati-
• Ripple-current rating: 12.1 A at 100 kHz tude to Richard Garvey, Bob Mammano, Bing Lu,
• ESR: < 3 mΩ and Bob Neidorff for their valuable discussions
during the preparation of this topic.
16. Verify the Design with a Bench Test
To verify the design’s performance, a physical vIII. references
converter needs to be built and bench tested.
Generally, one or more design iterations may be [1] “8-Pin High-Performance Resonant Mode
needed to meet all specifications and to optimize Controller,” UCC25600 Data Sheet, TI
the design. The final design used the following Literature No. SLUS846
parameters:
• Transformer turns ratio: n = 17:1:1 [2] “Using the UCC25600EVM,” User’s Guide,
TI Literature No. SLUU361
• Resonant network’s parameters: Lm = 280 μH,
Lr = 60 μH, and Cr = 24 nF [3] Bob Mammano, “Resonant Mode Converter
Topologies,” Unitrode Design Seminar, 1985,
Detailed design files and test results can be
TI Literature No. SLUP085
found in Reference [2]. Physical EVM boards are
also available from TI. Several critical test wave- [4] Bing Lu et al., “Optimal design methodology
forms are shown in Fig. 18 for immediate reference. for LLC resonant converter,” Applied Power
Electronics Conference and Exposition
V. Computer Simulation and FHA (APEC) 2006, pp. 533–538.
For designing an LLC resonant half-bridge
[5] S. De Simone, et al., “Design-oriented steady-
converter, it is strongly recommended that a
state analysis of LLC resonant converters
computer-based circuit-simulation method be used
based on first-harmonic approximation,”

26 SLUP263
International Symposium on Power Electron- [7] Thomas Duerbaum, “First harmonic approxi-
ics, Electrical Drives, Automation and Motion mation including design constraints,” Twentieth
(SPEEDAM) 2006, pp. S41-16 to S41-23. International Telecommunications Energy
[6] Hangseok Choi, “Analysis and design of LLC Conference (INTELEC) 1998, pp. 321–328.
resonant converter with integrated trans- [8] R.L. Steigerwald, “A comparison of half
former,” Applied Power Electronics Confer- bridge resonant converter topologies,” IEEE
ence and Exposition (APEC) 2007, pp. 1630– Transactions on Power Electronics, Vol. 3,
1635. No. 2, pp. 174–182, April 1988.
95
Topic 3
Input Voltage, Output Ripple Voltage 90 mV
Efficiency (%)
85 (50 mV/div)
Vin
405 V
390 V
375 V
75
65
1 5 10 15 20 25 Time (5 µs/div)
Load Current (A)
a. Efficiency. b. Output ripple voltage (full load).
VCr Vgs_Q2 (20 V/div)

1
(200 V/div)
1
(200 V/div) Ir
VL (1.2 A/div)
3 r 3
VLm
4
(200 V/div) VCr
(100 V/div)
Vds_Q2
(500 V/div)
2 4
Vds_Q2 (500 V/div)
2
Time (5 µs/div) Time (1 µs/div)
c. Voltage waveforms in resonant d. Resonant network’s current and

network (full load). voltage (full load).
Fig. 18. Critical test waveforms of the design.
3-27
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CONVERSORES CHAVEADOS DC-DC LINHA CHMC - Isolados - Automação Industrial

Os conversores DC-DC da MCE são ideais para uso industrial. Possuem alta eficiência e confiabilidade . Seu baixo custo permite utilização em larga escala.
Outros modelos poderão ser fornecidos sob encomenda.
Modelos
30W 100W 300W 725W
- Automação industrial
- Teste e medição
- Telecomunicações
- Áudio e vídeo
Aplicações Modelo Ve Vs Is Modelo Ve Vs Is Modelo Ve Vs Is Modelo Ve Vs Is
- Excelente desempenho CHMC 12-5-2 12V 5V 2A CHMC 12-5-5 12V 5V 5A CHMC 12-5-20 12V 5V 20A CHMC 12-5-30 12V 5V 30A
- Leve e compacta CHMC 12-12-2 12V 12V 2A CHMC 12-12-5 12V 12V 5A CHMC 12-12-20 12V 12V 20A CHMC 12-12-30 12V 12V 30A
- Alta eficiência CHMC 12-24-1 12V 24V 1A CHMC 12-24-2 12V 24V 2A CHMC 12-24-10 12V 24V 10A CHMC 12-24-20 12V 24V 20A
- Baixo custo CHMC 24-5-2 24V 5V 2A CHMC 24-5-5 24V 5V 5A CHMC 24-5-20 24V 5V 20A CHMC 24-5-30 24V 5V 30A
- Chaveamento em alta frequencia CHMC 24-12-2 24V 12V 2A CHMC 24-12-5 24V 12V 5A CHMC 24-12-20 24V 12V 20A CHMC 24-12-30 24V 12V 30A
- Proteção bateria baixa CHMC 24-24-1 24V 24V 1A CHMC 24-24-3 24V 24V 3A CHMC 24-24-10 24V 24V 10A CHMC 24-24-20 24V 24V 20A
- Proteção curto circuito CHMC 48-5-2 48V 5V 2A CHMC 24-48-2 48V 48V 2A CHMC 24-48-6 24V 48V 6A CHMC 24-48-10 24V 48V 10A
- Proteção contra sobre tensão CHMC 48-12-2 48V 12V 2A CHMC 48-5-5 48V 5V 5A CHMC 24-125-2 24V 125V 2A CHMC 24-125-4 24V 125V 4A
CHMC 48-24-1 48V 24V 1A CHMC 48-12-5 48V 12V 5A CHMC 48-5-20 48V 5V 20A CHMC 48-5-30 48V 5V 30A
CHMC 48-48-0,5 48V 48V 500mA CHMC 48-24-3 48V 24V 3A CHMC 48-12-20 48V 12 20A CHMC 48-12-30 48V 12V 30A
CHMC 125-48-0,5 125V 48V 500mA CHMC 125-48-2 125V 48V 2A CHMC 125-5-20 125V 5V 20A CHMC 125-12-30 125V 12V 30A
CHMC 250-5-2 250V 5V 2A CHMC 125-12-20 125V 12V 20A CHMC 125-24-30 125V 24V 30A
CHMC 250-48-0,5 250V 48V 500mA CHMC 125-125-5 125V 125V 5A
Dados técnicos
Limites da tensão de entrada ± 10% nominal ± 10% nominal ± 10% nominal ± 10% nominal
Isolação entrada / saída 1,5KV 1,5KV 1,5KV 1,5KV
Potência máxima saída 30W (conforme modelo) 100W (conforme modelo) 300W (conforme modelo) 725W (conforme modelo)
Ripple + ruído < 0,2% < 0,2% < 0,2% < 0,2%
Regulação de carga < 0,5% < 0,5% < 0,5% < 0,5%
Regulação de linha < 0,2% < 0,2% < 0,2% < 0,2%
Rendimento típico > 80% > 80% > 80% > 80%
Freq. chaveamento 100KHz 100KHz 60KHz 60KHz
Temperatura operação 0...60ºC 0...60ºC 0...60ºC 0...60ºC
Umidade 0...90%-sem condensação 0...90%-sem condensação 0...90%-sem condensação 0...90%-sem condensação
Filtro de entrada EMI sim sim sim sim
Proteção curto-circuito sim sim sim sim
Proteção aquecimento sim sim sim sim
Proteção sobretensão sim sim sim sim
Led power - on sim sim sim sim
Conexões bornes frontais bornes frontais bornes frontais bornes frontais
Rearme automático sim sim sim sim
Resfriamento convecção natural convecção natural ventilação forçada ventilação forçada
Fixação trilho DIN sim sim sim --------
Peso 300 g 600 g 1,5Kg 2,5 Kg
Dimensões L x A x P 37 x 75 x 115 mm 60 x 115 x 120 mm 85 x 175 x 160 mm 85 x 295 x 152 mm
Classe de proteção IP - 20 IP - 20 IP - 20 IP - 20
Invólucro / cor cx. metálica / preto fosco cx. metálica / preto fosco cx. metálica / preto fosco cx. metálica / preto fosco
Garantia 1 ano 1 ano 1 ano 1 ano
www.mcemicrotecnica.com.br / www.mctecnica.com.br
https://www.mctecnica.com.br/gerenciar-portal/area-adm/produto/0.363916001565109293.htm 1/1

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TND359/D

Disclaimer: ON Semiconductor is providing this reference design documentation

Figure 1: Reference Design Architecture Simplified Block Diagram

20% of 50% of 100% of

output output output

ENERGY STAR rev. 5.0

Table 1: Summary of Efficiency Targets

Input DC Output Current

Output Output Voltage Regulation (V) Tolerance Output Ripple

3.1 Primary Side: PFC Stage

3.2 Primary Side: Half bridge resonant LLC Converter

3.3 Secondary Side: Synchronous Rectification

3.5 Secondary Side: Monitoring and Supervisory Stage

3.6 Standby Power

Load as % of rated Output Current (A)

Table 3: Load Matrix for Efficiency Measurements

4.1 Total Efficiency

4.2 Power Factor

Table 6: Standby Power vs AC Line Voltage

4.4 Input Current

4.5 Inrush Current

4.7 Overshoot at Turn-On/Turn-Off

Measured and Calculated Data at 115V / 60HZ

Figure 2: Dynamic Load Test Waveforms

Output Ripple / Noise

4.8.1 100 VAC / 50 HZ - Ripple / Noise Test Waveform

No Load Full Load

No Load Full Load

No Load Full Load

No Load Full Load

No Load Full Load

Figure 3: 100 VAC / 50 HZ - Ripple / Noise Test Waveform

No Load Full Load

No Load Full Load

No Load Full Load

No Load Full Load

No Load Full Load

Figure 4: 115 VAC / 60 HZ - Ripple / Noise Test Waveform

No Load Full Load

No Load Full Load

No Load Full Load

No Load Full Load

No Load Full Load

Figure 5: 230 VAC / 50 HZ - Ripple / Noise Test Waveform

No Load Full Load

No Load Full Load

No Load Full Load

No Load Full Load

No Load Full Load

Figure 6: 240 VAC / 63 HZ - Ripple / Noise Test Waveform

4.9 Hold-up Time

Dropout Loading Measurement

Figure 7: Hold-up Time

4.10 Timing / Housekeeping / Control

AC On / Off Test Parameter Description

PS_ON On / Off Test Parameter Description

4.10.3 Logic Timings

4.11 Output Protection

4.11.2 Output Under-Voltage Protection