Design of CMOS Operational Amplifiers-Dehghani PDF

Design of CMOS
Dehghani
Operational
OS
Amplifiers
M
Rasoul Dehghani
C
Ra p at of
De rs l a
n
Am er n
so li io
Op sig
CMOS operational amplifiers (op amps) are one of the most important building
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Design of CMOS Operational Amplifiers
blocks in many of today’s integrated circuits. This cutting-edge volume provides
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De
professionals and students with an analytical method for designing CMOS op amp
circuits, placing emphasis on the practical aspects of the design process. Readers
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take an in-depth look at CMOS differential amplifiers and learn why and how they
serve as the main part of any op amp.
This book presents important details and design methodologies for different
architectures of single-ended op amps. Complete chapters are dedicated to
the critical issues of CMOS output stages, fully differential op amps, and CMOS
reference generators. Also included is an introduction to CMOS technology and a
discussion of the basics of the physical aspects of MOS transistors, providing the
foundation needed to fully master the material.
Rasoul Dehghani is an assistant professor in the Department of Electrical and

Computer Engineering at Isfahan University of Technology in Iran. He holds a
Ph.D. in electronics from Sharif University, Tehran, Iran. He is a well-published and
frequently cited author in the field.
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10 9 8 7 6 5 4 3 2 1
Contents
Chapter 1 Basic Specifications of Op Amps 1

1.1 Op Amp Parameters 1
1.2 Conclusion 13
Chapter 2 CMOS Technology and Physics 15

2.1 Basic Processes in MOS Transistor Fabrication 15
2.2 Principles of MOS Transistor Functioning 17
2.2.1 MOS Transistor Operating in Saturation Region 17
2.2.2 MOS Transistor Operating in Subthreshold Regime 21
2.3 Small-Signal Model of MOS Device 21
2.3.1 Gate to Substrate Capacitance 24
2.3.2 Gate to Source/Drain Capacitance 26
2.3.3 Source/Drain to Bulk Capacitance 27
2.4 Conclusion 31
Chapter 3 CMOS Differential Amplifiers 33

3.1 Source-Coupled Differential Pair Characteristic 33
3.2 CMOS Differential Amplifier with Active Load 36
3.2.1 Large-Signal Characteristic of CMOS
Differential Amplifier 36
3.2.2 Offset Voltage of CMOS Differential Amplifier 38
3.3 Common-Mode Behavior of CMOS Differential Amplifier 42
3.4 CMOS Differential Amplifier Frequency Response 43
3.5 Noise Calculations in CMOS Differential Amplifier 47
3.6 Conclusion 53
Chapter 4 CMOS Single-Ended Output Op Amps 55

4.1 CMOS Two-Stage Op Amp 55
4.1.1 Offset Voltage 56
4.1.2 Two-Stage Op Amp Frequency Response 59
4.1.3 CMOS Two-Stage Op Amp Design Procedure 65
Design Example 69
4.1.4 PSRR of CMOS Two-Stage Op Amp 72
4.2 Telescopic Cascode Op Amp 83
4.3 Folded-Cascode Op Amp 86
Design Example 87
4.4 Current Mirror Op Amp 90
Design Example 94
4.5 Rail-to-Rail Input Op Amp 96
4.6 Conclusion 105
vi Contents
Chapter 5 CMOS Fully Differential Op Amps 107

5.1 Advantages of Fully Differential Op Amps 107
5.2 Common-Mode Feedback Concept 109
5.3 Common-Mode Feedback Circuits 111
5.3.1 Common-Mode Feedback Circuit with Resistive
Sensing 112
5.3.2 Differential Difference Common-Mode Feedback
Circuit 114
5.3.3 Common-Mode Feedback Circuit Using MOS
Devices Operating in the Triode Region 118
5.3.4 Switched-Capacitor Common-Mode Feedback Circuit 119
5.4 Fully Differential CMOS Op Amp Architectures 123
5.4.1 Fully Differential Two-Stage Op Amp 123
5.4.2 Fully Differential Current Mirror Op Amp 127
5.4.3 Fully Differential Folded-Cascode Op Amp 129
Design Example 130
5.5 Conclusion 134
Chapter 6 CMOS Output Stages 135

6.1 Class A and Class B Output Stages 135
6.1.1 Source-Follower as an Output Stage 135
6.1.2 Class B Power Amplifier 139
6.2 Drain-Coupled Complementary Transistors as Output Stage 142
6.3 Low-Voltage Class AB Buffer 149
6.4 Class AB Output Stage Using a Translinear Loop 153
6.5 Case Study 159
Design Example 163
6.6 Conclusion 166
Chapter 7 CMOS Reference Generators 167

7.1 CMOS Voltage Reference Generators 167
7.1.1 Bandgap Voltage Reference Generator 168
Design Example 170
7.1.2 Low-Voltage Bandgap Reference Generator 173
Design Example 174
7.1.3 CMOS Voltage Reference Generator without Resistors 176
7.2 CMOS Current Reference Generators 180
7.2.1 Gm-Constant Circuit 182
7.2.2 Fully Integrated Precision CMOS Current Reference 186
7.2.3 CMOS Current Reference without Resistors 188
Design Example 191
7.3 Conclusion 193
Index 195
Chapter 1
Basic Specifications of Op Amps
An operational amplifier is one of the most important building blocks in many

analog systems. For instance, in an integrated analog filter such as a switched-
capacitor or a Gm-C filter, the op amp is an integral part of the circuit. Data
converters including both analog-to-digital and digital-to-analog converters are
other categories in which the op amp plays a fundamental role to achieve the
desirable performance. In voltage and current reference generators an op amp has
remarkable influence on the operation of these circuits. In the enumerated
instances many parameters of the system are extensively dependent on the
specifications of the op amps used in that system. It should be noted that the
criteria applied to the design of an op amp employed in such systems are usually
different from those used for designing a general-purpose op amp that is to be
available as a stand-alone component in discrete circuitries. In general, the
behavior of an op amp is described by many different parameters in which some of
them might be more important than others in a particular analog system. In this
chapter we introduce the main op amp parameters that have significant impact on
the behavior of an analog system where an op amp has been exploited.
1.1 Op Amp Parameters
DC gain: Ideally the value of this parameter is considered infinity but in reality,
due to the limited intrinsic voltage gain of each device used in the op amp circuit,
the entire gain of an op amp has a finite value in the typical range of to
(40 dB-100 dB). Exploiting an op amp in a linear amplifier involves putting the op
amp in a negative-feedback loop. In this situation a high dc gain of the op amp
could be essential. In the following we demonstrate the reason for such an
assertion. Supposing that the open-loop gain of the feedback is quite high, we can
calculate the closed-loop gain of the circuit based on the values of the feedback
network components independent of the op amp parameters. As an example
consider the inverting feedback amplifier shown in Figure 1.1. Denoting the
low-frequency voltage gain of the op amp as , we can calculate the exact
2 Basic Specifications of Op Amps
C2
C1
vi −
vo
+
Figure 1.1 Inverting feedback amplifier.
closed-loop voltage gain as

(1.1)
Where is the feedback factor. If it is assumed that ,

(1.1) can be approximated as . In an ideal case, for
, the amplifier gain is completely independent of the op amp gain and
equals . In practice, for a particular feedback gain error, we need to increase
the op amp gain above a certain level. For example, ideal feedback gain of
2 with an error less than 0.1% is achievable provided that
or if we have . Thus, in order to achieve more accurate
feedback gain the dc gain of the op amp needs to be quite high.
Limited linearity range. For a certain level of the input and output signal
variations, the internal devices of op amp operate in the linear part of their
characteristics. At input, the devices remain in their active operation region when
the variation range of the input common-mode voltage is limited to a particular
range known as input common-mode range (ICMR) [1]. This parameter depends
on the op amp structure and the type and biasing conditions of the input devices.
The linear operation range for a differential input signal in an open-loop state is
much more limited. Of course when an op amp is used in a negative-feedback
loop, the linearity behavior is significantly improved by the feedback mechanism.
An amplified signal at the output of an op amp can also swing in the limited range
at the most between two supply rails, although its precise level depends on the
particular structure utilized as the output stage.
Common-mode rejection ratio. One of the most outstanding advantages of an op

amp is its capability to amplify the difference of two input signals without output
being affected significantly by the changes in the input common-mode level. This
property results in immunity against any common-mode undesirable signal that
might appear at the inputs of the op amp. The parameter of common-mode

rejection ratio (CMRR) is used to quantify this performance [2]. The definition of
this parameter is a little bit different for the two types of op amp. In a fully
differential op amp in which both input and output signals are differential, the
differential-mode and common-mode components of the output voltage are
expressed as a linear combination of the corresponding input voltages as follows
!"# $# !%$ ## !%# (1.2a)
!"$ $$ !%$ #$ !%# (1.2b)
where ## and $$ are differential-mode and common-mode voltage gains,

respectively. $# and #$ exhibit the contribution of the common-mode and
differential-mode of the input; that is, !%$ and !%# in their corresponding
components in the output voltage, respectively. In an ideal differential op amp
with a fully symmetrical structure, we have $# #$ but in reality, due to
the device mismatches in the path of each input to two other outputs, this is not the
case. In this situation, CMRR is defined as the ratio of the differential voltage
gain ## to the common-mode to differential-mode voltage gain $# as
& ''() * ++
* (1.3)
,+
where & ''() denotes the fully differential CMRR. To measure the & ''() ,
we might exploit the circuit illustrated in Figure 1.2. The fully differential op amp
is configured as a unity voltage gain amplifier in a negative-feedback loop. The
internal common-feedback circuit and the external negative-feedback cause the
the common-mode reference voltage denoted by -$. . Representing the voltages at

output common-mode voltage and also the dc level of each output to be kept on
the inverting and noninverting inputs of the op amp as ! / and ! , respectively, we

can easily find these voltages as follows
!/ !" -$. -$0 (1.4a)
! !"/ -$. -$0 (1.4b)
From the above relations, the input differential-mode and common-mode voltages
are obtained
!%# ! !/ !"# (1.5a)
!%$ ! !/ !"$ -$. -$0 (1.5b)
R vo+
- + +
vod
R
+ - -
vo-
Vcm
R
+
Vcr
-
Figure 1.2 Test circuit used to measure the CMRR for a fully differential op amp.
By substituting (1.5a) and (1.5b) into (1.2a) and simplifying the result, we get
1,+
!"# 2
1++ !"$ -$. -$0 (1.6)
2
Now when the input voltage of -$0 is changed by 3-$0 , the terms of !"$ and -$.
have no variation and thus we have 3!"$ 3-$. . That gives
1,+
3!"# 2
1++ 3-$0 (1.7)
2
Since ## , we have
34 + ,+
34,5 67 889:
(1.8)
++
It should be emphasized that the gain of $# is not zero only when the
mismatches in the op amp circuit are considered. As a result, we have to perform
corresponding voltage gain of 3!"# 3-$0 for each run. Since the amount of the
an ac analysis for several Monte Carlo simulation runs and obtain the
be used to calculate the typical & ''() . As an example, in a fully differential op

mismatch changes in each run, we get various voltage gains whose mean value can
amp, 100 runs of Monte Carlo analysis give 3!"# 3-$0 ;< = >? as the mean
value of the data with a standard deviation of @ A = >? and thus for this op amp
the typical value of the CMRR becomes ;< = >?. The worst-case value could
reach B >? in the range of C@.
In an op amp with single-ended output the output voltage is represented by
!" #0 !%# $0 !%$ (1.9)
where #0 and $0 are differential-mode and common-mode voltage gains,

respectively. Here CMRR is defined as
& ''DE * +5
* (1.10)
,5
where & ''DE indicates the CMRR of a single-ended output op amp. As it will
be shown in the next chapters, in a fully differential op amp a high CMRR is
achievable by implementing a fully symmetrical circuit to minimize $# . In a
single-ended one, even when the op amp has a perfect symmetry in an ideal
condition, the CMRR would be limited by the output resistance of the tail current
source used in the differential pair. One method to measure the CMRR for a
! -$0 and ! / !" -$0 . Since !%# ! ! / and !%$ ! !/

single-ended output op amp is shown in Figure 1.3 [3]. In this circuit we have
, by
substituting these relationships into (1.9), we can write the output voltage as
!" #0 !" $0 F-$0 G (1.11)
Rearranging (1.11), we obtain the transfer function as
,5
1,5
4,5 +5 / 2
(1.12)
Noting that #0 H $0 , we see that the inverse of the obtained gain in (1.12)
approximately gives the & ''DE .
Offset voltage. The device mismatches in the input stage have the most
Vcm
−
+
−
vo
+
+ V
− cm
Figure 1.3 Measurement of the CMRR parameter for a single-ended output op amp.
contribution in this parameter. It is interesting that the nonzero common-mode
that, from (1.9) for !%# , we have !" $0 !%$ . This means the op amp output
voltage gain of an op amp also contributes to the input offset voltage [4]. To see
voltage varies in response to the input common-mode voltage variation in spite of

the fact that the differential mode of the input voltage has no variation. In this
situation, the op amp can be thought of as an ideal op amp in a sense that it just
reacts to the differential mode of the input voltage and the effect of the input
with the value of -%HIJ !" #0 or -%HIJ $0 !%$

common-mode changes is attributed to an equivalent differential input voltage
#0 . Therefore in an op amp
with nonzero common-mode voltage gain, the voltage of -%HIJ -%$ & '' is
added to the input-referred offset voltage. The main parameters of an op amp that
affect the offset voltage will be discussed in more detail in the next chapters.
Figure 1.4 represents two circuits to measure the offset voltage of single-ended
and fully differential op amps. Both op amps are configured as a voltage follower
without any external input. The left-side circuits depict the real op amps including
mismatches with finite CMRR.
All nonideal effects that create the offset voltage such as mismatches and
nonzero common-mode voltage gains of $0 and $# have been modeled by a dc
voltage source denoted by -"K that is placed in series with the input of an ideal op
!" #0 !%# and !"# ## !%# . Summing voltages around the loop from the
amp. Hence, the output voltage relationships for two types in an ideal case are
output to the input yields !%# -"K !" for the single-ended op amp and
!%# -"K !"# for the other one. Substituting these relationships into the
corresponding equations of the output voltages gives us the offset voltages as
Real includes mismatches
Ideal
− - −
vo vo
vid
+ + +
Vos +
−
(a)
Real includes mismatches
Ideal
− + - − +
+ vid +
vod vod
+ - - + + - -
+
−
Vos
(b)
Figure 1.4 Test circuits for (a) single-ended (b) fully differential op amp offset voltage.
!"HDE -"K #0 #0 and !"H() -"K ## ## for single-ended and

fully differential types, respectively. Since #0 H ## , the output voltages of
both circuits nearly represent the offset voltage. It should be pointed out that
similar to the method used for measuring CMRR of a fully differential op amp, the
op amp offset voltage can be obtained by running several Monte Carlo analyses on
the circuits of Figure 1.4 and taking the standard value of the data as the op amp
offset voltage. In the absence of systematic errors the mean value of the offset
voltage is almost zero.
Frequency bandwidth. The open-loop voltage gain of an op amp begins to drop

as frequency increases. This happens because of internal parasitic capacitances in
the op amp circuit. The bandwidth parameter is important because by dropping the
op amp voltage gain, the closed-loop gain would not be independent of the op amp
parameter anymore. In fact, the frequency bandwidth expresses how fast an op
amp can follow the time variations in the input signal. It is obvious that to amplify
fast signals we need to employ an op amp with adequate large bandwidth in such a
way that it can provide enough loop gain at maximum operating frequency. The
parameter denoted by LM , as illustrated in Figure 1.5. As its name suggests, LM is a

speed performance of an op amp is usually measured by the unity gain bandwidth
frequency at which the magnitude of the gain reaches unity. When an op amp is
instability problem at frequencies near LM . Thus the op amp should be properly

used as a voltage follower in a negative-feedback loop, it might suffer from the
designed to have an acceptable amount of stability in the frequency domain [5].
Slew rate. This parameter is used to express the time speed limitation of an op
Av(jω)
Av0
ωp2 ω
0 ωp1 ωu
Figure 1.5 Op amp voltage gain versus frequency.
vi(t)
Input step voltage
V
t
0
−
vo(t) vo(t)
Output response
vi(t) + V
(a) tsettle
tslew
t
0
(b)
Figure 1.6 (a) Voltage follower, and (b) time response of voltage follower to input step voltage.
amp output. When an op amp is placed in a negative-feedback loop and a rather

large-signal is applied to its input, the output cannot follow the rapid changes in
the input signal. This is another speed limitation in op amps that is raised in
conjunction with the large-signal behavior of op amps. Indeed, unity gain
bandwidth indicates the limitation of an op amp to follow the fast input signals
with very small amplitude while slew rate is considered an index of op amp large-
signal time response [6]. In some applications such as pipeline analog-to-digital
converters, both parameters play a key role in determining the maximum
achievable speed for the converter [7]. The response of a voltage follower to a step
voltage applied as input is plotted in Figure 1.6(b). As it can be seen, the output
time response consists of two parts. The first part is the time duration that the
output voltage changes from its initial value to approach its final level. This part is
associated with the limited op amp slew rate. The second part starts when the
difference between input and output voltages is small. Now the small-signal
frequency response of the op amp determines how long it takes to reach its steady
state. This time, known as settling time, is illustrated in Figure 1.6(b).
Noise. A complementary metal oxide semiconductor (CMOS) op amp is made of

several numbers of n-type MOS (NMOS) and p-type MOS (PMOS) transistors.
Channel thermal noise and flicker noise are two main noise sources in each MOS
device [8]. The total noise generated by each device is represented by two
generally correlated noise voltage and noise current generators at the input of an
op amp. Flicker noise has a higher level of energy at low frequencies while
thermal noise has a flat spectrum in the frequency domain. The variation of the
spectral density of the input-referred noise voltage including both flicker and
thermal noises is plotted in Figure 1.7. In this plot the thermal noise and flicker
Vn 2
f
Kf
f
4kTReq
f
0 fc
Figure 1.7 Spectral of input-referred noise voltage.
noise asymptotes intersect each other at a frequency called the flicker noise corner
frequency that is denoted by $ . In submicron CMOS technology, due to some
physical effects such as the hot electron effect, the level of the thermal noise in the
MOS device increases. According to Figure 1.7, the part of the frequency band
that is less than $ is mostly influenced by the flicker noise. At the frequencies
near zero there is no noticeable difference between the input offset voltage and the
flicker noise at the input.
Power supply rejection ratio. The amount of supply noise or any other
disturbances on the supply rail that can find its way to the op amp output depends
on this parameter [9]. Mathematically the power supply rejection ratio (PSRR) in
an op amp is defined as
NO'' P +P (1.13)
Q
where # is the differential voltage gain of the op amp and R is the voltage gain
from each supply to the op amp output. Supposing the op amp as a linear circuit,
we express its output voltage as a linear combination of the differential input
voltage and the noise voltage on the supply
!" # !%# R !R (1.14)
In (1.14) the first term is the desirable signal component and the second one
indicates the amount of supply noise at the output. Indeed, PSRR represents the
have two supply rails, two parameters of NO'' and NO''/ are usually defined
ratio of the desired signal to the supply noise at the op amp output. Since op amps
in which the corresponding voltage gain from positive and negative supply is
denoted by R and /R , respectively. In an integrated analog mixed-mode circuit
where different analog and digital blocks are fabricated on the same chip, special
attention should be paid to the PSRR parameter of op amps used in the circuit
[10]. For example, if the PSRR of an op amp is not good enough, any existent
noise on the supply rail such as digital noise created by the system clock can reach
the op amp output and amplified by the next stages can easily corrupt the quality
of the ultimate output signal. In addition, the behavior of PSRR at higher
frequencies is also important. In fact, the magnitude of this parameter at high
frequencies determines the amount of high-frequency supply noise that impacts on
the op amp output signal. In practice, PSRR can be measured by employing the
circuit shown in Figure 1.8. Assuming a finite differential voltage gain of # for
op amp and denoting the voltage gain from supply to the output by R , we can
write
!" R !R # !" (1.15)
Rearranging (1.15), we have
!" Q
!R (1.16)
+
Since # , we can obtain the PSRR as
NO'' Q
(1.17)
The circuit in the path from positive supply to the output is generally different
from the other path from negative supply to the output; thus, two different PSRR
parameters are usually defined for two op amp supply rails.
−
+ vo
Ad
vo
- +
+
vp
Figure 1.8 Circuit used to measure PSRR.
PSRR in a fully differential op amp has a similar relationship given in (1.13)

in which # is replaced with ## . It should be pointed out that if the circuit of the
fully differential op amp has perfect symmetry in an ideal case, the noise of supply
appears equally on both outputs and as a result there is no differential output
voltage. In reality, device mismatches in the op amp circuit reveal their
contributions as nonzero differential output voltage. Thus the mismatch is
responsible for nonzero PSRR in fully differential op amps. This means that to
& ''() . We can use the circuit of Figure 1.2 in which an ac voltage source is
measure PSRR we have to follow the procedure that was given to measure
placed in series with the supply while just common-mode voltage reference -$. is
applied to the input. Repeating the given method for CMRR calculation, we obtain
3!"# Q
1++ 3!R (1.18)
2
Equation (1.18) represents the change in the differential output owing to the
variation in the supply voltage. The parameter R denotes the voltage gain from
supply to the output. Since ## , from (1.18), PSRR is given by
NO'' ++
3S + (1.19)
Q
3SQ
By performing Monte Carlo analysis we can obtain the voltage gain from supply
to the differential output in different runs. Such simulation on the previous
3!"# 3!R A T >? as the mean value of data that based on (1.19) gives
example given for CMRR calculation produces the result of
NO'' A< T >? while its standard deviation is @ ; >?. This result reveals
that in the op amp of our example, the supply noise compared to the input
common-mode voltage variation is more effectively passed to the op amp output
in the presence of mismatches.
Table 1.1
Some Main Parameters of a Typical CMOS Op Amp
Value in
Parameter Parameter Typical Value
Relationship Ideal Unit
Name Symbol in a Real Op Amp
Case
DC voltage
gain 4 Depends on structure Infinity 40-120 dB
= W &'
-))
-%$H0UV -%$H0UV -))
Input
common- ICMR (e.g., in a simple V
mode range NMOS input op
amp)
Fully differential
* ++ *
Common-
mode ,+
CMRR Infinity > 80 dB
rejection Single-ended output
ratio op amp * +5*
,5
Depends on
-"K
Offset mismatches in
Zero <5 mV
voltage threshold voltage
and sizing
LM
op amps X0H%Y Z
Unity gain In most single-stage
Infinity < 100 MHz
bandwidth
Slew rate SR Usually as W Z Infinity = [ \]
Power
P +5
P
supply
PSRR Infinity > 80 dB
rejection Q
ratio
^ àb
Input- Channel thermal
-Y c[ dà
^ _ àb ;
referred noise and flicker
Zero
noise noise referred to the
voltage input
1.2 Conclusion 13
1.2 Conclusion
In this chapter, several important dc and ac parameters of op amps were

introduced and some methods were presented that can be used to measure these
parameters. The discussed parameters are associated with both single-ended output
and fully differential op amps. We have summarized some main parameters of a
typical CMOS op amp that were briefly discussed in this chapter as illustrated in
Table 1.1. It is worth keeping in mind that the exact relationship for each
parameter in this table depends extensively on the particular structure used in the
op amp circuit that will be the subject of the next chapters. The given numerical
data for some parameters indicate typical values that are usually observed in
currently designed CMOS op amps.
References
[1] Huijsing, J., Operational Amplifiers: Theory and Design, Second Ed, Springer, 2011.
[2] Baker, R. J., CMOS: Circuit Design, Layout, and Simulation, Third Ed, John Wiley & Sons,
2010.
[3] Allen, P. E., Holberg, D. R., CMOS Analog Circuit Design, Second Ed, Oxford University Press,
2002.
[4] Mancini, R., Carter, B., Op Amps for Everyone, Third Ed, Elsevier Inc., 2009.
[5] Ivanov, V., Filanovsky, M., Operational Amplifier Speed and Accuracy Improvement: Analog
Circuit Design with Structural Methodology, Kluwer, 2004.
[6] Baher, H., Signal Processing and Integrated Circuits, John Wiley & Sons, 2012.
[7] Plassche, R., V., D., CMOS Integrated Analog-to-Digital and Digital-to-Analog, Second Ed,
Boston, Kluwer Academic Publisher, 2003.
[8] Bhattacharyya, A. B., Compact MOSFET Models for VLSI Design, John Wiley & Sons, 2009.
[9] Shepherd, P. R., Integrated Circuit Design, Fabrication and Test, McGraw-Hill, 1996.
[10] Gejji, V. P., Analog and Mixed Mode VLSI Design, PHI Learning Private Limited, New Delhi,
2011.
Chapter 2
CMOS Technology and Physics
A part of the limitation in the performance of a CMOS circuit is related to how it

is implemented. Therefore a comprehensive perception of the CMOS circuit
fabrication and the required steps to get the final desirable circuit can significantly
aid in achieving a successful design. Furthermore, the advanced semiconductor
industry necessitates a close and tight collaboration between circuit designers and
process engineers, who need to understand their languages in order to exchange
information about possible technological capabilities and also existent constraints
in the fabrication process. In this chapter, we briefly describe the main sequence of
steps that are followed in the fabrication of an MOS transistor. Next, we introduce
the electric current equation for this kind of transistor and based on the physical
operation we present a complete small-signal model of the device. In the given
analysis we will refer to some physical effects such as short-channel behavior, and
subthreshold operation region and their impact on the circuit design. Interested
readers are referred to the references at the end of the chapter for deeper
discussions.
2.1 Basic Processes in MOS Transistor Fabrication
In an n-well process in which all PMOS transistors are to be put inside the n-wells,
the first step is to create an n-well inside the substrate of a p-type. The ion
implantation technique is usually used to create an n-well region. The next step is
to create isolation areas between adjacent transistors by growing a thick oxide
layer under which an extra ion implantation called channel-stop is done to increase
the effective threshold voltage of this area. After applying some trimming on the
threshold voltage of the active area, the gate pattern is defined and then the
source/drain junctions and also p-substrate and n-well contacts are formed by two
individual ion implantations for two NMOS and PMOS devices. After
source/drain ion implantation, a thermal process needs to be done and thereby the
damaged lattice structure is fixed. This process is known as annealing. Because of
the thermal process in the annealing, the impurity atoms in these areas penetrate
15
16 CMOS Technology and Physics
underneath the gate electrode due to lateral diffusion. The overlapped part of the
gate with the extended part of the source/drain regions creates an overlap parasitic
capacitance between the source/drain and gate terminals. These capacitances,
especially one that is formed between the gate and drain, can affect significantly
the frequency response of the circuits particularly in analog designs. Figure 2.1
summarizes the main steps mentioned above to fabricate two types of MOS
devices. The subject of CMOS technology and the fabrication process can be
found in [1-5] in much more detail.
Gate Oxide
sio2
Creation of n-well
in p-substrate (1) n-well
p-substrate
Gate Oxide Field Oxide

sio2
Channel-stop and threshold Channel-Stop
adjust implant and (2) n-well
growth of field oxide
p-substrate

sio2
Deposition of polysilicon gate Channel-Stop
of NMOS and PMOS devices (3) n-well
p-substrate

sio2
n+ n+ p+ p+ n+
Implantation of source, drain, and Channel-Stop
n-well contacts using two S/D of PMOS
individual masks in two steps for (4) S/D of NMOS
n-well n-well ohmic
NMOS and PMOS devices p-substrate contact
Figure 2.1 Main steps of MOS device fabrication.
2.2 Principles of MOS Transistor Functioning
Shown in Figure 2.2 is the cross-section view of an NMOS transistor. When a

positive voltage is applied to the gate, since the majority carries of the substrate
are the holes, they are repelled toward the bulk and as a result, a charge space of
the negative ions leaves behind at the surface. In device physics this operating area
of the device is known as the depletion mode. By increasing the gate voltage in the
positive direction the proper condition is provided for the majority carriers in the
source region to be injected into the substrate. More positive gate voltage causes
growth of electrons and at the same time reduction of the number of holes. This
ultimately leads to inverting the type of the semiconductor from p-type to n-type at
the surface. For a certain level of the gate-source voltage, the density of electrons
in the created inversion layer would be that of the substrate holes. In this situation
the transistor operates at the edge of a state called strong inversion. The
inversion condition is known as the threshold voltage and is denoted by -e . For

corresponding gate-source voltage that puts the device at the edge of the strong
-fD -e , the electrons concentration of the inversion layer is less than that of
the substrate holes and the transistor is in a state called weak inversion. This
operating area is known as the subthreshold region. In the following sections we
deal with the MOS functioning in these two operating areas.
2.2.1 MOS Transistor Operating in Saturation Region
In the presence of the conductive layer in a strong inversion state, an applied

voltage between the drain and source creates an electric field along the channel
and writing the channel conductivity in terms of inversion charge g%Y , it is shown
and makes the current flow from the source to the drain. By utilizing Ohm’s law
that [6] for a long-channel device the drain current equation in the triode region
can be approximated by a quadratic relationship that is a function of the gate-
S G D
FOX n+ n+ FOX
inversion layer
p_substrate
Figure 2.2 Cross section of an NMOS device.
source and drain-source voltages.

2
W) hY "V Z j -fD -e -)D l
i 4:k
(2.1)
where hY is the electron mobility in the inversion layer, "V m"V n"V is the gate
oxide capacitance per unit area with m"V as the oxide permittivity and n"V as the
gate oxide thickness, and o and p are the transistor channel width and length,
respectively. At a given -fD -e , increasing the drain-source voltage causes the
ultimately for -f) -e the electron charges at drain almost disappear such that
density of the free electrons of the inversion layer at the drain side to decrease, and
the device is put at the edge of the saturation region. The certain value of the
drain-source voltage at which the device is at the edge of saturation will be
-)D HKUq -fD -e (2.2)
For -)D -)D HKUq , the depletion region of the drain-bulk junction extends toward
the source. The excess voltage of -)D -)D HKUq extends across the depletion region
kept on -)D HKUq . This situation is very similar to the behavior of a bipolar junction
of the drain to the bulk junction and the voltage drop across the inversion layer is
transistor (BJT) operating in an active forward region in which the major part of
the collector to emitter voltage drops across the reverse-biased collector-base
junction and a small part of the total voltage drops across the forward-biased base-
emitter junction. To make clear the operation of the MOS device in saturation, the
drain-bulk junction and the inversion layer can be modeled by the series
connection of a reverse-biased diode indicating the drain-bulk junction and a
For a given constant -fD , -)D HKUq -fD -e is constant and thus the drain
resistor representing the inversion layer resistance, as illustrated in Figure 2.3.
current is fixed. In practice, by increasing the drain-source voltage, the voltage of
VGS=cte VDS D
+
+
S G D VDS-VDS,sat
VDS -
+
FOX n+ n+ FOX
Rch VDS,sat
L -
ID
∆L
Leff -
p_substrate S
Figure 2.3 MOS operation in a saturation region.
-)D -)D HKUq across the drain to bulk junction increases, which results in
extending the depletion area toward the source region. This causes the effective
length of the inversion layer to decrease, and as a result, the inversion layer
resistance slightly reduces. This effect leads to gradually increase the drain
current, which is known as channel length modulation. This phenomenon shows
itself as a small positive slope on the MOS output characteristic, as depicted in
Figure 2.4.
The drain current equation including the channel length modulation effect is a
quadratic equation in which channel length is replaced by an effective length as
W) hY -fD -e
i
"V Z (2.3)
rss
where pI p 3p with 3p as the depletion region width of the one-sided drain

junction [7]
3p -)D -)D HKUq

uv
tJw (2.4)
vxy
The slope of the curve shown in Figure 2.4 in saturation is denoted by X#K and can
be calculated by taking the derivation of (2.3) in terms of implicit variable -)D
z{: zZrss
X#K
z{:
z4:k zZrss z4:k
(2.5)
X#K |W) where the parameter | defined as

Using (2.3) and (2.4) and after some simple manipulations on (2.5), we have
ID
VGS=cte
slope=gds
VDS
0 VDS,sat
Figure 2.4 MOS characteristic in saturation with channel length modulation effect.
| }#K €~ pI t-)D -)D HKUq • (2.6)
where }#K • mK ‚ƒKM„ . Supposing 3p … p, (2.6) can be approximated as
|† F G
‡+v ‡+v
Zt4:k /4:k Hvˆ‰ Z
(2.7)
The parameter X#K is the dynamic conductance between drain and source terminals
of an MOS device and plays an important role in all MOS amplifiers. In fact, for a
given MOS transconductance, the maximum achievable voltage gain is determined
if the exploited MOS devices have minimum possible |. For a particular drain
by this parameter. In a CMOS current source, high output resistance is achievable
current, a practical way to minimize | is to use the maximum possible channel

length for MOS devices and also to increase the drain-source biasing voltage
and drain biasing conditions have usually less X#K in comparison to their NMOS
based on (2.7). It is interesting that PMOS transistors at the same channel length
counterparts. This is because PMOS devices are fabricated inside the n-well and
doping concentration of the n-well is usually greater than the impurity density in
channel length and biasing condition, }#K is smaller for the PMOS device. As an
the p_substrate of NMOS devices. Consequently at the same condition in terms of
p_substrate is ƒKM„ <C ‹ •Š/Ž and the doping density in n-well is

example, in a 0.25-\Š CMOS technology the impurity concentration in the
Œ
ƒ• I•• T = ‹ Œ
•Š , and as a result, factor ‘#K of the NMOS device is
/Ž
about < times of its corresponding factor in a PMOS device that leads to the
same increase in the parameter of | in the NMOS transistor.
Any potential difference between the source and bulk in an MOS device
increases the effective threshold voltage of the device according to the following
relationship [8]
-e -e ’“• ”• -D• • ”• – (2.8)
where -D• is the potential difference of the source and substrate and -e is the
threshold voltage with -D• . The parameters ’ and ”• are defined as
’
• uv Jwvxy
6 —
(2.9)
”• ™c
˜e wvxy
J Y
(2.10)
where ”• is the Fermi potential with respect to the midgap in the substrate,
‘ CA ‹ / Ž š › œ is the effective threshold voltage, and •% is the carrier

concentration in an intrinsic silicon and equals = ‹ •Š/Ž at C ž œ. The
parameter ’ depends on the technology parameters. For example, in a 0.18- Š
CMOS technology with n"V T cŠ and ƒKM„ C ; ‹ Œ
•Š/Ž (2.9) gives
’ TCd[. In this technology the zero-bias threshold voltage is equal to
-e T=[ and based on (2.10) we have ”• TT[. If there is a potential
difference of -D• =[ between source and bulk, with ’ TCd[, the effective
threshold voltage due to body effect changes to -e ==[ according to (2.8).
2.2.2 MOS Transistor Operating in Subthreshold Regime
For -fD -e , an MOS device works in weak inversion with the low density
of free carriers inside the inversion layer under the gate. In this situation, by
applying a drain-source voltage we will have a current with different nature. Here
the main cause of current flow is the diffusion effect that occurs due to
nonuniform distribution of the free carriers inside the inversion layer. In device
physics contexts [8], it is proven that the drain current follows an exponential
relationship similar to BJTs as
¡k ¢ £
W) W F GŸ
i ¤ ‰¥
Z
(2.11)
where W is the reverse saturation current and for an NMOS device is given by
ª :k
W hY -q¦ t © Ÿ/ ¬
uv Jwvxy
«£
§¨
(2.12)
In (2.11) o and p are the transistor channel width and length, respectively. - is
equal to #IR "V with #IR as the depletion capacitance per unit area and -q¦
is the thermal voltage.
2.3 Small-Signal Model of MOS Device
In the preceding drain current equations, the drain current generally changes as a
(i.e., !)D , !fD , and !D• ).

function of the voltages of the drain, substrate, and gate with respect to the source
®) !)D H !fD H !D• (2.13)
In (2.13) the instantaneous total value of each voltage has been indicated by
lowercase letters with uppercase subscripts. Supposing the amplitude of the ac
components is small enough in comparison to the bias values, we can write the
variation of the drain current as a linear combination of the voltage variations
3® ) * 3!fD * 3!)D * 3!D•

z%: z%: z%:
z ¡k 4 z :k 4 z k¨ 4
(2.14)
¡k :k k¨
The bias quantities are shown by capital letters for both voltage notations and their
subscripts. All derivatives are calculated at the bias points. The first and last terms
in (2.14) indicate the influence of gate-source and substrate-source voltage
variations on the drain current and thus are modeled by two different voltage-
controlled current sources. The second term represents the channel length
modulation that is modeled as a resistor across the drain-source in the equivalent
small-signal circuit. Denoting the ac component of each voltage by lowercase
letters for voltage name and its subscript, the drain current variation around its
quiescent value can be written in terms of ac components of the gate-source, drain-
source, and bulk-source voltages as
®# X0 !¯K X#K !#K X0„ !K„ (2.15)
If the strong inversion state is held and the transistor operates in saturation region,
using (2.3) we can obtain the transconductance relationship in terms of the
transistor parameters as
X0HKUq * • °W)
z%:
z ¡k 4
(2.16)
¡k
where ° hY "V o pI . When the transistor works in the subthreshold we

should use (2.11) to calculate X0 .
X0HKM„ *
z%: {:
z ¡k 4 ±4‰¥
(2.17)
¡k
As it is evident from (2.17) the transconductance of the MOS transistor when it

works in the subthreshold region is independent of its dimensions and controlled
only by the drain bias current. On the other hand, when the transistor operates in
saturation, for a certain drain bias current, based on (2.16) by raising the transistor
aspect ratio (W/L), it is possible to have larger transconductance. In such a
saturation. At a fixed drain current level of W) , when the quantity of W o p in

condition there is an upper limit at which the transistor still continues to operate in
(2.11) becomes greater than W) , -fD becomes less than -e and thus transistor enters
the subthreshold region in which the transconductance does not increase anymore
by raising the transistor sizing. We can get a rough estimation of the onset of
entering the subthreshold regime by equating the MOS transconductance
corresponding to two regions to arrive at the following relationship
h --q¦
{:
² "V
F G
(2.18)
³
where o p is the transistor size for that (2.16) and (2.17) are equal. Equation
(2.18) gives a rough criterion to find the correct MOS operating area in terms of
o p o p , an MOS device enters the subthreshold region that is

the given process parameters. At a certain dc drain current, when we have
equivalent to the transition from the strong inversion to the weak inversion state.
a moderate inversion state. Bearing this point in mind, the ratio of W) o p

In reality, this transition does not happen sharply but the transistor passes through
should be by far less than h "V --q¦ in order to be sure that the transistor
works in the subthreshold region. At the same drain current level if a PMOS
larger aspect ratio by the factor of hY hR , compared to its NMOS counterpart.

transistor is supposed to operate in the subthreshold region it needs to have a
This means that in the similar condition from current and sizing standpoints,
NMOS devices usually enter the subthreshold prior to PMOS transistors. The
and just depends on the technology parameters. For instance, consider a 0.25- Š
condition given by (2.18) is independent of the drain current or transistor sizing
CMOS technology in which for an NMOS device we have hY C= •Š ´ ],

"V < T ‹ /Œ µ •Š , and - T. By substituting the given data into (2.18),
aspect ratio) is adequately less than < \¶, the NMOS will enter the subthreshold
we can see if the left-side term (i.e., the normalized drain current to the device
\¶ and aspect ratio of o p

region. As a numerical example, an NMOS transistor with the drain current of
The drain-source dynamic conductance X#K is given by X#K |W) and X0„
operates in the subthreshold regime.
that shows the effect of source-bulk voltage variation on the drain current can be
determined by substituting (2.8) in (2.3) and differentiating the drain current with
respect to the source-bulk voltage around the bias point.
X0„ *
z%: z%: z4£
z k¨ 4 z4£ z k¨
(2.19)
k¨
From (2.3), we have ·®) ·-e X0

·-e ·!D• ’ •-D• ”• and thus
and from (2.8) we get
X0„
¸¯5
•4k¨ §¨
(2.20)
The negative sign in (2.20) indicates the drain current drops for the nonzero source
to bulk potential. This is because the effective threshold voltage rises due to the
body effect.
id
G D
+ gmvgs |gmb|vsb
vgs gds
-
S
+
vsb
- B
Figure 2.5 Low-frequency small-signal MOS device equivalent circuit.
Based on the obtained parameters for an MOS transistor, the low-frequency

small-signal equivalent circuit for such device is obtained as shown in Figure 2.5.
The derived small-signal circuit is valid at low-frequency. For adequate high
frequencies, we need to consider the effect of internal MOS capacitances.
Generally there are five main capacitances that should be inserted inside the circuit
of Figure 2.5. Three out of five of these capacitances are the capacitances that are
formed between gate and three other terminals (i.e., drain, source, and bulk) and
the latter two are associated with the junction capacitance of the drain and source
area with the substrate. In the following section, we will deal with each
capacitance and study its behavior in different operation areas of the MOS
transistor.
2.3.1 Gate to Substrate Capacitance
In the NMOS structure illustrated in Figure 2.6, the gate voltage drops across the
oxide and the surface of the semiconductor. In MOS physics contexts it is shown
G Lov
S D
-
- - - - - - wd- -
n+ - -
- -
- - - -
-
- - n+
-
L1 - -
-
p_substrate
Figure 2.6 NMOS device structure.
that the created electric charge at the surface, denoted by gD , changes with the
surface potential ”K , as depicted in Figure 2.7 [8]. The gate to substrate
semiconductor capacitance at the surface of the silicon. For ”D

capacitance consists of the series connection of the gate oxide capacitance and the
corresponding
which the surface charge is an exponential function of the surface potential ”D and
to negative gate-source voltage, the transistor operates in accumulation mode in
thus the semiconductor capacitance K$ ·¹gD ¹ ·”K is much greater than the
the substrate almost becomes ¯„ op "V in which p is the channel length

gate oxide capacitance. This results in the total capacitance between the gate, and
without the overlap length of p" , as indicated in Figure 2.6.

-fD -e , the surface potential varies between ”D ”• and
the depletion negative ion charges underneath the gate form the main part of gD . In
For
this situation, ¯„ is the series combination of "V and #IR mK o# with o# as

the depth of the depletion layer under the gate, as shown in Figure 2.6. When -fD
goes up before it reaches -e , o# increases and thus #IR decreases, which results
in lowering ¯„ . For -fD -e , in the event that the transistor works in the triode
region, an inversion layer of free electrons extends from the source to drain at the
surface to form a capacitor in which one electrode is the gate and the other one
consists of the n-type regions including source, drain, and inversion layer. As
discussed later, this capacitance is split up equally between the source and drain
that forms a part of the gate to the source/drain capacitance. In the triode region,
¯„ is a very small capacitance that is only related to a part of the gate polysilicon
that overlays on the field oxide. When the transistor works in saturation there is a
|Qs|
Electric Charge
Accumulation
2ψB
strong Inv
Depletion
Weak Inv
ψs
-0.4 -0.2 0 0.2 0.4 0.6 0.8
Surface Potential
Figure 2.7 Electric charge vs. surface potential in an NMOS device.
G
S D
- - - -- - - - - - - - -
- - - - - - - - - - - -- -
- - -
n+ - -- - - - -
- -
-
-
- n+
-
inversion layer -
- -
- -
p_substrate
depletion area
Figure 2.8 NMOS device structure in saturation.
depletion area near the drain junction so that it creates a partial depletion
capacitance at the surface of the semiconductor at the drain side, as depicted in
Figure 2.8. Hence, the total ¯„ capacitance in saturation will be
6 —6+rQ 4+y
¯„ op
Ž 6 — 6+rQ 4+y
(2.21)
where #IR -#„ is the drain-side depletion capacitance at the reverse voltage -#„ .
In (2.21) the coefficient of 1/3 appears because in saturation it can be proven that
the total charge under the gate is given by [8]
g$¦ op "V -fD -e

Ž
(2.22)
(i.e., g$¦ op "V -fD -e ) we can deduce that the effective channel length
Comparing (2.22) with the same relationship for the charge in the triode region
containing the inversion charge is two-thirds of the total length and one-third
forms the depletion area near the drain junction; thus, one-third of #IR becomes a
series connected with one-third of the gate oxide capacitance forming (2.21).
2.3.2 Gate to Source/Drain Capacitance
Here we introduce the gate to the source/drain capacitance of an NMOS device in

different operation areas. When the transistor is off there is no free carriers under
the gate and the only significant capacitance between the gate and source/drain is
due to the overlap between the gate electrode and the source/drain diffusion area.
The overlap is made because of lateral diffusion of the source/drain region in the
annealing phase of the fabrication process. From Figure 2.6 the overlap gate to
source/drain capacitance is given by
fD p" o "V (2.23)
where p" is the overlap length that depends on the used technology. In fact the
quantity p" "V fD" is determined by the technology and because of the
symmetrical structure of the MOS device, it is almost the same for both the source
and drain areas. In practice, the thickness of the polysilicon gate is much greater
than that of both the gate oxide thickness and overlap length so that the fringing
capacitance due to the fringing field lines is remarkable. This shows that the value
of the gate to the source/drain overlap capacitance should be larger than that given
in (2.23). When the transistor works in the triode, as discussed earlier, there is a
common capacitance between the gate and three of the same n-type areas of
source and drain regions with the value of =op "V. Thus the total gate-source
source, drain, and inversion layer. This capacitance is divided equally between the
and gate-drain capacitance in the triode region will be
¯K ¯# o "V p p" (2.24)
differentiating (2.22) versus -fD and adding the fixed gate overlap capacitance
The gate-source capacitance in the saturation region can be derived by
fD to it
¯K o "V Ž p p" (2.25)
the saturation region so that we have ¯# o "Vp" . Although ¯# is small in

The gate overlap of the drain is the only capacitance between the drain and gate in
saturation, in a common-source amplifier its effect on the circuit frequency

response is significant because of the Miller effect [7].
2.3.3 Source/Drain to Bulk Capacitance
region of the device. For -fD -e , the device is off and thus this capacitance is
The capacitance between the source/drain and bulk depends on the operating
actually the junction capacitance of the source/drain regions with the MOS body.
In this case the junction capacitance itself consists of two components. One is
related to the bottom part of the junction and the other is the sidewall junction
capacitance.
K # „ D ) º ND ) ºK• (2.26)
D ) opD ) is the source (drain) area with pD ) as the source (drain) region
physical length, ND ) o pD ) is the periphery of the source (drain),
º mK »# is the capacitance per unit area at the bottom of the source (drain) area
LS LD
G
S D
- - - - -- - - - - - --
n+
- - - - - - - - - - - -- - - - - - - - - - - -- -
n+
- -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-
- - - - - - - -
- - - - - -
Cjsw - Wd
- -
-
-
- -
-- -
inv. layer Cd
-
-
- -
-
- - - depletion
layer
Cj p_substrate
Figure 2.9 Capacitance of source/drain to bulk junction and channel depletion capacitance.
and ºK• is the capacitance per unit length of the junction sidewalls.
»# t mK ‚ƒKM„ -„% -D ) • is the depletion width of the source (drain) to
the bulk junction and -„% is the built-in potential of the junction. For -fD -e
inversion layer consisting of free electron carriers connects two • source and
when the NMOS device works in the triode region, as mentioned earlier, an
drain regions together. In this situation, the capacitance of the depletion region
under the gate as a parallel capacitance will be added to the junction capacitances
depletion capacitance. The depletion capacitance op # with # mK o# is

given by (2.26). Figure 2.9 helps to make clear the contribution of the channel
equally split up between drain and source junction capacitances and thus the total
K # „ is given by
K # „ D ) º ND¼ ) ºK• op # (2.27)
o# t mK ‚ƒKM„ ”• -D ) • is the width of the depletion region under the

gate for -)D . Supposing -„% ”• , we can conclude »# o# and thus we
have º #
ND ) o pD ) in which one side of the source (drain) area adjacent to the
. In (2.27) the source (drain) periphery has been modified as
inversion layer is omitted from the perimeter calculation because the source
no PN junction at that place. For -fD -e and if the device works in the
(drain) diffusion area and inversion layer are the same type at this area and there is
saturation region, two-thirds of the depletion capacitance is added to the source

junction capacitance such that the total source to bulk capacitance will be
K„ D º ND¼ ºK• op #
Ž
(2.28)
off triode
WL1Cox saturation
Capacitance
Cgb
0.67WL1Cox Cgs
0.5WL1Cox
Cgd
VGS
0 VT VT+VDS,sat
Voltage
Figure 2.10 Plot of main MOS capacitances in different operating regions.
At the drain side, we have only the drain junction capacitance according to the
relationship given by (2.26) in which º and ºK• should be calculated at the drain-
to-bulk bias voltage. The main capacitances formed between the gate and three
other terminals in an MOS device (i.e., ¯„ , ¯K , and ¯# ) in different operating
regions of the device are plotted in Figure 2.10. The small-signal model of an
MOS device including the main device parasitic capacitances is illustrated in
Figure 2.11. This model is usually used to analyze MOS circuits in high
frequencies.
One important high-frequency parameter that indicates the merit of a
is denoted by L e and defined as a frequency at which the current gain of the

transistor for high-frequency applications is known as transition frequency, which
device becomes unity. In order to find the L e for an MOS device, we obtain its
current gain when the transistor is used in a common-source configuration, as
depicted in Figure 2.12. Summing all currents at the drain node, we get
G Cgd
+ D
vgs Cgs
gds
Cgb - gmvgs |gmb|vsb Cdb
S
vsb+
Csb
B
Figure 2.11 High-frequency small-signal model of an MOS device.
iD ig id
Cgd
vG +
- VDS +
v
- Cgb Cgs gmv
-
Figure 2.12 Circuit used to calculate MOS transition frequency.
®# X0 ½ ¯# ! (2.29)
Since ®¯ ½ ¯ ! with ¯ ¯„ ¯K ¯# ,
¾ ®# ®¯ is obtained
the current gain defined as
¯5 /K6¿+
¾
K6¿
(2.30)
In the frequency domain, L e is defined as a frequency at which the magnitude of

the current gain is equal to unity (¹¾ ÀL e ¹ ). Thus from (2.30) we have
Le
¯5
6¿ 2
(2.31)
Â
Á /© ¿+ ¬
Â¿
In practice ¯# … ¯ and ¯ ¯K so we can arrive at a simple relationship of

L e X0 ¯K . Assuming the square law is held for the device, we substitute the
values of X0 and ¯K into the L e relationship to obtain L e for an NMOS transistor
as follows
Le
ŽÃÄ 4¡k /4£
Z2
(2.32)
As it is obvious from (2.32) by scaling down the technology dimensions, the
channel length. For a particular technology the bias condition also affects L e
transistor transition frequency increases as a quadratic function of the device
through the overdrive voltage of the device. Based on (2.32), for the same biasing
condition in a given CMOS technology, NMOS transistors have better frequency
response in comparison to their PMOS counterpart. This is because of the higher
electron mobility in NMOS transistors.
2.4 Conclusion 31
2.4 Conclusion
Familiarity with the basic fabrication process of MOS transistors can significantly
help to give more practical insight about circuit design in CMOS technology. In
this chapter, we first briefly introduced the fundamental steps involved in the
fabrication of two NMOS and PMOS transistors. Then the MOS drain current
relationships and some physical aspects of the device were briefly discussed.
Different operation regions of an MOS device including triode, saturation and
subthreshold, and their corresponding drain current relationships were introduced.
Since the nature of the formation drain current in saturation and subthreshold
region is totally different with completely distinct current equations, we derived a
relation that can be used as an index to distinguish the correct operating region of
the device. This greatly helps the designer to employ true relationships to calculate
the device parameters. Based on concepts of device physics and the given
relations, the small-signal equivalent circuit for both NMOS and PMOS transistors
in low and high frequencies were developed.
References
[1] Franssila, S., Introduction to Microfabrication, John Wiley & Sons, 2010.
[2] May, G. S., and Spanos, C. J., Fundamentals of Semiconductor Manufacturing and Process
Control, John Wiley & Sons, 2006.
[3] El-Kareh, B., Fundamentals of Semiconductor Processing Technology, Kluwer Academic
Publishers, 1995.
[4] Bagad, V. S., Fundamentals of CMOS VLSI, Technical Publications, Pune, India, 2009.
[5] Chang, C. Y., and Sze, S. M., ULSI Technology, McGraw-Hill, 1996.
[6] Muller, R. S., and Kamins, T. I., with Chan, M., Device Electronics for Integrated Circuits, Third
Edition, John Wiley & Sons, 2003.
[7] Gray, P. R., Hurst, P. J., Lewis, S. H. and Meyer, R. G., Analysis and Design of Analog
Integrated Circuits, Fourth Edition, John Wiley & Sons, Inc., 2001.
[8] Sze, S. M., Ng, K. K., Physics of Semiconductor Devices, Third Edition, Hoboken, New Jersey,
John Wiley & Sons, Inc., 2007.
Chapter 3
CMOS Differential Amplifiers
As its name suggests, in a differential amplifier the output signal generally is the
amplified version of the difference of two inputs of the amplifier. Because of the
exclusive properties of this type of amplifier, it is considered as one of the most
important building blocks in many analog circuits. In this chapter, we first analyze
a source-coupled circuit as a differential voltage-to-current converter and then deal
with the CMOS differential amplifier in which a current mirror circuit is employed
as an active load for the source-coupled pair. This amplifier is regarded as an
integral part at the input of most single-ended output operational amplifiers so that
many properties of an op amp depend on the parameters of this block. We study
the large-signal characteristics of this amplifier in detail. Offset voltage, frequency
response, and noise behavior of the amplifier are the subjects for the rest of this
chapter.
3.1 Source-Coupled Differential Pair Characteristic
In the differential pair shown in Figure 3.1, it is assumed that M1 and M2 are
exactly the same and both operate in saturation. Furthermore, the channel length
modulation effect is ignored and it is presumed that the drain current of each
iD1 iD2
+ M1 M2
vi
-
I0
Figure 3.1 Differential pair amplifier.
33
34 CMOS Differential Amplifiers
device follows a quadratic relationship. Thus the gate-source voltage of M1 and

M2 can be written as
!fD -e t
%:ÅH2
H Æ
(3.1)
where ° hY "V o p H . hY is the free electrons mobility, "V is the gate

capacitance per unit area, and o and p are the channel width and length of M1
and M2, respectively. Since !% !fD !fD , from (3.1) we have
•®) •®) t !%
Æ
(3.2)
Summing drain currents at the common node of sources gives ®) ®) W,

which yields
“•®) •®) – •®) •®) W (3.3)
Substituting (3.2) into (3.3), we get
•®) •®) W !%
Æ
(3.4)
Since “•®) •®) – W •®) •®) , from (3.4) we obtain
•®) •®) t W !%
Æ
(3.5)
The multiplication of (3.5) by (3.2) gives the differential current ®"Mq in terms of
the differential input voltage
Æ 2
®"Mq ®) ®) •°W !% t Ç{
(3.6)
Thus the drain current of each MOS transistor is obtained as
Æ 2
®) •°W t
{
Ç{
(3.7)
Æ 2
®) •°W t
{
Ç{
(3.8)
The plot of each drain current of the differential pair is illustrated in Figure 3.2.
3.1 Source-Coupled Differential Pair Characteristic 35
iD2 I0 iD1
0.5I0
vi
2I0 0 2I0
-
β β
Figure 3.2 Differential pair drain currents versus differential input voltage.
We see that for • W ° !% • W ° both transistors conduct and when !%
entire tail current W is steered toward the other transistor. The large-signal
goes beyond this range one of the two transistors, M1 or M2, turns off and the
variation based on (3.6) is plotted in Figure 3.3. As it can be seen, ®"Mq is an odd
characteristic of the differential output current in terms of the differential input
function of !% . This means that for a large sinusoidal input voltage, the differential
the derivative of (3.6) versus !% , we can find the incremental transconductance of

output current contains only odd harmonics of the input signal frequency. Taking
the differential pair versus the differential input voltage
ÉS2
/
È0 !% •°W !%
z% x‰ { {
tÆ tÆ
2Ê
z ÉS2
(3.9)
Á /
ËÊ
It is clear that the differential pair transconductance generally changes as an even
iout
+I0
2I0
-
β
vi
0 2I0
β
-I0
Figure 3.3 Differential output current versus differential input voltage.
function of the input signal and its small-signal value for !% … • W ° becomes
•°W .
3.2 CMOS Differential Amplifier with Active Load
A single-ended output differential amplifier can be implemented by putting a

PMOS current mirror on top of the circuit of Figure 3.1 as illustrated in Figure 3.4
other and thus the tail current W is equally divided between M1 (M3) and M2
[1]. In this circuit, (M1, M2) and also (M3, M4) are mutually identical with each
(M4) in the absence of differential input voltage. In this situation because of the
circuit symmetry, the dc voltage level at the drain of M1 and M2 is the same and
equals to
-"#$ -)) Ì-eR Ì
{
tÆ (3.10)
Q
where °R hR "V o p ŽHÇ . hR is the hole carriers mobility and o p ŽHÇ is the
M3 and M4 aspect ratio.
3.2.1 Large-Signal Characteristic of CMOS Differential Amplifier
voltage the drain current in M1 and M2 will change around its static value of W
When an ac differential input voltage is superimposed on the bias common mode
In the differential amplifier shown in Figure 3.5 for variation of !% in the

in the opposite direction.
Figure 3.4 Single-ended output differential amplifier in dc state.
VDD
M3 M4
vo
M1 M2
+ +
+vi/2 - - -vi/2
I0
+ VB
Vcm M5
-
Figure 3.5 Differential amplifier with differential input.
• W ° !% • W ° , the drain current of M1 and M2 is

determined based on (3.7) and (3.8). When !% rises, due to the positive voltage
range of
gain of the amplifier, the output voltage with a steep positive slope goes up and
This occurs for a rather low positive change in !% . After M4 enters the triode
M4 quickly approaches the triode region where the voltage gain starts dropping.
region, with more increase in !% , the output voltage !" continues to rise with a
lower rate. At the same time the tail current steers toward M1 and the current of
When differential input voltage reaches • W ° , the entire tail current flows
M2 and M4 approaches zero.
through M1 and thus M2 turns off. At this point, M4 is in triode with zero drain
voltage is fixed on [ÍÍ . When input voltage changes in the negative direction, the
current, which means the drain-source voltage of M4 is zero and thus the output
output voltage rapidly drops again due to the differential amplifier voltage gain
and this time M2 goes to the triode region. As long as the tail transistor operates in
saturation, M5 acts as a current source, and M3 with a diode connection structure
M4 is more than -D)HKUq , it will operate in saturation and the current mirror
always remains in saturation. On the other hand, if the source-to-drain voltage of
M2 is in triode and therefore the drain currents of M1 and M2 remain on W . For

consisting of M3 and M4 forces M1 and M2 to have the same current even though
large negative differential input voltage the tail transistor ultimately enters the
triode region where the tail current starts decreasing with the input. As a result, the
I0 iD1
0.5I0
iD2
vi
0 2I0
β
Figure 3.6 Variations of differential amplifier drain currents versus input.
drain currents of M1 and M2 also decrease in parallel with each other. The drain
currents of M1 and M2 versus the differential input voltage variation are plotted in
Figure 3.6. The large-signal characteristic of the CMOS differential amplifier with
a current mirror load is depicted in Figure 3.7.
3.2.2 Offset Voltage of CMOS Differential Amplifier
inputs are the same, the output voltage places on -)) -DfŽ , as illustrated in
In a single-ended output differential pair that has perfect symmetry when two
Figure 3.7. In practice, due to different mismatches in the circuit, the output dc
a differential voltage to the input in order to put the output back on -)) -DfŽ . In
voltage has a different value from the ideal case. In this situation we have to apply
such a case the applied differential input voltage is called the input-referred dc
offset voltage [2]. In the circuit of Figure 3.8 we can write
-ÎD -fD -fD (3.11)
To obtain an analytic relationship for -ÎD , first we define average and

difference quantities for the circuit parameters as below
vo
VDD
VDD-VSG3
High Gain
Area
vi
0 2I0
β
Figure 3.7 Large-signal characteristic of differential amplifier.
VDD
M3 M4
Vo
ID1 ID2
VOS M1 M2
+
−
I0
Figure 3.8 Differential amplifier with input offset voltage.
-eY
4£ÄÅ 4£Ä2
(3.12)
3-eY -eY -eY (3.13)
W)
{:Å {:2
(3.14)
3W) W) W) (3.15)
°Y
ÆÄÅ ÆÄ2
(3.16)
3°Y °Y °Y (3.17)
Since -fD H -eY H t W) H °Y H , by substituting the above expressions into

(3.11), we have
3Ê: 3Ê
/2Ê:
-ÎD 3-eY t Æ ÏÁ Á Ð
{: 2Ê: :
3ÉÄ 3ÉÄ
/
(3.18)
Ä
2ÉÄ 2ÉÄ
After some manipulations on (3.18) and neglecting higher-order terms, we get
-ÎD 3-eY tÆ F { G
: { : 3{ 3ÆÄ
ÆÄ
(3.19)
Ä :
In the current mirror active load we have -DfŽ -DfÇ -DfR and thus
W)Ž W) “-DfR Ì-eRŽ Ì–

ÆQÑ
(3.20)
W)Ç W) “-DfR Ì-eRÇ Ì–

ÆQË
(3.21)
Again we define average and difference quantities for the current mirror circuit
parameters as follows:
Ì-eR Ì
Ì4£QÑ Ì Ì4£QË Ì
(3.22)
3-eR Ì-eRŽ Ì Ì-eRÇ Ì (3.23)
°R
ÆQÑ ÆQË
(3.24)
3°R °RŽ °RÇ (3.25)
By substituting the above quantities into (3.20) and (3.21) and neglecting higher-
order terms, we can obtain the approximate expressions for the drain currents of
M3 and M4 as
W)Ž † W) © ¬
3ÆQ 34£Q
ÆQ 4k¡Q /Ì4£Q Ì
(3.26)
W)Ç † W) © ¬
3ÆQ 34£Q
ÆQ 4k¡Q /Ì4£Q Ì
(3.27)
with 3W) W)Ž W)Ç , from (3.26) and (3.27), we can obtain 3W) W)
3{: 3ÆQ 34£Q

{: ÆQ 4k¡Q /Ì4£Q Ì
(3.28)
Now we substitute (3.28) into (3.19) and use -DfR Ì-eR Ì • W) °R to reach
-ÎD 3-eY tÆ © Æ ¬ tÆ 3-eR

: { Q 3Æ 3ÆÄ Æ
Q
ÆÄ
(3.29)
Ä Q Ä
where °YHR hYHR "V o p YHR . Mismatch in the size of two pairs of NMOS and
PMOS devices and also mismatch due to the difference in the gate oxide thickness
of devices represents itself as a mismatch in "V; all of them have been
summarized in two terms 3°R °R and 3°Y °Y in (3.29). It is obvious from (3.29)
that any threshold voltage mismatch in the input transistors M1 and M2 directly
appears in the input-referred dc offset voltage. This fact proves how significant it
is to have symmetrical devices at the input. In a careful design in order to achieve
maximum symmetry for M1 and M2 in the layout design, each transistor is split
into two identical parts and diagonally connected together, as illustrated in Figure
3.9. This technique is called common centroid, which makes M1 and M2 immune
from cross-chip gradients in the oxide thickness and doping and provides the best
matching performance for the circuit [3-5]. The price paid for that is to impose
more complexity on doing the layout. The common centroid technique helps to
leads to nearly zero average for 3-e . The absolute statistical variation of threshold
evenly distribute the threshold voltage mismatches between two transistors that
voltage is determined by the gate area as
@4£ £
diZ
(3.30)
where 4e is the threshold proportionality factor and depends on the technology

used. It is shown that it has a roughly linear relationship with the gate oxide
thickness [6]. From (3.30), minimum random variation in threshold voltage is
achievable by taking the maximum possible value for the MOS gate area. As
discussed later, choosing a large gate area helps to reduce the effect of the flicker
of °Y and °R appears in the offset voltage by a weighting factor of the overdrive

noise as well. From (3.29) it can be seen that any mismatch error in the parameters
voltage of the input transistors. Thus in a low-offset design we need to minimize

the input MOS device overdrive voltage. On the other hand, a small overdrive
voltage for input MOS devices results in a lower linear operating range of the
differential pair. This is a contradictory situation in a design that simultaneously
point that can be deduced from (3.29) is that 3-eR as the mismatch of the load
requires a low offset voltage and high linear operating range. Another interesting
transistors appears in the input offset voltage by a weighting factor of •°R °Y . So
will be shown later, a small °R °Y reduces the input-referred noise due to M3 and
minimizing this ratio can also help to reduce the total offset voltage. Moreover, as
M4. Every measure taken to reduce 3-eY in doing the layout for the input device
is applicable to 3-eR in the load transistors as well.
M1a M2a
M2b M1b
Figure 3.9 Common-centroid technique for better matching performance.
3.3 Common-Mode Behavior of CMOS Differential Amplifier
What has made a differential amplifier an important building block in analog

systems is its capability to amplify the differential changes at its input in the
presence of a large common-mode voltage. In an ideal differential amplifier we
expect that the amplifier output just changes in response to the differential part of
its input and any change in the input common mode does not impact on the output
voltage. This capability can provide a good immunity for the circuit against the
existing common mode noise and as a result raise the circuit performance,
especially in a noisy environment. In practice, the output of a differential amplifier
consists of the amplified voltage of both differential and common-mode parts of
!" #0 !%# $0 !%$

the input
(3.31)
where #0 and $0 express the amount of contribution of differential and

common-mode components at the output, respectively. In a good differential
amplifier the common-mode voltage gain of $0 is normally much less than the
differential voltage gain of #0 . In order to quantify the performance of a
differential amplifier in rejecting the input common mode variations, a parameter
called common-mode rejection ratio (CMRR) is defined as
& '' * +5
* (3.32)
,5
To see what parameters of the amplifier can considerably affect $0 , we replace

the small-signal equivalent circuit for the amplifier of Figure 3.5, as illustrated in
Figure 3.10. In this circuit only the common-mode component of the input has
neglected. 'q is the equivalent output resistance of the tail current source.
been considered and both body effect and ac output resistance of M1 and M2 are
Summing voltages around the loop containing the input voltage 3-%$ , gate-source
voltage of M1 or M2 and potential across 'q , we obtain
3-%$ ! X0 X0 'q ! (3.33)
Summing currents at the output node, we have
X0Ž !Ž X0 !
. Ë
(3.34)
Noting that !Ž Ò"Ž Ó X0Ž X0 ! and using (3.33) and (3.34), we can
obtain the common-mode gain as
- gm4v3
v3 ro3||(1/gm3) ro4
+
∆Vic ∆Vic
+
+
vo
v -
gm1v gm2v
-
Rt
Figure 3.10 Small-signal equivalent circuit of differential amplifier for calculating common-mode
voltage gain.
¿
¯5Å /¯52 . Ñ / 52
Ò"Ç
¿5Ñ
$0 34 , Ô
Å
¯5Å ¯52 8‰ ÕF. Ñ G
(3.35)
¿5Ñ
Assuming Ò"Ž X0Ž and Ò"Ž † Ò"Ç , we can approximate (3.35) as

¿
¯5Å /¯52 . Ñ / 52
¿5Ñ
$0 ¯5Å ¯52 8‰
(3.36)
From (3.36) we see the mismatch between M1 and M2 (X0 Ö X0 ) and the finite
output resistance of the tail current source 'q are two main reasons that cause the
differential amplifier to have a nonzero common-mode voltage gain. In order to
improve the CMRR parameter the matching between the input transistors is
provide enough large output resistance (high 'q ).

important. In addition, the circuit used to implement the tail current source should
3.4 CMOS Differential Amplifier Frequency Response
The study of the behavior of both differential and common-mode voltage gains
( #0 and $0 ) of a differential amplifier in the frequency domain is important.
Indeed, the first shows how fast the amplifier is able to follow the rapid changes in
the input differential signal and the second provides a figure of merit for the
amplifier about its capability to attenuate high-frequency disturbance signals that

appear at the input as common-mode noise. To simplify the frequency analysis we
consider only two main internal capacitances of the circuit that form two largest
time constants at their corresponding nodes. Figure 3.11 shows a differential
amplifier where represents the gate capacitance of the current mirror load and
•
The equivalent resistance seen at node A is rather small ( X0Ž ) but its
is the total capacitance including the load capacitance at the output node.
parasitic capacitance that mainly consists of the gate-source capacitance of M3

and M4 could be considerable in such a way that its corresponding time constant is
noticeable. The high resistance at the output and the equivalent capacitance at this
node create the dominant time constant of the circuit at this node. The high-
frequency small-signal equivalent circuit of Figure 3.11 is depicted in Figure 3.12
in which we have ignored the body effect in M1 and M2 and also neglected the
output resistance of the tail current. It is also assumed that two pairs of (M1, M2)
resistance for NMOS devices are denoted by X0w and Ò"w , respectively, and those
and (M3, M4) are mutually symmetrical. The transconductance and output
of PMOS devices by X0× and Ò"× . Before writing the required equations to obtain
the circuit transfer function, first we replace the indicated lower-part of the circuit
with its Thevenin equivalent circuit. This can be done by replacing the two
voltage-controlled current sources by their Thevenin equivalent circuits as
-q X0w Ò"w - - X0w Ò"w -% and 'q Ò"w , respectively. By replacing the
illustrated in Figure 3.13. The equivalent Thevenin voltage and resistance are
lower-part circuit in Figure 3.12 with the Thevenin equivalent circuit, we get a
Ø X0× ½ and Ø• Ò"× Ò"× • ½ are the impedances obtained

simplified form of the small-signal equivalent circuit shown in Figure 3.14 where
VDD
A
M3 M4
CA
B
Vo
CB
+ M1 M2
vi
-
I0
Figure 3.11 Differential amplifier with two main capacitances impacting on frequency response.
-
gmPv3
v3 roP||(1/gmP)
roP
+ CA CB
Thevenin
Equivalent
+
vo
A -
B
+ + +
v1 roN roN v2
gmNv1 gmNv2
vi - -
-
Figure 3.12 High-frequency small-signal equivalent circuit for differential amplifier.
from the parallel combination of with X0× and that of • with Ò"× ,
respectively. Summing voltages around the loop in Figure 3.14, we obtain
Ø Ø• 'q W X0× Ø• -Ž -q (3.37)
Substitution of -Ž Ø W in (3.37) gives
W
4‰
Ù1 Ù¨ 8‰ ¯5Ú Ù1 Ù¨
(3.38)
Since -" Ø• X0× Ø W and -q X0w Ò"w -% , we can obtain the circuit
Rt A B
- Vt +
roN roN
− −
+ +
gmNroNv1 gmNroNv2
Figure 3.13 Circuit for obtaining Thevenin equivalent circuit.
-
v3 I
ZA ZB
+
gmPZBv3
+
−
vo
Rt Vt
+
Figure 3.14 Simplified small-signal equivalent circuit.
−
-"
voltage gain in the s-domain as follows:
4 ½
-%
¯5Û . Û . Ú ¯5Ú K61
. Û . Ú 61 6¨ K 2 Ô61 . Ú . Û . Ú ¯5Ú . Û 6¨ ÕK ¯5Ú . Û . Ú
(3.39)
Assuming the transfer function has two real poles, we can write the general form
of this function as
v
4 ½ 4 v
ÜÝ
v
© ¬© ¬
(3.40)
ÜQÅ ÜQ2
where
¯5Û ¯5Ú . Û . Ú
4 ¯5Ú . Û . Ú
(3.41)
LÞ
¯5Ú
61
(3.42)
Supposing LR is the dominant pole of the circuit (LR … LR ), from (3.39) and
(3.40) we can determine the approximate value of LR as
LR C TC
¯5Ú . Û . Ú
61 . Ú . Û . Ú ¯5Ú . Û 6¨
and
LR
¯5Ú . Û
. Û Ó. Ú 6¨ . Û 61
(3.44)
In practice X0× Ò"w Ò"× and (3.41) can be simplified as 4

X0w Ò"w Ó Ò"× . In (3.43) the second term in the denominator is much greater than
the first one and thus the dominant pole can be approximated by
LR
. Û Ó. Ú 6¨
(3.45)
The first term in (3.44) is much less than the second one and also X0× Ò"w ,
so that we can approximate the second pole as
LR
¯5Ú
61
(3.46)
The nondominant pole is created by the current mirror circuit, hence known as the
plane. The gain magnitude ¹ 4 ÀL ¹ and phase ß 4 ÀL are plotted versus

mirror pole. The magnitude of this pole is half of the left-hand-side zero in the s-
frequency in Figure 3.15
3.5 Noise Calculations in CMOS Differential Amplifier
A noisy differential amplifier can be viewed as a noiseless two-port network in

which all internal noise generators are modeled as two generally correlated voltage
and current noise sources at the input, as illustrated in Figure 3.16. In a CMOS
|AV(jω)|
AV0
ωz ω
ωp1 ωp2
AV(jω)
0 ω
o
-45
-90o
Figure 3.15 Gain magnitude and phase versus frequency for CMOS differential amplifier.
RS RS V2n,i
+ Noisy + - + Noiseless
vs Differential vs Differential
Amplifier I2n,i Amplifier
- -
Figure 3.16 Amplifier noise viewed as equivalent input voltage and current noise sources.
much greater than the source resistance 'D and thus áááá -YHà is the dominant noise
differential amplifier for low-frequency operation, the input impedance is typically
source. To calculate - áááá

YHà for a differential amplifier, we first introduce the main
noise sources in an MOS device. In an MOS transistor the channel thermal noise
current and the flicker noise voltage are considered as the two main sources of
noise. When a transistor operates in saturation there is an inversion layer under the
gate with a limited resistance. This resistor like any other resistor generates some
thermal noise current whose mean-square is given by
WâY T‘ãÈ3 (3.47)
where ‘ is Boltzmann’s constant with the value of CA ‹ / Ž š ›œ, ã is

temperature in ›œ, È ' is the conductance, and 3 is the bandwidth on which
noise is calculated. The inversion layer conductance in a long-channel NMOS
device that operates in saturation can be shown to be [7]
X#K hY -fD -e
i
Ž "V Z (3.48)
In (3.48) hY "V o p -fD -e is the channel conductance when an MOS
by X#K . On the other side, this term is similar to the relationship for the
device operates in triode with a zero drain-source voltage that is usually denoted
also be represented by X0 . For short-channel devices, some physical phenomena

transconductance of a long-channel MOS transistor working in saturation so it can
such as hot electron effects occur that affect the effective channel resistance.
Therefore, the general relationship for the mean-square of the channel thermal
noise current is expressed as
WâY T‘ã’X0 3 C T;
where ’ is a factor inserted to consider the short-channel effects with a value of

2/3 for a long-channel condition and higher value in short-channel situations. It
more complex relationship and X#K cannot be simply replaced by X0 In a more

should be pointed out that in short-channel condition MOS transconductance has
accurate relationship X0 in (3.49) is replaced by X0 ¾ in which ¾ is defined as
¾ X0 X#K with the value of less than unity [8-9].

The channel noise current can be added in parallel with the voltage-controlled
current source in the small-signal equivalent circuit of an MOS device, as depicted
in Figure 3.17. In this circuit, we have
® X0 !¯K WY X0 !¯K
{Ä
¯5
(3.50)
By defining !¯K¼
!¯K !Y where !Y WY X0 , the noisy MOS device acts like a
noiseless device with the noise voltage !Y added to its ac gate-source voltage.
Another important noise source in an MOS device is flicker noise. The origin
of this type of noise in MOS devices is attributed to the lattice defects at the
interface of the silicon and gate oxide at the surface of the device. Dangling bands
and stress due to the different sizes of the silicon atoms and silicon dioxide
molecules at the interface of the silicon and gate oxide are the main reasons to
create energy states inside the silicon bandgap at the surface. These states act as
traps to randomly capture and release the channel carriers in such a way that
causes some fluctuation in the device threshold voltage. The time constant of the
capture and release process is in the range of a few tenths to several milliseconds
and thus the corresponding flicker noise has the most energy at low frequencies.
The mean-square of the flicker noise voltage is given by
-Y
‡ 3
iZ6 —
(3.51)
where } is the flicker noise coefficient that depends on the technology and the
type of the device. Channel thermal noise and flicker noise voltages are generally
uncorrelated and thus the total input-referred noise voltage represented at the gate
of an MOS device is given by
i
G D
+ gmvgs
vgs ro
In
-
S
Figure 3.17 MOS device small-signal equivalent circuit including channel thermal noise current.
áááá
-YHà F
Ç˜e¸ ‡
G3
¯5 iZ6 —
3.52)
Now by adding an equivalent noise voltage source in (3.52) at the gate of each
transistor in a differential amplifier, we can calculate the effect of each noise at the
amplifier output and then by dividing the result by the low-frequency gain of the
amplifier reaching the equivalent input-referred noise voltage. Assuming that
transistor noises are uncorrelated, we calculate the total input-referred noise
voltage by adding the mean-square values of all transistor noises referred to the
amplifier input. The CMOS differential amplifier including all equivalent noise
voltages at the gates of transistors is shown in Figure 3.18.
Utilizing (3.52), we can write the noise contribution of each device at its gate
as
áááá
-Yä ©
Ç˜e¸ ‡å
¬3 À H HCHTH=
¯5å iå Z å 6 —
(3.53)
Denoting the total input-referred noise voltage by ááááá

-YHàY , from Figure 3.18 we see
that áááá
-Y and áááá
-Y associated with the noise contribution of M1 and M2 directly
appear in áááááá
-YHàY . In order to calculate the noise contribution of M3 while only
considering áááá
-YŽ and setting other noise voltages to zero, we multiply áááá -YŽ by X0Ž
to obtain the equivalent noise current at the drain of M3 and then replace the
Ò"w represents the drain-source series resistance of M1 and M2 while it is

small-signal equivalent circuit of Figure 3.18 as illustrated in Figure 3.19, in which
assumed that Ò" æ. Summing currents at node A, we have
® X0× !Ž WYŽ (3.54)
where WYŽ X0Ž -YŽ. We can also write
-Y"Ž Ò"× ® X0× !Ž (3.55)
!Ž Ò"w ® -Y"Ž (3.56)
The solution of above equations gives
-Y"Ž W
. Ú / ¯5Ú . Û . Ú
¯5Ú . Û . Ú YŽ
(3.57)
In practice, X0× Ò"w Ò"× and X0× Ò"w Ò"× Ò"× and thus (3.57) can be
approximated as
-Y"Ž '"Mq WYŽ (3.58)
VDD
2
v n3 v2n4
M3 M4
v2no
v2n1 v2n2
M1 M2
v2n5
M5
Figure 3.18 CMOS differential amplifier with noise contribution of all devices.
where '"Mq Ò"w Ó Ò"× . In the same way, we can obtain the noise contribution of
-Y"Ç WYÇ
M4 at the output
. Ú ¯5Ú . Û . Ú
¯5Ú . Û . Ú
(3.59)
Applying the same approximations used for -Y"Ž , we reach the same result (i.e.,
-Y"Ç '"Mq WYÇ ). Since M3 and M4 can be considered identical, WYŽ WYÇ and
their mean-square is given by
áááá
WYŽ Wáááá FT‘ã’X0× X0×
‡Q
G3
YÇ iÚ Z Ú 6 —
(3.60)
-
In3
v3
1/gmP
+ gmPv3
A
roP
2roN Vn,o3
i
Figure 3.19 Small-signal equivalent circuit for calculation of M3 noise contribution.
where o× and p× are the channel width and length of PMOS load transistors (M3,
M4). The noise contribution of M3 and M4 in the total input-referred noise of ááááá
-YHàY
is obtained by dividing -Y"ŽHÇ by the amplifier low-frequency gain, X0w '"Mq .
Using (3.60), we have
ááááááááá
áááááááá
-YHàY ŽHÇ
4Ä2 ÑHË
ç
Ç˜e¸¯5Ú
2
‡Q
F
¯5Ú
G è3
¯5Û 8 x‰ 2 ¯5Û iÚ Z Ú 6 — ¯5Û
(3.61)
Based on (3.61) a large transconductance value for the input transistors M1 and
M2 can help to reduce the contribution of the thermal noise component of the load
transistor at the input. To reduce the contribution of the load flicker noise
and then for a particular value of X0w , we need to minimize the load transistors
contribution, first it needs to choose the largest possible gate area for M3 and M4
transconductance X0× . As discussed earlier, these measures also aid the designer
in reducing the effects of the load transistor mismatches on the input-referred
offset voltage. The noise current of the tail transistor flows through both M1 and
M2 as a common-mode current. As a result the amount of variation at the drain of
M1 and M2 due to this current is the same. Noting this point, to calculate the noise
effect of the tail transistor on the output noise, we first obtain the small-signal
X0w and thus -Y appears at its drain as

voltage gain from the gate of M5 to the drain of M1. In Figure 3.18 the equivalent
( X0 -Y X0w ). This voltage is amplified by the common-gate stage

resistance seen at the drain of M5 is
( X0w X0× ). The total voltage gain from the gate of M5 to the drain of M3 and
consisting of M1 and M3 as its diode-connected load with the gain of
( X0 X0× ). The output noise due to the noise of M5 is obtained as

correspondingly to the output node of the differential amplifier will be
áááááá
-Y" F
¯5é
G áááá
-Y
Ç ¯5Û
(3.62)
Dividing (3.62) by the square of the differential amplifier voltage gain, we can
It should be noted that the coefficient of áááá

-Y in (3.62) is usually small. As a result,
obtain the noise contribution of the tail transistor in the total input-referred noise.
when áááááá
-Y" is divided by the square of the differential amplifier voltage gain, the
input-referred noise owing to M5 will be negligible in comparison to that of the
other four transistors and the total input-referred noise of the CMOS differential
amplifier can be approximated as
ááááá
-YHàY áááááá
- áááááá F ¯5Ú G
-
Y H YŽHÇ ¯5Û
(3.63)
For X0× X0w … , from (3.63) we notice that M1 and M2 have the most
contribution to the input-referred noise. This noise can be minimized by increasing
3.6 Conclusion 53
both the gate area and transconductance of the input transistors M1 and M2.
3.6 Conclusion
In this chapter the large-signal and small-signal behaviors of an MOS differential

pair with a current mirror as its active load were studied. In the structure of an op
amp, a differential amplifier usually appears as the first stage. This causes several
important op amp parameters such as input offset voltage, common-mode rejection
ratio, and input-referred noise mainly affected by this stage. As a result an accurate
examination of the parameters of an MOS differential amplifier can help to design
a more realistic CMOS op amp. The input-referred offset voltage was defined and
some proper techniques to reduce this error voltage presented. The frequency
response of the amplifier was calculated and finally the noise behavior and
corresponding relationships in such an amplifier were briefly discussed.
References
[1] Jaeger, R. C., Blalock, T. N., Microelectronic Circuit Design, McGraw-Hill, 2007, Ch. 15.
[2] Witte, F., Makinwa, K., and Huijsing, J., Dynamic Offset Compensated CMOS Amplifiers,
Springer, 2009.
[3] Baker, R. J., CMOS: Circuit Design, Layout, and Simulation, Third Ed, John Wiley & Sons,
2010, Ch. 5.
[4] Hastings, R. A., The Art of Analog Layout, Second Ed., Pearson Prentice Hall, 2006.
[5] Graeb, H. E., Analog Layout Synthesis: A Survey of Topological Approaches, Springer, 2010.
[6] Pelgrom, M. J. M., Duinmaiger, A. C. J., and Welbers, A. P. G., “Matching Properties of MOS
Transistors,” IEEE J. Solid-State Circuits, Vol. SC-24, Oct. 1989, pp. 1433-1439.
[7] Tsividis, Y., Operation and Modeling of the MOS Transistor, Second Ed, Boston: McGraw-Hill,
1999.
[8] Ziel, A. V. D., Noise in Solid State Devices and Circuits, John Wiley & Sons, Inc., 1986.
[9] Shaeffer, D. K., and Lee, T. H., “A 1.5V, 1.5GHz CMOS Low Noise Amplifier,” IEEE J. Solid-
State Circuits, Vol. 32, No. 5, May 1997, pp. 745-759.
Chapter 4
CMOS Single-Ended Output Op Amps
In Chapter 1, we introduced the main general parameters of an operational

amplifier. An op amp normally consists of several building blocks among which a
differential pair usually is the first stage in different architectures. In fact, the input
differential voltage is converted to its equivalent current by the differential pair.
Then, the produced current will flow through a high-impedance element realized
usually by an active device to convert back the current to a voltage with larger
amplitude. The method used to convert back the generated current to a single-
ended output voltage defines different architectures for the single-ended output op
amps category. In this chapter, we deal with the analysis and design of several op
amps of these types, including two-stage, telescopic cascode and a particular
configuration of it known as folded-cascode, and current mirror structure. Some op
amp parameters that were introduced in Chapter 1 are examined for each type.
Because of the importance of the rail-to-rail input op amp in low-voltage
applications, the chapter ends by introducing different techniques employed to
implement this kind of op amp.
4.1 CMOS Two-Stage Op Amp
In a two-stage op amp, as its name suggests, the circuit consists of two cascaded
stages. The first stage is a differential pair with a current mirror active load and the
second stage is a common-source amplifier again with an active load to provide
adequate voltage gain. A simple CMOS two-stage op amp with NMOS transistors
as the input devices is shown in Figure 4.1.
In the circuit of Figure 4.1, M5 acts as the tail current source of the
differential pair and M7 is the active load of the common-source amplifier in the
second stage. As discussed earlier, because of full symmetry between (M1, M2)
and (M3, M4) the dc voltage at the drain of M2 (M4) is equal to the voltage at the
M3 that is lower than -)) by one gate-source voltage of M3. The gate-source and
drain of M1 (M3). Diode-connected M3 sets a specific dc voltage at the drain of
drain-source voltages of M3 and M4 are identical and all equal to the gate-source
55
56 CMOS Single-Ended Output Op Amp
VDD
M3 M4 M6
I0 vo
- M1 M2
vi
+
I0
M0 M5 M7
Figure 4.1 Two-stage CMOS op amp.
voltage of M6. In an ideal case, we expect that the gate-source voltage of M6 can
the output voltage is set at an appropriate level between the ground and [ÍÍ . In
keep both M6 and M7 in the saturation region in such a way that the dc level of
reality, if the sizing of M6 and M7 are not chosen properly in conjunction with the
sizing of the differential pair devices, we encounter a special offset voltage that is
called systematic offset voltage. In the next section, we discuss this offset voltage.
4.1.1 Offset Voltage
Systematic Offset Voltage: In the quiescent condition without any ac input signal,
we expect both M6 and M7 to operate in saturation. In an ideal case, this condition
occurs if the gate-source voltage of M6 that is equal to that of M3 and M4 can
provide an appropriate quiescent output voltage for equal drain currents of M6 and
one of the ground or [ÍÍ , taking either M6 or M7 to the triode region. Let us take
M7. In practice, this condition may not occur and the output voltage goes toward
-Dfê as the gate-source voltage of M6 for which the latter happens and -ë Dfê as the
a dc voltage source -$0 at the output node that takes a value in the middle of
ideal M6 gate-source voltage that keeps both M6 and M7 in saturation. By placing
ground and [ÍÍ , as shown in Figure 4.2, we can force both M6 and M7 to remain
in saturation for the gate-source voltage of -Dfê but now the drain current of two
change the gate-source voltage of M6 from -Dfê to -ë

transistors is no longer the same. In order to make currents identical, we have to
Dfê . The systematic offset
voltage is defined as the difference between these two mentioned gate-source
voltages of M6 when divided by the voltage gain of the differential pair and
referred to the op amp input:
VDD
+
VGS6
-
M6
ID6
ID6-ID7
+ V
cm
ID7
-
M7
Figure 4.2 Systematic offset voltage explanation circuit.
4k¡í /4î
-"KHKìK k¡í
(4.1)
+Å
where # is the voltage gain of the differential pair. To eliminate this offset, the
source of -$0 at the output node, while keeping both devices in the saturation
size of M6 and M7 should be chosen such that in the presence of the voltage
region, no current flows through the source -$0 that is equivalent to having
W)ê W)Œ . On the other side, from -DfŽ -DfÇ -Dfê and under the assumption
that the drain current of all MOS devices have a square-law dependence on the
gate-source voltage, we can write
Ì-eRŽ Ì Ì-eRê Ì
{:Ñ {:í
t ÆÑ
t Æí
(4.2)
where
°ŽHê hR "V F Z G
i
ŽHê
(4.3)
Assuming Ì-eRŽ Ì Ì-eRê Ì and neglecting channel-length modulation effect, since

W)ê W)Œ , we can get °Ž °ê W)Ž W)Œ . Because of equal gate-source voltage of
° °Œ W) W)Œ ). In the quiescent condition, the tail current W is equally divided

M5 and M7, a similar relationship can be written for these devices (i.e., we have
between M3 and M4 such that W)Ž W)Ç W . From two given ratios, the
following relationship is obtained
² ²
F³G F³G
Ñ é
² ²
F G F G
(4.4)
³ í ³ ï
If we do not neglect the channel length modulation effect, the drain current
equation for NMOS and PMOS devices should be modified as
W)YHR “-fDYHR -eYHR – “ |YHR -)DYHR –

ÆÄHQ
(4.5)
Following the same procedure and considering the channel length modulation, we
can obtain
² ²
ðÄ 4:kï F G F G ðQ 4k:í
³ í ³ é
² ²
ðÄ 4:ké F G F G ðQ 4k:Ñ
(4.6)
³ Ñ ³ ï
where |Y and |R are the short-channel parameters. -)D -$0H% -fD H

-$0H% as the input common-mode voltage. Furthermore, we have
with
-D)Ž -)) -DfŽ (4.7)
-D)ê -)) -"

and
(4.8)
If it is assumed that |Y H |R … , by using (4.4) and substituting (4.7) and (4.8) into
(4.6) and neglecting higher-order terms, we can obtain the quiescent output
voltage as
-" -)) -DfŽ -$0H% -fD

ðQ ðÄ
ðÄ ðQ ðÄ ðQ H (4.9)
In (4.9) the values of -DfŽ and -fD H depend on the tail current and for a certain
tail current they are fixed. In this condition, the dc output voltage approximately
changes with the input common-mode voltage according to the (4.9).
Random Offset Voltage: As discussed for the differential pair, this kind of offset is
related to any mismatch among different devices used in the circuit. Since any
offset voltage created by the second stage is reduced by the voltage gain of the
first stage while referring to the input, we can say that the most significant
contribution in the input-referred offset voltage in a two-stage op amp is given rise
to by the first stage differential pair. As such, any measure taken to reduce the
offset voltage of the first stage results in lowering the entire offset voltage. Some
offset reduction techniques for the differential pair were discussed in the previous
chapter. For instance, perfect matching in the layout of two pairs of (M1, M2) and
(M3, M4) and taking a large enough geometry for them were some measures that
help to get a low random offset voltage at the input. In the layout phase, if each
transistor is to be split into several smaller unit cells, particularly when the
transistor size is large, all unit cells should be distributed in a manner that any
error due to probable oxide thickness or substrate doping gradient is distributed
evenly among all unit cells. The mentioned steps can result in a random offset
voltage with a nearly zero mean value, otherwise the input offset voltage would
have a nonzero mean value that is added to the systematic offset voltage.
4.1.2 Two-Stage Op Amp Frequency Response
The output nodes of the differential pair and the common-source amplifier in the
second stage are two high-impedance nodes in the circuit of Figure 4.1. The gate-
source capacitance of M6 and the op amp load capacitance are the two most
significant capacitances seen at these nodes. Denoting these capacitances by
two-stage op amp as illustrated in Figure 4.3. ' and ' designate the parallel
and , respectively, we substitute the small-signal equivalent circuit of the
combination of the drain-source dynamic resistance of two pairs of (M2, M4) and
(M6, M7) in the first and second stage, respectively, and ¯#ê is the overlap drain-
gate capacitance of M6. Summing currents at the node A and at the output node,
we have
X0 -% F½ G -U ½ ¯#ê -U -"
8Å
(4.10)
X0ê -U F½ G -" ½ ¯#ê -" -U

82
(4.11)
Solving two equations, we can obtain the voltage gain transfer function as
vÂ¿+í
¯5Å ¯5í 8Å 82 © / ¬
½
¿5í
4 ñ8Å “6¿+í 6Å – 82 “6¿+í 62 – ¯5í 8Å 82 6¿+í òK 8Å 82 “6Å 62 6Å 6¿+í 62 6¿+í –K 2
(4.12)
As it can be seen from (4.12), the circuit displays a right half-plane zero and two
poles in the left half-plane in the s-domain. Supposing both poles are real, we can
represent (4.12) as a general form
Cgd6
A Vo
+ gm1Vi +
gm6Va
Vi
Va
- R1 C1 R2 C2
-
Figure 4.3 High-frequency small-signal equivalent circuit of two-stage op amp.
v
/
4 ½ 4 Å Å
ÜÝ
Å
© ¬K K2
(4.13)
ÜQÅ ÜQ2 ÜQÅ ÜQ2
where 4 X0 X0ê ' ' is the op amp dc voltage gain, LÞ X0ê ¯#ê is the
zero on the right half-plane, and LR and LR are two real left half-plane poles. If
LR is assumed as the dominant pole of the circuit (i.e., LR … LR ), comparing
(4.12) with (4.13), we can approximate two poles as follows:
LR
8Å “6¿+í 6Å – 82 “6¿+í 62 – ¯5í 8Å 82 6¿+í
(4.14)
¯5í 6¿+í
LR
6Å 62 6¿+í 6Å 62
(4.15)
The denominator of (4.14) is the summation of three different time constants,
multiplication of ' by an equivalent capacitance of IJ X0ê ' ¯#ê . Although

among which the last term is a dominant one. The dominant time constant is the
¯#ê is small, its effective value has increased by the factor of the second stage
voltage gain. This is known as the Miller effect [1].
Frequency Compensation: The two-stage op amp as it has been represented in

Figure 4.1 usually suffers from instability in the frequency domain when it is used
within a negative-feedback loop. This fact can be explained by taking a more
precise look at the poles and zero locations. The capacitance mostly consists of
the load capacitance and thus its value is usually much greater than and ¯#ê in
(4.15). Therefore the second pole can be approximated by
6¿+í
LR
¯5í
62 6Å 6¿+í
(4.16)
¯#ê and
therefore LR could not be very far from LR . On the other side, the zero is usually
Since includes the gate-source capacitance of M6, we have
much farther away from the two poles on the right half-plane. The magnitude and
4.4. As it can be seen from Figure 4.4, at the unity gain frequency of LM , the phase
phase plot of the op amp frequency response in this situation is shown in Figure
is close to A › , which shows a nearly zero phase margin! Before proceeding to
LM in terms of circuit parameters. With this end in view, a simplified schematic of

provide a solution for the instability problem, we first obtain the relationship for
source X0 !% models the output of the first stage and block X0ê represents the
the circuit of Figure 4.1 is depicted in Figure 4.5. The dependent current
second stage amplifier. In the circuit of Figure 4.5, the output voltage in the
s-domain can be written as
|AV(jω)|
AV0
ωp1 ωp2 ωu ω
z ω
AV(jω)
0 ω
-90
-180
Figure 4.4 Gain and phase versus frequency for an uncompensated two-stage op amp.
-"
¯5Å 4
K6¿+í
(4.17)
LR L LR , which is very similar to an integrator behavior. Frequency LM is

Equation (4.17) describes the behavior of the circuit in the frequency range of
this equation we obtain LM X0

defined as a frequency at which the magnitude of the voltage gain is unity. From
¯#ê . The capacitance ¯#ê is too small and
thus LM appears at high frequency usually after the second pole location. That is
exactly the reason why the phase margin drops dramatically. It is interesting that
Cgd6
gm6 Vo
gm1Vi C2
Figure 4.5 Schematic of op amp used to calculate u.
when ¯#ê increases, both LR and LM decrease and at the same time LR
increases, all of which help to increase the phase margin and make the op amp
frequency response more stable. In practice, this condition can be realized by
adding an appropriate capacitance in parallel with ¯#ê across the drain-gate of
as frequency compensation. The compensation capacitance is chosen such that LM

M6. The process of adding shunt capacitance to improve phase margin is known
occurs before LR . Since the phase margin is defined as the distance of the phase
at LM to the angle of A ° , from (4.13) we have
N& A óôc/ © ¬ nö•/ © ¬ nö•/ F G

› õx õx õx
õQÅ õQ2 õÝ
(4.18)
In practice since LM LR , we have óôc/ LM LR ; °

and thus the phase
margin will be
N& ; nö•/ © ¬ nö•/ F G

› õx õx
õQ2 õÝ
(4.19)
The ratio of LM LÞ in (4.19) is independent of the compensation capacitance and

it is equal to X0 X0ê . This term adds a negative phase to the phase margin that is
because the zero location is on the right half-plane. The added compensation
capacitance denoted by $ is usually much greater than ¯#ê and therefore
¯#ê 6 is approximately equal to $ . Assuming $
replacing ¯#ê with $ , we can approximate the second pole as X0ê
, from (4.16) by
.
According to (4.19), for a particular $ , increasing the load capacitance moves the
second pole toward lower frequencies and increases the negative phase
to move LR and LÞ adequately far away from LM . If it is supposed that

contribution of the second pole. To achieve an appropriate phase margin we need
LÞ ÷ LM , the contribution of the zero in the phase margin will be less than
= B› . In this condition, a minimum phase margin of < › , for example, is
attainable provided that LR ÷ LM that is equivalent to have $ ÷
Satisfying the condition of LÞ ÷ LM , is equivalent to have X0ê ÷ X0 that
.
requires to take quite a large value for X0ê and, in turn, dictates to employ a large
the effect of the right half-plane zero without having to increase X0ê is to move
device with a high current for M6. The better method to reduce or even eliminate
the zero into the infinity to entirely cancel its effect or move it to the left half-
plane to add a positive phase in the phase margin relationship. This can be
accomplished by adding a series resistance with the compensation capacitor. The
op amp schematic including the added RC series compensation circuit and its
small-signal equivalent circuit is shown in Figure 4.6. Summation of currents at
nodes A and B in the circuit of Figure 4.6(b) gives
VDD
M3 M4 M6
Rc
Cc
vo
- M1 M2
vi
+
Vb M7
M5
(a)
A Cc Rc B Vo
+ +
gm1Vi gm6Va
Vi Va
- R1 C1 R2 C2
-
(b)
Figure 4.6 (a) Two-stage op amp including compensation circuit. (b) Op amp small-signal equivalent
circuit.
X0 -% F ½ G -U
4ˆ /4
Å
8Å 8,
(4.20)
vÂ,
X0ê -U F ½ G -"
4 /4ˆ
Å
8, 82
(4.21)
vÂ,
Omitting -U between the two equations above, we can calculate the transfer
function of op amp as
Å
K6, F8, / G
½
¿5í
4 4 „K $K #K Ñ
2 (4.22)
where 4 X0 X0ê ' ' is the low-frequency voltage gain and coefficients øH ùH
and ú in the denominator are defined as
ø ' $ ' $ X0ê ' ' $ '$ $ (4.23a)
ù ' ' $ $ '$ $ ' ' (4.23b)
ú ' ' '$ $ (4.23c)
From (4.22) it is obvious that for '$ X0ê the zero will be eliminated in the
transfer function or equivalently the zero is moved into infinity and thus we have
'$ X0ê the zero moved into the left half-plane. Supposing that all three poles
no phase contribution due to the zero in the phase response of the op amp. For
of the transfer function are real, we can represent (4.22) as

v
½
ÝÅ
4 4 Å Å Å Å Å Å Å
F GK F GK 2 F GK Ñ
(4.24)
QÅ Q2 QÑ QÅ Q2 QÅ QÑ Q2 QÑ QÅ Q2 QÑ
Assuming poles û and ûŽ are widely separated with respect to û and also
ûŽ û , by equating the corresponding coefficients in (4.22) and (4.24), the
dominant pole û is nearly given by û ø and the second and third poles are
almost equal to û ø ù and ûŽ ù ú , respectively. In practice, we have
H $ and ' H ' '$ and thus by neglecting the small terms based on
the circuit components as û X0ê ' ' $ , û X0ê , ûŽ '$ ,

these approximations, we can easily obtain poles and zero relationships in terms of
and ü $ '$ X0ê . As it can be seen, adding the series resistance of

'$ does not create much change in the position of two first poles with respect to
the previous circuit. The role of '$ is to move the zero into the left half-plane and
compensation is that we take '$ X0ê to entirely eliminate the existing zero.
adding an extra far away third pole. As mentioned earlier, one way for
Another and usually better procedure is that we choose '$ such that it moves the
zero into the left half-plane and put it exactly on the second pole in order to have
one zero-pole cancellation. Figure 4.7 shows the op amp poles and zero locations
condition is obtained by setting ü û , which gives

in the s-plane in this condition. The required compensation resistance to meet this
'$ F G
62
¯5í 6,
(4.25)
In reality, in addition to ûŽ , the circuit has another high-order pole due to the
current mirror active load of the differential pair that is called the mirror pole. As
jω
s-plane
z1
X X X σ
p3 p2 p1
Figure 4.7 Cancellation of second pole by zero.
discussed before, this pole is equal to X0ŽHÇ ¯KŽHÇ and since ¯KŽHÇ is usually
much smaller than $ , for '$ close to X0ŽHÇ , the mirror pole is larger than ûŽ . In
be far enough from LM in order to achieve a proper phase margin. By substituting

the condition that one pole-zero cancellation has happened, these two poles should
(4.25) into ûŽ '$ and assuming ûŽ LM , we can determine a certain

minimum compensation capacitance to meet our desirable phase margin.
© ¬
¯5Å 6Å Ç62 ¯5í
$ ¯5í
t 6Å ¯5Å
(4.26)
4.1.3 CMOS Two-Stage Op Amp Design Procedure
In this section, we intend to present a procedure to design a CMOS two-stage op

amp based on the given specifications in a particular CMOS process. In
accordance with the given process in which our op amp is to be designed, some
design parameters are usually dictated by the process. Some of most important of
these parameters are the device threshold voltage, minimum permissible channel
- for MOS devices working in the subthreshold region. In the design of a CMOS
length, mobility of carriers, gate oxide capacitance, and subthreshold parameter of
circuit on paper, we usually make our lives easier by using simplified models for
devices. We are doing this in order to be able to put through our design. In fact,
designing on paper gives us an initial evaluation of the behavior of the targeted
circuit. Performing circuit simulations by employing very intricate advanced
models such as BSIM [2] helps the designer to direct the design toward his/her
goal. Of course, the designer needs to have comprehensive information about the
different physical limitations raised in the modern deep submicron CMOS process.
Phenomena such as short-channel effects, carrier mobility constraints due to high
longitudinal and transverse electric fields, and operating in a subthreshold region
are some critical points that should be taken into account in the design phase.
These pieces of information help the designer understand how to change MOS
device sizes in order to move the results obtained from simulations toward those
obtained from paper calculations. As it will be followed by a numerical design
LM , slew rate O', load capacitance Z , dc voltage gain 4 , and phase margin N& ,
example, here we assume the op amp parameters, including unity gain frequency
are given as our design goals and we plan to design a two-stage op amp to meet
these specifications. We now enumerate the different steps required in the design
of such an op amp.
Compensation Capacitance Determination: Our ultimate strategy is to cancel the
the first nondominant pole becomes ûŽ '$ where '$ is determined by

second pole by moving the right half-plane zero onto this pole. In this situation,
(4.25) such that we have
ûŽ
6, ¯5í
62 6, 6Å
(4.27)
As mentioned earlier, the main part of consists of the external load capacitance
and here we can almost take Z Selecting a small value for
. $ is an
as an on-chip component but a small $ relative to the load capacitance moves ûŽ

advantage in terms of saving in the required chip area to implement this capacitor
to lower frequencies and thus reduces the phase margin. Therefore there is a trade-
T Z . As discussed later, this selection is considered as an initial value for

off between the chip area and the phase margin. As a starting point, we choose
$
$ and we have not yet utilized (4.27) to ascertain optimum compensation
capacitance.
Calculating X0 and X0ê : Knowing just the value of $ does not help us to
calculate other parameters because X0ê and are unknown and both depend on
compensation resistance '$ is chosen in such a way that the zero of the circuit has
the sizing and biasing of M6. Hence, at present, we assume the series
been moved into infinity. By keeping this point in mind, we have LR X0ê Z
bandwidth, it is possible to calculate LR and thereby X0ê will be achievable. By

as the second pole. Now based on the required phase margin and unity gain
moving the right half-plane zero to infinity, and assuming LR … LR , the phase
margin is obtained from N& ; ° óôc/ “LM LR –. For example, if we need a
phase margin greater than < ° , it is enough to have LR ÷ dCLM . Since
LR X0ê Z , by knowing LR and based on the given Z , X0ê is obtained.
Based on the chosen value for $ H X0 is achievable from LM X0 $ . After
determination of X0 and X0ê according to the above discussion, at the end we
can increase '$ to place the zero on LR , which causes one-pair pole-zero
cancellation. By eliminating LR , the first nondominant pole will now be ûŽ given
in (4.27). This makes the phase margin larger than that of the considered design
goal. Therefore we can reduce $ as far as the phase margin reaches the given
value. At this stage, reduction of $ gives us an extra bonus: the widening of LM
without needing to increase X0 .
specified based on the op amp slew rate. Slew rate is calculated from O' W $
Tail Bias Current: The differential pair tail transistor current in the first stage is
with W as the current of the tail transistor and thus W $ ‹ O'. Again, reducing
$
important point regarding the value of W as the bias current of the differential pair.
in the previous step can help to increase the slew rate. Here there is an
It is quite possible that in a special design we need a wide bandwidth while having
a very large slew rate is not important to us. In this case if we take a rather small
hand, we need to have a large transconductance X0 to achieve the desirable

value for the slew rate, the calculated bias current becomes small. On the other
bandwidth. Supposing that the square law is held for differential pair input
transistors, to get the required transconductance at a certain bias current, we have
to take a large aspect ratio for our MOS devices. However, as discussed in Chapter
2, this condition causes device operation area changes to the subthreshold region
the transconductance. In fact, in this region we have X0 W --q¦ . As it is

with a completely different current equation and thus a different relationship for
obvious, increasing the device sizing has no effect on X0 , we first need to obtain
the least bias current that is able to provide required X0 in subthreshold region
and if this current is greater than that obtained from the slew rate data, we have to
choose the larger one as the bias current. Another issue with regard to
transconductance calculation is that using the square law to calculate
transconductance just gives a rough estimation of the value of transconductance.
This is because of the short-channel effect in new submicron MOS devices.
Taking into account the constraining effects of the short-channel and thin gate
oxide of the device on the mobility of free carriers, we should modify the drain-
current equation as [3]
4¡k /4£ 2
W) h
i
"V Z þ
©ý ¬ 4¡k /4£
(4.28)
³ vˆ‰
where h is the carrier mobility at low electric fields. Parameter represents the
oxide thickness drops. -KUq designates the velocity saturation of carriers. The
mobility degradation due to the high vertical electric field and increases as the gate
-fD
incremental transconductance is obtained by taking the derivative of (4.28) versus
X0HK$ h "V -fD -e ¾ ¾X0HZ6

z{: i
z4¡k Z
(4.29)
where X0HK$ and X0HZ6 denote the MOS transconductance in short and long-
channel states, respectively, and ¾ is defined as
Å þ
©ý ¬ 4¡k /4£
¾
2 ³ vˆ‰
2
þ
(4.30)
ç ©ý ¬ 4¡k /4£ è
³ vˆ‰
Equation (4.30) indicates that ¾ always is less than unity and drops by decreasing
calculations, we usually use simply a square law relationship to calculate X0 that

the channel length and gate oxide thickness in an MOS device. On paper
in fact gives X0HZ6 in (4.29). The actual transconductance is less than that
calculated on paper. Thus we take the goal transconductance a few percent more in
order to compensate this error.
First Stage Transistor Sizing: When the transconductance and drain current of M1
transconductance relationship X0 H •hY "V o p H W . The channel lengths of

and M2 is determined, we can easily obtain the input transistor aspect ratios from
M1 and M2 are determined based on the minimum required voltage gain of the
differential pair. As discussed in Chapter 3, the voltage gain of a differential pair is
given by
TC
¯5ÅH2
4 ¯ 2 ¯ Ë
where X" |Y W and X"Ç |R W are the small-signal output conductances

of M2 and M4. By substituting the transconductance relationship into (4.31), we
get the first-stage voltage gain as
•ÃÄ6 — i Z ÅH2
4 “ðÄ ðQ –•{
(4.32)
smaller |Y and |R and thus higher voltage gain.

For a certain bias current, using a longer channel length for M2 and M4 leads to
The size of M3 and M4 are calculated by assuming a reasonable value for the
voltage of the differential pair is -%$H0UV -)) -DfŽHÇ -eY that is nearly equal
overdrive voltage of these devices. The upper limit for the input common-mode
to -)) -"#HŽHÇ with -"#HŽHÇ as the M3 and M4 overdrive voltage. A small -"#HŽHÇ
helps to have high -%$H0UV , but at a certain bias current, low overdrive voltage
necessitates using PMOS devices with large aspect ratios that may cause the
designer to be faced with some constraints on other op amp parameters. First, low
overdrive voltage corresponds to high transconductance of M3 and M4, which
gives rise to more channel thermal noise contribution of these transistors in the
total input-referred noise. Moreover, a large aspect ratio of M3 and M4 magnifies
the mismatch threshold voltage of the devices in the input-referred offset voltage,
as indicated in Chapter 3. Another issue with a large PMOS load of the first stage
is associated with the op amp frequency response. Since the gate-source
capacitance of M3 and M4 determines the mirror pole location, using large sizes
for M3 and M4 increases this capacitance and thus lowers the mirror pole that
leads to degrade the phase margin. The aspect ratio of the tail transistor M5 is also
calculated based on choosing a proper overdrive voltage for this device. Here the
voltage of the differential pair according to -%$H0%Y -fD H -"#H . Knowing the
low overdrive of M5 helps to decrease the lower limit of the input common-mode
aspect ratio of M5, we assume a reasonable value for the M5 channel length and
then obtain its channel width. As discussed later, using a long-channel length for
M5 can help to improve the low-frequency CMRR of the op amp. Of course, in
order to keep the aspect ratio of M5 unchanged, we have to increase the transistor
width in direct proportion to the channel length. With a wide tail transistor, the
parasitic capacitance seen at the common-source node of M1 and M2 also
increases due to the M5 drain to the substrate capacitance. This capacitance

degrades the CMRR at high frequencies, as will be shown later.
The dimension of M6 and M7 are specified with regard to the systematic
offset voltage. As proved at the beginning of this chapter, by satisfying the
following relationship this offset can be eliminated:
² ²
F G F G
³ í ³ ï
² ²
F G F G
(4.33)
³ Ñ ³ é
To take care of matching issues associated with the layout, it is best to use the
same lengths for M5 and M7. The large channel length of M6 and M7 again helps
to increase the output resistance of the common-source stage that makes the
voltage gain of this stage larger. Of course the designer should watch out for the
effects of sizing on the stage frequency response.
Design Example
We plan to design a CMOS two-stage op amp in a 0.25- Š CMOS technology.

The given parameters by the process are -eY Ì-eR Ì =-, hY "V
= \¶ [ , hR "V = \¶ [ , and the subthreshold factor - #IR "V
T. The required op amp specifications are:
Dc voltage gain: 4 ÷ = ( or greater than BT >?)

Unity gain bandwidth: M ÷ = _ à
Phase margin: N& ÷ < °
Slew rate: O' ÷ [ \]
Load capacitance: Z = µ.
The design procedure begins by choosing $ T Z µ. Assuming the

zero has been moved to infinity, for N& ÷ < , we have LR X0ê Z ÷ dCLM .
With the given data, we need to have X0ê ÷ B Š¶ [. From LM ÷ X0 $ , we
°
obtain X0 ÷ < A \¶ [. Based on the given slew rate, from O' ÷ W $ , the tail
\¶. The minimum required aspect ratio of the
input transistors is determined from X0 ¾•hY "V o p H W ÷ < A \¶ [.
current should be greater than
Supposing that ¾ ;, we obtain the aspect ratio of the input transistors as

o p H ÷ A. Such large sizing with low level of drain current for these
transistors causes these devices to work in subthreshold. As discussed in Chapter
sizing and given by X0 W) --q¦ . For X0 < A \¶ [, W) should be

2, the transconductance in such an operating area is independent of the device
greater than C \¶. In order to make sure that input transistors work in saturation,
their drain currents should be larger than C \¶. By choosing W) C \¶,
recalculation of transconductance gives o p H ÷ C<. We choose o p H

T . Assuming p p \Š, to have enough voltage gain for the first stage we
will have o o T \Š. Referring to what was discussed about the M3 and
M4 overdrive voltage, a reasonable value for this parameter can be -"#ŽHÇ [
and therefore o p H ÷ C . We choose o p ŽHÇ T with pŽ pÇ = \Š
and thus oŽ oÇ \Š. Here we take the length of PMOS devices less than
that of NMOS. It is justified by knowing that |R is usually less than |Y and by
taking a lower channel length for PMOS at the same bias conditions, we can make
the output resistance of two NMOS and PMOS transistors close together which, in
turn, leads to maximum voltage gain for the first stage. Small sizing of M3 and M4
helps to improve the frequency response by moving the mirror pole to higher
=[, we will obtain o p T with p \Š and

frequencies, as mentioned earlier. By taking the overdrive voltage of the tail
o T \Š. Assuming the square law is held for all transistors, we can write the
transistor M5 less than
transconductance of M3 and M6 as X0Ž hR "V o p Ž -DfŽ Ì-eR Ì and

X0ê hR "V o p ê -Dfê Ì-eR Ì , respectively. On the other side, we have
-DfŽ -Dfê , and thus we can write X0ê X0Ž o p ê o p Ž .X0Ž
¾•hR "V o p Ž W C Š¶ [ X0ê B Š¶ [
o p ê o p Ž A A. By rounding this ratio to 9 and from (4.33), we have
and and thus
o p ê C< and o p Œ A . For pê = \Š and pŒ \Š, we get

oê oŒ A \Š. From circuit simulation, we obtain the transconductance of
M1,2 and M6 as X0 H = Š¶ [, X0ê ;< Š¶ [, and dc voltage gain as
4 B; ; >? Now we choose the compensation resistance '$ such that the zero
and the second pole, LR , cancel each other out. To this end, we calculate the
resistance from '$ X0ê Z $ A œ . Repeating simulation
while adding '$ , we obtain N& B< <° and LM ‹ CT ; _ à. Phase margin
is more than our desirable value but the bandwidth does not meet our requirement.
$ that simultaneously leads to increase LM X0 $ . Modifying the

As said before, here we have enough room to lessen the phase margin by lowering
compensation components as ë$ µ and '$ X0ê “ Z

ë$ – œ ,
we get N& < and LM
°
‹ < A _ à which both satisfy the required
specifications.
Now the reader may raise the question of how we can realize the
compensation resistor. In a CMOS mixed-mode technology, several different types
extensive variations with process. From (4.25) we see that the term X0ê '$
of on-chip resistors are available. The main problem with this kind of resistor is its
process. By implementing '$ with an MOS device that works in the triode region
depends on the ratio of two capacitances that it could be quite stable versus
it is possible to provide this condition [4]. The schematic of the two-stage op amp
in which the compensation resistor has been replaced by MOS devices is shown in
Figure 4.8. In this circuit we can write
VDD
M10 M3 M4 M6
Cc
M9
M11 vo
Ib M1 M2
-
vi
+
M8 M7
M12 M5
Figure 4.8 MOS devices used for frequency compensation.
-Dfê Ì-eR Ì
{:í
ÁÃQ 6 ²
—F ³ G
(4.34)
í
-Df Ì-eR Ì
{:Å
ÁÃQ 6 ²
—F ³ G
(4.35)
Å
If the current density in M6 and M10 are equal (i.e., we set W)ê o p ê
W) o p ), from (4.34) and (4.35) we have -Dfê -Df . Summation of the
-Dfê -Df -Df -Df and therefore we have -Df -Df . The diode-
gate-source voltages around the loop consisting of M6, M9, M10, and M11 gives
connected M11 always works in saturation while M9 operating in triode with zero
drain current and thus its drain-source voltage is also zero. The equivalent
resistance of M9 is
'"Y ²
ÃQ 6 — F G “4k¡ /Ì4£Q Ì–
(4.36)
³
On the other hand, the overdrive voltage of M11 is given by
-Df Ì-eR Ì -Df Ì-eR Ì

{:ÅÅ
tÃ
Q 6 — i Z ÅÅ
(4.37)
From (4.36) and (4.37), we have
²
F G
'"Y
³ ÅÅ
²
F G ¯5ÅÅ
(4.38)
³
If '"Y is used as the compensation resistor, from (4.38) it can be seen that
X0 '"Y depends on the size ratio of M11 and M9 with the minimum sensitivity
to the process variations. By replacing '$ in (4.25) with (4.38), we have
²
¯5í F ³ GÅÅ 6³
¯5ÅÅ F²G 6,
(4.39)
³
Where is approximated by Z. The transconductance ratio in (4.39) can be

written as
²
F G
Á
¯5í {:í
t{
³ í
²
¯5ÅÅ F G
(4.40)
:ÅÅ
³ ÅÅ
Since the current density in M6 and M10 are equal and also W) W) , from
(4.39) and (4.40) the size of M9 is obtained as
²
F G
F G F G Á
i 6, i ³ ÅÅ
²
Z 6³ 6, Z ê F G
(4.41)
³ Å
The aspect ratio of M11 is not critical and here we take o p to save
of the devices used to realize the resistor '$ . The amount of bias current in a two-
the chip area. Now to complete our design example, we determine the dimensions
series diode-connected M10 and M11 is optional. From W)ê o p ê

W) o p , and by choosing W) B = \¶, pê p p p = \Š,
we can obtain o W) W)ê oê = \Š and from (4.41) we have o
B = \Š. Simulation with these data gives N& < ° and LM ‹ <A A _ à.
to B \Š, we reach rather better results of N& < A° and LM ‹ B < _ à

By applying a fine adjustment on the size of M9 through changing its width
while the total power dissipation is A; Š .
4.1.4 PSRR of CMOS Two-Stage Op Amp
This parameter indicates how much an op amp is able to attenuate any disturbance
signal on its way from each supply to the op amp output. To obtain the
relationship of the positive PSRR we put an ac source voltage at this supply and
then replace the op amp circuit with its small-signal equivalent circuit and
calculate the circuit transfer function. Figure 4.9 shows the op amp circuit in the ac
Vp M3 M4 M6
Cc
Vo
M1 M2
Thevenin
equivalent
M7
gm4V
Vp -
1/gm3 ro4
V
2ro1,2
Thevenin
equivalent
Figure 4.9 Op amp in ac condition with small-signal equivalent of its differential pair.
condition before replacing devices by their small-signal equivalent circuits and

also the small-signal equivalent circuit of the differential pair under the
simplifying assumption that the output resistance of the tail transistor is infinity.
Figure 4.9, we get the Thevenin equivalent voltage as -q¦ -R and the Thevenin
By inspection of the small-signal circuit of the differential pair shown in
equivalent resistance as
X"Ç
¯5Ñ ¯5Ë
8‰¥ ¯5Ñ . ÅH2
(4.42)
with X0Ž X0Ç and assuming X0Ž Ò" H , we obtain 'q¦ Ò" Ó Ò"Ç ' .
Now we replace the entire small-signal model for the circuit of Figure 4.9 as
illustrated in Figure 4.10. Summing currents at nodes A and B, we have
½ - -"
41 /4Q
8Å $ (4.43)
½ $ -" - X"Œ -" X0ê “- -R – X"ê “-" -R – (4.44)
From (4.43) and (4.44), we can calculate the circuit transfer function as
R1 A
+ V -
Vp gm6V Vp
ro6
Cc
B Vo
ro7
Figure 4.10 Simplified small-signal model for op amp PSRR calculation.
Å Å
¯5í ¯ í F K6, G K6, /¯5í
× ½ Å
Å
Å
K6, ¯ í ¯ ï F K6, G/K6, K6, /¯5í
(4.45)
Å
By denoting X"ê X"Œ ' and noting that X"ê … X0ê , we can simplify (4.45)
as
Å ¿5í Å
K6, F8Å G
½ X"ê '
¿ í ¿ í
× K6, 8Å 82 ¯5í 8Å 82
(4.46)
In (4.46), the last term inside the parenthesis in the nominator is much greater than
the two first terms. The same statement is true for the denominator as well. Thus,
function as LR X0ê ' ' $ and LÞ X"ê X0ê ' $ .

we can obtain the approximate value of the single pole-zero pair of the transfer
We have LÞ LR X"Œ X"ê X"Œ which means the zero takes place
before the pole as depicted in the gain and phase frequency response of the
transfer function in Figure 4.11.
|AP(jω)| (dB)
0 ωz ωp ωp2 ω
AP0
AP(jω)
0 ω
Figure 4.11 Gain and phase versus frequency for positive supply to output transfer function.
The PSRR is defined as the ratio of the differential voltage gain of the op amp
and the voltage gain from supply to the op amp output
NO'' X * + ºõ
* ™ ¹ # ÀL ¹ X ¹ × ÀL ¹ (4.47)
Ú ºõ
If the op amp frequency response # ÀL is approximated as a single-pole

transfer function, the magnitude of the PSRR+ frequency response can be
magnitude of PSRR at low frequencies (less than LÞ ) is even greater than the op
represented as illustrated in Figure 4.12. As can be seen from Figure 4.12, the
amp dc voltage gain but at the frequency of LÞ that is less than the op amp open-
loop bandwidth, PSRR starts dropping. This fact indicates that the performance of
frequency higher than LÞ . This behavior is regarded as the main drawback of the
the op amp to prevent the supply noise from penetrating to the output degrades at
two-stage op amp with this particular architecture.

Before dealing with the circuits that can solve this issue, we first obtain the
corresponding PSRR for the negative supply in order to compare its behavior with
its positive supply counterpart. As explained in Chapter 1, the transfer function of
a voltage follower implemented by an op amp from any supply to the output
defines the PSRR associated with that particular supply. Hence, we utilize the
4.13 we have -" # -" × -K and since #

/
, we can write -K -"
circuit shown in Figure 4.13 to calculate the PSRR of negative supply. In Figure
# ×
that gives the approximate value of the PSRR for negative supply. In Figure 4.14
the small-signal equivalent circuit of the voltage follower is shown in which two
main capacitances at the outputs of two-stages, compensation capacitance of $ ,
and the gate-drain overlap capacitance of M7 are taken into account. Summation
of currents at nodes A and B results in
È ½ ½ $ - X0 ½ $ -" (4.48)
PSRR+
PSRR0
20log|Ad|
- 20log|AP|
ω
ωz ωp
Figure 4.12 PSRR+ frequency response of a two-stage op amp.
−
Vo
Ad
+
Vs
Figure 4.13 Configuration used to calculate PSRRR of the negative supply.
“X"ê X"Œ ½ ½ $ ½ ¯#Œ –-"Mq X0ê ½ $ -

“X"Œ ½ ¯#Œ –-K (4.49)
where È ',È X"ê X"Œ with X"ê Ò"ê , and X"Œ Ò Œ . Solving
(4.48) and (4.49), we can derive the PSRR of the negative supply as
UK 2 „K fÅ f2 ¯5Å ¯5í
NO'' /
4v
4 “K6¿+ï ¯ ï –ÔK 6Å 6, fÅ Õ
(4.50)
where ö $ $ ¯#Œ $ ¯#Œ and ø È “ $

¯#Œ – È $ X0ê X0 $ .
From (4.50), the dominant pole of PSRR- is LR È $ , which is
larger to that of PSRR+. This proves that the performance of the op amp shown in
Figure 4.1 to prevent the high-frequency noise on the negative supply voltage from
degrading the op amp output signal is better with respect to its positive supply
counterpart. For a two-stage op amp with complementary structure in which the
input transistors of the differential pair are PMOS, PSRR+ has a better high-
frequency characteristic.
A Cc B
gm1Vo + +
gm6V1
R1 C1 C2 Cgd7
ro6 ro7
V1
Vo
- -
Vs
ro5
Figure 4.14 Small-signal equivalent circuit of a voltage follower.
Improvement of the PSRR+ Frequency Response: The reason for imperfect

performance of the PSSR+ frequency response in the op amp shown in Figure 4.1
is the existence of a low impedance path between the positive supply and output.
This path is created by the fixed gate-source voltage of M6 and the compensation
capacitor $ in this path. By adding a common gate stage between the gate and
drain of M6, as shown in Figure 4.15, we can remove the low-impedance path.
Prior to showing how the common gate stage realized by transistor M8 can
improve the PSRR+, we first derive the voltage gain of the modified circuit in
order to have a comparison between the main parameters such as dc voltage gain
and the dominant pole location of the new circuit and the previous one. The small-
source theorem on X0 - is shown in Figure 4.16, where ' Ò" Ó Ò"Ç Ó Ò"R ,
signal equivalent circuit and its modified version with the applied transformation
with Ò"R as the output resistance of the upper current source of W . ' is the same as
in Figure 4.6, and Ò"Y is the output resistance of the lower current source of W , and
since Ò"Y X0 we can take Ò"Y Ó X0 X0 .
Summing currents at the input and output nodes, we can write
X0 -% È ½ - X0 - (4.51)
È ½ -" X0ê - X0 - (4.52)
As before, we denote È ' ,È ' . The voltage - across the resistance

of Ò"Y Ó X0 is nearly equal to ½ $ -" X0 ½ $ . Solving the above
equations, we can obtain the voltage gain in s-domain as
VDD
I1
M3 M4 M6
vo
Vbias
M1 M2 M8
-
vi Cc
+
I0
Vb Vb M7
M5 I1
Figure 4.15 Modified two-stage op amp for PSSR+ improvement.
gm8V2
Cc
+ - +
gm1Vi gm6V1
R1 C1 ron C2
V1 V2 R2 Vo
- + -
Cc
+ + +
gm1Vi gm8V2 gm6V1
R1 C1 C2 V
V1 V2 ron||1/gm8
R2 o
- - -
Figure 4.16 Small-signal equivalent circuit of a modified two-stage op amp.
½
4
4 4Å
Â,
¯5Å ¯5í K
¿5
fÅ f2 Â Â Â, ¿5í Â, Â, ÂÅ Â2 Â, Â2 Â, ÂÅ Â, ÂÅ 2 ÂÅ Â2 Â, Ñ
F Å 2 GK F GK K
(4.53)
¡Å ¡2 ¿5 ¡Å ¡2 ¡2 ¡Å ¡2 ¿5 ¡2 ¿5 ¡Å ¡Å ¡2 ¡Å ¡2 ¿5
First we consider a case that all three poles are real; in this situation the
general form of the transfer function can be written as
v
½
ÝÅ
4 4 v v v
F GF GF G
(4.54a)
QÅ Q2 QÑ
or
v
½
ÝÅ
4 4 Å Å Å Å Å Å vÑ
F GK F GK 2
(4.54b)
QÅ Q2 QÑ QÅ Q2 QÅ QÑ Q2 QÑ QÅ Q2 QÑ
where 4 X0 X0ê È È and ü X0 $ . Because of Ò"R loading on the

first stage output, here ' is a little bit smaller than that of previous circuit and
assumed that û … û H ûŽ , we have

thus the dc voltage gain somewhat less than that of our initial circuit. If it is
û ÂÅ Â2 Â, ¿5í Â, Â, (4.55)
¡Å ¡2 ¿5 ¡Å ¡2 ¡2
Since the term of X0ê $ È È in the denominator of (4.55) is the largest term,
the approximate value of the dominant pole becomes È È X0ê $ . This proves
circuit before adding M8. If we can also assume û û … û ûŽ H û ûŽ , from (4.53)

that the location of the dominant pole is almost the same as that of our initial
and (4.54), we have

6Å 62 6, 62 6, 6Å 6, 6Å
RÅ R2 fÅ f2 ¯5 f2 ¯5 fÅ fÅ f2
(4.56)
In practice, H $ and X0 È H È and as a result, the right side of (4.56)

can be approximated by $ È È . Using (4.55) and (4.56), we can get
the relationship for the second pole as
û
¯5í 6,
Â,
62 6Å F G
(4.57)
Â2
It is interesting to note that under the condition that $ $ , the

condition that is usually met, according to (4.57) the second pole of the modified
circuit is larger than that of our initial circuit. By equating the coefficient of the
cubic term in the denominator of (4.53) to its corresponding term in (4.54) and
using the approximate value of (4.57), we can obtain the third real pole as
ûŽ T =A
¯5
6v
where K $ $ and $ . Since K $,

we have ûŽ ü . The locations of poles and zero in the modified two-stage op
is the series connection of
amp is shown in Figure 4.17. Now we consider another possibility in which the
modified circuit has one real pole and two conjugate poles. In this situation, the
general form of the circuit transfer function can be represented by
v
½ T =;
ÝÅ
4 4 v v v2
F G~ •
QÅ Ü Ü2
jω
s-plane
X X X σ
p3 z1 p2 p1
Figure 4.17 Poles and zero positions of the modified op amp.
where L and g are the natural frequency and quality factor of the circuit,
respectively. The zero ü has not changed. By expanding the denominator of
(4.59) and equating corresponding coefficients in (4.53) and (4.59) and applying
the same approximations used in previous case, we will have
¯5í 6,
RÅ õ fÅ f2
(4.60)
6Å 62 6,
RÅ õ õ2 fÅ f2
(4.61)
6Å 62 6,
RÅ õ2 fÅ f2 ¯5
(4.62)
If û is assumed as the dominant pole, we have L g û and L û L g and

thus from the above equations we can determine the relationship for û H L , and g
û
as follows:
¯5í 8Å 82 6,
(4.63)
L
¯5í ¯5
t 6Å 62
(4.64)
¿5í
g Á
6, ÂÅ
¿5
6, 62
(4.65)
Â2
Equations (4.64) and (4.65) show that increasing X0 helps to shift L to higher
frequencies and simultaneously decrease the quality factor g, which both help to
improve the op amp stability According to (4.65), decreasing $ can also lessen g,
but because this leads to increase LM X0 $ , it causes LM to approach L and
as a result, the phase margin degrades. It should be pointed out that in the modified
circuit there is no need for an extra resistance to move the right half-plane zero
creates a left half-plane zero with a value of X0 $ . The price that has been paid
into the left. In fact, M8 in addition to improving the PSRR+ as shown next, M8
loading of the current source of W on the output of the first stage, increased input-
for the gained advantages are slight reduction of the dc voltage gain due to the
referred noise generated by the added active devices including current sources and
M8, and more power dissipation.
PSRR+ Calculation in the Presence of the Common Gate Stage: Now we are ready
to obtain the frequency response of the PSRR+ for the circuit of Figure 4.15. We
put an ac voltage source at the positive supply and use the Thevenin equivalent
circuit of the first stage based on our previous discussion associated with Figure
R1 A
+ V1 -
VP VP
ro8 ro6
gm8V2 gm6V1
B
+ Cc C +
V2 ro7 Vo
ron
- -
Figure 4.18 Small-signal circuit for modified op amp PSRR calculation.
4.9. The equivalent circuit in the ac condition is illustrated in Figure 4.18.

Summation currents at nodes A, B, and C gives
È X" - X" X0 - È -× (4.66)
-X" - X" X0 X"Y ½ $ - ½ $ -" (4.67)
X0ê - ½ $- È ½ $ -" X0ê X"ê -× (4.68)
Neglecting X"ê and X" against X0ê and X0 in (4.66), (4.67), and (4.68), we have
-"
½
×
-×
¡Å ¿5í
¯ ¯ Ä¯5í F 6 KG
¿5í ¿ Ä ,
fÅ f2 ¯ Ä ¯5 f2 ¯ Ä¯ K6, fÅ f2 f2 ¯ fÅ ¯ Ä ¯ Ä¯ fÅ ¯5 ¯5 ¯5í
(4.69)
Since X0ê H X0 È H È H XÎY H X" , we can obtain the approximate value of single
zero and pole of × ½ as LÞ X"Y $ and LR È È X0ê $ . In practice,
X"Y È È X0ê , which means the zero takes place after the pole. By considering
the op amp voltage gain frequency response as a single-pole transfer function and
responses (i.e., # ÀL , × ÀL , and PSRR+) is plotted in Figure 4.19. This plot

using (4.47), we can obtain PSRR+. The magnitude of all three frequency
shows the modified circuit is able to attenuate the noise on the positive supply up
to higher frequencies in comparison to our initial circuit.
Op Amp Slew Rate in the Presence of the Common Gate Stage: When the op amp
is used as a voltage follower and a relatively large step voltage is applied to its
input, the slew rate limitation indicates itself by steering the entire tail current of
the differential pair to one side and cutting off the other side of the pair. If the
circuit of Figure 4.15 is used as a voltage follower and we apply a positive step
voltage as its input, in a large-signal condition the total current of the tail
PSRR+
PSRR0
20log|Ad|
- 20log|AP|
ω
ωp ωz
Figure 4.19 PSRR+ frequency response of a modified two-stage op amp.
transistor, W , steered toward M2 and M1 is turned off. The internal circuit of the
circuit, the charging current of $ (i.e., W ) is equal to W W W . In order to

voltage follower under the stated condition is represented in Figure 4.20. In this
keep M8 on, we need to have W W . In the falling edge of the input voltage step,
the direction of the current W is reversed and a current W / in the opposite direction
of W discharges $ , which is equal to W W W . In order to have an output
voltage with the same positive and negative slopes we need to have W W / that is
equivalent to having W W W , which results in having a slew rate of W $ . An
condition of W W W forces the designer to employ high current for the bias
op amp with a large slew rate requirement needs to use high tail current and the
current sources. This situation not only increases the total power dissipation of the
circuit, but also decreases the effective resistance seen at the output of the first
stage, and in turn reduces the dc voltage gain of the op amp.
VDD
I2
I0
M6
ID8
Vbias
M8
M2
Vi I+ Vo
Cc
I0 I1
Vb M7
Figure 4.20 Modified op amp circuit in large-signal conditions.
VDD
M7 M8
M5
Vbp M6
Vo
CL
M3
Vbn M4
+ M1 M2
Vi
-
I0
Figure 4.21 Telescopic op amp.
4.2 Telescopic Cascode Op Amp
In a two-stage op amp the entire voltage gain is the product of the voltage gain of
two cascaded stages that can be a large number. This is one of the main
advantages of this architecture, particularly in submicron CMOS technology in
which providing a high voltage gain through a single stage is difficult. This is
because of rather low drain-source resistance of MOS devices due to the short-
channel effects. A telescopic cascode op amp, in fact, is a differential pair whose
active load is a wide swing current mirror rather than a simple one and the
converted differential current at the drains of the differential pair is injected to the
load through a current buffer implemented by a common gate stage. A telescopic
op amp with NMOS input devices is shown in Figure 4.21.
In the absence of an ac signal, similar to a normal differential pair the dc
-)) -DfŒH . The low-frequency voltage gain is determined by the total equivalent
voltage at the output is the same as that of the drain of M3-M5 and is equal to
resistance seen at the output node that consists of a parallel combination of the
'"Mq X0Ç Ò"Ç Ò" Ó X0ê Ò"ê Ò" , the small-signal voltage gain of the cascode
resistances of two lower NMOS and upper PMOS cascode structures. By denoting
op amp becomes X0 '"Mq . The drain-source resistance of each MOS device

depends on its bias drain current as Ò"% |% W)% for ® HTH<HA. Assuming the
drain current of M1 and M2 following the square law, we can write X0 H
•hY "V o p H W and thus the dc voltage gain relationship can be written as
Ç•ÃÄ6 — i Z ÅH2
4 2
(4.70)
2 Q
Ï Ä Ð{
tþÄ Â — ² ³ ÑHË tþQ Â — ² ³ éHí
where |Y | |Ç and |R |ê | denote the parameter of | for NMOS and

PMOS devices. Equation (4.70) indicates that for a particular tail current W , the
only way to increase the dc voltage gain is to decrease |Y and |R by taking a long
channel length for M2, M4, M6, and M8 and also choosing a large aspect ratio for
input devices M1 and M2 and cascode transistors M4 and M6.
The Frequency Response: The largest resistance is seen at the output node where
there is the load capacitance so that the dominant pole of the circuit is made by
the gate of M7-M8 with a value of X0ŒH

this node. The second pole is generally associated with the mirror pole created at
¯KŒH . This pole is usually widely
separated from the dominant pole such that the unity gain frequency normally
op amp is plotted in Figure 4.22. The dominant pole is LR '"Mq Z and the
occurs before the second pole. The magnitude and phase frequency response of the
unity gain bandwidth is given by LM X0 Z . This shows that when the load
capacitance increases, LR and LM decrease while the second pole LR is kept
unchanged. As a result, increasing Z helps to improve the op amp stability, which
is the opposite of what happens in a two-stage op amp where increasing the load
capacitance degrades the phase margin. Of course, the price that we have to pay
for this advantage in telescopic structure is the reduction of bandwidth for a larger
Z.
|AV(jω)|
AV0
ωp1 ωu ωp2
ω
AV(jω)
0 ω
-90
-180
Figure 4.22 Gain and phase versus frequency for a telescopic op amp.
Now we proceed to introduce a major drawback of the telescopic structure.

Let us use this op amp as a voltage follower as depicted in Figure 4.23. The
maximum allowable level of the output voltage swing is limited by entering M2
into the triode region, which happens when the output voltage goes beyond the
-„Y -fDÇ , this is equivalent to have -" -„Y -fDÇ -e . On the other side,
voltage of node A by one threshold voltage. Noting that the voltage at node A is
triode region. Thus the lower limit of the output voltage will be -„Y -eÇ . As a
when the output voltage goes down, its swing is limited by entering M4 into the
-„Y -eÇ -" -„Y -fDÇ -e or equivalently we have -"H0UV -e

result, the allowable variation range of the output voltage is determined by
-fDÇ -eÇ -e -"#Ç . This proves that the maximum output swing of our
voltage follower is less than one threshold voltage independent of the value of the
supply voltage. This is considered as a major drawback of telescopic structure,
particularly in low-voltage design where providing large output voltage swing is
significant. The previously mentioned imperfection regarding telescopic cascode
can be treated by applying some modifications on the circuit structure that brings
up the folded-cascode structure as the subject of the next section.
VDD
M7 M8
Vbp M5
M6
Vo
Vbn M3
M4
A
+ M1 M2
Vi
-
I0
Figure 4.23 Telescopic op amp used as a voltage follower.
4.3 Folded-Cascode Op Amp
In a usual telescopic cascode the same type of transistors used in cascode

structures are stacked in the differential pair. In a folded-cascode structure the type
of the transistors used as common gate stage is different from those used in the
differential pair.
The PMOS transistors M6 and M7 in the circuit of Figure 4.24 act as cascode
transistors. The PMOS current sources M4 and M5 provide the bias currents of the
differential pair and the cascode transistors. If this circuit is used as a voltage
which is -"H0UV -„R Ì-eR Ì where -„R -)) -"#Ç -Dfê with -"#Ç as the
follower, the maximum swing of the output is limited by entering M7 into triode,
M4 overdrive voltage. Since -Dfê Ì-eR Ì -"#ê , supposing -Î#Ç -"#ê and
denoting it by -"#R , we have -"MqH0UV -)) -"#R . Similarly, we can easily
indicate that the lower limit of the output voltage swing is -"H0%Y -"#Y where
-"#Y is defined as the equal overdrive voltage for M8 and M10. However, in a
voltage follower configuration implemented by such an op amp, prior to reaching
this minimum level, the lower output voltage swing will be limited by the input
differential pair because the tail transistor M3 approaches the triode region.
Now we obtain the low-frequency voltage gain of the folded-cascode op amp.
replace the small-signal equivalent circuit, as shown in Figure 4.25. ' denotes the
In differential mode, the sources of M1 and M2 are virtually grounded and we can
' Ò" X0 Ò" Ò" , and ® represents the ac current entering the diode-
output resistance of the cascode stage consisting of M9 and M11 that is equal to
input current X0 -% that is divided between two parallel resistances of Ò" Ó Ò"Ç
connected configuration of M8 and M10 and equals the partial component of the
and ' Ò"ê X0 X0ê Ò"ê X0ê . Since Ò" Ó Ò"Ç X0ê ,
VDD
M4
Vbp1
M5
B
M6
Vbp2 M7
+ M1 M2 Vo
Vi
M8
-
Vbn
M9
Vb M3 M10 M11
Figure 4.24 Folded-cascode op amp.
gm6vsg6 gm7vsg7
A B vo
i10 +
gm1vi/2 + ro6 gm1vi/2 ro7
vsg7 i10
vsg6 RA 1/gm10 R9
ro1||ro4 ro2||ro5
- -
Figure 4.25 Differential-mode half-circuit small-signal equivalent circuit.
almost the entire current of X0 !% flows through ' and ® X0 !% .

Summation currents at nodes B and the output node give the following equations
X"Œ “!K¯Œ !" – X0Œ !K¯Œ !%

v¿ï ¯5Å
8
(4.71)
® X"Œ “!" !K¯Œ – X0Œ !K¯Œ

8
(4.72)
where ' Ò" Ó Ò" . From (4.71) and (4.72), the small-signal low-frequency
voltage gain is obtained:
X0 F G
8ï 8 . ï
8ï 8 8ï
(4.73)
'Œ designates the equivalent resistance seen at the drain of M7 with the value of
'Œ Ò"Œ X0Œ Ò"Œ '. By defining '"Mq 'Œ ' 'Œ ' and noting that
X0Œ Ò"Œ ¾X0 '"Mq with ¾ “ X0Œ Ò"Œ –.
The coefficient ¾ is less than one but it is very close to unity. As it is clear, the
, we rewrite (4.73) as
folded-cascode structure has the same voltage gain relationship as the telescopic.
Moreover, in terms of frequency response, both structures have the same behavior.
the mirror pole with approximate values of L X0ê ¯Kê and L0%..
The higher-order poles are formed at node A (or B) and at the gate of M10-M11 as
X0 “ ¯K ¯K –, respectively.
Design Example
In this section we intend to design a folded-cascode op amp with exactly the same
specifications given for the two-stage one. Here for the sake of simple reference,
The technology parameters are -eY Ì-eR Ì =[, hY "V = \¶ [ ,

we repeat these specifications.
hR "V = \¶ [ , and subthreshold factor - #IR "V T. The

required op amp specifications are
Dc voltage gain: 4 ÷ = (or ÷ BT >?)

Phase margin: N& ÷ < ›
Slew rate: O' ÷ C [ \]
Load capacitance: Z = µ.
The design procedure begins by determining the required tail current from the
calculated from O' W Z . As a result, we should take W ÷ = \¶ that gives

given value for the slew rate. In a folded-cascode structure, the slew rate is
W) W) B= \¶. From the given bandwidth the minimum required

transconductance of the input devices is obtained from LM X0 Z , which for
LM ‹ = _ à gives X0 < Š¶ [. The schematic of the op amp
including bias circuitry is depicted in Figure 4.26.
Here we have used PMOS devices as the input transistors of the differential
pair. In an n-well CMOS technology, PMOS devices are implemented within the
n-well and it is possible to tie the body and source terminals together for each
PMOS device that has been placed in a separate n-well. This possibility can help
us to avoid the body effect. Moreover, from the noise standpoints, as discussed
previously, the flicker noise of PMOS transistors is less than that of NMOS at least
by one order of magnitude which in turn helps to reduce the input refereed noise.
Because the mobility of carriers in PMOS transistors is less than that of carriers in
NMOS devices, to get the equal transconductance at the same bias current, we
have to choose the PMOS aspect ratio larger to the extent that it compensates for
VDD
M16
M14 M3 M10 M11
I0
Vbp
M8 M9
M18
+ M1 M2
Ib vi vo
-
CL
Vbn
M15 M7
M6
I4 I5
M12 M13 M17

M4 M5
Figure 4.26 Design example of a folded-cascode op amp with PMOS input devices.
its smaller carrier mobility. This larger size, as an extra bonus, helps to reduce the
input noise and offset voltage as well. Of course, large devices with rather small
drain current may put PMOS devices in the subthreshold region. If that occurs, we
no longer can reach the required transconductance by increasing the aspect ratio
; \¶ to make sure the required transconductance is achievable. A low-level drain

for a fixed drain current. As a result, the drain current of M1 and M2 is raised to
current makes it easier to get the required voltage gain by increasing the drain-
source resistance of transistors but because sizing is rather large, devices work
somewhere between saturation and moderate inversion, which causes deviation of
considered by taking ¾ B With this value for ¾, from

the transconductance relationship from the ideal quadratic form. This issue may be
X0 H ¾ •hR "V o p H W ÷ < Š¶ [ we need to meet the inequality

o p H =A . By taking o p H < and in order to avoid dropping the
dc gain due to short-channel effects in M1 and M2, we choose p H T \Š and
thus o H T \Š. The current sources implemented by M4 and M5 should
provide the drain current of M1 and M2 and also the current of cascode transistors
M6 to M8. In a large-signal condition when the tail current is steered toward M1
or M2, the tail current plus the cascode bias current flow through M4 or M5 and
therefore the current of M4 or M5 should be larger than the tail current in order to
avoid turning off the cascode devices in this condition. Thus the amount of current
WÇ W W < \¶ The size of the rest of the main transistors including

in M4 and M5 is chosen somewhat more than the tail current. Here we take
M4 to M11 are all calculated by allocating proper overdrive voltages to them. To
Š[ is allocated to M6, M7, and about

get reasonable aspect ratio for devices and enough output voltage swing, an
Š[ is chosen for M4 and M5 and M8 to M11. The reason that we choose a

overdrive voltage of approximately
smaller overdrive voltage for NMOS devices is that when this architecture is used
as a voltage follower, the lower limit of the output voltage swing is determined by
that is !"H0%Y -"# -"#Œ , but the output swing from above, prior to reaching
the sum of the overdrive voltage of the output NMOS transistors (i.e., M5 and M7)
-)) -"# -"# , is limited by M1 and M3 in the input stage. This means that
allocating large sizes to M8 to M11 just degrades the stability by lowering the
Š[ to
mirror pole location without influencing the effective output swing. M4 (M5)
carries the largest current and thus its overdrive voltage is chosen about
overdrive voltages, the aspect ratio of o p

get reasonable aspect ratio. Based on the given process data and with these
and o p ÇH < for M4 and M5. In order to have adequate large output
is obtained for M6 to M11
p = \Š is selected for M6 to M11. Therefore the aspect ratio of M6 to M11

resistance to achieve the required dc voltage gain, the channel length of
will be obtained as < \Š = \Š. The loading effect of the drain-source

resistance of M4 and M5 leads to decrease the voltage gain. Since these devices
carry relatively large currents, it is necessary to minimize the parameter of
| }#K “p•-)D -)DHKUq – to gain the maximum resistance (Ò" |W) )). With
this aim in view, we increase the drain-source voltage, -)DÇ -)D -„Y
-fDêHŒ , by raising -„Y and select a channel length of pÇ p \Š, as well. The
transistors (M15, M16) and (M17, M18) are used to provide the bias voltages -„Y
and -„R , respectively. The bias current source W„ A \¶ with the aid of M12,
BT C >?,
M13, and M14 supplies the current of the tail transistor M3 and transistors M4 and
M5. The results obtained from the circuit simulation are 4
LM ‹= _ à, N& B;› , and a power dissipation of C Š . Output
slew rate on the positive slope is O' ; = [ \] and on the negative slope is
O'/ C= B [ \]. Although these results indicate the performance superiority of a
two-stage op amp over the folded-cascode architecture in terms of the voltage
gain, bandwidth, and power consumption but the PSRR frequency response of a
folded-cascode is much better than that of a normal two-stage one. More
importantly, the process of frequency compensation here is very simple. Actually
the load capacitance itself plays the role of the compensation capacitance and there
is no need for an extra component as a compensation capacitor.
4.4 Current Mirror Op Amp
A basic schematic of a current mirror op amp is shown in Figure 4.27. In the

presence of the ac input signal the total current of M1 (M3) and M2 (M4) can be
written as
®) ®)Ž W
¯5ÅH2
(4.74)
®) ®)Ç W
¯5ÅH2
(4.75)
These currents are amplified by two current mirror pairs of M4-M6 and M7-M8
and appear at the drain of M6 and M8:
®)ê }W }
¯5ÅH2
(4.76)
®) }W }
¯5ÅH2
(4.77)
resistance seen at the output node (i.e., '"Mq X"ê X" . The output
The difference of the two currents above flows through the equivalent output
voltage becomes -" '"Mq ®)ê ®) and thus the low-frequency small-signal
voltage gain is given by
‡¯5ÅH2
¯ í ¯
(4.78)
VDD
M5 M3 M4 M6
1:1
1:K
M1 M2 + vo
vi
-
CL
2I0
M7 1:K M8
Figure 4.27 Schematic of a CMOS current mirror op amp.
Since X"ê |R W)ê and X" |Y W) with W)ê W) }W and assuming the
write X0 H • hY "V o p H W) H , from (4.78) we have

square law is held for the drain current of M1 and M2 such that we can
²
t ÃÄ 6 — F ³ G
ÅH2
“ðÄ ðQ –•{
(4.79)
current mirrors. Thus, for a certain bias current W , the only way to increase the
It is interesting to note that the dc voltage gain is independent of the K factor in the
voltage gain is to choose a long-channel length for M6 and M8 and increase the
aspect ratio of the input devices, M1 and M2, provided that these devices remain
in strong inversion. As discussed earlier, by increasing the transistor aspect ratio,
at a certain drain current, an MOS device ultimately reaches a point at which the
following inequality is held:
hY --q¦
{:ÅH2
² "V
F G
(4.80)
³ ÅH2
When the left-side term in (4.80) is adequately less than the right-side term,
transconductance, X0 H W) H --q¦ . In this condition the dc voltage gain is

transistors work in the weak inversion area with a new relationship for the
specified as
“ðÄ ðQ –±4‰¥
(4.81)
In the subthreshold region, corresponding to a weak inversion state, the voltage

gain can be increased just by selecting a large channel length for the output
devices M6 and M8.
Frequency Response: The highest resistance is seen at the output node. Thus, we
expect the dominant pole of the circuit to be formed by this resistance and the load
M5 or M4-M6 with the value of X0Ç Ç where Ç is the total capacitance seen at
capacitance at the output. The second pole is normally related to the gate of M3-
the common gate of M4 and M6 and it is equal to Ç } ¯KÇ . Since

X0Ç • hR "V o p Ç W and ¯KÇ C op Ç "V, the second pole can be
written as
LR
ÃQ {
ti 6
Ž
Ñ (4.82)
Ë —
˜ Z2Ë
If the second pole places after the unity gain bandwidth frequency, the voltage
plotted in Figure 4.22 for a folded-cascode op amp. Here we have LR LM

gain frequency response of the current mirror op amp will be similar to what is
}X0 '"Mq and LR '"Mq Z , which gives LM }X0 Z .

Although the current mirror gain of } has no effect on the dc voltage gain, but for
with
the same amount of X0 and Z in current mirror and folded-cascode structures,

the bandwidth is expanded by the factor of } in the current mirror op amp. In
other words, at certain load capacitance in a current mirror op amp, it is possible to
achieve the same bandwidth as the folded-cascode structure by choosing a lower
input transconductance that alleviates the design of the input differential pair. The
slew rate in a large-signal case, when the tail current entirely conducted by one of
}W ) charges or discharges the load capacitor and thus the slew rate is given by
two branches of the differential pair, the amplified copy of the tail current (i.e.,
O' }W Z . Here again, current gain factor of } helps to improve the slew
rate. Now the question may be raised that based on what criterion is the value of }
determined. The answer to this question is found in conjunction with the op amp
of LM }X0 Z , we notice that increasing } simultaneously raises the

frequency response stability. From (4.82) and based on the bandwidth relationship
according to N& ; óôc/ “LM LR –. For example, to have a phase margin of

bandwidth and lowers the second pole, and thus lessens the phase margin
< › we need to have LR ÷ dCLM or equivalently the following inequality should

be satisfied:
÷ dC
¯5Ë ‡¯5Å
‡ 6¿vË 6³
(4.83)
By substituting transconductance relationships into (4.83), we have
²
ÃQ F G
} } } Á ³ Ë 6³
² ã
ŽÃÄF G 6¿vË
(4.84)
³ Å
The plot of Figure 4.28 illustrates the maximum allowable value of } that can
meet our minimum acceptable phase margin in which ã denotes the fixed right-
parameters, the range of C } = is appropriate to achieve the required phase

side term in (4.84). In practice, based on the typical values for the circuit
margin. The main drawback of the structure in Figure 4.27 is that it cannot provide
enough dc voltage gain. This imperfection can be treated by employing cascode
configuration, as shown in Figure 4.29. Similar to the simple structure, the dc
voltage gain is obtained as
‡¯5ÅH2
f Q f Ä
(4.85)
where È"R X" X" X0 and È"Y X" X" Ç X0 . Assuming the same
transconductance for the cascode devices, M10 and M12, and denoting it as X0$
with the square law condition being held, we have
X0$ } thR "V W F G

i
Z ŽHÇ
(4.86)
Now by substituting the output conductance of each device with X" |W) and
using (4.86), we can rewrite (4.85) as
² ²
Ç6 —tÃÄÃQ F ³ G F ³ G
ÅH2 ÑHË
{ “ð2 2
Ä ðQ –
(4.87)
Here again the current gain factor } has no effect on the dc voltage gain and the
possible measures that can be taken to increase the voltage gain are to use long
f(k)
K/(K+1)
T0
Kmax K
Figure 4.28 Plot to determine the upper limit of the current mirror gain factor.
VDD
M7 M5 M6 M8
1:1 1:K
Vbp
M3 M4 M10
M9
M1 M2
+
vi vo
-
CL
I0
Vbn
M11 M12
1:K
M13 M14
Figure 4.29 Current mirror op amp with a cascode structure.
channel length for output devices including M8, M10, M12, and M14, to increase
region, and finally, if possible, to lower the bias current W , although the value of W
the aspect ratio of M1 to M4, of course as long as they operate in the saturation
is usually set in advance based on the given specification for the op amp slew rate.
Design Example
Now we proceed to design our op amp with the previously given parameters and
in the same technology, but this time we employ the current mirror structure. In
both previous design examples, in order to provide the required transconductance
of the input devices we had to take a larger tail current that led to obtaining higher
Here we choose a slew rate of T [ \] from scratch. To achieve the required

slew rate. In general, this can be regarded as a benefit from a design point of view.
BT-dB voltage gain, we use the cascode structure shown in Figure 4.29.
First, by choosing } T from the given slew rate, we obtain the tail transistor
current. The relationship of O' }W Z , for Z = µ and O' T [ \], gives
W = \¶. Then, based on the required bandwidth we calculate the input device’s
transconductance from X0 H LM Z } that gives X0 H C;C \¶ [. By being
specified X0 H and the bias current, we can calculate the input device aspect
ratios. Using a quadratic relationship for the drain current, we obtain the aspect
ratio from X0 H ÷ ¾•hY "V o p H W with ¾ A, we should have

o p H ÷ T. We choose o p H C in order to ensure that our required
size of the technology to channel length but taking p H = \Š leads to larger

transconductance is reached. At this stage, we can allocate the minimum feature
By this channel length the input transistors widths become o H = \Š. Sizing
gate area, which helps to reduce the flicker noise and input-referred offset voltage.
desirable output voltage swing. We have !"H0UV -)) -"#R with -"#R as the
of the output transistors M8, M10, M12, and M14 are calculated based on the
overdrive voltage of the PMOS devices. For !"H0UV ÷ [, we need to have

-"#R [. Since the drain current density W) o p is the same for all MOS
devices from M3 to M14, the overdrive voltages of all PMOS devices are equal to
apply the condition of -"#R [ for M3 to M6. The inequality -"#Ž [

each other. The same statement is true for all NMOS devices. Thus we can also
gives o p Ž ÷ =, which can also be used for M4, M5, M6, M7, and M8. By
setting o p Ž/ C , the overdrive voltage of about A[ is obtained. An
=[ for M11 and M12 leads to aspect ratio of
o p H Ž . To somewhat minimize parameters |Y and |R and in order to
overdrive voltage of
here we set the length of all PMOS transistors on = \Š. As discussed in Chapter
take into account the matching issues in the layout of current mirror circuitries,
2, the parameter |R in PMOS devices, at the same bias and channel length
condition, is slightly smaller than |Y . On the other hand, the maximum voltage
gain is achievable if the equivalent output resistances of the PMOS and NMOS
transistors, it is possible to have |Y |R . For the same drain current, this results in
devices are equal to each other. By allocating larger channel length to NMOS
= \Š is chosen for the channel length of all NMOS

having equal output resistance in PMOS and NMOS devices and thus maximum
voltage gain. In this design,
become = \Š for all transistors from M3 to M8 and M11 and M13. The sizing of
devices. With the given length for PMOS and NMOS transistors, their widths
M8, M10, M12, and M14 are larger by the factor of } in two upper and lower
show the designed op amp has more than A >? voltage gain with the phase
current mirror circuits. After adding proper bias circuitries, simulation results
margin of <T› but its bandwidth is less than TA _ à This is because of some extra
parasitic capacitances of the devices at the output that increase the effective load
input transconductance X0 H The second way is to increase the current mirror

capacitance. There are two ways to increase the bandwidth. One way is to raise the
gain of } by a little bit. The latter is more feasible because the phase margin is
more than our requirement and there is still enough room to make LM and LR
closer together. The complete designed circuit including the bias circuitries with
all sizes is shown in Figure 4.30. Summarized specifications of the designed
current mirror op amp are:
VDD=2.5 V
1/0.5
5/0.5 5/0.5 15/0.5
M18 M7 M5 M6 M8
M20 M21 1:1
1:K 65/0.5
10 µA 5/0.5 Vbp
M17 M10
M9 M3 15/0.5 M4
M1 15/0.5 M2 +
vi
vo
-
5/0.5 5/0.5
M16 CL=5 pF
M24 M15 25/0.5
5/0.5 M19
5/0.5 Vbn
M22 M11
M12
15/1.25 65/1.25
0.5/1 1:K
M23 M13 M14
Figure 4.30 Schematic of the designed current mirror op amp.
• Dc voltage gain: 4 A < >?

• Unity gain bandwidth: M = ; _ à
• Phase margin: N& < T›
• Slew rate: O' T ; [ \] H O' / C< A [ \]
• Power dissipation: N# =C Š
•
• NO'' ;B T >?H /Ž#• T= œà
Power Supply Rejection Ratio:
• NO'' / A= >?H /Ž#• TB œà
4.5 Rail-to-Rail Input Op Amp
In a voltage follower implemented by a single-ended output op amp, three voltages

at the inverting and noninverting inputs and at the output are all approximately
equal to each other. This means that the input common-mode voltage that is
defined as the average of the voltages at two inputs is the same as the input or
output signals. Hence if we intend to have a single-ended output op amp where the
output voltage can swing close to two supply rails, the input common-mode range
(ICMR) also needs to be able to have the same swing without any remarkable
change in the main op amp specifications such as voltage gain, bandwidth, and
phase margin.
Thus far, in all op amp architectures that we have studied, the input stage
consists of an NMOS or PMOS differential pair in which the input common-mode
voltage is limited at a level quite below the positive supply or above the ground
level depending on the type of the differential pair used. In an NMOS differential
pair, the input common-mode voltage can change close to [ÍÍ but it is limited to
-%$H0%Y -fDY -"#H{ from below, where -fDY is the gate-source voltage of the
NMOS input devices. In fact, when -%$ goes below -%$H0%Y the tail current source
transistor enters the triode region, and in consequence, the tail current starts
dropping. As a result, the input stage transconductance begins to fall. The opposite
occurs in the case of a PMOS differential pair where the input common-mode
-%$H0UV -)) -DfR -"#H{ , with -DfR as the dc gate-source voltage of the
voltage can go down around the ground level, but from above it is restricted to
PMOS input devices. A pictorial representation of the matter is illustrated for two
different types of differential pairs in Figure 4.31.
Since the input transconductance has a direct impact on voltage gain and
variation in -%$ . From Figure 4.31, the first idea that may come to mind is to use
bandwidth, we need to keep the input transconductance constant in spite of
the parallel combination of two PMOS and NMOS differential pairs. Figure 3.32
represents the schematic of the related circuit and its corresponding
transconductances. As it is obvious, the downside of the circuit is that its total
VDD
ICMR gmn
+
vi M1 M2
- VGSn
I0
Vod,I0
Vic
0 VTn VGSn+Vod,I0 VDD
VDD
I0 Vod,I0
gmp
VSGp
+ M1 M2
vi
-
ICMR
Vic
0 VDD-VSGp-Vod,I0 VDD
VDD-|VTp|
Figure 4.31 ICMR of NMOS and PMOS differential pairs with their corresponding transconductance
variation versus .
Figure 4.32 Schematic of combined NMOS and PMOS differential pairs with their corresponding
transconductance variation versus Vic.
transconductance has a bump in the middle zone of -%$ where both pairs are on and
differential pairs have the same transconductance in the midrange of -%$ .

as a result, the total transconductance is nearly twofold if it is supposed that two
This variation in transconductance shows its effect on voltage gain,

bandwidth, and phase margin, and it is quite possible that causes instability. We
common-mode voltage changes between 0 and [ÍÍ . If the condition of square law
need to find a way to keep the total transconductance constant when input
differential pairs are X0Y •hY "V o p Y W•w and X0R •hR "V o p R W•× ,
is held for all MOS devices, the transconductance of two NMOS and PMOS
respectively, where o p Y and o p R are the associated aspect ratios of two

pairs. Assuming hY "V o p Y hR "V o p R ° , we have X0q •°“•W•w
•W•× – In order to have a constant total transconductance, the term inside the
parenthesis in X0q should be kept constant. A translinear loop can provide this
condition.
A translinear loop is a closed-loop consisting of translinear components. Any
electronic device whose transconductance is a linear function of its current or
voltage is known as a translinear element. For example, a bipolar transistor with an
transconductance is a linear function of the collector current (X0 W6 -q¦ ). An

exponential relationship is a current translinear device because its
MOS device with quadratic relationship for the drain current acts as a voltage
source voltage X0 ° -fD -e . Now consider the given circuit in Figure 4.33.
translinear device in which the transconductance is a linear function of the gate-
The gate-source voltages of M1 to M4 form a translinear loop. Summation of

voltages around the loop results in
-fD -fD -fDŽ -fDÇ T AA

Figure 4.33 MOS translinear loop.
Since for each device we have
-fD% -e% ® H HCHT

{:
ÁÃÄ 6 ²
—F ³ G
(4.89)
current for each device from (4.88) and (4.89), we have •W•w •W•× = •W . A
Assuming all transistors are identical, by substituting the corresponding drain
practical circuit that works based on this concept is shown in Figure 4.34 [5]. (Ma,
Mb) and (Mc, Md) are two parallel PMOS and NMOS differential pairs with MP
circuit. The currents WŽ and WÇ are adequately less than currents W, W•w , and W•× . As
and MN as their tail transistors whose currents are controlled by the rest of the
well, all PMOS devices including M1, M2, M3, M4, M5, and MP are identical.
Transistors MP, M3, M4, and M5 form a translinear loop with the following
relationship among their gate-source voltages:
-DfÚ -DfŽ -DfÇ -Df T;
current and thus we have -DfŽ -Df -Df . On the other side, for M1 we can
In the circuit of Figure 4.34 two identical devices, M2 and M3 have the same drain
write
-DfŽ -Df Ì-eR Ì

{¨Û {Ñ
ÁÃ ²
Q6 —F ³ G
(4.91)
Å
By substituting each gate-source voltage into (4.90) by its value given in (4.89)
VDD
M2 M1
M4 I3
MP
IBP M5
+ M6 M7 + Mc Md
vi vi
M3
- -
+ Ma Mb
IBN IBN
vi
Vbias
- I I4 MN
M8
Figure 4.34 A constant-gm circuit that works based on the translinear loop concept.
and (4.91), and taking into account the associated drain current of each device,
after simplification, we obtain
•W•× •W•w WŽ •W WÇ •WÇ (4.92)
Since WŽ … W•w and WÇ … W, we can approximate (4.92) as •W•× •W•w dW. The
derived relationship can be qualitatively justified as follows. When the input
thus M1 carries the small current of WŽ . The current mirror M1-M2 makes a copy
common-mode voltage is too small, the differential pair M6, M7 is almost off and
of WŽ into M2 and M3. The gate-source voltage of M3 is small because of its low
decrease in -DfŽ should be compensated for by increasing -DfÚ , which in turn,

drain current. As a consequence, since the right side of (4.90) is fixed, and a
raises the tail current W•× . When the input common-mode voltage is close to [ÍÍ ,
W•w flows through M1-M2 and then flows into M3 and establishes its gate-source
the differential pair (Ma, Mb) is almost off but (M6, M7) is on and the bias current
voltage -DfŽ . From (4.90), we see that a noticeable voltage places across the gate-
source of MP, but because its drain current is too small, MP goes to the triode
region with the following relationship:
2
4k:
W)Ú hR "V F Z G ç“- fÚ Ì-eR Ì–-D)Ú è
i Ú
×
(4.93)
From (4.93), with W)Ú , we have -D)Ú and -DfÚ Ì-eR Ì -D)Ú
Ì-eR Ì. This analysis proves that in spite of the drain current of MP being too small,
this device does not operate in the subthreshold region, a working area in which
Figure 4.35 Another example of a circuit that works based on the translinear loop concept.
-DfÚ Ì-eR Ì and the drain current equation is completely different. Now by
substituting -DfÚ Ì-eR Ì in (4.90) and repeating the same procedure that was done
to reach (4.92), we will get
•W•w WŽ •W WÇ •WÇ (4.94)
The existence of the current source WŽ in the circuit is important. In fact, for a
and WŽ is the only remarkable current that causes M1 to remain in the saturation
too-small input common-mode voltage the pair of (M6, M7) is approximately off
region. Otherwise for very low level drain current of M1, this device and also M2
and M3 would operate in the subthreshold region. In this situation, due to the
exponential relationship for the M3 drain current, the loop consisting of MP, M3,
M4, and M5 no longer acts as a conventional translinear loop.
Figure 4.35 indicates another circuit that works based on the translinear loop
concept to realize a constant-gm input stage [6]. Here the translinear loop consists
of transistors M1, M2, M3, and M4. A detailed analysis of the circuit is left as an
exercise to the interested reader.
Another method to attain a constant-gm input stage is to utilize the quadratic
relationship of the MOS drain current. The transconductance of an MOS device
with such a relationship changes as a square root function of the drain current. If it
is supposed that the transconductances of two differential pairs are the same at the
midrange of the input common mode voltage, the total input transconductance will
extremes of the input common-mode voltage variations between 0 and -)) , one of
be two times the transconductance of each single pair. Now in two low and high
two differential pair turns off and it is just enough to increase the tail current of the
conducting differential pair fourfold. This causes a single turned-on differential
pair that provides the same total transconductance that would be produced in the
midrange of the input common-mode voltage by both pairs. Different constant-gm
Figure 4.36 Newly introduced constant-gm input stage.
circuits have been introduced in the literature that all work based on the above-
mentioned principle [7-8]. The circuit shown in Figure 4.36 is another example
that uses this method to provide a constant transconductance against the variation
of the input common-mode voltage.
In this circuit, when the input common-mode voltage is close to zero, two
NMOS differential pairs (M1, M2) and (M12, M13) turn off, and in consequence,
(M3, M4) and (M6, M7) turn on, and as a result, current W•× flows through (M6,
M5, M10, and M11 also turn off. On the other hand, both PMOS differential pairs
M7), which turns M8 and M9 on. But M5 is off and thus M9 goes to the triode
M15-M16 is off. The current mirror M8-M14 transfers the current W•× to the
with nearly zero drain current and voltage. This ensures that the current mirror
second current mirror created by M17-M18 that adds three times of W•× to the tail
of the PMOS input differential pair. At the other extreme of the input common-
mode voltage close to the positive supply, two PMOS differential pairs (M1, M2)
and (M6, M7) are off. This time M8, M9, and M14 are off and M10 goes to the
M17-M18 off. In this situation, the current mirror M11-M15 transfers W•w to the
triode region with nearly zero drain-source voltage, which makes current mirror
current mirror of M15-M16 with the gain of three that adds CW•w to the tail current
varies somewhere at the middle of zero and [ÍÍ , all differential pairs of both types
of the NMOS differential pair (M3, M4). When input common-mode voltage
conduct. Assuming W•× W•w , we can see the current flowing through two
transistors pairs of (M5, M9) and (M10, M14) are approximately the same, and
therefore both current mirrors M15-M16 and M17-M18 are nearly off and cannot
add noticeable current to the tail current of the input differential pairs. In this
condition, the aggregated transconductance of the NMOS and PMOS differential
pair contribute in total transconductance. In low-power designs, MOS devices
usually work in the subthreshold region where transconductance is directly
proportional to the drain current (X0HKM„ W) --q¦ ). In this case, obtaining a

constant transconductance is feasible by keeping the sum of the drain bias current
of the two differential pairs constant [9]. The circuit realization of this condition is
normally more convenient in comparison to the situation where MOS devices
work in strong inversion with the square law relationship.
Current Combiner Circuit: We now proceed to study the circuit used for
combining the drain currents of the input stage to reach a single-ended output
voltage. Figure 4.37 represents one circuit that can be used for this purpose where
for the sake of clarity, the circuit used for keeping the input transconductance
constant has not been shown.
Summing currents at the drain of M5 and M6 and at the source of M9 and
M10, we obtain the following equations:
® ®)Ž ® (4.95)
® ®)Ç ®Ž (4.96)
® ®) W (4.97)
® ®) W (4.98)
VDD
i i
IS M5 M6
iD3
iD4
M3
M4
vi1 vi2 VBP M7
M1 M2 M8
i3
Vo
IS
i1 i2
iD1 iD2
M9
VBN M10
I0 I0
Figure 4.37 Schematic of a current combiner.

From the above equations, we can get the output current as
®"Mq ®Ž ® ®) ®) ®)Ž ®)Ç (4.99)
where ®) ®) is the differential output current of the PMOS differential pair that
is equal to X0R !% !% . Similarly, we have ®)Ž ®)Ç X0Y !% !% for the
NMOS pair. The ac output current ®"Mq flows through the equivalent resistance
seen at the common drain of M8 and M10 (i.e., '"Mq ). By denoting !% !% !% H
the output voltage becomes !" “X0Y X0R –'"Mq !% with '"Mq '"w Ó '"× in
which '"× X0 Ò" Ò"ê Ó Ò"Ç and '"w X0 Ò" Ò" Ó Ò" . Ò" represents the
output resistance of the current source W .
It should be pointed out that the bias voltages -•w and -•× need to be
saturation at the extremes of the input common-mode voltage, -%$ . For instance
carefully chosen such that all input transistors, M1 to M4, always remain in
when -%$ varies around the zero, the pair of (M1, M2) is the only conducting pair,
threshold voltage of Ì-eR Ì in order to keep these devices in saturation. This means
and thus the maximum drain voltage of M1 and M2 should not be beyond one
that we should have -•w -fD Ì-eR Ì. Likewise, at the other extreme (i.e., for
-%$ -)) ), we need to meet the condition of -•× -)) -DfŒ -eYŽ to keep
is related to the value of W . As discussed earlier, for -%$ , the X0 control circuit
M3 and M4 in saturation. Another important point with regard to the dc condition
increases the tail current of the PMOS pair from WK to TWK to have a constant X0 in
the input stage. In this case, we have W) W) WK and W W WK where W is
on these devices we need to have W or equivalently W WK . In the midrange,

the dc current of the cascode transistors (i.e., M7 to M10). In order to keep turning
when we have -%$ -)) , W) W) WK and W W WK . Now we have to

meet W WK and finally at the extreme of -%$ -)) , W)Ž W)Ç WK and W W.
remain on for -%$ variation between to -)) , is that we use a fixed value of 2WK for
One measure that can be taken to make sure that the cascode devices always
W . In this condition, W changes from zero to WK when -%$ changes from to -))
This causes a significant variation of the small-signal parameters of the cascode
second pole, in turn, impacts on the amplifier stability. To achieve a constant W in

devices that can affect the dc voltage gain and also changes the location of the
spite of the variation of -%$ , first we set W WK . Then for -%$ , we add a current
of WK to W by paralleling a WK current source to W . In the midrange, for -%$ -))
, we need to add current of WK to W WK and finally, when -%$ -)) , there is no
need to add any current to our initial current W WK . All these actions can be done
by using the same control circuit that is used to change the tail currents of two
differential pairs in the input stage.
4.6 Conclusion 105
4.6 Conclusion
The subject of this chapter was about the design of single-ended output op amps.
Some most popular architectures of this category usually employed in an analog
system were introduced. Each structure has its own advantages and drawbacks.
Choosing a particular type of op amp totally depends on the application and
required specifications for that particular application. For example, when design is
to be done in a deep submicron technology, achieving a large voltage gain is not a
simple task. In this case the two-stage op amp perhaps is the first candidate. But
from a frequency stability point of view, a designer may get into trouble when
he/she uses such architecture with a large load capacitance. The behavior of a
current mirror op amp is well-defined and its design procedure is straightforward
though it cannot provide enough voltage gain. Of course this shortcoming of
current mirror structure is compensable to some extent by using cascode
configuration. Among different studied architectures the folded-cascode structure
can meet most expected specifications while also being appropriate for low-
voltage applications. This chapter also dealt with the rail-to-rail input op amps and
introduced several methods to achieve this goal. In the method presented the input
stage is designed such that the total transconductance of the input devices of the op
amp have minimum variation when the input common-mode voltage changes
between two supply rails.
References
[1] Gray, P. R., Hurst, P. J., Lewis, S. H., and Meyer, R. G., Analysis and Design of Analog
[2] Liu, W., MOSFET Models for SPICE Simulation Including BSIM3v3 and BSIM4, John Wiley &
Sons, Inc., 2001.
[3] Tsividis, Y., Operation and Modeling of the MOS Transistor, Second Ed, Boston: McGraw-Hill,
1999.
[4] Allen, P. E., Holberg, D. R., CMOS Analog Circuit Design, Second Ed, Oxford University Press,
2002.
[5] Nagaraj, K. “Constant Transconductance CMOS Amplifier Input Stage with Rail-to-Rail
Common Mode Voltage Range,” IEEE Trans. Circuits Syst. II, Vol. 47, No. 12, 2000, pp. 1560–
1564.
[6] Botma, J. H., et al., “A Low-Voltage CMOS Op Amp with a Rail-to-Rail Constant-Gm Input
Stage and a Class-AB Rail-to-Rail Output Stage,” Proc. of the IEEE Int. Symp. on Circuits and
Systems, 1993, pp. 1314-1317.
[7] Hogervorst, R., et al., “A Compact Power-Efficient 3 V CMOS Rail-to-Rail Input/Output
Operational Amplifier for VLSI Cell Libraries,” IEEE J. Solid-State Circuits, Vol. 29, No. 12,
1994, pp. 1505-1513.
[8] Moldovan, L., and Li, H. H., “A Rail-to-Rail, Constant Gain, Buffered Op Amp for Real Time
Video Applications,” IEEE J. Solid-State Circuits, Vol. 32, No. 2, 1997, pp. 169-176.
[9] Peeters, E., Steyaert, M., Sansen, W., “A Fully Differential 1.5V Low-Power CMOS Operational
Amplifier with a Rail-to-Rail Current-Regulated Constant-gm Input Stage,” Proceedings of the
IEEE Custom Integrated Circuits Conference, 5-8 May 1997, pp. 75-78.
Chapter 5
CMOS Fully Differential Op Amps
The name of the single-ended output op amp evidently states its unique property of
having a single output voltage or current. This is against another important
category of operational amplifiers that states that both input and output signals
appear as differential voltage or current. As the design criteria in the
implementation of an op amp to be used within an analog-integrated circuit is
significantly different from those of traditional stand-alone op amps, critical
specifications such as the amount of PSRR and CMRR need to be considered in
such applications. For example, in an integrated mixed-mode circuit such as
analog filters or data converters, op amps and other digital sections coexist on a
common chip [1]. This causes any noise from digital parts to go through the
common substrate into the analog blocks. This issue highlights the unquestionable
importance of high CMRR and PSRR which have critical roles in alleviating these
issues. Using differential output signals instead of a single counterpart, we can
significantly keep such circuits immune against common-mode noises or
interferences. In this chapter, first we outline the remarkable advantages of fully
differential op amps (FD op amps) compared to their single-ended alternative.
Next, we deal with the common-mode feedback circuit as an indispensable
building block in FD op amps and introduce some subtle issues with regard to this
block. At the end, we briefly study different structures in this category.
5.1 Advantages of Fully Differential Op Amps
In this section, some predominant benefits of differential output amplifiers are

briefly introduced to demonstrate the reasons behind the widespread application of
this amplifier in analog integrated circuits.
High Immunity against Common-Mode Noises and Interference Signals: Since the
differential output voltage is the amplification of the difference of two input
voltages, any unwanted interference signal that appears as a common-mode signal
107
108 CMOS Fully Differential Op Amps
on both inputs would disappear at the output in an ideal case [2]. This issue is
critical particularly in an analog mixed-mode circuit where it is quite possible that
some unwanted digital signals such as clock voltage reaches the op amp inputs
through different ways like capacitive coupling, shared substrate, or common
power supply rail.
Increased Output Swing: In a differential output op amp, since two outputs change
in the opposite directions in reference to the ground node of the circuit, thus the
difference of them will be twofold in comparison to that of its single-ended output
counterpart. Improved output swing leads to increase of the dynamic range, a
critical point in low-voltage designs. Moreover, this feature helps to improve the
signal-to-noise ratio of the circuit.
Elimination of Even Harmonics: In a large-signal condition, the general
!"# !%# . Supposing the amplifier has a full symmetric structure, by

relationship between the difference of inputs and outputs can be represented as
interchanging two inputs, we will have the same output with opposite polarity.
difference voltage !%# and thus only odd terms will appear in the Taylor series
This means that the input-output relationship is an odd function of the input
expansion of !"# in terms of !%#
!"# ö !%# öŽ !%#

Ž
ö !%# (5.1)
For a sinusoidal input voltage, substituting !%# -0 ù ½L n into (5.1) and using
trigonometric formulas to simplify the relationship, we obtain
!"# ù ½L n Ž ù ½CL n ù ½=L n (5.2)
This reveals that in an ideal FD circuit only odd harmonics are generated due to
the circuit nonlinearity. The property of an odd characteristic also shows that to
invert the polarity of a differential signal there is no need for an extra amplifier
and it is enough to interchange the order of two differential input signals.
Omission of the Systematic Offset Voltage: In a differential output amplifier, a

common-mode feedback circuit should be used to fix the output voltage to a
desirable level. This action eliminates any concern about dc output level deviation.
Removal of the Mirror Pole: Since no current mirror active load is employed in
the structure of a differential output amplifier, we have no mirror pole similar to
what happens in a single-ended output op amp.
In contrast to all the above mentioned advantages of differential output op
amps, we can enumerate two main downsides. First, when an FD op amp is used
as an amplifier in a negative-feedback loop, the required number of elements in
5.2 Common-Mode Feedback Concept 109
the feedback network becomes twofold. For instance, in a switched-capacitor

amplifier implemented by such an op amp we need four capacitors instead of two.
This can occupy a considerable area of the chip in an integrated analog circuit. The
second challenge with an FD op amp is its mandatory requirement of an extra
circuit called common-mode feedback circuitry (CMFB). The function of the
CMFB circuit is to keep the dc output voltage on an appropriate level in order for
output devices to operate in the saturation region.
5.2 Common-Mode Feedback Concept
When a single-ended output op amp is used within a negative-feedback loop, the
circuit shown in Figure 5.1 and let the output voltage be changed by 3-" . This
feedback helps to stabilize the common-mode (CM) output level. Consider the
variation through the feedback path appears at the inverting input as 3- /

Ô' ' ' Õ3-" , is multiplied by the op amp voltage gain, and returns to the
output as 3-"¼ # 3- # Ô' ' ' Õ3-" . Since #
/
, it is obvious
that any change in the dc output voltage is compensated by a strong negative-
in Figure 5.2. Generally, the variation of the CM output voltage (3-"$ !"$ ) can
feedback mechanism. Now consider the same condition for an FD amplifier shown
be written as !"$ #$ !%# $$ !%$ with #$ and $$ as the differential to CM

and CM voltage gains, respectively, and 3-%$ !%$ . For the case of !%#
illustrated in Figure 5.2, when the output CM voltage changes by 3-"$ , the
as
3-%$ Ô' ' ' Õ3-" . This time the voltage 3-%$ is multiplied by $$ and
corresponding variation in the input CM voltage becomes
causes the output voltage change by 3-"$¼ $$ Ô' ' ' Õ3-"$ . Since $$
in -"$ . Hence it is completely possible that the output CM voltage changes

is a small quantity, the negative-feedback loop cannot compensate for the changes
uncontrollably toward one of two supply rails. This proves that unlike a single-
R2
R1
Vref −
Vo
Ad
+
Figure 5.1 Single-ended output op amp within a negative-feedback loop.

R2
R1
- + ∆Voc
+
Vref Ad Vod
- - ∆V
+ oc
R1
R2
Figure 5.2 Differential output op amp within a negative-feedback loop.
ended op amp, in a differential op amp we need an additional circuit to maintain

the output dc voltage on a certain level that ensures output devices operate in the
op amp. The signal !K at the CMFB output exhibits the control signal used to
saturation region [3]. Figure 5.3 shows the CMFB block in association with an FD
adjust the op amp output dc voltage to a desirable level. The variation of the
differential and CM voltages of the op amp in the presence of the CMFB block can
be represented by
!"# ## !%# $# !%$ K# !K (5.3)
!"$ #$ !%# $$ !%$ K$ !K (5.4)
K# and K$ show the amount of contribution of the control signal !K in the

differential and CM output voltages, respectively. On the other side, the voltage !K
itself depends on these voltages through the CMFB circuit according to the
following relationship:
!K #K !"# $K !"$ (5.5)
Vic + + Voc
+
+
vid vod
-
Vic - - - Voc
vs
Common-mode
feedback
Figure 5.3 Op amp with a CMFB network.

where #K is the voltage gain of the CMFB for the differential output voltage and
$K is the corresponding gain for the output CM voltage. The role of the CMFB
of !K to adjust the output CM level. Hence we expect to have #K … $K or

block is to detect the output CM voltage variation and produce the control signal
!K $K !"$ . In the quiescent condition when !%# , from (5.4) the output CM
variation is given by
!"$ $$ !%$ K$ !K =<
In reality, the voltage gain of K$ in the CMFB circuit is much greater than the op
amp CM voltage gain of $$ and thus !"$ K$ !K . As a result, from (5.5) and
(5.6) the open-loop gain for the loop consisting of the CMFB block and op amp
becomes approximately 67 Z K$ $K . The behavior of the CMFB in relation to
the op amp can be depicted in a system level representation as shown in
Figure 5.4. From Figure 5.4 we can express the output CM voltage in terms of the
desirable CM level as
-$0H"Mq Â ³
-$0H.I =B
Â ³
For 67 Z we have -$0H"Mq -$0H.I . The stability issue is the most important
matter in the design of the CMFB circuit. This requires that the pole and zero
locations in the transfer functions of $K and K$ are such that the system open-
loop gain has adequate phase margin in the frequency domain. K$ is the voltage
gain from the CMFB circuit output to the op amp output thus its transfer function
is determined by a part of the op amp circuit that exists in this path. The gain of
$K depends on the structure used to implement the CMFB circuit. It should be
pointed out that we need to take actions to achieve the required stability for the
CMFB circuit while it should not degrade largely the main op amp parameters
such as dc voltage gain, bandwidth, and stability.
5.3 Common-Mode Feedback Circuits
A CMFB block usually consists of two main parts, as illustrated in Figure 5.5. The
first part is a CM detector circuit that is connected directly to the op amp output
Vcm,ref + Vcm,out
Acs Asc
-
Figure 5.4 System representation of a CMFB control loop.

vi+ + vo+
+
vi- - vo-
- vs
Common-mode
detector
Vcm,out
+
- Vcm,ref
Figure 5.5 CMFB circuit details in an FD op amp.
and provides a current or voltage signal proportional to the op amp output CM

voltage. The second part is a comparator that compares the signal provided by the
first block with a reference CM level and produces a control signal as a voltage or
current that is applied to an appropriate point of the op amp to move the op amp
output CM voltage toward the desirable level. There are different architectures to
realize the CMFB circuit while each of them has its own advantages and
disadvantages. Employing a particular circuit for CMFB depends to a large extent
on the particular op amp structure.
5.3.1 Common-Mode Feedback Circuit with Resistive Sensing
The simplest way to get the op amp output CM voltage is to place two resistors
with equal resistances at the op amp output, as shown in Figure 5.6 [4]. Although
the circuit is simple, its main drawback is its loading effect on the op amp output,
which extensively lowers the dc voltage gain. The loading effect can be mitigated
to some extent by using large resistances. But large on-chip resistors occupy a
significant area of the chip and add considerable parasitic capacitances at the
vo+
+ +
R
- - R
vo-
+ Vcm,out
− Vcm,ref
Figure 5.6 CMFB circuit with resistive detector.

output that in turn limit the op amp frequency response. As shown in Figure 5.7,
by employing source-follower stages at each op amp output, we can solve the
loading problem.
Since the CM voltage produced in this case is lower than the op amp output
CM by one gate-source drop voltage, we need to use the same source-follower for
capacitors, the resistors ' and the input parasitic capacitance of the comparator
the reference CM voltage, as depicted in Figure 5.7. In the absence of the parallel
form a low-pass circuit in which the op amp output CM voltage is considered as its
input signal, as illustrated Figure 5.8. The capacitance K is the input parasitic
capacitance of the comparator. The transfer function of the low-pass circuit
becomes
4 Å
4 , 86v K
(5.8)
The created pole of LR ' K adds a negative phase shift in the transfer
function of $K ½ that results in degrading the loop stability. By placing a proper
parallel capacitor across the resistor ', we can create a zero to cancel the
mentioned pole. The main drawback of the resistive CMFB circuit with buffer is
VDD
M1
vo+
+ +
C R
I0
- -
vo- VDD
C R
M2
Vcm,out-VGS
I0
VDD
+ Vcm,ref
vs M3
− Vcm,ref-VGS
I0
Figure 5.7 Resistive CMFB circuit with source-follower.

Voc
R
Vo1
R Cs
Voc
Figure 5.8 Low-pass circuit formed in a CMFB block.
because when each op amp output voltage becomes less than -fD -"# with -"#
that its performance is limited by the op amp differential output swing. This occurs
as the bias current source overdrive voltage in the buffer circuit, the source-
follower stage fails to follow the op amp output and thus the CM level produced is
no longer acceptable.
5.3.2 Differential Difference Common-Mode Feedback Circuit
It is possible to use two identical NMOS or PMOS differential pairs at the output
of an FD op amp in order to detect the op amp output CM level. The circuit of
Figure 5.9 shows a PMOS sample of such a circuit. M1 to M4 are exactly the same
have the same drain voltages for M1 to M4. In a quiescent condition for !"#
and M6 with the diode-connected configuration is also identical to M5 in order to
-"$ -$. , M1 to M4 have equal currents of W

if
. In this circuit both the
differential and CM level of the op amp output affect the drain currents of M1 to
voltages are denoted by 3®#0 and 3®$0 , respectively, the drain currents of M3 and
M4. If the change in the drain current due to the output differential and CM
M4 can be written as
®)Ž 3®$0 3®#0 =;

{
®)Ç 3®$0 3®#0 =

{
From (5.9) and (5.10), the drain current of M5 becomes ®) ®)Ž ®)Ç W
3®$0 . This means that ®) depends only on the changes of the output CM voltage.
To control the output CM level in an FD op amp we can use the M5 current to
adjust the tail current of the op amp through a current mirror circuit. We can write
(5.9) and (5.10) as long as both differential pairs of M1-M3 and M2-M4 remain
VDD VDD
I0 I0
Vcr
vo+ M3 M4 M2 vo -
M1
vs
M5 M6
Figure 5.9 PMOS differential difference CMFB circuit.
This condition is satisfied when !"#H0UV d -" in which -" •W ° /Ç is the

turned on at the maximum level of the differential output voltage of the op amp.
overdrive voltage of M1 to M4 with ° /Ç hR "V o p /Ç . Therefore we need

to use a large enough -" by increasing the tail current and decreasing the device’s
aspect ratios to cover the variation range of the differential output voltage.
Now we proceed to obtain the low-frequency voltage gain of $K for this
reference CM level -$. and the output CM voltage -"$ is given by

circuit. Variation in the drain current of M3 and M4 due to any difference between
3®)Ž X0 HŽ -"$ -$. =
3®)Ç X0 HÇ -"$ -$. =
Since X0 HŽ X0 HÇ X0 , the variation of the drain current of M5 becomes

3®) 3®)Ž 3®)Ç X0 -"$ -$. , which creates an ac voltage !K
X0 X0 -"$ -$. across the diode-connected M5. This gives
v ¯5
$K 4 , /4, ¯5é
(5.13)
To limit the power consumption of the CMFB circuit, the tail current W cannot be
too large and consequently the required overdrive voltage for M1 to M4 is
to a small transconductance X0 . On the other hand, there is a restriction imposed

achievable by taking small aspect ratios for these devices. All these measures lead
on X0 that does not allow us to arbitrarily make X0 too small. This constraint is
forced in conjunction with the CMFB frequency response. Denoting total
capacitance seen at the gate of M5 including the M5 gate-source capacitance and
dominant pole in the voltage gain transfer function $K would be X0

total capacitance associated with the CMFB control input of the op amp, by the
Although according to (5.13), decreasing X0 helps to increase the dc voltage gain

.
of $K , it simultaneously lowers the dominant pole and as a result degrades the

stability of the CMFB loop. A modified differential difference CMFB circuit to
achieve higher $K is shown in Figure 5.10. Similarly, we can write the drain
currents of different devices as
®) 3®$0 3®#0 = Tô
{
®) 3®$0 3®#0 = T
{
®)Ž 3®$0 3®#0 = T•

{
®)Ç 3®$0 3®#0 = T>

{
From the equations above we have ®) ®)ê W 3®$0 , ®)Ž ®)Ç W

3®$0 , and therefore ®K ®)Ž ®)Ç ®) T3®$0 . The output resistance seen at
the drain of M5 is '"Mq Ò" Ó Ò"Ž Ó Ò"Ç . Moreover, we have
3®$0 X0 /Ç -"$ -$. that gives the dc voltage gain of the CM detector
circuit as
VDD VDD
I0 I0
vo+ Vcr vo-

M1 M3 M4 M2
iD3+iD4
vs
is iD5
M5 M6
1:1
Figure 5.10 High-gain PMOS differential difference CMFB circuit.

$K
v
X0 /Ç '"Mq
4 , /4,
(5.15)
As can be seen the voltage gain is significantly improved but the major issue is the
CMFB loop. It is possible to improve stability by adding an ' compensation

small pole created at the drain of M5 that drastically degrades the stability of the
network, as shown in Figure 5.11. Denoting the parasitic capacitance at the drain
of M5 due to the input control of the op amp by K , we obtain the equivalent
impedance at the M5 drain as
Ø ½
8, 6, K
Ô8 x‰ 6, 6v 8, 6, ÕK 8 x‰ 8, 6, 6v K 2
(5.16)
Supposing Ø ½ has two real poles; we represent (5.16) as a general form of a

second-order transfer function
v
Ø ½ '"Mq
ÝÅ
v v
F GF G
(5.17)
QÅ Q2
We can cancel out one pole-zero pair by setting û ü . In this situation, the only
remaining pole is û ' K with ' '$ Ó '"Mq . In practice '$ … '"Mq and
thus the pole is moved to a higher frequency that leads to improving the CMFB
VDD VDD
I0 I0
vo+ Vcr vo-

M1 M3 M4 M2
Rc
Cc
vs
M5 M6
1:1
Figure 5.11 Differential difference CMFB circuit with compensation network.

loop stability.
5.3.3 Common-Mode Feedback Circuit Using MOS Devices Operating in the

Triode Region
Figure 5.12 indicates another circuit that can be used to detect and adjust the
output CM voltage [5]. Transistors M11 to M21 form the CMFB circuitry. Series
denoted by W . The dc bias current of M9 and M10 in the op amp circuit is

transistors M11 and M12 form a cascode current source with a fixed current
composed of two components of W and WK . The devices in two exactly identical

controlled by the current mirror of M13-(M9, M10) in which the current of M13 is
pairs of M14-M15 and M18-M19 operate in the triode region and act as a resistor.
The pair of M14-M15 implements a fixed resistance controlled by the reference
voltage. As long as the op amp output voltages keep M18 and M19 in the triode
region, this pair acts as a resistor whose equivalent resistance depends on the
output CM level and the differential component has no effect on its resistance. To
show this matter we write the current equation of two devices in the triode region
as
®) ° F!" -eY :k
G !)D (5.18a)
®) ° F!"/ -eY :k
G !)D (5.18b)
Where ° hY "V o p H . The drain current of M20 and M21 is the

summation of these currents:
¢
®) °F -eY :k
G !)D (5.19)
VDD
I0 M10
M9 M13 M17 M21
1:1
M7
v i+ M1 M2 v i- Vbp M8 Is
vo- vo+ I1
M16
Vbn2 M12 Vbias M20
M5 M6
Vref Vref v o+ vo-

Vbn1 M11 M14 M15 M18 M19
M3 M4
Differential Op Amp CMFB

Figure 5.12 Differential op amp with CMFB circuit using MOS devices in the triode region.
!"$ !" !"/

As it is obvious the total current depends only on the output CM voltage
. Similarly we can write the total current relationship for M14-
M15 as
®) ê ° F-.I -eY :k
G !)D (5.20)
From (5.19) and (5.20) it is possible to derive the equivalent resistances of two
'"YH$0
pairs as
:2 Æ , /4£Ä
(5.21a)
S:k
'"YH.I :Åí Æ“4 rs /4£Ä –

(5.21b)
S:k
where the second-order term is ignored for a small !)D . In the case of !"$ -.I ,
having equal currents in M16 and M20 and therefore we get WK . If !"$ is less
series resistances in the sources of M16 and M20 are the same. This leads to
than -.I , we have '"YH$0 '"YH.I and thus WK ®) ê ®)

situation the total drain current of M13 becomes W WK , which by injection of a
. In this
output nodes, raises the output CM voltage. For !"$ -.I , the opposite process
larger current through the current mirror of M13-(M9, M10) into the op amp
causes WK to become negative and lower the output CM level. It should be pointed
out that this analysis is valid provided that M14-M15 and M18-M19 remain in the
triode region for the maximum possible swing of the op amp differential output
If the differential output voltage is denoted by !"# , the minimum level of each
voltage. This condition actually imposes a limitation on the op amp output swing.
device turned on (i.e., we need to satisfy !"H0%Y -"$ “!"#H0UV – -eY or

output should be greater than one MOS threshold voltage in order to keep the
/
!"#H0UV -"$ -eY with !"#H0UV !"H0UV !"H0%Y /
also need to keep the devices in the triode region that require !"H0%Y -eY
). On the other hand, we
/
-)D H .
-)D H -„%UK -fD , we have -"$ “!"#H0UV – -eY -„%UK -fD .
Noting that
These result in !"#H0UV -"$ -eY -„%UK -fD , which imposes another
upper limit on the differential output voltage. As the relationships show, two
imposed limits are approximately the same.
5.3.4 Switched-Capacitor Common-Mode Feedback Circuit
All previously analyzed CMFB circuits except for the resistive divider type
suffered from the imposed constraint on the op amp differential output voltage
swing, although the resistive divider type did also have its own problems. In this
vo+ φ2 φ1
vi+ + + Vcr
Cf Cs
φ2 φ1
VB
vs Cf Cs
φ2 φ1
vi- - -
vo-
Figure 5.13 Switched-capacitor CMFB circuit.
part, another type of CMFB circuit is studied that does not impose serious
limitation on the differential output swing while its loading effect on the op amp
output could be ignored by providing the required conditions as discussed later.
This circuit is realized only by capacitors and clock-controlled switches. The
switched-capacitor (SC) CMFB circuits are particularly appropriate for the
category of switched-capacitor circuits such as SC filters or amplifiers in which
other parts of the system are using controlled switches and thus the required clock
signal is already accessible. The general scheme of an SC CMFB circuit is
illustrated in Figure 5.13.
The switches are controlled by two nonoverlapping clocks called and .
The half-circuit equivalent of the circuit in the common-mode state is shown in
Figure 5.14.
φ2
s4
Cf
Vcr φ1 Cs φ2 Voc
Asc
s1 s3
s2 φ1
VB
Figure 5.14 Common-mode half-circuit equivalent of differential op amp with switched-capacitor
CMFB circuit.
At the phase of , switches O and O are closed and the capacitor K charges
to - -$. -• . At the end of , O and O are open and then OŽ and OÇ are
closed when is active. If n is considered at the leading edge of the first
pulse on , according to the charge conservation law, the total electric charge
g / g at n
before and after change in the switches’ states is kept unchanged (i.e.,
/
write K - “ D –- with - as the voltage across the parallel combination of

). Assuming the initial voltage across is zero, we can
K n
from zero to - “ K “ K ––-. In the second cycle, during two consecutive
and for . As a result, the voltage of in the first clock cycle changes
of is - and therefore the voltage changes to

phases of and , the same process is repeated but this time the initial voltage
3-6s - -
6v
6v 6s
(5.22)
The voltage across at the end of the second cycle becomes - - 3-6s . In a
similar fashion, it is possible to calculate the voltage of at the cycle of •
in terms of its voltage at the previous cycle as follows:
-Y -Y - -Y
6v
6v 6s
(5.23)
Denoting !Y -Y -, from (5.23), after simplifying, we reach the following

recursive equation:
6s
!Y !
6v 6s Y
(5.24)
The general solution of such an equation is as !Y } "Y with } “ K –.

The parameter ¾ is obtained by substituting the general solution into (5.24) that
gives ¾ and as a result !Y } Y . The coefficient is an arbitrary constant
that is determined by using the given initial condition. Since ! - - and it is
assumed - , we have ! - and thus the complete solution becomes
-Y - } Y for • . Since } approaches - as •
tends to infinity. The circuit parameter } determines how fast -Y approaches its
, the voltage across
final value. Clearly, the smaller } is chosen, the less time the circuit spends in a
equal to - and consequently

transient state. That condition is met when is chosen adequately smaller than
K . In steady state the voltage of is approximately
the charge on K during two consecutive phases of
the charge on K is K -$. -• and in
and does not noticeably
K
with a charge of D -"$ -K , as illustrated in Figure 5.15. Equating these
change. In is placed in parallel
charges together, we obtain the CM level control signal of -K as

with
Cs
- +
Cf
Voc
Vs Asc
Figure 5.15 Common-mode half-circuit equivalent of differential op amp in the steady state.
-K -• -"$ -$. (5.25)
Equation (5.25) shows that the actions of output CM detection and comparison
$K . When -"$ is greater than -$. the control voltage -K is larger than the bias
with reference both are simultaneously carried out with the unity voltage gain for
voltage -• . The control voltage given by (5.25) can be exploited in an NMOS
current. In the case of -"$ -$. , we have -K -• , which by decreasing the tail
differential pair to lower the output CM level by increasing the tail transistor
current the opposite action occurs. In practice, the switches used in the circuit of
Figure 5.14 are implemented by MOS transistors that operate between the two
regions of cutoff or triode depending on whether the switch is off or on. When the
MOS switch is on an inversion layer of free charges is formed in the channel under
regions of source and drain. For example, in Figure 5.14 when switches O and O
the gate. When the switch turns off the channel charge is distributed between the
turn off, a part of their channel charge denoted by 3g transfers to K so that the
actual charge on K in becomes K -"$ -K 3g, and in the steady state, the
CM control voltage -K becomes
-K -"$ -$. -•
3
6v
(5.26)
an error by amount of 3g K . By choosing small sizes for switches and rather

From (5.26) we see that the actual output CM voltage in the steady state will have
large capacitance K we can reduce the effect of the channel charge sharing error.
In relation to the loading effect of switched-capacitor CMFB circuit there is
an important point that the designer should pay special attention to. The sampling
capacitor K and two switches controlled by and act as an equivalent resistor
with the resistance of $•˜ K with $•˜ as the clock signal frequency that
controls the switches. For large clock frequency the equivalent resistance is small
_ à and K µ an equivalent
and it can extensively load the op amp output which causes a significant drop in
the voltage gain. For example, for $•˜
resistance of œ is added at the output. Such resistance is regarded as a small
load in a high-gain op amp and can drastically degrade the dc voltage gain.
Moreover, the effective capacitance of the CMFB network is added to the load
capacitance that in turn limits the bandwidth and slew rate of the op amp [6].
5.4 Fully Differential CMOS Op Amp Architectures
In this section, several architectures of differential op amps are briefly studied.

Many different op amp parameters previously discussed for the single-ended op
amp are equally applicable for the differential op amps. Therefore we deal with
only some key points that are associated with the CMFB circuit when included in
a particular structure.
5.4.1 Fully Differential Two-Stage Op Amp
The essential difference between an FD two-stage op amp with a single-ended one

is that in a differential op amp the current mirror load in the first stage is replaced
by two normal current sources. In order to provide a differential output, we have to
use two identical common-source stages as the second stage. The circuit of an FD
current is controlled by the CM control signal -K to adjust the output CM level.

two-stage op amp is shown in Figure 5.16, in which a part of the tail transistor
An important question about this architecture is how the CMFB circuit should
be used to adjust the CM output level. Generally there are two strategies to employ
VDD
Vbp
M8 M4 M6
M3
IB Rc Cc Cc Rc
vo+ vo-
CL vi+ M1 M2 vi- CL
M9 M5a
M0 M7
M5b Vs
Figure 5.16 Schematic of an FD two-stage op amp.

CMFB circuit in a two-stage op amp. The first one is to use two independent
CMFB circuits for each stage [7], and the second one is to detect the CM level of
the second stage output and apply the control signal to the first stage by employing
a single CMFB circuit. Although the second method requires less components and
looks more convenient, there is a subtle point with this method that should be
considered in order to avoid instability when the op amp is used in an external
negative-feedback loop [8]. In the following, we proceed to this matter.
The CM voltage gain of a two-stage fully differential op amp in the absence
of the CMFB circuit is the product of the CM voltage gain of the differential pair
and the voltage gain of the common-source stage. The differential pair has an
adequately small CM voltage gain due to the high output resistance of its tail
current source but the voltage gain of the second stage could be noticeable.
Denoting the CM voltage gain of an op amp without CMFB circuit by $0 , we
have $0 $0 with $0 as the differential pair CM gain and as the
common-source voltage gain. When CMFB is added to the op amp, any change in
the output CM voltage is sensed and through a negative-feedback mechanism this
change is compensated. Thus the CM voltage gain of an op amp in the presence of
CMFB circuit is too small. This matter is more obvious by representing the system
level behavior of this mechanism, as depicted in Figure 5.17. From Figure 5.17 the
closed-loop CM voltage gain of the op amp is given by
4 , ,5
$0 4, e Ä‰
(5.27)
where ã%Yq $K K$ is the open-loop gain of the CMFB circuit. As long as the
condition of ã%Yq is satisfied, $0 is too small and any change in -%$ cannot
appreciably affect the op amp output CM level. Now consider our two-stage FD
op amp with its single CMFB network is exploited in a negative external feedback
loop. To study the behavior of the op amp against the input CM variation here, we
only consider the circuit in the common-mode condition with no differential
signal. Figure 5.18 shows the circuit and its half-circuit equivalent in this
condition. $0 is the op amp CM voltage gain in the presence of CMFB circuit
Vic + Voc
Acm0
-
Tint
Figure 5.17 System level representation of a CMFB mechanism.

R2
R2
R1
Voc
- +
Vic
Vref R1
Half-circuit Vref Voc
Acm Acm
R1 Vic
+ -
R2
Figure 5.18 Two-stage FD op amp inside an external negative-feedback loop.
CM voltage -%$ acts as a positive feedback. In such a situation, in order to make

that is normally small but its sign is positive and thus the external feedback for the
sure that no instability occurs we need to have an open-loop gain that is less than
unity. For the half-circuit represented in Figure 5.18 we obtain
-"$ F G -%$ -
82 82
8Å 8Å .I
(5.28)
The open-loop gain is ãIVq $0 with ' ' ' . In a normal condition
the internal CMFB circuit keeps $0 adequately small and there is no concern
about the loop instability. This condition is met provided that the CMFB loop has
5.16, the CMFB loop gain becomes ã%Yq X0 „ Ò"Ž

a large open-loop gain according to (5.27). For the case of the circuit of Figure
$K in which $K is the
voltage -%$ drops below -fD -"# , the tail transistor M5 enters the triode region
voltage gain of the CM sense amplifier. If for any reason the op amp input CM
that causes a simultaneous drop in X0 „ and increase in $0 , which both lead to

raising the $0 . If $0 increases to the extent that the external loop gain of ãIVq
becomes greater than unity, the stability condition is violated and the CMFB
circuit will not be able to keep the output CM voltage on a desirable level. This
matter can be explained more clearly by drawing the graph of (5.28) as the load
line and the transfer function of the op amp output CM voltage versus its input CM
voltage together, as illustrated in Figure 5.19. The nearly flat part of the curve is
associated with the case that the CMFB circuit has enough large loop-gain to keep
the output CM voltage constant, which corresponds to a too-small $0 . As the plot
shows when the factor of } ' ' changes in the range of } } #, the
load line has three individual intersection points with the characteristic curve that
is acceptable. At point the output CM voltage is zero and point $ is an unstable

is equivalent to having three different operating points, among which only point
equilibrium point that the circuit cannot remain permanently at that point, and with
K1>K*
Voc
K*
K=0
Vref
C
R2
K
R1
B
0 Vic
A Vref
-K*Vref
-K1Vref
Figure 5.19 CM input-output characteristic of an op amp with a load line.
the smallest disturbance it moves quickly toward one of the two other points. For
example, if the op amp is to be used as a voltage follower with the unity voltage
} is zero, which leads to three different operating points.

gain, an application that is quite popular in sample and hold circuits, the parameter
feedback resistances (i.e., ' and ' ) are much greater than the op amp output
It should be pointed out that this condition happens provided that the external
resistance. This is because (5.18) is derived based on this condition. It is

interesting that the above mentioned condition is usually met in switched-capacitor
problem can be solved by changing the injection point of the control CM signal -K .
circuits where capacitors are used in the feedback network. The instability
Instead of controlling the tail transistor current, it is possible to control the load
current sources M3-M4, as seen in Figure 5.16. The partial section of the whole
circuit associated with the new CM control circuitry is shown in Figure 5.20.
VDD
Vs
− Voc
M3 Acs
+ Vcr
M8
Vic M1
Voc
M9
Vbn
M5
Figure 5.20 Partial modified CMFB circuit to solve the instability problem.
Voc
K>0
K=0
Vref
R2
K
R1
0 Vic
Vref
-KVref
Figure 5.21 Modified CM input-output characteristic of an op amp.
Now assume the same condition occurs and -%$ drops below -fD -Î# ,
which causes the tail transistor M5 to enter the triode region. Again X0 „ drops
but this time the gain of K$ is provided by the common-source stage amplifier
consisting of M3 and the cascode load of M1 and M5. Here M3 operates in the
fact, in this situation we can keep $0 small for -%$ near to zero, as is obvious
saturation region and its gain is not appreciably dropped, as is the case for M5. In
happens when }
from the graph shown in Figure 5.21. In this condition, even for the worst case that
, the circuit has only one stable operating point and there is
no concern about the instability issue caused by external feedback.
As mentioned at the beginning of this chapter, except for the CMFB circuit
design, all discussions about the design of a single-ended op amp are mostly
applicable for differential op amps. For instance, the frequency response of the
two-stage op amp given in Figure 5.16 can be calculated by employing its
equivalent half-circuit model shown in Figure 5.22. The circuit is exactly the same
as the single-ended two-stage op amp that was studied in detail in Chapter 4 and
thus here we ignore further discussion about this subject.
5.4.2 Fully Differential Current Mirror Op Amp
The schematic of a simple differential current mirror op amp is illustrated in

Figure 5.23. It is clear that this structure is very similar to the corresponding
single-ended one in which one stage is added to provide two differential outputs.
The frequency response analysis of this circuit follows all points that were
mentioned with regard to the single-ended current mirror op amp in Chapter 4. As
in the case of single-ended, the higher dc voltage gain is achievable by using a
cascode structure. The reader may wonder if an FD current mirror op amp needs a
CMFB circuit or not.
Rc Cc
vod/2
C2
M8 R2
vi/2 M1 C1
R1
small signal
equivalent
(a)
Rc Cc vod/2
+
gm1vi/2 + gm8vgs8
vi/2 C1 C2
- R1 vgs8 R2
R1=ro1||ro3 R2=ro8||ro9
(b)
Figure 5.22 Half-circuit ac model of an FD two-stage op amp. (a) Transistor level schematic and (b)
small-signal equivalent circuit.
VDD
K:1 M5 1:1 1:1 M6 1:K

M11 M3 M4 M12
vo+ + M1 M2 vo-
vid
-
CL CL
2I0
M10 K:1 M9
M7 1:K M8
Figure 5.23 Schematic of an FD current mirror op amp
There is an interesting point about the CMFB network requirement for such
an architecture. Remember that in a simple differential pair with current mirror
load the dc level of the floating drain is identical with that of the drain of the
diode-connected device. Here we encounter the same configuration for two current
mirrors of M7-M8 and M9-M10. Consequently at the absence of CMFB circuit we
expect the output CM voltage to be equal to the same gate-source voltage of M7
and M9. This means that in the current mirror architecture, unlike other
differential op amps, the level of the output CM is well-defined, even when there
VDD
K:1 1:K
M5a M3a M3b M5b
M6a 1:1 M4a M4b M6b

1:1
vo+ vo-
vi+ vi- vi+

M1a M2a M1b M2b
M8a M7a 2I0 2I0 M7b M8b

K:1 1:K
Figure 5.24 Another structure for a differential current mirror op amp.
is no CMFB block. But in many applications we may need to have a certain output
dc voltage that is different from a gate-source voltage drop as in this circuit. In
such conditions we have to exploit an appropriate CMFB network to keep the
output CM level of the current mirror op amp output on our desirable reference
level. Because of a large similarity between a single-ended and differential op amp
with the current mirror structure, we avoid giving more explanation about the
circuit of Figure 5.23 and just introduce another circuit that can act as a differential
current mirror op amp as depicted in Figure 5.24 [9]. In fact, this op amp is
comprised of two identical single-ended current mirror op amps that together
provide the differential output voltage. From a performance point of view we can
say that this architecture exhibits nearly the same performance as with the
previous one. However, from the frequency response point of view, in the same
conditions in terms of devices aspect ratios the location of the second pole in the
latter is a little farther and as a result the phase margin is better. The reason for that
shown in Figure 5.23 is } ¯KŽ , for the latter it is }

is behind the capacitance seen at the drain of M1 and M2. While this capacitance,
¯KŽU . The reader
can readily obtain the differential voltage gain of this op amp as
+ ‡¯5ÅH2
#0 ¯ é ¯
(5.29)
+
Where !"# !" !"/ , !%# !% !%/ , X" X" U X" „ and, X" X" U
X" „ . It is recommended that the interested reader perform all analyses such as
frequency response and slew rate calculation for both given differential current
mirror op amps by pursuing the procedure described in Chapter 4.
5.4.3 Fully Differential Folded-Cascode Op Amp
As discussed in Chapter 4, in fact folded-cascode architecture is a variant of the

telescopic cascode in which the output swing limitation has been eliminated and
thus it is suitable for low-voltage applications. Figure 5.25 shows the schematic of
an FD folded-cascode op amp. When this circuit is compared with its single-ended
counterpart we notice that the only difference between the two architectures is that
the wide swing current mirror is replaced by a simple current source. Here again
all analyses presented in Chapter 4 for the single-ended folded-cascode op amp are
applicable for the FD one. Therefore we can use all given relationships in Chapter
4 to design the differential type. It should be pointed out that employing a proper
CMFB circuit to stabilize the output CM voltage in this structure is also
indispensable.
Design Example
Since the FD folded-cascode has the most application in low-voltage design, we

put forth a design procedure for such an architecture, which is shown in
Figure 5.25. On the other hand, many differential op amps are usually used in
switched-capacitor circuits or in a mixed-mode system where a digital clock signal
is naturally accessible. For this reason we choose the switched-capacitor method to
realize the CMFB circuit in order to utilize all its benefits. This time we intend to
-eY Ì-eR Ì T=[, hY "V = \¶ [ , hR "V = \¶ [ , and the

design our op amp in a 0.18-\Š CMOS technology where its main parameters are
subthreshold factor equals - #IR "V T. The required op amp

specifications are:
Figure 5.25 FD folded-cascode op amp.

Dc voltage gain: 4 % =
(BT-dB)
Phase margin: N& ÷ < ›

Slew rate: O' ÷ T [ \]
Load capacitance: Z C µ
rate. As the slew rate is calculated from O' WqU%• Z we need to have WqU%•
First we determine the value of the tail transistor current from the given slew
W)Ž \¶ and thus W) W) < \¶. From the given bandwidth, the
LM X0 Z , with LM ‹ = _ à, we get X0 ;T Š¶ [. From

minimum required transconductance of the input devices is obtained. Since
X0 H ¾ •hY "V o p H W)Ž ÷ ;T Š¶ [ with ¾ A, we reach the

inequality o p H = . In practice, different output parasitic capacitances
including the capacitances of the CMFB circuit are added to the load capacitance
and thus reduce the effective bandwidth. Moreover, the given dc voltage gain with
a limited input transconductance is achievable if we have a large output resistance
by using long-channel devices in the cascode stage. This of course leads to a large
taking o p H we obtain a larger X0 H to help to alleviate some of these

gate area for these devices and as a result affects the frequency response. By
issues. The channel length is chosen as p H \Š to minimize the short-channel

effect that gives o H \Š. Since transistors M4 and M5 act as current
sources that provide the drain current of M1, M2, M6, and M8, we take W)Ç
W) W)Ž \¶. Allocating equal bias currents for the differential pair of
devices also becomes W)ê/ < \¶. The sizes of M6 to M11 are calculated
(M1, M2) and the cascode transistors M6 and M7 the bias current of the cascode
based on choosing an appropriate value for the overdrive voltage of each device.
Š[ is allocated to all NMOS

To get a reasonable aspect ratio for devices and attain enough output voltage
Š[ is allocated to M6 and M7. Based

swing, an identical overdrive voltage of about
devices from M8 to M11 and less than
of o p = is obtained for M8 to M11. In order to have adequate large output

on the given data for the process and with these overdrive voltages, the aspect ratio
resistance to achieve the required dc voltage gain, the channel length of p \Š
= \Š \Š. The loading effect of the drain-source resistance of M4 and M5

is selected for M8 to M11. Consequently the size of M8 to M11 will be
currents, it is necessary to minimize the parameter of | }#K “p •-)D -)DHKUq –

leads to decrease the voltage gain. Since these devices carry relatively large
to attain the maximum resistance (Ò" |W) )). The drain-source voltage can be
increased by lowering the dc bias voltage of -„R , while selecting a channel length
of pÇ p = \Š helps to increase the output resistances of the devices as
well. The bias current W• \¶ supplies the current of the tail transistor M3.
In the design of the CMFB circuit, some points should also be taken into
account. The sampling capacitance K is determined based on a trade-off among
several parameters including speed, accuracy, and loading effect. As discussed

earlier, a large K helps to reduce the charge sharing error due to the switches, and
CMFB circuit to reach its steady state through lessening the factor }. But at a
if it is chosen adequately larger than it can also decrease the transient time of
certain clock frequency a large K reduces the equivalent resistance of the CMFB
circuit seen at the op amp output, which lowers the dc voltage gain. To minimize
o p K• = \Š A \Š to the switches employed in the CMFB circuit and

the error of charge sharing, we allocate a small size of
take = µ and K = µ, which gives } C. It should be

pointed out that the usual ac simulation in SPICE here cannot be used to obtain the
ac parameters such as dc voltage gain, bandwidth, or phase margin of the op amp.
This is because there is an SC CMFB circuit whose switches are controlled by the
clock signal in the time domain. Hence we have to use periodic steady state (pss)
analysis in SpectreRF [10] to get these parameters. The whole designed circuit
(including the bias circuitries and all device sizes) is shown in Figure 5.26.
BT >?, LM ‹ T; A _ à, N& BB› , and power

Performing this simulation on the circuit using the BSIM4 model for all MOS
devices, we obtain 4
dissipation of =T Š .
As we know in single-ended op amps, slew rate simulation is performed by
placing the op amp within a voltage follower configuration and applying a
relatively large step voltage as input. For FD op amps we cannot use such a
configuration. As a result we use a feedback amplifier with a voltage gain of one,
as shown in Figure 5.27. Very large parallel resistors are used across all capacitors
to provide the required dc path to avoid any simulation error. In reality the
combination of switches and capacitors realizes such a dc path when the op amp is
and negative slope is O' C= [ \]. The reason for the difference between our
used in a real switched-capacitor circuit. The output slew rate on both the positive
design goal and the obtained result is associated with other parasitic capacitances
except for the load capacitance from the output devices and CMFB circuit, which
are added to the load capacitance. If reaching the given spec for slew rate is
important to us, we can increase the tail current of the differential pair. Of course
this action causes a reduction in the dc voltage gain that can be compensated by
increasing the channel lengths of the devices that have contributed to the voltage
gain.
VDD=1.8V
200/1.5
20/1.5 M4 M5 M17
M13
20/1.5
50/0.5 M7
IB=12 µΑ M6 M15
1/0.5
vi+ M1 100/1 M2 vi-
vo- vo+
M3 50/1 M9 M16
100/1 M8
1/1
M10
10/1 M12 M11
M0 M14
10/1 50/1 10/1
Cf Cf
0.25 pF 0.25 pF
clk
M21 M23 φ2
M19
0.5/0.18
M24
1/5 Cs Cs
0.5 pF 0.5 pF
M20 M22 φ1
M18
Vcr
M25
1/5
Figure 5.26 Complete designed FD folded-cascode op amp.
100 MΩ
0.5 pF c2
100 MΩ
0.5 pF c1
vi- - vo+
+
0.5 pF c1 - vo-
vi+ +
100 MΩ 0.5 pF c2
100 MΩ
Figure 5.27 Unity gain differential amplifier used to simulate op amp slew rate.
5.5 Conclusion
In this chapter, we studied a fully differential op amp, which is one of the most
important building block in mixed-mode integrated circuits. The CMFB as a key
network that is a dispensable part of any FD op amp was first introduced from the
systematic point of view and then its stability issue was discussed in detail.
Different types of CMFB circuits that normally are used in FD op amps were
studied and advantages and disadvantages of each type were described. At the end,
one design example was given in which we dealt with a folded-cascode FD op
amp. A switched-capacitor network was selected as the CMFB circuit of our op
amp and some practical design points in conjunction with the employed switched-
capacitor CFMB circuit were pointed out.
References
[1] Spinelli, E. M., Garcia, P. A., and Guaraglia, D. O., “A Dual-Mode Conditioning Circuit for
Differential Analog-to-Digital Converters,” IEEE Trans. Instrumentation and Measurement, Vol.
59, Jan. 2010, pp. 195-199.
[2] Huijsing J., Operational Amplifiers: Theory and Design, Springer, May 25, 2011.
[3] Baker R. J., CMOS: Circuit Design, Layout, and Simulation, Third Ed, John Wiley & Sons, 2010.
[4] Razavi B., Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
[5] Pasch, T., Kleine, U., and Klinke, R., “A Low-voltage Differential Op Amp With Novel Common
Mode Feedback,” IEEE ICECS 1998, Vol. 2, 1998, pp. 345-348.
[6] Garduno D. H. and Martinez J. S., “Continuous-Time Common-Mode Feedback for High-Speed
Switched-Capacitor Networks,” IEEE J. Solid-State Circuits, Vol. 40, No. 8, August 2005, pp.
1610-1617.
[7] Rabii S. and Wooly B. A., “A 1.8-V Digital-Audio Sigma–Delta Modulator in 0.8-h& CMOS,”
IEEE J. Solid-State Circuits, Vol. 32, No. 6, June 1997, pp. 783-796.
[8] Tauro, A., et al., “Common Mode Stability in Fully Differential Voltage Feedback CMOS
Amplifiers,” IEEE ICECS 2003, Vol. 1, 2003, pp. 288-291.
[9] Johns D. A. and Martin K., Analog Integrated Circuit Design, New York: Wiley, 1997.
[10] Telichevesky R., Kundert K. S. and White J. K., “Efficient Steady-State Analysis Based on
Matrix-Free Krylov-Subspace Methods,” Proceedings of the 32nd Design Automation
Conference, June 1995.
Chapter 6
CMOS Output Stages
The output stage is the last part of an op amp, which is employed to provide the
required driving current for a heavy resistive or capacitive load. It is important that
this stage does not impose any noticeable distortion in the output signal or
remarkable drop in the total voltage gain. The frequency response of the stage
should not also impose any limitation on the main amplifier bandwidth. Two other
important parameters in the design of an output stage are power efficiency and
maximum possible output voltage swing. In this chapter, different structures
usually used as the output stage of an op amp are discussed.
6.1 Class A and Class B Output Stages
As we know, in a class A amplifier, in the absence of an ac input signal, the

transistor operates in its active region and the ac signal is superimposed on the bias
point. In an amplifier working in class B, in an ideal case, the transistor is biased
exactly at the edge of conduction such that applying an ac signal causes the
transistor to turn on [1]. A class A power amplifier has the best performance in
terms of linearity, but its power efficiency is generally smaller than a class B
amplifier. In this section some different structures in class A and class B
amplifiers are briefly introduced.
6.1.1 Source-Follower as an Output Stage
Since the output resistance of a source-follower stage is usually low it can be used
at the output as a simple driver. For the circuit shown in Figure 6.1 we have
!" !% !fD (6.1)
!fD -e t Æ:
%
(6.2)
Å
135
136 CMOS Output Stages
VDD
M1
vi
iD vo
I0 RL
-VSS
Figure 6.1 Source-follower output stage.
where ° hY "V o p with hY as an electron mobility, "V as the gate-oxide

capacitance per unit area, and o p as the M1 aspect ratio. The effective
threshold voltage -e in (6.2) itself is given by
-e -e ’ • ”• !" -D• • ”• (6.3)
where -e is the zero-bias MOS threshold voltage, ’ is the body effect factor, ”•
is the Fermi potential, and -D• is the source-to-body potential. The drain current is
given by
®) W
8³
(6.4)
Using the above equations, we can get the relationship between input and output
as
S
Á
©{ ¬
! !% -e ’“• ”• !" -D• • ”• – ³
ÆÅ
(6.5)
According to (6.5), this stage shows a nonlinear behavior that results in generating
higher harmonics at the output for a pure sinusoidal input voltage. If the dc level
condition for !%
of the input voltage is the same as the dc gate-source voltage of M1, in static
, the dc level of the output voltage becomes zero as well. In
derivation of (6.5) with respect to !% at !%

this condition the small-signal voltage gain can be calculated by taking the
.
ö * * *
# ¸ # ÉÅ ³ #
# ' • §¨ 4k¨ # ' S # '
(6.6)
2©Ê ¬
' ' Á ³ '
ÉÅ
After some manipulation on (6.6), the voltage gain is obtained as
ö
¯5 8³
¯5 Ì¿ Ì
(6.7)
5y ³
In (6.7), X0 is the MOSFET’s transconductance and ¹X0„ ¹ expresses the body

effect. As discussed in Chapter 2, X0„ is given by
X0 „
¸¯5
• §¨ 4k¨
(6.8)
To find the output voltage swings, the ideal current source is replaced with the
swing depends on the values of W and 'Z so that if we have 'Z W [ , the swing
current mirror circuit, as illustrated in Figure 6.2. The lower limit of the output
a result the output voltage is clipped at 'Z W . If the maximum input voltage is
is limited when M2 enters the triode region; otherwise, M1 turns off earlier and as
less than [ÍÍ , M1 always remains in saturation and the upper limit of the output
voltage is much less than [ÍÍ Based on this discussion, the output-input large-
signal characteristic of the source-follower stage can be obtained as plotted in
load (small 'Z ) entails a large amount of dc bias current W , which leads to
Figure 6.3. Evidently, a large swing toward the negative rail for a low-resistance
increasing the power dissipation and gives low-power efficiency. In the source-
VDD
Iref
vi M1
vo
I0 RL
M3 M2
-VSS
Figure 6.2 Source-follower with current mirror bias circuit.
vo
M1: Triode Region

VDD
VDD-Vod1
-VSS+Vod2+VGS1
VT1-RLI0 0 vi
VGS1 VDD+VT1
M1: Off
-RLI0
-VSS+Vod2
-VSS
M2: Triode Region
Figure 6.3 Output-input large-signal characteristic of a source-follower stage.
follower stage the output swing is usually quite less than the supply voltage. To
increase the swing, we can use a common-source stage as shown in Figure 6.4.
The maximum output voltage swing downward (upward) is limited when M1 (M2)
enters the triode region. When the output voltage goes up eventually M1 turns off
and if M2 remains in saturation the peak of the current is delivered to the load that
equals the drain current of M2. In the negative cycle of the input voltage the
current sunk from the load is
®Z/ ®) W “!% -DD -e – W

ÆÅ
(6.9)
As long as M1 remains in saturation, ®Z/ increases with !% , as stated by (6.9) until
VDD
I0
VB M2
vo
vi RL
M1
-VSS
Figure 6.4 Common-source output stage.
M1 is placed at the edge of the triode region where the maximum of ®Z/ is obtained
®Z0UV
from
/ 4kk /4 SÅ
8³
(6.10)
where -" is the overdrive voltage of M1. For small 'Z , ®Z0UV /
than the bias current of W and thus the output voltage swing is not symmetric in
could be greater
two directions. The power efficiency is defined as the ratio of the consumed power
in the load to the average power drawn from the supply [2]
Å
8 %2
( 2 ³ ³
4:: {
(6.11)
Assuming maximum load current is limited to W and M2 is at the edge of the

triode for this level of current, we can achieve the maximum possible power
efficiency for a class A power amplifier as
() *+
4:: /4 S2
Ç 4::
(6.12)
where -" is the M2 overdrive voltage. For -)) -" , we have () *+ , =- .

Having a fixed and independent quiescent current with respect to the process,
supply voltage, and temperature variations (PVT), high-output swings and good
linearity are the main advantages of a common-source class A power amplifier but
low-power efficiency and unsymmetrical swings are its disadvantages.
6.1.2 Class B Power Amplifier
By using two complementary PMOS and NMOS transistors as two source-

follower stages, it is possible to implement an output stage with the capability of a
driving high-output current and high-power efficiency. In the circuit shown in
Figure 6.5, owing to the threshold voltage of M1 and M2 when the input voltage
VDD
M1
vi vo
M2 RL
-VSS
Figure 6.5 A simple Class B CMOS output stage.
changes in the range of . Ì-e × Ì !% -e Y , both transistors are off and as a result
there is no voltage at the output. Thus a distortion known as cross-over distortion
appears at the output. The diode-connected transistors M4 and M5 shown in
Figure 6.6 put M1 and M2 at the edge of the conduction state that leads to
reduction of this kind of distortion [3].
!%
In Figure 6.6 suppose M1 and M2 are the same; in a static condition when
!fD Ç !Df !fD !Df

we have
(6.13)
In a no-signal condition, the bias currents of M3 to M6 are all W and for the same
drain current in M1 and M2 (®) , ®) ), using (6.13), we have
-e Y Ì-e × Ì -e Y Ì-e × Ì
%: Å %: 2
t t
{ {
tÆ tÆ ÆÅ Æ2
(6.14)
Ë é
where °% hYHR "V o p % for ® H HTH=. In (6.14) we have ®) , ®) W)

and thus the quiescent current in M1 and M2 can be calculated as
Å Å
W) W / 0
•ÉË •Éé
Å Å (6.15)
•ÉÅ •É2
Equation (6.15) proves that the quiescent current of the output transistors only
VDD
I0
VB M3
M4 M1
vo
RL
M5 M2
vi M6
-VSS
Figure 6.6 Class B output stage with elimination of cross-over distortion.
depends on the sizing of M1, M2, M4, and M5 and it is almost independent of
In the negative cycle of the input voltage of !% , the drain voltage of M6

process, temperature, and voltage.
increases, which makes M1 more conductive and simultaneously decreases the

conduction of M2, so M1 provides the required drive current to the load. In this
condition the output voltage swing reaches the upper limit when M3 enters the
triode region
!" 0 -)) -"#Ž !fDÅ (6.16)
Writing !fD in terms of the load current and noting that the load current itself is a
function of the output voltage, we can derive !" 0 as
!" 0 -
• ÆÅ 8³ 4Å
(6.17)
- -)) -"#Ž -e Y
where
(6.18)
Figure 6.7 shows the variation of !" 0 versus the load resistance when it changes
from zero to infinity. In practice, for large 'Z it is possible that !" 0 becomes
greater than - . Under this condition the drain current of M1 is too small and
therefore M1 operates in the subthreshold region with !fD -e Y .
With the provided dc bias voltage at the gates of the output transistors in
Figure 6.6, this stage indeed works as a class AB power amplifier in which the
cross-over distortion is minimized and at the same time the circuit holds a
minimum stable quiescent current. The supply current for a sinusoidal input
efficiency of the amplifier. For [ÍÍ [ the average power drawn from the
voltage is shown in Figure 6.8. This current can be exploited to derive the power
supply is
NK
4:: {Ú
1
(6.19)
vom+
V1
RL
0
Figure 6.7 Maximum output voltage swing vs. load resistance.
isup
IP
isup+ isup-
t
0 T/2 T 3T/2
Figure 6.8 Supply current waveform of a class B output stage.
And power efficiency in terms of the peak of the load current W× will be
(
1 8³ {Ú
Ç 4::
(6.20)
In an ideal case for 'Z W× -)) the maximum efficiency is T. Of course in this
circuit the output peak voltage is - , which is quite less than [ÍÍ and this is
considered as the main drawback of this structure.
6.2 Drain-Coupled Complementary Transistors as Output Stage
The deficiency of the previous circuit in the output voltage swing can be
configuration, as illustrated in Figure 6.9. The dc voltage sources -• are used to

compensated by using two PMOS and NMOS transistors in a common-source
put both transistors at the edge of conduction. In the positive half-cycle of the ac
input voltage, M1 is more conductive while the amount of conduction in M2
reduces so that the output voltage goes down and M1 sinks the load current. In the
negative half-cycle of the input, the role of M1 and M2 are interchanged and M2
VDD
M2
+ VB
-
vi vo
+
- VB
RL
M1
-VSS
Figure 6.9 Complementary common-source configuration as an output stage.
sources the current to the load while M1 approaches the cutoff region. The upper
(lower) level of the output voltage swing is limited when M2 (M1) enters the
the triode region by !"0 , we see M1 is off in this condition and the entire load
triode region. Denoting the maximum output voltage that places M2 at the edge of
current is provided by the drain current of M2. For !" !"0 , M2 places at the
edge of the triode region and thus we can write
!D) -)) !"0

%: 2
HKUq
t Æ2
(6.21)
Since ®) !"0 'Z , using (6.21) we can obtain !"0 as follows
!"0 -))
• Æ2 8³ 4::
(6.22)
Similarly !"0
/
as the maximum output swing in the negative half-cycle of the
output voltage is given by
!"0
/
-))
• ÆÅ 8³ 4::
(6.23)
A symmetrical output swing is achievable provided that two PMOS and NMOS
output devices are identical. This condition is satisfied by choosing proper sizing
for M1 and M2 in such a way that we have
F G F G
i ÃÄ i
Z ÃQ Z
(6.24)
large 'Z and also higher ° h "V o p

It is apparent from (6.22) or (6.23) that the maximum output swing increases for
for M1 or M2. Generally the load
current in the circuit of Figure 6.9 is the difference of the M1 and M2 drain
®Z ®) ®)
currents
(6.25)
If it is supposed that M1 and M2 are exactly identical, the drain current

relationships for these devices become
®) !% -• -KK -e
Æ
(6.26)
®) -## -• -e !%
Æ
(6.27)
where it is assumed that ° ° °. Hence the load current when both M1 and
M2 are on and operate in the saturation region is given by
®Z ° -)) -• -e !% (6.28)
When M1 or M2 turns off, the load current is equal to the drain current of the
current W) is obtained by setting !%

other conducting device. If there is no ac signal at the input, the output quiescent
in (6.26) or (6.27)
W) -)) -• -e
Æ
(6.29)
input voltage !% . The capability to source or sink a lot of current to or from a

Figure 6.10 depicts the load current and the M1 and M2 drain currents versus the
heavy load and having a symmetrical rail-to-rail output swing are the remarkable
advantages of this structure but its main drawback is that its quiescent current
depends drastically on process, voltage, and temperature. This issue can be
with respect to -)) H -e , and -• as

quantified by using (6.29) to express the relative variation of the quiescent current
2{: 234 4 24¨

{: 4Å 4Å
(6.30)
If we expect to drive heavy loads such as small 'Z or large load capacitance by
this circuit, the channel aspect ratio of the output transistors should be taken
according to (6.29), we need to minimize - -)) -• -e . This results in two

adequately large. On the other hand, in order to have a small quiescent current
consequences. First, it reduces the linear operation range of the circuit, as can be
io, iD1, iD2
VDD/RL
iD1
iD2 V1=VDD-VB-VT
IDQ
0 vi
-V1 +V1
io=iD2-iD1
-VDD/RL
Figure 6.10 Load current variation in terms of ac input signal.

seen from Figure 6.10. Second, it increases the sensitivity of the quiescent current
-)) =[H -e =[H -• ;[, and ° T Š¶ [ , the quiescent current

to PVT variations based on (6.30). As an example, in a typical condition, for
\¶. Now suppose at high temperature in the fast corner of the

process, -e changes to C=[ and supply voltage also increases by 4% ( [). This
becomes about
causes W) increases to T= \¶! So in spite of the remarkable advantages of this

circuit we need to have a class AB output stage with the symmetrical and rail-to-
rail output voltage swing and also stable quiescent current with respect to PVT
variations. Figure 6.11 shows one such circuit.
It is assumed that the circuit is symmetrical about axis AA'so that the pairs of
static condition for !%

M1-M2, M3-M4, M5-M9, and M6-M10 are mutually identical with each other. In
, summing the gate-source voltages in the loop
consisting of M5, M6, M3, and M2 gives
-fD -Df ê -Df Ž -fD (6.31)
Using the corresponding relationships of the gate-source voltages for an MOS

device whose drain current follows the square law, from (6.31) we get
A VDD
M7 M11
M5 M9
vi
M1 M2
vo
M6 M10 RL
M3 M4
I1 I2
I0 I0
M8 M12
A’ -VSS
Figure 6.11 A CMOS class AB output stage with stable quiescent current.
-e Y *-e R * *-e R * -e Y
{ { {Å {Å
tÆ tÆ tÆ tÆ (6.32)
é í Ñ 2
From (6.32) the static current W is obtained
Å Å
W W / 0
•Éé •Éí
Å Å (6.33)
•É2 •ÉÑ
can be written and solved to get W as follows

There is another equation exactly similar to (6.31) for M1, M4, M9, and M10 that
Å Å
W W / 0
•É •ÉÅ
Å Å (6.34)
•ÉÅ •ÉË
The quiescent current of the output transistors M11 and M12 are copies of W and
W , which are produced by the current mirrors M7-M11 and M8-M12, respectively.
²
F G
W) W
³ ÅÅ
²
F G
(6.35)
³ ï
²
F G
W) W
³ Å2
²
F G
(6.36)
³
In the static condition, if no dc current flows through the load for !%

!" . Because of the circuit symmetry, we have W W so the output voltage in
we have
dc state becomes zero if we have W) W) . From (6.35) and (6.36), this

condition is equivalent to meet the following relationship:
² ²
F G F G
³ ÅÅ ³ Å2
² ²
F G F G
(6.37)
³ ï ³
In the circuit of Figure 6.11 due to the fixed bias current W , the gate-source
voltages of M5 and M6 are constant. Thus by going up the input voltage !% , the
effective voltage across two series gate to source of M2 and M3 decreases and that
of M1 and M4 increases, and as a result the drain current of M2, M3, and M7
decreases while the corresponding current in M1, M4, and M8 increases. These
changes are reflected to the output stage through the current mirrors M7-M11 and
M8-M12. Consequently it will sink the current from the load more than what M11
sources current to the load, and thus the output voltage goes down. We now obtain
VDD
vi
M1
VB
M4
i2
M8
-VSS
Figure 6.12 A part of the circuit of Figure 6.11 used to derive 6.
the analytic relationship for the currents ® and ® in the presence of the input !% .
For the partially drawn circuit shown in Figure 6.12, we can write
!% !fD !Df Ç -• (6.38)
where -• is defined as: -• -e Y • W ° *-e R * • W ° . Equation

(6.38) can be rewritten as follows:
!% -e Y t Æ2 *-e R * t Æ2 -e Y *-e R *
% % { {
tÆ tÆ (6.39)
Å Ë Å
By solving (6.39) we get a relationship for ® in terms of !%
® !% - 5 !% -
Æ
(6.40)
where ° ° °Ç “•° •°Ç – and - • W “ •° •° –. Similarly,

a part of the main circuit used to derive ® is shown in Figure 6.13. Here -fŽ is the
applied voltage to the gate of M3 and defined as -fŽ !% -fD -Df ê . For
this circuit we have
!fD !Df Ž !% “-fD -Df ê – (6.41)
Similar to (6.39), we have
-e Y t ÆÅ *-e R * t ÆÅ !% -e Y *-e R *
% % { {
tÆ tÆ (6.42)
2 Ñ é í
VDD
M7
M2
i1
VG3 M3
-VSS
Figure 6.13 A part of the circuit of Figure 6.11 to derive 9.
And finally from (6.42) we get ®
Æ7
® -8 !% 5 !% -¼ (6.43)
where °8 ° °Ž “•° •°Ž – and -8 • W “ •° •°ê –. Because

of the circuit symmetry, we have - - ¼ and ° °8. Figure 6.14 illustrates
changes of ® and ® versus !% .
For the size ratio of ‘ in the current mirror circuits implemented by M7-M11
and M8-M12, the ac load current will be
®Z ‘ ® ® < TT
i1 , i2
i1 i2
β
I1=I2= V12
2
vi
-V1 +V1
Figure 6.14 i1 and i2 variation versus vi.
Substituting (6.40) and (6.43) into (6.44), we get
®Z °‘- !% (6.45)
By applying !% to the gate of M2 (M9) and connecting the gate of M5 (M1) to
positive supply with -DD

ground, the output current will be in phase with the input. If the circuit has a single
, the gate of M2 (M9) and M5 (M1) should be tied to
an appropriate positive bias voltage. This voltage needs to be high enough in order
to keep M3 and M4 in saturation in the worst case when MOS transistor threshold
voltage is on the highest value, which happens in the slow-slow process corner and
at minimum operation temperature. Using a little bit of modification in the circuit
of Figure 6.11, this circuit can be changed to a fully differential class AB
amplifier, as shown in Figure 6.15.
6.3 Low-Voltage Class AB Buffer
In the circuit of Figure 6.11 we had two voltage drops across the gate-source of
M6 (M7) and M9 (M8) plus two overdrive voltages of M1 (M2) and M4 (M3)
between two rails. As a result, the minimum total supply voltage of the circuit
needs to satisfy the following inequality
-)) ¹-DD ¹ ÷ -e Y *-e R * T-" (6.46)
VDD
M13 M5 M6 M14
M9 M10
vi+ M1 M2 vi-
vo+ vo-
M11 M12
M3 M4
I1 I2
I0 I0
M15 M7 M8 M16
-VSS
Figure 6.15 A fully differential class AB amplifier.
VDD
1:m
M3
Mc Md M1 M5 M7 M11
1:(1+α)
iD3 iD5 Vbp
M8
I1
iD1
vo
+ Ma Mb
vi
- I2 Vbn
M9 RL
2I0 M4
M2 M6 M10 1:m M12
1:(1+α)
-VSS
Figure 6.16 A low-voltage class AB power amplifier.
where -" is the overdrive voltage for each MOS device. Therefore the circuit of
Figure 6.11 is not appropriate for low-voltage applications. In this section, we will
In a static condition when !%

analyze an adopted low-voltage buffer [4] that is shown in Figure 6.16.
divided equally between Ma and Mb and we have -Df $ -K) $ -Df # -D) # ,
, the input differential pair tail current is
therefore all MOS transistors including Mc, Md, M1, M3, and M5 have the same
gate-source voltage and thus identical drain current density
{: Å {: Ñ {: é {
² ² ² ²
F G F G F G F G
(6.47)
³ Å ³ Ñ ³ é ³ +
Supposing o p o p Ž o p # , we have
W) Ž W) W) W (6.48)
W) Ç ¾ W) ¾ W
and
(6.49)
W W) Ç W) Ž ¾W
So
(6.50)
On the other hand, we have
W) ¾ W) Ž ¾ W (6.51)
For o p ê o p and since -fD ê -fD we also have
W) ê W) W (6.52)
So we can get W
W W) W) ê ¾W (6.53)
The quiescent current in M11 and M12 is obtained from W and W through two
current mirrors M8-M11 and M10-M12
W) W) ¾&W W (6.54)
Equation (6.54) shows that the quiescent current in the output transistors depends
only on transistor sizing ratio and the fixed dc bias current and consequently its
sensitivity to PVT is minimized. In [4] the low sensitivity of the quiescent current
is attributed to the behavior of the diode-connected transistors M7-M8 and M9-
M10 as an adaptive dynamic load. Based on the description given in [4] at low-
level ac input signal corresponding to static conditions, the dynamic resistance of
the diode-connected circuit is low and thus the voltage gain of the preamplifier
consisting of M3-M6 is low and any voltage change due to the process or supply
variation has less impact on the current of the output stage transistors. To more
closely see the dynamic behavior of the circuit, we examine one of these diode-
circuit is plotted in Figure 6.18. In the circuit of Figure 6.17 for ! -e Y , M1 is off
connected circuits, which is shown in Figure 6.17. The I_V characteristic of this
and ® when ! becomes greater than the threshold voltage of M1; M1 and M2
turn on and initially both operate in saturation so that with the assumption that
both transistors are identical, we can write
®) ®) F-„Y -)D -e G “! -e Y –
Æ Æ
Y
(6.55)
And thus we have
-)D -„Y ! (6.56)
M2 Vbn
v
M1
-
Figure 6.17 Diode-connected configuration as a dynamic load.
β
(Vbn-VTn)2
2
v
VTn
Figure 6.18 I_V characteristic of the circuit of Figure 6.17.
But by rising !, -)D decreases and eventually M1 enters the triode region while
M2 stays in saturation. Therefore, by equating the drain currents of M1 and M2
when M1 is in the triode region, we get
4:k 2
F-„Y -)D -e G °Ô“! -e Y –-)D Õ
Æ Å
Y
(6.57)
Neglecting the term -)D for a small -)D at the right-hand side, we can obtain
the relationship between ® and ! as follows
2
® ç“-„Y -e Y – è
Æ “4yÄ /4£ Ä –
/ 4£ Ä 4yÄ
(6.58)
As can be seen from Figure 6.18, the equivalent dynamic conductance of the
amplitude of the voltage !.

circuit corresponding to the slope of this curve, decreases by increasing the
The minimum supply voltage limitation in this architecture can be lowered up

to one gate-source voltage plus one overdrive voltage. In fact the lower limit for
AB output stage. In the presence of the ac input signal, when !% goes up, the drain
the supply voltage is determined by the input differential pair rather than the class
current of Ma (®) U ) increases and through the current mirror Mc-M3, M5 causes
the drain current of M3 and M5 to increase. On the other hand, by going up, the
drain voltage of Mb the drain current of M1 reduces, which results in reducing the
changes increase W and decrease W and finally the current that is sunk from the
drain currents of M4 and M6 through the current mirror M2-M4, M6. All these
load increases with !% . Similarly we can show when the input goes down, W
increases and W decreases, which leads to an increase in the current delivered to
the load. Since both output and input common-mode voltages are the same, when
the circuit is used as a voltage follower, the minimum level of the output swing is
limited by the input stage rather than M12 at the output. The lower limit of the
common-mode voltage for the input differential pair in Figure 6.16 is given by
-%$ 0%Y -KK -)D HKUqHqU%• -fD H

!" 0%Y (6.59)
The maximum output level, especially for a heavy load, is usually determined by
the overdrive voltage of M11
!D) -## !" 0UV

%³ 5ˆ—
HKUq t ÆÅÅ
(6.60)
where ®Z 0UV is the maximum load current in which M11 is placed at the edge of
the triode region. Since !" 0UV 'Z ®Z 0UV, we get a quadratic equation versus
®Z 0UV
'Z ®Z 0UV F 'Z -## G ®Z 0UV -##
ÆÅÅ
(6.61)
By solving (6.61) we can find ®Z 0UV , thereby obtaining the maximum output
swing from !" 0UV 'Z ®Z 0UV
6.4 Class AB Output Stage Using a Translinear Loop
There is another low-voltage architecture for a class AB power amplifier that we
in [5]. In this circuit W%Y is the ac input current that is provided by the first stage.
will analyze in this section. The circuit indicated in Figure 6.19 has been reported
M6 and M7 create a floating current source in which the current is determined by

two translinear loops consisting of PMOS transistors M1, M2, M5, and M6 and
NMOS transistors M3, M4, M7, and M8 [6]. For the PMOS translinear loop we
can write
-Df -Df -Df -Df ê (6.62)
current density in M1 and M5 are equal (i.e., for W) o W) o ), we have

Presuming the same channel length for M1, M2, M5, and M6 and also if the drain
-Df -Df and thus from (6.62) -Df -Df ê we get W) o W)ê oê As a
result, since W) W , the drain current of M6 is given by
W) ê W
ií
i2
(6.63)
In a similar way, in the NMOS translinear loop we reach the same relationship for
VDD
M5 M9
M1
Iin
I0 M13
M6
M2 M10 vo
M7
M11
M14 RL
M3
I0
M4 M8 M12
-VSS
Figure 6.19 Class AB output stage with a translinear loop.
the drain current of M7:
W) Œ W
iï
iÑ
(6.64)
For oê =o and oŒ =oŽ , M6 and M7 will have the same bias current of
=W and therefore the total bias current in M5 and M8 is W . There are another
two complementary translinear loops at the output that are used to determine the
quiescent current of the output transistors (M13 and M14). This loop consists of
M1, M2, M10, and M13 with the following relationship among gate-source
voltages of these transistors:
-Df -Df -Df -Df Ž

(6.65)
Assuming M5 with M9, M6 with M10, M7 with M11, and M8 with M12 have the
same sizing, we can follow a similar method that is used to calculate the dc bias
current of the floating current source to reach the quiescent current in M13 and
W) Ž W
M14:
iÅÑ
iÅH2
(6.66)
The quiescent current of M13 can be easily adjusted as a multiple or fraction of W

with minimum sensitivity to PVT. The quiescent current of M14 at the output is
determined through the second translinear loop consisting of M3, M4, M11, and
M14. The procedure to reach this current is exactly the same as for M13. The
W) W
result is
iÅË
Ç iÑHË
(6.67)
In static condition (!% ) we desire to have !" so the dc currents in M13 and
M14 need to be equal, and thus from (6.66) and (6.67) we obtain
iÅÑ iÅË
iÅH2 iÑHË
(6.68)
Considering the circuit in Figure 6.20, an injection of W%Y to the source of M10
increases the M10 gate-source voltage by !R , which results in a change in ®) as
®) X0 !R (6.69)
The sum of the drain currents of M10 and M11 is a fixed current of W , so when the
ac current W%Y is injected into the source of M10, to keep the total current constant,
result, the drain current M11 reduces by :Í :Í , which means !fD is

M10 and M11 drain currents have to be changed in the opposite direction. As a
lowered by an amount of !Y and consequently the drain current of M11 is

changed by
®) X0 !Y (6.70)
Since the gate voltage of M11 is fixed, its source terminal voltage goes up by !Y .
VDD
I0
Iin
Vbp iD11
M10
iD10 Vbn
M11
I0
-VSS
Figure 6.20 Preamplifier before the output stage transistors.
Nothing that ;®) ;®)

X0 † X0 , we will have !R † !Y . This means when an ac current is
and from (6.69) and (6.70) by assuming
injected into the source of M10, the source node voltages of both M10 and M11
will change by the same amount. In other words, there is a constant voltage
between two nodes, or equivalently, sources of M10 and M11 in a dynamic state
are shorted together. Therefore the total dynamic resistance seen from these nodes
in the circuit of Figure 6.19 becomes
'K H
Ò" Ó Ò" (6.71)
Since 'K H is a large resistance, a minimum ac current injected into the source of
output transistors M13 and M14. Now we obtain an analytical relationship for ®) Ž
M10 will cause quite a large voltage change at this node or at the gate of the
in the presence of an ac input signal. We said that M1, M2, M10, and M13 form a
translinear loop described by (6.65) in which the left side has a fixed value given
by
-Df -Df ©*-e R * tÆ ¬

{
(6.72)
ÅH2
Now let the ac current W%Y be drawn from the source of M10, which reduces the
voltage of this node by Ò" Ó Ò" W%Y . Since its gate voltage is fixed, it results in
lessening !Df in such a way that for !Df ¹-e R ¹, M10 operates in the
subthreshold region where the drain current relationship is given by
Sk¡ Å ¢* £ Q *
®) WD Ÿ ¤ ‰¥
(6.73)
In which - #IR "V with #IR and "V as the MOS depletion and gate
oxide capacitances, respectively, -q¦ ‘ã ‚ is the thermal voltage, and WD is the
reverse saturation current of M10. Using (6.65), (6.72), and (6.73), we find
*-e R * *-e R *+--q¦ ™c F : Å G

% %: ÅÑ
t
{
tÆ {k ÆÅÑ
(6.74)
ÅH2
From (6.74), ®) Ž
can be found as
®) ç t --q¦ ™c F : Å Gè
ÆÅÑ { %
Ž Æ {k
(6.75)
ÅH2
Equation (6.75) indicates when ®) decreases ®) Ž

increases, and theoretically
when ®) approaches zero, ®) Ž goes to infinity! In practice, by rising ®) Ž , M13

eventually exits the saturation region and operates in the triode region and
therefore the maximum output current in M13 will be limited. As can be seen in
Figure 6.21 when M13 is at the edge of the triode, we can write:
%: ÅÑH5ˆ—
!D) Ž
!D) KUq t -## 'Z ®) ŽH0UV
ÆÅÑ
(6.76)
Solving (6.76), we can obtain ®) ŽH0UV, from which the maximum positive output
voltage swing !" 0UV 'Z ®) ŽH0UV is found as
!" 0UV -## • ° Ž 'Z -##

ÆÅÑ 8³
(6.77)
For ®) ŽH0UV, the drain current of M10 is nearly zero so that we can say almost all
the current of M9 flows through M11 (or W) † W ). We use this result to get the
drain current of M14 for ®) ŽH0UV. As mentioned before, M3, M4, M11, and M14
form a translinear loop with the following relationship:
-fD Ž -fD Ç -fD -fD Ç

(6.78)
The left side of (6.78) is equal to -e Y • W °ŽHÇ , which is fixed, and for
®) † W (when W) † , using (6.78), we can get the drain current of M14:
VDD
iD13,max
M13
vo
RL
Figure 6.21 Output stage configuration at the positive peak output swing.
©-e Y tÆ ¬ -e Y
%: ÅË
t
{ {
tÆ ÆÅË
(6.79)
ÑHË ÅÅ
After some simplifications and for o p = o p ŽHÇ ,

M14 for ®) ŽH0UV is obtained as
the drain current of
²
F G
®) “d – W
³ ÅË
Ç ²
F G
(6.80)
³ ÑHË
In a similar way when the ac current W%Y flows in the opposite direction, (i.e., it is
voltage greatly increases and !Df rises while !fD reduces, which leads M11 to
injected into the source of M10), due to the high resistance seen at this node, the
eventually go to the subthreshold and ®) approaches W . In fact the roles of M10

and M11 and also those of M13 and M14 are equally interchanged. We can follow
the same procedure, this time from (6.78), when M11 operates in the subthreshold,
we find
-e YŽ -e Y -e Y <-q¦ ™c F :ÅÅ G -e Y
% %: ÅË
t
{
tÆ {k ÆÅË
(4.81)
ÑHË
different from zero-bias condition (-e Y ). Assuming -e YŽ † -e Y , the drain

In practice, because of the body effect in M3 and M11, their threshold voltages are
current of M14 will be
®) ç t --q¦ ™c F : ÅÅGè
ÆÅË { %
Ç Æ {k
(6.82)
ÑHË
As W%Y goes up, W) reduces and ®) Ç increases until M14 reaches at the edge of
the triode region. Figure 6.22 shows the output stage when M14 is on and M13 is
off:
vo
iD14,max
M14 RL
-VSS
Figure 6.22 Output stage configuration at the negative peak output voltage.
6.5 Case Study 159
iD13
iD14
iout (mA)
IQ
I in ( µA)
Figure 6.23 Output transistor currents versus input ac current.
%: ÅËH5ˆ—
!)D Ç
!)D KUq t -KK 'Z ®) ÇH0UV
ÆÅË
(6.83)
The maximum output voltage swing in the negative direction becomes
!"/ 0UV -KK • ° Ç 'Z

ÆÅË 8³
(6.84)
By the same reasoning used to reach ®) Ç

in (6.80), we can get ®) Ž
as
²
F³G
®) Ž ²
ÅÑ
“d – W
F G
(6.85)
³ ÅH2
Figure 6.23 depicts the output transistor currents (i.e., ®) Ž

and ®) Ç ) as a function
of W%Y in a typical design.
6.5 Case Study
In this section we study an op amp with a class AB output stage in which the
quiescent current of the output devices is determined by a translinear loop. The
schematic of the circuit is depicted in Figure 6.24. The circuit is a two-stage op
amp in which a folded-cascode structure has been used as the first stage and a
CMOS common-source amplifier acts as its second stage. The capacitors $ are
used to compensate the op amp frequency response. As discussed in the previous
section, a translinear loop controls the quiescent current of the CMOS amplifier
VDD
M9 M10 M14 I0
IQ=mI0
nI0
M7 M8
I0
M18
M12 M13 Cc
- M1 M2 0.5I0 vo
vi 0.5I0
+
I0 M11 M16 Cc CL
M17
M5 M6
I0
M15
M3 M4
Figure 6.24 Op amp with a translinear loop class AB output stage.
independent of PVT. The floating current source between two wide swing diode-
connected configurations is implemented in the same way as the two transistors
M11 and M12. This current source holds a constant current while the variation of
the voltage across its transistors is negligible and thus acts as an ac shorted circuit.
Under this assumption, the small-signal equivalent circuit is obtained as illustrated
in Figure 6.25. Summing different currents flowing to the output node and also
three other nodes of 1, 2, and 3 in this circuit, we get the following equations:
=X0 !% È X0ê X"ê ½ $ ! X"ê ! ½ $ !" (6.86)
X"ê X0ê ! X"ê X" ½ ! X0 X" !Ž =X0 !% (6.87)
X" ! X" X" Ž X0 ½ $ !Ž ½ $ !" (6.88)
½ $! X0q ! ½ $ !Ž ÔÈ ½ $ Õ!" (6.89)
where È X" X"Ç , È X" Œ X" , and X0q X0 Œ X0 . In order to

reach the op amp transfer function we have to solve the equations above. Of
course such a solution is too complex and would not give much perceptible
information for design. As a result, we need to ignore some small parameters such
as output conductance of the transistors to achieve a simple transfer function. It is
evident that the obtained solution under these conditions just gives a rough
estimation of the circuit behavior but it can help to an extent to find some main
6.5 Case Study 161
Cc
gm6v1 gm11v3
1 3 Cc vo
2
+ + +
0.5gm1vi gm6v2
ro6 v2 c1 ro11 c2
v1 v3
R1 ro13 R2
- 0.5gm1vi
- -
Figure 6.25 Small-signal equivalent circuit of a two-stage class AB op amp.
transconductance for the cascode transistors as X0ê X0 X0$ and neglecting

circuit parameters that affect important op amp specifications. Assuming the same
the output conductance of all devices, we can obtain the approximate op amp
voltage gain as
Â, ÂÅ Â,
K/ K2
½
¯5Å 2¿5, 2¿5‰ ¿5,
4 K6, ÂÅ Â2 2Â, ÂÅ Â2
K K2
(6.90)
2Â, ¿5‰ 2¿5‰ ¿5,
The applied approximation cause the first dominant pole that was too small now to
move to zero and thus the dc voltage gain tends to infinity, but the second-order
term in (6.90) nevertheless gives meaningful information about the position of
some other nondominant poles and also zero locations in the s-plane. Comparing
ö½ ø½ Ô ½ L g ½ L Õ, we notice that the circuit has two real

the second-order term in (6.90) with the general form of
zeros and two generally complex poles if g =H a condition that is usually
(6.90) equal to zero, we get the zeros and the values of natural frequency L and
satisfied in such an architecture [7]. Putting the numerator and denominator of
quality factor g of the circuit as
¿5,
LÞ = >Á ?
¯5‰ Â,
H 6Å
¿5‰ (6.91)
ÂÅ
L
¯5‰ ¯5,
t 6Å 62
(6.92)
¿5‰
g Á 2¿5,
6, Â
Å
62 6,
(6.93)
Â2
One zero places on the left-half plane with the approximate value of
jω
ω0 s-plane
ω0
- 2Q
σ
ωz1 ωp1 0 ωz2
Figure 6.26 Pole-zero locations of a two-stage op amp.
LÞ X0$ $ and the other one is much far away on the right-half plane with
the approximate value of LÞ X0q X0$ $ . The pole and zero locations
with adequate bandwidth, the natural frequency L should be large enough that
including the dominant pole are shown in Figure 6.26. For the design of an op amp
according to (6.92) it entails both fractions X0q and X0$ are adequately
large. If the ratio of these fractions is made large it results in increasing the quality
factor, which causes peaking in the frequency domain. This effect can drastically
deteriorate the op amp phase margin. Of course for a certain extent of load
capacitance , it is possible to lower the coefficient of the radical sign in (6.93)
by taking small compensation capacitance $ compared to . In addition, a small
$ also helps to improve the bandwidth though it decreases the phase margin as
well so that the reduction of $ is possible as long as the minimum required phase
margin is provided. As is evident from (6.92), a large X0q
L that is required to make sure there is adequate stability in a wide bandwidth
allows for a large
op amp. As discussed in the previous section, the quiescent currents of the output
devices are determined by a translinear loop as
²
F G
W) W
³ Åï
ŒH ²
F G
(6.94a)
³ ÅéHÅí
²
F³G
W) H ²
Å
W
F G
(6.94b)
³ ÅÑHÅË
It is interesting to note that we cannot increase X0q by increasing the output

6.5 Case Study 163
transistor aspect ratios or equivalently increasing the channel width for a particular
channel length. This is because the capacitance mainly consists of the gate
sizing. Assuming both output devices are identical with o Co Œ

capacitances of the output transistors, which increase by raising the transistors’
(for hY ChR ), we have
²
Žt ÃÄ6 —F G {:ÅïH
¯5‰ ³ Åï
6Å ÇiÅï ZÅï 6 —
(6.95)
Substituting (6.94a) into (6.95) and taking the same channel length of p for all
devices, we have
2þÄ Ê
t²
¯5‰ Ž ÅéHÅí
6Å Ç Z•6 —
(6.96)
high X0q
From (6.96) we notice that for a certain channel length the only way to obtain a
is to increase the current density of the diode-connected MOS
devices, including M15-M16 and M13-M14 in the translinear loops for NMOS
and PMOS types, respectively. A high aspect ratio for the output devices is
important to provide enough current drive capability in the heavy load condition.
Design Example
shown in Figure 6.24. In our design we need to have at least = _ à of bandwidth

We plan to design an op amp in a 0.25-\Š CMOS technology with the structure
and a < › phase margin. Since an op amp consists of two cascaded stages
including a folded-cascode and a CMOS amplifier, it is predictable that its dc
µ and 'Z
voltage gain will be noticeably high. Our op amp will be able to drive a parallel
capacitive and resistive load of Z
the maximum output voltage swing is !"HRR =[. For 'Z
, respectively, while
, with this
peak of ®)H0UV B = Š¶ and thus their sizes are determined based on this current
peak of output voltage the output transistors should be able to provide a current
!)DHKUq B[ Of course, it does not mean that the output of the op amp when
level. In order to achieve a reasonable aspect ratio for these devices, we choose
than B[. This is because when one output device enters the triode region, owing
used as a voltage follower cannot follow the input voltage variations less
to the large voltage gain provided by the first stage, the total open-loop gain still
distortion level. From !)DHKUq • ®)H0UV °Y B[ and for hY "V

remains rather high and thus the negative feedback is able to minimize the
= \¶ [ , we obtain o p Y C< from which the size of o p Y B is
achieve the required X0q

chosen. According to (6.96), choosing the minimum channel length helps to
with minimum power dissipation but there is another
important issue that needs to be considered. In order for the translinear loop to
VDD=2.5V
M22 15/0.35 15/0.35

M11 M23 M26
15/0.35
60/0.35 25/1
M7
5/1 M5 M29
5/1
M10 M20 15/0.35 0.6 pF
Cc
3/1 M3 M21
60/0.35 15/0.35
I0 180/0.35
Ib 7.5/0.35 M31
M19 7.5/0.35 15/0.35
20/0.5 M17 M25 C=1 µF
4 µA - M8 M9 0.5I0 vo
vi 0.5I0
+ M18
M16 M28 60/0.35 CL RL
2.5/0.35 100 Ω
2.5/0.35 5/0.35
M30
20 pF
5/0.35
5/0.35
0.5/1.5 M14 Cc
M6 M15
0.6 pF
M2 M4 25/1
5/1 M1 M24
5/1 5/1 15/0.35
15/0.35 5/0.35
M12 M13 M27
Figure 6.27 A designed two-stage class AB op amp.
work properly, it is required that all MOS devices in the loop operate in saturation
with the square law relationship for their drain currents. Holding the square law to
some extent can be met by taking the channel length a little bit more than the
we choose pY C= \Š and thus the width of the NMOS output device becomes
minimum permissible device channel length that is forced by the technology. Here
oY < \Š. If the quiescent current of the output devices is made too small it is
aspect ratio. The ratio of W) o p Y for an NMOS device should be made

quite possible that they will operate in the subthreshold region due to their large
adequately larger than the term of hY "V --q¦ in order to make sure that the
about < \¶ and thus for o p Y B the static drain current needs to be
device remains in saturation. The value of this term in the given technology is
sufficiently greater than B ‹ < \¶ \¶. A static drain current of

W) T \¶ can meet this requirement quite well. This quiescent current is
about 3% of the full load current. By choosing the current of W \¶ for the
be greater than that of these diode-connected devices by the factor of &

bias current of the diode-connected devices, the sizing of the output devices should
order to achieve W) T \¶. All these measures result in achieving a rather

in
large value for X0q and thus the required X0$ for a particular L would be
small. This means that X0$ can be made rather small with a low bias current in the
cascode transistors that aids in saving the power consumption and increases the
output resistances that in turn help to increase the dc voltage gain of the folded-
obtained based on the required bandwidth from LM X0

cascode stage. The transconductance of the differential pair in the first stage is
$ . The schematic
of the designed circuit including the bias circuit and all device sizing in microns is
shown in Figure 6.27
µ and without the load resistor give the dc voltage gain of 4 A= >?,
The results obtained from simulation in the presence of the load capacitance
Z
the bandwidth of $o = T _ à, and the phase margin of N& < ›. The total
6.5 Case Study 165
− C=1 µF
vo
+ CL
Vp=0.75V RL
Vdc=1 V 20 pF 100 Ω
fin=1 MHz
Figure 6.28 Voltage-follower test circuit.
= Š . Then the op amp is used as a voltage

follower with a parallel resistance of 'Z
static power dissipation is
across Z , as shown in Figure
6.28. A sinusoidal input voltage with the peak value of -R B=[, -#$ [, and
%Y _ à is applied to the circuit. The input and output waveforms and the
harmonic distortion (THD) of the output voltage is about CC- and the power
currents of two output MOS devices are depicted in Figure 6.29. The total
efficiency at full load is T - .
2
input voltage
output voltage
Voltage (V)
−1
0 0.5 1 1.5 2 2.5 3 3.5 4
Time (us)
8
iD30
6 iD31
Current (mA)
0
0 0.5 1 1.5 2 2.5 3 3.5 4
Time (us)
Figure 6.29 (a) Input and output waveforms. (b) Currents of output devices.
6.6 Conclusion
In this chapter, some topics in conjunction with CMOS output stages have been
studied. Several of the most common structures normally employed as output
stages were introduced. Such circuits should be able to provide high levels of
current and voltage across the load and thus linearity and power efficiency are two
significant parameters that should be taken into account in the design of such
circuits. This entails choosing large enough sizes for the devices used in these
stages to properly drive the heavy loads. In a class AB power amplifier utilized as
an output stage, it is important that the quiescent current of the stage is accurately
controlled and made fixed against process, voltage, and temperature variations.
Several architectures of class AB amplifiers in terms of quiescent current stability
and also the capability to work in low-voltage designs were studied and at the end
one design example was presented and analyzed in detail.
References
[1] Salivahanan, S., Linear Integrated Circuits, McGraw-Hill, 2008.

[2] Tasic, A., Serdijn W. A., Setti G., Circuits and Systems for Future Generations of Wireless
Communications, Springer, 2009.
[3] Gray, P. R., Hurst, P. J., Lewis, S. H., and Meyer, R. G., Analysis and Design of Analog
[4] You F., et al., “Low-Voltage Class AB Buffers with Quiescent Current Control,” IEEE Journal of
Solid State Circuits, Vol. 33, No. 6, 1998, pp. 915-920.
[5] Hogervorst, R., et al., “A Compact Power-Efficient 3 V CMOS Rail-to-Rail Input/Output
Operational Amplifier for VLSI Cell Libraries,” IEEE J. Solid-State Circuits, Vol. 29, No. 12,
1994, pp. 1505-1513.
[6] Seevinck, E., Vittoz, E. A., du Plessi, M., Joubert, T. H., and Beetge, W., “CMOS Translinear
Circuits for Minimum Supply Voltage,” IEEE Trans. Circuits Syst. II, Vol. 47, No. 12, 2000, pp.
1560–1564.
[7] Ribner, D. B., and Copeland, M. A., “Design Techniques for Cascoded CMOS Op amps with
Improved PSRR and Common-Mode Input Range,” IEEE J. Solid-State Circuits, Vol. 19, No. 6,
1984, pp. 919-925.
Chapter 7
CMOS Reference Generators
Voltage and current reference generators are integral parts in most analog circuits.
They should have minimum sensitivity to PVTs. For instance, in analog amplifiers
a single master current source usually provides the current for biasing of devices.
Furthermore, there are many different current sources that operate as active loads
in amplifiers whose currents are supplied by this single master current reference
generator. This master current is supposed to be nearly independent of PVTs. Data
converter is another category in which a fixed voltage or current as a reference
signal is demanded. In radio frequency applications some sensitive blocks like
voltage-controlled oscillator, should sometimes be supplied by a separate
reference voltage to alleviate the effect of power supply noise on their
performance.
In this chapter, several special architectures of CMOS voltage and current
reference circuits are analyzed. Some of these circuits are different from typical
circuits in terms of low operating voltage or capability to be implemented as a
fully integrated circuit without using resistors in a submicron CMOS technology.
7.1 CMOS Voltage Reference Generators
The voltage reference generator is actually a circuit with dc voltage output. In the
design of this circuit we attempt to keep the output voltage stable against the
variation in different parameters such as supply voltage and temperature. In the
design of an integrated reference voltage another important issue is to have an
output voltage independent of process parameters. One of the most popular
methods to establish such a voltage is based on using bandgap voltage. We will
study this technique along with the practical CMOS circuits to realize this type of
voltage.
167
168 CMOS Reference Generators
7.1.1 Bandgap Voltage Reference Generator
The basic building block in any reference circuit is the bandgap reference circuit
whose principal theory is well studied in different relevant documents [1-3]. The
main idea behind a bandgap circuit is to combine two voltages with opposite
temperature coefficients (TCs). By proper weighting it is possible to get a near-
zero TC output voltage. The comparison between MOS and bipolar junction
parameters like -q¦ (thermal voltage) and base-emitter junction voltage (-•E are
transistor (BJT) devices in semiconductor technology shows that some BJT
much more insensitive to process variations. In a bandgap circuit two voltage

components with opposite TCs are produced by using BJTs in order to minimize
the effect of process changes. A typical bandgap circuit that is usually used in
most designs is shown in Figure 7.1.
Assuming an exponential relationship between the collector current and the
base emitter voltage and supposing M1, M2, and M4 have the same size, we can
easily prove that the reference output voltage is obtained from
-.I -E•Ž ™c • -q¦

82
8Å
(7.1)
In practice, due to the offset voltage of the operational amplifier, -.I is given by
-.I -E•Ž Ô™c • -q¦ -"K Õ

82
8Å
(7.2)
VDD
M1 M2
M3 M4
Ibias
Vref
- +
R2
R1
A nA nA
Q1 Q2 Q3
Figure 7.1 Typical bandgap voltage reference circuit.

The op amp input offset voltage might be comparable to the term of ™c • -q¦ . It
thus would be quite possible that the op amp offset voltage and its drift with
temperature directly affects the reference output voltage. To lessen the effect of
large with respect to -"K . Figure 7.2 shows a circuit that realizes this idea by
offset voltage the first term inside the square brackets in (7.2) needs to be made
voltage is modeled by the series source voltage of -"K . Equating the voltages of the
increasing the mentioned term by a factor of two. In Figure 7.2 the op amp offset
op amp inputs, we have
-"K -E• -E• ' W -E•Ç -E•Ž (7.3)
Supposing that the same current flows through M1 to M4, we can obtain the
output voltage as
-"Mq -E• F G Ô -q¦ ™c • -"K Õ
82
"Y 8Å
(7.4)
where it is assumed that -E• -E• -E• "Y . All BJTs in the circuit are vertical
PNP transistors whose current gains ° are normally low. In the absence of
transistors M5 to M8 and Q5, the emitter current of Q1 (Q3) is the sum of the
drain current of M3 (M4) and the base current of Q2 (Q4), which is different from
that of Q2 (Q4) so that the base-emitter junction voltages in Q1 and Q2 (Q3 and
VDD
M3 M1 M2
M5 M4
Vout
+ R2
-
+
−
VOS I
R1
Q5 Q2
A
Q1 Q4
A nA
Q3
nA
M6 M7 M8
Figure 7.2 Modified bandgap voltage reference to reduce the op amp offset voltage effect.
and Q5 are added to the circuit. Let Q5 have the same ° as other BJTs. As a result,
Q4) would not be exactly the same. To eliminate this error the devices M5 to M8
its terminal base current will be equal to that of Q2 and Q4. This current by the
current mirrors M6-M7 and M6-M8 is taken out from the emitters of Q1 and Q3.
The amount of the drawn currents from the emitters of Q1 and Q3 is equal to what
is added to them by the base currents of Q2 and Q4 so that the assumption of
having equal emitter-base junction voltages for Q1 and Q2 (Q3 and Q4) should be
accurate.
Design Example
A bandgap voltage reference is to be designed in a 0.25- m CMOS technology.
First of all we should choose an appropriate value for • that is defined as the
The adopted architecture is shown in Figure 7.3.
emitter area’s ratio of Q1 and Q2. The larger the • is chosen, the lesser sensitivity
to the op amp offset voltage is achievable. This is because the term of -q¦ ™c • in
(7.2) becomes greater than -"K . To compromise the occupied chip area and for the
sake of simple and symmetrical layout for BJTs we choose • T. By equating the
' '
derivative of (7.1) with respect to temperature to zero, we can obtain the ratio of
z4 rs
™c •
z4@¨Ñ ˜ 82
ze ze J 8Å
(7.5)
where ‘ is the Boltzmann’s constant and ‚ is the electron charge with

‘ ‚ A< Š[ A . Here ' ' is surmised to be independent of T that is true
proved by setting the derivative of ' ' with respect to ã to zero

if both resistors have the same temperature coefficients. This statement can be
VDD=2.5V
Ms5 M3 M1 M2
Ms6 M4
5/0.5 5/0.5 5/1 10/1 10/1 10/1
Ms3 Vref
1/5 Ibias
- +
a b
R1 R2
Ms4 Ms2
Ms1
5/0.25 10/0.25
5/0.25
A n=4 nA nA
Q1 A=5X5 Q2 Q3
Figure 7.3 A designed bandgap voltage reference.

F 2G F G
z 8 82 z82 z8Å
ze 8Å 8Å 82 ze 8Å ze
(7.6)
for R1 and R2 from his/her technology file. Typical value for ·-E•Ž ·ã is about
To meet the above condition the designer should choose the same type of resistors
B Š[ A. This figure is obtained by a simple dc sweep simulation over

temperature for a BJT with shorted collector-base terminals whose collector
quantities we get ' ' T T. Resistance R1 can be derived based on the

current is supplied by a dc current source. Solving (7.5) with the mentioned
chosen current for M2 (or Q2). For example, if we choose W) \¶ we have

' -q¦ ™c • W) C < œ and thus ' = A œ . As it is clear from
Figure 7.3, the op amp bias current is provided by the bandgap circuit itself. This
makes the role of a startup circuit more crucial because at the beginning the bias
current is insufficient to run the op amp with adequate voltage gain. Transistors
Ms1 to Ms6 form the startup circuit. At start time if the current of the main core of
the bandgap (i.e., the drain current of M1 or M2) is low, the voltage of the node
marked as <a> is low and then Ms1 is off, and Ms3 as a simple resistor provides
the bias current for the current mirror Ms2-Ms4. This current through the second
current mirror Ms5-Ms6 supplies the initial required op amp bias current. After the
circuit starts the voltage of node <a> rises, which turns on Ms1 and causes Ms1 to
enter the triode region that turns Ms2 off, and thus the startup circuit is disabled.
An important point that needs to be considered in checking the performance of the
startup circuit is that it should be tested by performing a transient analysis by
applying a step voltage with a relatively long rise time as the power supply
voltage. This point is important because most of the time a designer is enticed
when he or she thinks that the startup circuit functions properly by performing a dc
sweep simulation over the supply voltage and gets an acceptable response while it
is not the case. Even transient simulation with a fast rise time step for supply
voltage is not a reliable test method for checking the performance of the startup
circuit, because in this condition small parasitic capacitances in the circuit can
establish a path to inject the needed current to start the circuit while for long rise
time it would not be able to do this. In Figure 7.3 the gate capacitance of all PMOS
devices at the output of the op amp appear as the load capacitance of the op amp.
This capacitance should be considered in selecting the appropriate op amp
architecture. For instance a two-stage op amp can provide a rather large dc voltage
gain but the op amp stability can be degraded depending on the size of the PMOS
transistors M1 to M4. For example, when the capacitance seen at the op amp
output is increased, its second pole is reduced and as a result the op amp stability
degrades. In certain circumstances it may even causes instability in the bandgap
circuit. Here the folded-cascode architecture with a PMOS input differential pair
can be a good candidate, because more load capacitance at the output of such an
op amp helps to make it more stable. In addition, PMOS devices have one order of
magnitude less input-referred flicker noise voltage compared to their NMOS
counterparts. The schematic of the op amp and the sizing of its transistors are
VDD=2.5V
M4 M5
Mb7 5/0.5 5/0.5 Mb9
5/0.5 5/0.5
M6
M7
5/0.5
Mb5 5/0.5
2/1
vo
Mb3 M3
5/0.5 10/0.5
IPTAT M2
v i+ v i- Mb8
M1 10/0.25
M8 1/1
10/0.25 M9
10/1
10/1
Mb2 Mb4 Mb6

Mb1 M11
5/0.5 M10
5/0.5 5/0.5 5/0.5 20/1
20/1
Figure 7.4 A designed folded-cascode op amp.
depicted in Figure 7.4.

Circuit simulation using polysilicon resistors from the technology shows that
the output voltage will have minimum variation with respect to temperature if the
' ' < we have ' << œ and ' T TB œ . Figure 7.5 shows the
resistances R1 and R2 are modified a little bit. With a resistance ratio of
plot of the reference voltage versus temperature. From this plot the temperature
coefficient of the circuit is given by
4 rs5ˆ—/4 rs5 Ä
ã ( B<‹ /ê
A
4 rs e5ˆ—/e5 Ä
(7.7)
B < Š A while -.I ==[.

Thus the temperature coefficient of the designed bandgap voltage reference is
Vref
1.58 mV
1.254V
T(oC)
-40 +125
Figure 7.5 Bandgap reference voltage versus temperature.
7.1.2 Low-Voltage Bandgap Reference Generator
-.I -•E }-q¦ , the K value for which the temperature coefficient of -.I
In the bandgap voltage circuit studied in the previous section for
becomes zero generates a reference voltage around 1.25V. On the other hand, in
low-voltage application we usually need to have a stable reference voltage against
process, temperature, and supply with the value of usually below one volt. One
method to get such a stable voltage is to use a conventional bandgap reference
voltage with the output of 1.25V and then use a simple resistive divider to lower
this voltage to the desirable level. This action has two drawbacks. First, we
generally require a buffer at the output of the divider, and secondly and more
importantly, we would require a main supply voltage greater than 1.25V to
generate such voltage. This is not appropriate and sometimes not feasible in a low-
voltage circuit. One solution is that before adding two voltages with opposite
temperature coefficients, we first convert each voltage to its equivalent current and
then add two currents with proper coefficients. At the end the resultant current is
sent to a proper resistor to convert it to the desired output voltage. One sample
circuit that carries out this job is shown in Figure 7.6 [4]. In this circuit the inputs
of the op amp are normally low and using a PMOS differential pair at the op amp
input is preferable. In this circuit we can write
-U -„ -E• (7.8)
VDD
M1 M2
M3 M4
I Vref
Ibias
Va Vb
- +
I2 R3
R1a I1 R1a
R2
+ R1b R1b +
VEB1 VEB2
- -
A nA
Q1 Q2
Figure 7.6 Low-voltage bandgap reference voltage.

W
4y
8Åˆ 8Åy
(7.9)
W
4y /4@¨2
82
(7.10)
By defining ' U ' „ ' and using (7.8), since -E• -E• -q¦ ™c • we
have
W W W
4@¨Å 4‰¥ BC Y
8Å 82
(7.11)
-.I 'Ž W - -q¦ ™c c

8Ñ 8Ñ
8Å E• 82
(7.12)
It is clear from (7.12) that the reference output voltage -.I consists of two terms
with opposite temperature coefficients. It is possible to achieve our desirable
of 'Ž ' and 'Ž ' ™c • . The supply voltage of this circuit can be as low as
output voltage with near-zero variation with temperature by appropriate selection
-E• -)DHKUq H provided that the op amp can operate correctly at this level of
supply voltage.
Design Example
In this section we intend to design a bandgap voltage reference of -.I =[ in a

0.25- m CMOS technology. First, by a simple simulation we determine the
derivative of -.I in (7.12) with respect to temperature to zero, we obtain the

temperature coefficient of BJTs as described previously. Then, by setting the
following relationship that can be used to calculate the resistance ratio of ' '
™c •
8Ñ z4@¨Å 8Ñ ˜
82 ze 82 J
(7.13)
Assuming ·-E• ·ã B= Š[ D E, from (7.13) we get ' ' <A. W is
by the resistors. Here for • T, by choosing W \¶ we have ' =C œ

chosen based on compromise between power consumption and occupied chip area
and ' C < œ . By substituting these values into (7.12) for -.I =[
resistance 'Ž ; œ obtained. R1, R2, and R3 are realized by the polysilicon
in the given process with the sheet resistance of A ]F In order to reduce the
at \Š. Figure 7.7 shows the output voltage over the temperature range from
width tolerance effect in resistors, minimum width of all resistances is chosen
A to = A for the supply voltage of -)) [.
ã ( = T Š A. By increasing the BJT emitter areas the emitter-base voltage

From this curve we can obtain the circuit temperature coefficient as
for a specific collector current is lowered, which makes it possible for the circuit to
Vref
499.65 mV
0.39 mV
499.7 mV
499.55 mV
T(oC)
-20 27 +125
Figure 7.7 Low-voltage bandgap reference voltage variation versus temperature.
work with a lower supply voltage.

The same result can be attained by reducing the current level and using higher
resistance without needing to increase the BJT areas. A folded-cascode
architecture with PMOS input transistors has been used for the op amp in this
circuit. It is a good idea to use a cascode structure instead of M1 to M4 to make
7.6 if the input offset voltage of the op amp, -ÎD , is considered it can be shown
the output less sensitive to the supply voltage variations. In the circuit of Figure
that an extra term of Ô 'Ž ' 'U '„ 'Ž ' „ Õ-ÎD is added to -.I
in (7.12). For ' U CB œ and ' „ = ; œ and other given values this adds
T-ÎD to -.I . Since -.I is small this shows that the amount of op amp offset
Š[ adds a random
voltage with the average of T Š[ to -.I = Š[ that causes large random
voltage here is critical. As an example, an offset voltage of
variations in the reference voltage. Moreover, it causes the output reference

voltage to follow the offset voltage variation with temperature. As a result in a
low-voltage bandgap circuit when the op amp offset voltage is noticeable, the
output reference voltage is neither stable against the process variations nor
insensitive with respect to the temperature variations. This happens even though
we have used BJTs for stability against process and added two currents with
equally opposite temperature coefficients to get a low TC. It is interesting that just
the op amp offset voltage is responsible for this deficiency. Therefore the op amp
employed in this circuit should be carefully designed in terms of minimum
possible input-referred offset voltage. For example, the gate area of the input
transistors should be made adequately large and paid special attention to do a full
symmetrical layout for the input devices of the op amp by using the common
centroid techniques as discussed in detail in Chapter 3.
7.1.3 CMOS Voltage Reference Generator without Resistors
resistor is to convert the emitter-base voltage -•E and PTAT voltage }-q¦ to
Resistors are used in all previously studied bandgap circuits. The role of the
current. The currents after being added together flow through another resistor to
produce the reference output voltage. In all relationships for such circuits, the
resistance appears as a ratio of two resistances, and as long as this ratio is kept
unchanged with respect to temperature and voltage variations, the absolute
variation of resistance has no significant effect on the reference output voltage.
The nonsilicide polysilicon type resistor is the most popular resistor that is usually
used when we have access to a mixed-mode CMOS technology. Under certain
circumstances a designer may have to work with a digital CMOS process without
access to such a resistor. In this condition a bandgap structure that does not require
any resistors can be more applicable. One example of this type of bandgap circuit
is depicted in Figure 7.8 [5]. Diodes D1 and D2 are implemented by tying the
drain, source, and gate of a PMOS transistor together to form the anode with its
substrate terminal used as cathode, as shown in Figure 7.9. Two differential pairs
of M1-M2 and M3-M4 have an unbalanced sizing by a factor of B. We will return
to the reason for that unbalanced sizing later but now we assume the two pairs are
balanced, and based on this assumption we write the drain current of M4 (M6) as
W)Ç •°W t W)ê

{ Æ 34: 2 34:
Ç{
(7.14)
VDD
ID I0 10ID GI0
AW/L ABW/L
W/L BW/L
M3 M4 M2 M1
+ +
Vout
VD1 D1 D2 VD2
- -
M6 M5
1 : G
Figure 7.8 Bandgap reference without a resistor.

K A
n+ P+ P+
n-well
P-substrate
K
Figure 7.9 PMOS transistor used to realize a diode.
where ° hR "V o p and 3-) -) -) . The M1 drain current is provided

by M4 through the current mirror M5-M6 with the current gain of G
W) È W)ê È•°W t
f{ Æ 34: 2 34:
Ç{
(7.15)
If -%# -"Mq -) designates the difference in voltage at the input of the M1-M2
differential pair, W) is given by
Æ4 2+ 4 +
W) t ÈW t
f{ Æ
Çf {
(7.16)
Since W) W) , from (7.15) and (7.16) we have -%# dÈ 3-) and therefore the
output voltage becomes
-"Mq -) dÈ 3-) (7.17)
Equation (7.17) is similar to (7.1) in which the coefficient of the proportional to

absolute temperature (PTAT) voltage is realized by two gain factors of G and A.
Now we deal with the reason for using unbalanced differential pairs in Figure
[ for a near-zero temperature

7.8. Equation (7.17) proves that this circuit acts like a conventional bandgap
coefficient so that assuming -) <[, the difference in voltage at the input of

circuit with the output voltage of about
differential pair M1-M2 is about <[. In order for both M1 and M2 to conduct
voltage -Df Ì-eR Ì . By using unbalanced input transistors in the differential pair
with this level of input difference voltage, they need to have a high effective
of M1-M2 and also M3-M4, an intentional offset voltage is created at their inputs.
Thus the required effective voltage is reduced by the amount of the added offset
voltage. To clarify the matter, we now calculate the added offset voltage owing to
the unbalancing. For the unbalanced differential pair shown in Figure 7.10, since
-Df -Df , we can write

{:Å {:2
² ²
F G F G
(7.18)
³ Å ³ 2
Because W) W) Wq , we will have
W) Wq
•
•
(7.19)
W) Wq
•
(7.20)
voltage of -ÎD to the input. In the circuit of Figure 7.11, for -%# -ÎD we have
In Figure 7.10 in order to balance the drain currents we have to apply an offset
W) W) Wq and thus
-ÎD -Df -Df (7.21)
currents, from (7.21) the equivalent input offset voltage -ÎD is given by
If it is assumed that the square law relationship is held for the M1 and M2 drain
-ÎD
{‰
tÆ d•
(7.22)
2
Thus when the size of one transistor in a differential pair is B time of the other
one, it is equivalent to having an ideal differential pair (balanced) with an offset
-ÎD is subtracted from the applied input differential voltage.

voltage source series with its input. In the circuit of Figure 7.12 the offset voltage
VDD
It
W/L BW/L
M2 M1
iD2 iD1
Vcm
Figure 7.10 Unbalanced PMOS differential pair.
VDD
It
VSG2 + +
VSG1
- W/L BW/L -
M2 M1
+ VOS
iD2 iD1 -
+ Vcm
-
Figure 7.11 Unbalanced PMOS differential pair with balancing input offset voltage.
Illustrated in Figure 7.13 is the complete circuit of the bandgap voltage
È < and $ T. The bias current of D2 is mainly provided by the current

reference without resistor including the startup circuit. For this circuit we have
mirror M8-M12. By choosing a large aspect ratio and low current level for diode-
connected M11, its gate-source voltage can be approximated by its threshold
voltage. For the loop consisting of D1, D2, M7, and M11, we have
-fDŒ -) -fD -) (7.23)
VDD VDD
It It
VOS
W/L BW/L W/L W/L
+
-
M2 M1 M2 M1
Figure 7.12 Unbalanced PMOS differential pair and its symmetric equivalent with input offset voltage.
VDD
Ms1 M8
M9 M10 M13
M12
Ms5 ID7
Ms2
M7 M11
+ +
Ms3 VGS11
VGS7
- -
M3 M4 M2 M1
+ +
Vout
Ms4 VD1 D1 VD2
D2
- -
M6 M5
Figure 7.13 Complete CMOS bandgap voltage reference without resistor.
W)Œ 3-)
Æï
(7.24)
where 3-) -) -) . The tail currents of two differential pairs M1-M2 and
M3-M4 are provided through W)Œ by using the current mirrors of M8-M9 and
M8-M13. Ms1 to Ms5 constitute the startup circuit. At the beginning the source
M11 raises the voltage of this node. When these transistors conduct, W)Œ flows
voltage of Ms5 is low so it conducts and by injecting current to the gate of M7 and
through the diode-connected M8 and thus current flows to the diode-connected

M11 through the current mirror M8-M10. The current of M10 raises the gate
voltage of M11, which causes Ms5 to ultimately turn off in stable condition. When
Ms5 is off the startup circuit is isolated from the rest of the circuit.
7.2 CMOS Current Reference Generators
Current reference is employed in many different analog blocks such as amplifiers

and data converters. In analog circuits we usually need a reference current
generator known as a master bias current from which all required dc currents are
made by using different current mirrors. This section deals with the circuits that
I1=Iref
I2
M1 M2
+ +
VGS1 VGS2
- -
Figure 7.14 Simple current mirror circuit.
are commonly used to realize such a master current source.

In a simple current mirror circuit from a predefined current reference and by
adjusting the size ratio, one copy of this current is duplicated in another transistor,
If M1 and M2 are identical we have W W.I . Now there is one important

as exhibited in Figure 7.14.
question: From scratch, how we can provide the reference current W.I from which
other currents are to be produced? The first way that may come to mind is to place
a PMOS current mirror circuit on top of the NMOS current mirror, as depicted in
Figure 7.15.
is ignored we would have only one equation, W W , and therefore we have an

In this circuit, if the channel length modulation effect in the MOS transistors
unlimited number of solutions including zero for the circuit. Indeed, two NMOS
and PMOS current mirrors form a closed-loop feedback. When the transistor
channel modulation effect is considered, it can be shown that this feedback is a
positive one at the beginning. To prove this statement we calculate the circuit
open-loop gain with the aid of Figure 7.16. Although both NMOS and PMOS
channel modulation effect yields different current gains ¾Y and ¾R as follows:

current mirrors are assumed to have the size ratio of unity but considering the
VDD
1 : 1
M3 M4
I1 I2
M1 M2
1 : 1
Figure 7.15 Twin-loop current mirror circuit.

VDD
αp : 1
M3 M4
Iin
I2
Iout
M1 M2
1 : αn
Figure 7.16 Open-loop current mirror circuits.
¾Y
{ x‰ ðÄ 4:k2
{2 ðÄ 4:kÅ
(7.25)
¾R
{2 ðQ 4k:Ñ
{Ä ðQ 4k:Ë
(7.26)
where -D)Ž -## -fD , -DfÇ -D)Ç , and -fD -)D . At the beginning,
PMOS and NMOS transistors are small and -)D -)D , -D)Ž -D)Ç , and
because of low-level currents in the circuit the gate-source voltages for both
therefore both ¾Y and ¾R are greater than one. Consequently, the loop gain
Z ¾Y ¾R is greater than unity. The positive-feedback loop raises the loop initial
current in a regenerative manner. By increasing the drain currents the gate-source
voltages increase, which results in dropping of the drain-source voltages in both
¾Y and ¾R are decreased and therefore Z is reduced. When the loop gain Z
NMOS and PMOS devices. By reducing NMOS and PMOS drain-source voltages
approaches unity, the loop reaches its steady state with a certain limited current. In
practice the drain current changes as a function of all terminal voltages, and
particularly for a short-channel case exact prediction of this current is simply not
possible. However, it is apparent that transistors with a larger size and also a
higher supply voltage cause the circuit to reach its steady state at higher current
level.
7.2.1 Gm-Constant Circuit
As proved in the previous section for a twin-loop current mirror circuit, the current
level at which a circuit reaches its steady state is not accurately predictable.
Adding a series resistance in the source of one of the PMOS or NMOS current
mirrors can reduce the loop gain to a value less than unity and solve the
VDD
1 : 1
M3 M4
I1 I2
M1 M2
+ +
VGS1 VGS2
- -
R
Figure 7.17 Added series resistor in a twin-loop current mirror circuit.
uncertainty in the current level caused by the instability problem. In Figure 7.17 a
series resistor is added to the NMOS current mirror. In this circuit we can write
-fD -fD 'W (7.27)
Assuming the square law relationship is held for the M1 and M2 drain currents,
from (7.27) we have
-e -e 'W
{Å {2
tÆ tÆ (7.28)
Å 2
Supposing -e -e , we obtain
W ©'W tÆ ¬
ÆÅ 2 {
(7.29)
2
The PMOS current mirror M3-M4 forces W and W to be equal so that the circuit
equilibrium point will be the intersection of the curve of W W given by
(7.29) and the bisector of the first quadrant of the W GW Cartesian coordinate
system, as plotted in Figure 7.18. The circuit has two different stable points, one of
which is placed on the origin. Obviously this is an undesirable point for the circuit
to transfer the circuit to the second desirable stable point with the current of W . By
to be placed. To avoid such a condition the circuit needs a startup circuit that helps
I1
I1=f(I2)
I0
I1
I2 =
I2
0 I0
Figure 7.18 Equilibrium points of a twin-loop current mirror with a series resistor.
substituting W W W into (7.29), the circuit current is given by
W F G
ÆÅ 8 2 d‡
(7.30)
where } o p o p and ° hY "V o p . The current W is

independent of the threshold voltage and the main process parameter that affects W
is the gate oxide thickness. The current W changes with temperature because
carrier mobility in ° is dependent on temperature as ã / . The supply voltage
affects W if the channel length modulation for the transistors is taken into account.
In practice, the threshold voltage of M2 is greater than that of M1 due to the body
effect in an n-well process. This can cause an extra error. To eliminate this error
the source degenerative resistor can be added to the source of the PMOS current
mirror, as depicted in Figure 7.19.
VDD
R
+ +
VSG3 VSG4
- -
M3 M4
I0
M1 M2
1 : 1
Figure 7.19 Twin-loop current mirror with a source degenerative resistor in a PMOS current mirror.
VDD
1 : 1
M3 M4
I1
I2
M1 M2
+ +
VGS1 VGS2
- -
Figure 7.20 Another structure for the current reference-eliminating body effect.
prove that the same relationship is applied for W . Now let an MOS transistor be
Another option is to use the circuit of Figure 7.20. By simple analysis we can
relationship of X0 • ° W , by replacing W with (7.30) we obtain

biased by the current generated from this kind of current reference. In the
X0
8 d‡
(7.31)
Here X0 is nearly independent of biasing current or process parameters, hence this
is taken into account (| Ö ) supply variation can change the reference current
kind of current reference is also known as a gm-constant circuit. When body effect
effect is to choose M3 and M4 with a long channel length to lower |. Another way
through the limited drain-source resistance of M3. One approach to reduce this
is to use an op amp to force M3 and M4 to have equal drain-source voltages, as
VDD
M3 M4
- +
R
I0
M1 M2
Figure 7.21 Gm-constant circuit using an op amp.

illustrated in Figure 7.21. This circuit consists of two different positive- and
negative-feedback loops. The op amp and the common-source stage amplifier
formed by M2 and M4 constitute the negative-feedback loop and the other one
similarly formed through M1 and M3 except that the open loop voltage gain of the
latter is much lower than that of the first one. Therefore the negative feedback is
stronger and it guarantees the stable operation of the circuit. The gm-constant
of the presence of the carrier mobility parameter h, which changes with

circuit has two main drawbacks. First, its current depends on temperature because
temperature as h ã h ã ã / . Second, it depends inversely on the square

of resistance. Thus the current of W can change greatly in a given process due to
the large absolute variation of resistance in that process.
7.2.2 Fully Integrated Precision CMOS Current Reference
the term of h that appears in the denominator of (7.30). One idea to make a
In a gm-constant circuit the current has a positive temperature coefficient due to
current nearly independent of temperature is to combine two currents with

opposite temperature coefficients in such a way that the total current is almost
independent of temperature. The main idea can be described with the aid of a new
circuit shown in Figure 7.22 [6].
-. . The reference voltage of -. is produced by a bandgap voltage generator whose

In this circuit the op amp forces the drain-source voltage of M1 to be equal to
temperature coefficient is deliberately made positive. Supposing -. is less than the

saturation voltage of M1, we put M1 in the triode region with the following drain
current
VDD
M4 M6
1 : 1 M5
Iout
Vr
+
M3
-
M1 M2
2 : 1
Figure 7.22 Architecture of a new current reference.

42
W) ° j -fD -e -. l (7.32)
The diode-connected M2 works in saturation and we can write
W) -fD -e
Æ2
(7.33)
From (7.32) and (7.33) and noting that -fD -fD , the relationship between W)
and W) can be derived as follows:
42
W) ° ç©t -. ¬è
{:2
Æ2
(7.34)
The PMOS current mirror M4-M5 forces the drain current of M1 and M2 to be
equal. In this situation the circuit equilibrium point can be found by the
intersection of the corresponding curve of (7.34) and the bisector of the Cartesian
coordinate system, as plotted in Figure 7.23. As can be seen, the circuit has two
considered as a suitable operating point. Substituting W) W) W into (7.34)

different stable points in which only the one with the larger current level is
yields the following equation:
ÆÅ 4 2
W F G ° -. W F G
ÆÅ
Æ2
(7.35)
Solutions of (7.35) give the current W. If we have ° ° , the first quadrant
become coincident and the current will be W ° -. . In this case for

bisector will be tangent to the curve in Figure 7.23 and thus two operating points
ID1
ID1=f(ID2)
2
ID
1=
ID
0 ID2
Figure 7.23 Equilibrium points of a new current reference.

° hY "V o p the ratio of W o p becomes hY "V-. . As was
subthreshold region is that the ratio of W) o p is less than hY "V --q¦ , thus
proved in Chapter 2, a rough estimation that shows an MOS transistor works in the
for -. --q¦ , M1 and M2 work in the subthreshold and none of the above
the small value of -. . But for ° Ö ° we can shift the circuit to our desirable
relationships are applicable, a condition that is quite possible to occur because of
operating point with the aid of an appropriate startup circuit. At the new operating
example, for ° ° , (7.35) gives two solutions:

point with a higher current level, all aforementioned equations are valid. As an
ÆÅ 4 2
W C> d (7.36)
In which the bigger solution guarantees the validity of the derived equations. In
W ·W ·ã
order to have an output current with approximately zero temperature coefficient,
we set for the term with a plus sign in (7.36), which results in
z4 zÆÅ
4 ze ÆÅ ze
(7.37)
Using h ã h ã ã / in ° hY "V o p by manipulating (7.37), we

can obtain the desired relative variation of -. with respect to temperature as
z4 Œ
4 ze e
(7.38)
where ã C › œ. Therefore, the temperature coefficient of -. should be around

=‹ /Ž
›œ. This means that in order to have a reference current with a near-
= ‹ /Ž ›œ. Note that -. is a

zero temperature coefficient it is enough to use a low-voltage bandgap voltage
with a positive temperature coefficient of
only process parameter that can mainly affect W is the gate oxide thickness n"V,
bandgap voltage and there is no resistance parameter in (7.36). We see that the
which appears in ° hY o p "V with "V m"V n"V. Thus it can be

claimed that this circuit has minimum variations with process in addition to a near-
zero temperature coefficient.
7.2.3 CMOS Current Reference without Resistors
There is another current reference architecture that is very similar to the gm-
constant circuit. But in this circuit, instead of a resistor an MOS transistor working
in the triode region has been used. The circuit is shown in Figure 7.24 [7]. By
choosing a large aspect ratio for M1 and M2 and taking a low-level drain current
for them, these transistors would work in the subthreshold region. Therefore, their
gate-source voltages can be written as
VDD
M3
M7 M4
1 : 1 1 : 1
I1
I2 I1
n:1
M1 M2
M6 M5
1 : m
Figure 7.24 CMOS current reference without a resistor.
-fD -eY --q¦ • H I

{Å
²
{v F G
(7.39)
³ Å
-fD -eY --q¦ • H I

{Å
²
{v F G
(7.40)
³ 2
We can also write
-fD -fD -)D (7.41)
Using (7.39), (7.40), and (7.41), and surmising -eY -eY , we obtain
-)D --q¦ ™c • (7.42)
Equation (7.42) shows that the M5 drain-source voltage is a small voltage and
therefore this transistor operates in the triode region with the following relation for
its drain current:
W ° F-fD -eY G -)D

4:ké
(7.43)
Diode-connected M6 works in saturation with W °ê -fDê -eY . Since

-fD -fDê , we can replace the term of -fD -eY in (7.43) with • W °ê, which
yields
W ° ©t 2 ¬ --q¦ ™c •
{ ±4‰¥ BC Y
Æ
(7.44)
í
The current mirror M3-M7 forces W to be equal to W , thus the circuit operating
line of W W . By definitions W W W and ! --q¦ ™c • and noting that

point will be the intersection of the curve represented by (7.44) and the straight
° &°ê , the equation from which the current W can be calculated will be
W & °! W ° !Ç
Ç
(7.45)
Two solutions of (7.45) are given by
> •02 /0
W ° --q¦ ™c •
0/
(7.46)
In (7.46) the current of W depends on temperature because of the presence of °

and -q¦ . For h ã h ã ã / we can conclude from (7.46) that W J ã . In
this architecture our current reference mainly depends on the gate oxide thickness
like the previous one but its variation with temperature is not negligible. The
circuit has two stable equilibrium points A and B that are the same as shown in
Figure 7.23. If the circuit places in point A the current level at this point is too
small and therefore it needs to be transferred to the other stable point B. This can
be carried out by adding an appropriate startup circuit. Assume the circuit of
Figure 7.24 initially operates in the operating point of A. The startup circuit should
act in such a way that it can temporarily increase the drain current of M1. When
this current increases the M6 current also increases through the current mirror
M3-M7, which causes the gate-source voltage of M6 and M5 to rise. This
increases the drain current of M5 and M1. By repeating the above mechanism,
toward point B. Figure 7.25 shows the increase path in W and W that is initiated by
which acts as a positive feedback, the operating point of the circuit quickly moves
the startup circuit and continues through the positive-feedback mechanism.
I1
I2
I1 =
I1=f(I2)
B
I2
A
0
Figure 7.25 Transfer path from point A to point B by a startup circuit.

threshold voltages. This difference adds an error term of 3-eY -eY -eY to
In an n-well process the body effect causes M1 and M2 to have different
(7.42). Since this term changes with process and temperature the reference current
will have more variation in comparison to what is predicted by (7.46). To solve
this issue the circuit can be replaced by its dual circuit, as depicted in Figure 7.26.
The substrate terminal of M2 is tied to its source. This eliminates the body effect
in M2.
Design Example
In this example a current reference circuit is to be designed with W \¶ in a

0.25- m CMOS technology. The chosen structure is based on the architecture of
Figure 7.26. In order to make sure that M1 and M2 work in the subthreshold, their
aspect ratio should satisfy the following inequality:
hR --q¦
{:
² "V
F G
(7.47)
³ Å
For W) \¶, in the given process, with h× "V = \¶ [ , - T and from

(7.47) we should have o p B =. In practice an MOS transistor passes
through the moderate inversion before entering the subthreshold region that is
equivalent to the weak inversion under the gate. Taking into account the moderate
inversion region and in order to be sure that the transistors work in the
what the inequality of (7.47) predicts. Here we choose o p < . For •

subthreshold in all process corners, it needs to make the ratio much more than
we have o p . In this circuit the difference between the drain-source
voltage of M4 and M3 and that of M7 is large. Thus the nonzero value of | in

voltage of M1 and that of M2, as well as the difference between the drain-source
short-channel effects the channel lengths of M1 and M2 are chosen p H = \Š

these transistors significantly affects their current levels. In order to minimize the
that yields o C \Š and o < \Š. From (7.46) for W \¶ and

& , the size of M5 can be obtained as o p ; . We choose p = h&
Figure 7.26 Current reference circuit without a body effect error.

Table 7.1
Output Reference Current in Different Process Corners
W \¶
Process Corner Slow-Slow Typical-Typical Fast-Fast Slow-Fast Fast-Slow
p = \Š)
(Figure 7.26, 1.021 1.117 1.234 1.142 1.094
W \¶
p = \Š)
(Figure 7.27, 1.030 1.089 1.150 1.115 1.063
and o = \Š. So the size of M6 becomes pê = \Š and oê = \Š. M3,
minimize the channel modulation effect, oŽHÇHŒ pŽHÇHŒ = \Š are selected. Data
M4, and M7 are current mirrors with the size ratio of one. To save chip area and
obtained from the simulations in the different process corners at ã =A are
The most change in W is related to the transition from the typical-typical (TT)
summarized in Table 7.1.
to the fast-fast (FF) corner with =- variation. In the given process the
maximum relative variation from TT to FF or slow-slow (SS) due to the gate oxide
thickness variation is about 5.<- . More variation with respect to what is predicted
in the theory is due to the large difference drain-source voltage of M1 and M2
despite the fact that we have used the long-channel MOS transistors.
By adding an op amp to the circuit as depicted in Figure 7.27, it is possible to
have nearly the same drain-source voltage for M1 and M2 and also for M4 and
M3, M7. In such circumstances, using transistors with even shorter channel
a channel length of = \Š for all transistors and with the same aspect ratio, the
lengths gives better results in terms of variation in different process corners. With
transistor areas are decreased by the amount of two orders of magnitude. Of
VDD
M5 M6
m:1
1 : n
M1 M2
- +
M4
M3 M7
Figure 7.27 Improved current reference circuit.

7.3 Conclusion 193
course, the op amp itself occupies some area of the chip. Simulation results in the
variation from a typical to a fast corner is = <- , which is exactly consistent with
presence of the op amp are also included in Table 7.1. In this case, maximum
the process gate oxide thickness variation.
7.3 Conclusion
In this chapter different structures of bandgap voltage reference generators were

introduced. These included conventional bandgap, fully CMOS, and low-voltage
bandgap circuits. In the low-voltage bandgap reference voltage generator, it was
observed that the op amp offset voltage could degrade remarkably the performance
of the circuit, so the design of an op amp with adequately low offset voltage is
essential in this situation.
We also examined different architectures of current reference circuits. As a
matter of fact, the current reference circuit is extensively used in different analog
circuits as a bias current or active load and thus designing a current reference
circuit with the most stability against PVT is very important. As well, some fully
integrated current reference circuits in CMOS technology were analyzed. In
several given design examples some practical points were presented, which will
aid the designer in achieving a realistic design. As we noticed, the op amp as an
integral part of all these circuits plays a key role in meeting the desired
performance.
References
[1] Allen, P. E., and Holberg, D. R., CMOS Analog Circuit Design, Second Edition, Oxford
University Press, 2002.
[2] Razavi, B., Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
[3] Gray, P. R., Hurst, P. J., Lewis, S. H, and Meyer, R. G., Analysis and Design of Analog
[4] Banba, H., et al., “A CMOS Bandgap Reference Circuit with Sub-1-V Operation,” IEEE J. Solid-
State Circuits, Vol. 34, pp. 670-674, May 1999.
[5] Buck, A. E., McDonald, C. L., Lewis, S. H., and Viswanathan, T. R., “A CMOS Bandgap
Reference without Resistors,” IEEE J. Solid-State Circuits, Vol. 37, pp. 81-83, Jan. 2002.
[6] Dehghani, R., and Atarodi S. M., “A New Low-Voltage Precision CMOS Current Reference with
No External Components,” IEEE Trans. on Circuits and Systems—II, Vol. 50, Dec. 2003.
[7] Oguey, H. J., and Aebischer, D., “CMOS Current Reference without Resistance,” IEEE J. Solid-
State Circuits, Vol. 32, pp. 1132-1135, July 1997.
Index
Active load low-voltage, 173
common-source amplifier, 55 design example, 174
issues in two-stage op amp, 68 without resistors, 176
single-ended output differential CMOS circuit fabrication, 15
amplifier, 36 CMOS current reference
Adaptive dynamic load, 151 near-zero temperature coefficient, 188
Annealing, 15 subthreshold region, 188
Bandgap reference circuit, 168 without resistor, 188
instability, 171 design example, 191
Bandgap voltage reference CMOS differential amplifier
design example, 170 dominant pole, 47
BJT, 18, 168, 171, 174, 175 drain currents, 38
Body effect flicker noise reduction, 41
coefficient, 20 frequency response, 43
effective threshold voltage, 20 input-referred offset voltage, 38
transconductance, 23 mismatches, 38
zero-bias threshold voltage, 20 gate oxide thickness, 40
BSIM model, 65 threshold voltage, 40, 41
Channel length modulation total input-referred noise, 52
effective channel length, 19 CMOS, deep submicron, 65
meaning, 19 CMRR
Channel-stop, 15 CMOS differential amplifier, 42
Charge space, 17 definition, 3
Class A equivalent offset voltage, 6
power efficiency, 139 fully differential op amp, 3
Class B single-ended op amp, 5
power efficiency, 142 Common centroid technique, 41, 175
CMFB Common gate stage, 77, 83, 86
differential difference, 114 Common-mode feedback. See CMFB
modified differential difference, 116 Common-mode rejection ratio. See
MOS devices in the triode region, 118 CMRR
resistive sensing, 112 Common-mode to differential-mode
resistive sensing with source- voltage gain, 3
follower, 113 Common-mode voltage gain, 3, 5, 6, 42,
switched-capacitor, 120 43
control voltage, 122 Common-source amplifier, 27, 55, 59,
loading effect, 122 159
system level representation, 111 Common-source stage, 69, 123, 124,
CMOS bandgap voltage reference 127, 138, 186
195
196 Index
Compensation capacitance, 62, 65, 66, CMFB, 123

75, 90, 162 instability, 125
Compensation resistor, 64, 66, 70 Fermi potential, 20, 136
Constant-gm input stage Filter
based on square-law, 101 Gm-c, 1
based on subthreshold region, 103 switched-capacitor, 1
based on translinear loop, 101 Flicker noise corner, 9
current combiner circuit, 103 Floating current source, 153, 154, 160
Cross-over distortion, 140, 141 Folded-cascode op amp, 86
Current gain, 169 as voltage follower, 86
Current mirror design example, 87
current gain, 181 low-frequency voltage gain, 87
loop gain, 182 small-signal equivalent circuit, 87
positive feedback, 181 Frequency compensation, 62, 71
Current mirror gain, 92, 93, 95 folded-cascode op amp, 90
Current mirror op amp two-stage op amp, 60
cascode configuration, 93 Fully differential op amp
design example, 94 advantages, 107
frequency response, 92 Fully integrated circuit, 167
dominant pole, 92 Gate overlap length, 27
phase margin, 92 Gm-constant circuit, 185
second pole, 92 supply variation, 185
low-frequency small-signal voltage with op amp, 185
gain Input common-mode range, 2, 96
saturation, 91 Integrated mixed-mode circuit, 107
subthreshold, 91 Ion implantation, 15
slew rate, 92 Isolation areas, 15
Current reference generator, 1, 167 Low-voltage design, 85, 108, 130, 166
Data converters Master bias current, 180
analog-to-digital, 1 Mirror pole
digital-to-analog, 1 differential pair, 47
Depletion mode, 17 folded-cascode, 87
Differential pair omission in FD amplifier, 108
unbalanced, 176, 177 telescopic cascode, 84
Drain current Moderate inversion, 23, 89, 191
short channel effect, 67 Modified two-stage op amp, 78, 79, 82
Drain-source dynamic resistance, 20 conjugate poles, 79
Equilibrium point, 125, 183, 187, 190 Monte Carlo simulation, 4
Even function, 36 MOS capacitances
Even harmonics, 108 fringing, 27
FD op amp gate to source/drain, 26
current mirror gate to substrate, 24
CMFB, 128 overlap gate to source/drain, 26
low-frequency voltage gain, 129 source/drain to bulk, 27
design example, 130 MOS channel charge, 26
folded-cascode MOS fabrication
architecture, 130, 133 n-well, 15
two-stage steps, 16
Index 197
MOS inversion states offset voltage, 5

strong inversion, 17 PSRR, 9
weak inversion, 17 slew rate, 8
MOS operating regions with class AB output stage
saturation, 18 design example, 163
subthreshold, 21 Output stage
triode, 17 class A power amplifier, 135, 139
MOS small-signal equivalent circuit class AB
high frequency, 29 case study, 159
MOS surface charge, 25 low voltage, 149
MOS Transconductance op amp design example, 163
saturation relationship, 22 stable quiescent current, 145
short channel effect, 67 translinear loop, 153
subthreshold relationship, 22 class B power amplifier, 139
MOS transition frequency quiescent current, 140
definition, 30 drain-coupled complementary
relationship, 30 transistors, vi, 142
Natural frequency, 80, 161, 162 source-follower, 114, 135, 137, 138,
Near-zero temperature coefficient, 177, 139
188 nonlinear behavior, 136
Noise output voltage swing, 137
channel thermal noise current, 48, 49 Oxide thickness cross-chip gradients, 41
flicker noise coefficient, 49 Periodic steady state, 132
flicker noise voltage, 48, 49, 171 Pipeline analog-to-digital converters, 8
MOS input-referred noise voltage, 49 Polysilicon resistors, 172
op amp, 8 Positive-feedback loop, 182
Nonoverlapping clocks, 120 Power supply rejection ratio. See PSRR
Nonsilicide polysilicon resistor, 176 PSRR
Odd function, 35, 108 definition, 9
Odd harmonics, 35, 108 fully differential op amp, 11
Offset voltage measurement, 10
bandgap, 168, 175 modified two-stage op amp
CMOS differential amplifier, 38 frequency response, 80
relationship, 40 two-stage op amp, 72
fully differential op amp, 6 improvement, 77
measurement, 6 positive supply frequency response,
single-ended op amp, 6 75
threshold voltage mismatches, 41 small-signal equivalent circuit, 73
two-stage op amp Quality factor, 80, 161, 162
random, 58 Rail-to-Rail input op amp, 96
systematic, 56 current combiner, 103
unbalanced differential pair, 177 input transconductance, 98
On-chip component, 66 translinear loop, 99, 101
Op amp Resistive divider, 119, 173
bandwidth, 7 Right half-plane zero, 59, 62, 65, 66, 80
Dc gain, 1 Sheet resistance, 174
linearity range, 2 Slew rate
noise, 8 modified two-stage op amp, 81
198 Index
Source/drain overlap parasitic absolute statistical variation, 41

capacitance, 16 gate area, 41
Source-coupled differential pair threshold proportionality factor, 41
drain currents, 34 Total harmonic distortion, 165
large-signal transconductance, 35 Translinear element, 98
SpectreRF, 132 Translinear loop
Stable points, 183, 187 class AB, 153
Startup circuit definition, 98
bandgap voltage reference, 171 Twin-loop
bandgap voltage reference without current mirror, 182, 183, 184
resistor, 180 instability, 7, 60, 126, 183
CMOS current reference, 188 Two-stage op amp
test method, 171 compensation resistor realization, 70
Subthreshold dc voltage gain, 60
criterion, 23 design example, 69
relationship, 21 design procedure, 65
reverse saturation current, 21 frequency compensation, 60
Subthreshold factor, 69, 87, 130 low-frequency voltage gain, 63
Surface potential, 25 phase margin, 62
Symmetrical devices, 40 positive supply transfer function, 74
Symmetrical layout, 170, 175 random offset voltage, 58
Systematic offset voltage elimination, 57 slew rate, 66
TC small-signal equivalent circuit, 59
bandgap systematic offset voltage, 56
resistors, 170 voltage gain transfer function, 59
base-emitter junction, 171 Unity gain bandwidth
Telescopic cascode op amp, 83 definition, 7
frequency response, 84 two-stage op amp, 60
low-frequency voltage gain, 84 Vertical PNP transistor, 169
output voltage swing, 85 Voltage reference generator, 167, 193
Thermal voltage, 21, 156, 168 Voltage-controlled oscillator, 167
Threshold voltage Voltage-to-current converter, 33
definition, 17 Zero-pole cancellation, 64
mismatch

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Design of CMOS

Rasoul Dehghani is an assistant professor in the Department of Electrical and

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ISBN 10: 1-60807-153-7

British Library Cataloguing in Publication Data

Cover design by Adam Renvoize

ISBN 13: 978-1-60807-153-1

© 2013 ARTECH HOUSE

Chapter 1 Basic Specifications of Op Amps 1

Chapter 2 CMOS Technology and Physics 15

Chapter 3 CMOS Differential Amplifiers 33

Chapter 4 CMOS Single-Ended Output Op Amps 55

Chapter 5 CMOS Fully Differential Op Amps 107

Chapter 6 CMOS Output Stages 135

Chapter 7 CMOS Reference Generators 167

An operational amplifier is one of the most important building blocks in many

1.1 Op Amp Parameters

Figure 1.1 Inverting feedback amplifier.

closed-loop voltage gain as

Where is the feedback factor. If it is assumed that ,

Common-mode rejection ratio. One of the most outstanding advantages of an op

might appear at the inputs of the op amp. The parameter of common-mode

!"# $# !%$ ## !%# (1.2a)

!"$ $$ !%$ #$ !%# (1.2b)

where ## and $$ are differential-mode and common-mode voltage gains,

the common-mode reference voltage denoted by -$. . Representing the voltages at

the inverting and noninverting inputs of the op amp as ! / and ! , respectively, we

!/ !" -$. -$0 (1.4a)

! !"/ -$. -$0 (1.4b)

!%# ! !/ !"# (1.5a)

!%$ ! !/ !"$ -$. -$0 (1.5b)

be used to calculate the typical & ''() . As an example, in a fully differential op

!" #0 !%# $0 !%$ (1.9)

where #0 and $0 are differential-mode and common-mode voltage gains,

! -$0 and ! / !" -$0 . Since !%# ! ! / and !%$ ! !/

!" #0 !" $0 F-$0 G (1.11)

Rearranging (1.11), we obtain the transfer function as

contribution in this parameter. It is interesting that the nonzero common-mode

voltage varies in response to the input common-mode voltage variation in spite of

with the value of -%HIJ !" #0 or -%HIJ $0 !%$

!"HDE -"K #0 #0 and !"H() -"K ## ## for single-ended and

Frequency bandwidth. The open-loop voltage gain of an op amp begins to drop

parameter denoted by LM , as illustrated in Figure 1.5. As its name suggests, LM is a

instability problem at frequencies near LM . Thus the op amp should be properly

designed to have an acceptable amount of stability in the frequency domain [5].

Figure 1.5 Op amp voltage gain versus frequency.

amp output. When an op amp is placed in a negative-feedback loop and a rather

Noise. A complementary metal oxide semiconductor (CMOS) op amp is made of

!" # !%# R !R (1.14)

!" R !R # !" (1.15)

Rearranging (1.15), we have

Since # , we can obtain the PSRR as

Figure 1.8 Circuit used to measure PSRR.

PSRR in a fully differential op amp has a similar relationship given in (1.13)

Slew rate SR Usually as W Z Infinity = [ \]

In this chapter, several important dc and ac parameters of op amps were

A part of the limitation in the performance of a CMOS circuit is related to how it

2.1 Basic Processes in MOS Transistor Fabrication

Gate Oxide Field Oxide

Gate Oxide Field Oxide

Gate Oxide Field Oxide

Figure 2.1 Main steps of MOS device fabrication.

2.2 Principles of MOS Transistor Functioning