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Layouts Ds PDF
Layouts Ds PDF
and CMOS
Design Rules
Stick Diagrams
Layout Diagram
Examples
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Design Rules: Introduction
Design rules are a set of geometrical specifications
that dictate the design of the layout
These rules usually specify the minimum allowable line widths for
physical objects on-chip
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Stick Diagrams: Basic Rules
Poly crosses diffusion forms transistor
Red (poly) over Green(Active), gives a FET.
L:W
nFET/
nMOS
Aspect Ratio
L:W
pFET/pMOS
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Stick Diagrams: Basic Rules
Blue may cross over red or green, without
connection.
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Stick Diagrams(NMOS): Basic Steps
Normally, the first step is to draw two parallel metal (blue)
VDD and GND rails.
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Enhancement-Mode MOSFET :
0
n+ n+
S D
p bulk Si
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Enhancement-Mode MOSFET :
When the gate is at
a high voltage:
Source Gate Drain
Positive charge on
Polysilicon
gate of MOS capacitor
SiO2
Negative charge
attracted to body
Inverts a channel 1
n+ n+
under gate to n-type S D
p bulk Si
Now current can flow
through n-type silicon
from source through
channel to drain,
transistor is ON
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Inverter Using MOSFET
Enhancement-Mode MOSFETs act as switches.
Enhancement-mode as pull-up:
Vo(max) = VDD
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Inverter Using MOSFET
Pull Up
Output
Pull Down
Input
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NMOS Inverter: Enhancement load
Vdd
Zpu = 2/1
Vout
Vin Zpd=1/2
GND
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NMOS Inverter: Enhancement load (Stick diagram)
VDD
2:1
Vout
Vin 1:2
GND
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NMOS Inverter: Depletion load
Vdd
Zpu = 2/1
Vout
GND
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NMOS Inverter: Depletion load (Stick Diagram)
Vdd
2:1
Vout
Vin
1:2
GND
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NMOS 2 I/P NAND Gate :
Vdd
Zpu = 4/1
Y = !(ab)
I/P a Zpd = 1/2
b Zpu = 1/2
GND
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NMOS NAND (Stick Diagram) :
Vdd
Y=!(ab)
a
b
GND
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NMOS 2 I/P NOR Gate :
Vdd
Zpu = 2/1
Y=!(a+b)
Zpd = 1/2 Zpd = 1/2
a b
GND
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NMOS NOR (Stick Diagram)
Vdd
2:1
Y=a+b
1:2
1:2
a b
GND
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MOSFET
L
N-type transistor
A silicon wafer
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Aspect Ratio For Pull-up and Pull-down
The size of a MOSFET depends on the reference inverter design.
The reference inverter for nMOS logic design is the inverter with
depletion mode load.
Therefore:
if MOSFETs are connected in series, the
effective L/W = (L/W)1+(L/W)2+….
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Aspect Ratio For Pull-up and Pull-down
For NMOS:
There are two values of Rinv, that are sufficient
for all NMOS basic gates:
Rinv = 4:1
To save space.
Rinv = 8:1
When input is taken from a pass transistor.
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Inverter Ratio for NMOS Gates :
Gates Rinv ZPU ZPD
Inverter 4 2:1 1:2
4:1 1:1
8 8:1 1:1
4:1 1:2
2:1 1:4
NAND 4 4:1 1:2 (Each)
(2 I/P) 2:1 1:4 (Each)
NOR 4 2:1 1:2 (Each)
(2 I/P) 4:1 1:1 (Each)
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NMOS NAND and NOR :
NMOS NAND NMOS NOR
Two nmos in series. Two nmos in parallel.
Gate delay and area NOR works quite well
increases with for any no of inputs.
increase in no of
inputs. Width is proportional
Length also increases to number of inputs.
with increase in no of
input.
NMOS NOR is faster
NMOS NAND is slower
for same no of inputs
for same no of inputs and power dissipation.
and power dissipation.
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Types of Layout Design Rules
Industry Standard: Micron Rule
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Types of Design Rules (Contd…)
Industry Standard: Micron Rule
All device dimensions are expressed in terms
of absolute dimension(μm/nm)
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Types of Design Rules (Contd…)
λ Based Design Rules :
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Types of Design Rules (Contd…)
λ Based Design Rules
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Design Rules
• Minimum length or width of a feature on a
layer is 2
• To allow for shape contraction
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Design Rules :
Two Features on different mask layers can
be misaligned by a maximum of 2 on the
wafer.
Metal
Diffusion
3
2 2
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Design Rules: NMOS
PolySi – PolySi spacing 2
Metal - Metal spacing 3
Diffusion – Diffusion spacing 3 To avoid the possibility of their
associated regions overlapping and conducting current
Metal
3
Diffusion
Metal
Diffusion
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Polysilicon
Design Rules: NMOS
Metal lines can pass over both diffusion and polySi
without electrical effect
Metal
Polysilicon
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Contact Cut :
Metal connects to polySi/diffusion by contact cut.
Contact area: 2*2
4
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Contact Cut
Contact cut – contact cut: 2 apart
Why? To prevent holes from merging.
2
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Design Rules: NMOS
Minimum diff width 2
Minimum poly width 2
Minimum metal width 3
poly-poly spacing 2
diff-diff spacing 3
(depletion regions tend to spread outward)
metal-metal spacing 3
diff-poly spacing
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Design Rules: NMOS
Poly gate extend beyond diff by 2
Metal contact
Butting contact
Buried contact
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Metal contact :
Contact cut of 2λ * 2λ
in oxide layer above
poly and diffusion
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Butting Contact
• The gate and diffusion of NMOS device can be
connected by a butting contact.
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Butting Contact
Disadvantages:
• Metal descending the hole has a tendency to fracture at the
polySi corner, causing an open circuit.
• Requires a metal cap.
Metal
Insulating
Oxide
n+ n+
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Butting Contact
Metallization is required only over the butting contact
holes which are 2 λ x 4λ in size
Advantage:
No buried contact mask required and avoids associated
processing.
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NMOS INVERTER-
Enhancement load
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NMOS INVERTER: Enhancement Load
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NMOS INVERTER-
Enhancement load
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Buried Contact
The buried contact window defines the area where
oxide is to be removed so that polySi connects
directly to diffusion.
2
Contact Area
2
Advantages: No metalDarshana
cap Sankhe
required.
Disadvantage: An extra mask is required.
Buried contact :
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Buried Contact
PolySi
Channel length
2
Buried contact 2
Diffusion
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Buried Contact
The buried contact window surrounds this contact
by λ in all directions to avoid any part of this area
forming a transistor.
2
λ
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NMOS INVERTER
Depletion load
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NMOS INVERTER:
Depletion Load
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NMOS NAND
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NMOS NAND
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NMOS NOR
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NMOS NOR: Layout
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CMOS :
Pull-up is PMOS
Pull-down is NMOS
10 ns
1 ns
PMOS
pMO
CMOS
100 ps S nMOS
100 uW 1 mW 10 mW
Darshana Sankhe 100 mW
Aspect Ratio :
For CMOS:
Rinv = 1:1(Ratioless)
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Stick Diagram (CMOS): Basic Steps
Steps for CMOS are similar to NMOS
First step is to draw two parallel rails for VDD and GND.
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PMOS :
Body tied to high Source Gate Drain
voltage (VDD) Polysilicon
Gate low: SiO2
transistor ON
Gate high:
transistor OFF
p+ p+
Bubble indicates
inverted behavior n bulk Si
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CMOS Invertor (Cicuit Diagram)
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CMOS Inverter :
VDD VDD
OFF ON
A=1 Y=0 A=0 Y=1
ON OFF
GND GND
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CMOS Invertor (Stick Diagram)
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CMOS Invertor (Stick Diagram)
VDD
Out
In
GND
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Well Biasing :
The various N and P diffusions must be reverse
biased to ensure that those wells are insulated
from each other.
p+ n+ n+ p+ p+ n+
n well
p substrate
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CMOS NAND (Cicuit Diagram)
VDD
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CMOS NAND:
ON ON
Y=1
A=0
OFF
B=0
OFF
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CMOS NAND (Stick Diagram)
VDD
A Out
B
GND
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CMOS NOR (Cicuit Diagram)
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CMOS NOR (Stick Diagram)
VDD
A Out
GND
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Design Rules: CMOS
Line size and spacing:
metal1:
Minimum width=3, Minimum Spacing=3
metal2:
Minimum width=3, Minimum Spacing=4
poly:
Minimum width= 2, Minimum Spacing=2
ndiff/pdiff:
Minimum width= 3, Minimum Spacing=3,
wells:
minimum width=6,
minimum n-well/p-well space = 6( They are at same potential)
= 9 (They are at different
potential)
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Design Rules: CMOS
Transistors:
Min width=3
Min length=2
Min poly overhang=2
Contacts (Vias)
Cut size: exactly 2 X 2
Cut separation: minimum 2
Overlap: min 1 in all directions
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CMOS
Inverter:
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CMOS NAND
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CMOS NOR :
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CMOS INVERTER
(This layout does not have n-well and contacts for n-well and substrate)
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CMOS NAND
vdd
B
!(A.B)
A
GND
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CMOS NAND
This layout does not have n-well and contacts for n-well and substrate)
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CMOS NOR(Circuit Diagram)
Vdd
A
!(A+B)
B
GND
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CMOS NOR
This layout does not have n-well and contacts for n-well and substrate)
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Design of NMOS/CMOS Circuits:
PDN – The Function to be implemented, must be expressed
in a inverted form.
_________
F = (A + BC) D
F = (AB + C) (D + E)
__
F = A + B + CD
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F’ = A + B + CD
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Thank you
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