EJectronk: Devices & Clrcults-1(MU) 4-1

Electronic Devices & Circuits-1

Chapter 1 : PN Junction Diode

0.1 OeftM tMmier potential forward biased. Generally a resistance is connected in series with
the diode to limit the current flowing through it. Forward biasing of
Ana.:
a diode is us shown in Pig. l.2(a) and the symbolic representation
~ t~ the prese~ce o~ immobile positive and negative ions is as shown in Pig. l.2(b). The current "lp" is a conventional
on opposite Stdes of the JUnction. an electric tield is created across current that flows in the circuit due to the forward biasing.
tbe ?~on. This ~lc:mc fie!d is known as the "barrier potential"
or 1uncnon potential or cut m voltage. lt has fixed polarities .
Q. 2 Draw symbol of PN Junction Diode . •..····"''j~"·····
Curront ~ ······:
Ana.:
Anode I I Cathode
limiting
1'99istor
.,
::
··...
,______•
.....··
, .... --~

~rode --p-.L--n~.a Elec~rode v v

1 2
(a) Forward biasing of a diode (b) Symbolic representation
(a) A p-o junction forms a semiconductor diode
<B-18) Fig. 1.2
p-side n-slde
0 L.......r>t ...-J a
Operation of forward biased diode :
Anode ......... .. Ca;:ode Due to the negative terminal of external source connected
I to the n-region, free electrons from n-side are pushed towards the
{b) Circuit symbol of a diode p-side. Similarly the positive end of the supply will push holes
(8-17) Fig. 1.1 from p-side towards the n-side.
With increase in the external supply voltage V, more and
Q. 2(a)Explaln the operation of a p-n junction diode In
more number of holes (p-side) and electrons (n-side) st3!t
the forward biased condition. travelling towards the junction as shown in Fig. 1.3.
Ana. :
If tbe p-region (anode) is connected to the positive terminal
oC lbe external DC source and n-side (cathode) is connected to the
oegative terminal of the DC source then the biasing is said to be
"forward biasing". In other words the diode is then said to be

-- --
p n

--
Barrier potential decreases
due to reducUon of depletion
region wtdth

-- -
Current
limiting
reeillanoe
--
' - - - - - - - - - + -Width of depletion region decreases
due to the holes and electrons
1.. . -- -----•;llt----------' approaching the junction

v
Fig. 1.3 : The etrect of increased forward bias on the depletion region and barrier potential

1be boJe1 wiU start cooverting the negative ions into
DeQtraJ IIOOU and the electrons will coovert the positive ions into
DeUtraJ ai.Oml. AJ a result of dUB, the wid~ of de~letio~ region
. . redtlce. Due 10 reduction in the depleuon reg1on w1dth, the
barrier poceacial will a!Jo reduce. Eventually at a ~articular value of
v the dep&etion region will collapie. There 1s absolutely no
oppoiitioo 10 the now of electrons and holes. Hence a large
ownber of eJectrooJ and holes (majority carriers) can cross the
juoaloc u.oder me influeace of ext.emally connected DC voltage..
The iar&e number of majority caniers crosrring the junction
c:oeliti~U~e& a currena caJJ.cd u the forward current. ·n~e current now
ibowo in fig. 1.3 is the electron current which is in the opposite
direction to that of a conventional c11rrent. With increase in the
forward bias. the width of the depletion region decreases and so
does the barrier potential.
0.3 Explain the operation of a p-n Junction diode In
the reverse biased condition.
Ana. :
If the p-region of a diode is connected to the negative
tenninal of the external DC supply and n-region is connected to the
positive terminal of the DC supply as shown in Fig. l.4(a) then a
diode is snid to be ·•re\'erse biased". Fig. l.4(b} shows the reverse

I ' ,I •. • · II I II II II II ~.
 "-2
E1ectronic Oevice8 & Circuita-l MU . ( ot allowed to flow into the n-region)
held back on ~e P suit. ~ntains the thermal equilibrium. ·
bluina ecbematically. The reverse twTent is denoted bY. ls and it arc
'lbe potenb
·at bafOer then maJ
r
Oows from tbe cathode to anode of the diode.
Thus rc\"Cf'Se CUJTetlt flows exactly in the opposite direc~o~ _v+
to lhit of tbe forward CUJTetlt. Resistance R is connected to limit
the reverse curreot.
------.1111-----
..........
........... ..... .................,
~
....···· Is ··...
(......... ....·· '··.... - !-'+_.)__
'------t v

(b) SymboUc representation

Ec i'"-rfv!H
EFp -------~-------+-------- EFn

(B-12) Fig. 1.4

Ev 1""-..._!
: ;
._-
Opel don of a revene blued diode :
Wben a diode is reverse biased, holes in the p-region are
aaractcd towards the negative terminal of the supply and electrons
011 die n-side are aaracted towards the positive terminal of the· - (b)
(a)
~Y as sbown in Fig. 1.5.

0 Holes
• l3eclron8

6 PoeiUw Immobile ion

8 NegaUv!l Immobile ion ~
EleQt%! q(Vbl +:
(B-23) Fig. 1.5 : Operation ora reverse biased diode EFp ----------1 . r__f__ ____ EFn
Iacreue in barrier potential : Due to more number of
iom present on opposite sides of the junction, the barrl.er.potential
or juoctioo potential will increase. The process of widening of
~ Hole flow
deplcQoo regioo does not continue for a long time, because the~ is
no steady flow of holes from right to left i.~~ from the n-side to p- (c)
side.
(F-3674) ~- 1.6 : Energy band diagrams of a PN junction
Q. 4 Judfy that the apace charge width increase with
,..,.... blued voltage In a p-n juncUon diode. 2. Reverse bias :
l•l§MICI ~ e~ergy band diagram of a reverse ·biasC!d PN junction is
as shown m Ftg. 1.6~). It shows that potential ofn-region is higher
Ane.: than that of the p-stde. ~nee the Fermi energy on the n-side is
f Due to tbe movement of electrons and holes away from the lower than that m th: p-stde. The total potential hamer is higher
junction, width of tbe depletion region-increases happens due .nus tJtan. that for the no btas condition. Due to this increased potential
to tbe creation of more number of posi~ve and negative immobile b~er the electrons and holes will be held back 'n the n and p
i.ooa. ~gto~s respectively and there will be no flow of charges across the
Q. 5 Dr8W energy band diagram of PN juncUon for JllnCtion.
zero. Hence
. current flowing through the Junction
· · would be
Z«<, forward, reveree bias clearly showing
junction diagram, depletion width, Fermi energy 3. Forward bias :
lewl end berr1er potential. '*hfl101 The energy band diagram · f. ·
in Fig 1 6(c) It sh
. . ·
m orward btased state ts shown
. Ane.! lower iev~l ~ th ~~sththat the. Fermi level in the p-region is at
10
The mecbaniJm of current flow in a pn junction with the is reduced So 1 a e n-regiOo. The total potential barrier alsO
~ of tbe eoetgy bend diBgrami is as follows : regions re~pec:v:trons and holes are not held baclc in the n and P
to the process of di~J?e holes and electrons cross the junction due
1. Thet'm8l equJJJbrtum : ston and current starts fl .
The holes · · . owmg. .
The energy bend d!Jtgram of a. pn junction in thermal carriers there. Simi;~~ted mto the n~region become min~ty
eQuilibrium i1 lbown in Fig. 1.6(a). Here the electrons see a large become minority earn~ the el~tro~s mjected into the P:re~on
poteoti.aJ bl.triet bccauJe ot which a large number of electrons are of excess carriers will tak · ~ ~ffus10n as well as recombmatton
hekl beck in tbe o-regioo. (they can not flow into the p-region). e P ace m these regions.
Similarly boles .00 see this potential barrier from the p side and Q, 8 01raw and explain V-1 characterlattca of
unctton diOde.
PN
 ..
4-.3
Me.:
The V-1 characleristi¢S
.
can be Ul
A:v·dcd.
• · mto· two pnrts :
l. ~-~. ofp-n junction DIOde • f---VA--ol
.LIX: IYIWanf C'bvacteri ti • '
c:alfiOde furwanl \!01~ v . ver:u~ ~ the graph of the anode to +
diode Ott). The furwant cb~teri . . . fo':"~ c~nt through the
AB and BC as shown i .,. 1 stic IS ,diVIded mto two portions, =~ A (_.. ...-·j~·~·i;;·····:·)
· n r:tg. .7(a) and the di
sbownin Fig. l.7(b). correspon ng circuit is
- +
AeQ1on A to B : v

ln cbe region A to B of the ti (a) Arrangement to reverse bias a diode

Fig. l.7{a). the forward voltag . orward characteristics shown in
YOJuge. Tbel:eforc lhe forw e ts small and less than the cut in
small. With fiutbel' increase~ c;:eot
flowing through the diode is VR ln. volts 0
leYel oflhe cut in roltage and th .~ard voltage, it reaches the Reverse/;,:,.------...J. · ··10 {Aeverae satura11on
~- e WI of depletion region goes on breakdown Bmakdown current)
vollzlge
~lnmA
Reverae a.rrent
fsin,.A

· (b) Reverse characteristics of a diode

(B-Z7) Fig. 1.8

:{,.·· Current flowing through a diode in .the reverse biased state

is the reverSe saturation current which .f lows due to the minority
;;ot"-~Cut~-ln-'-v-ol-:-ta-g-e- - - - VF volts
(Knee voltage)
ccuriers. Therefore it is treated..as a negative current Hence the
reverse characteristic appears in the third quadrant as shown in Fig.
(a) Forward characteristics of a diode · l.8(b). As the reverse voltage is increased, the reverse saturation
current remains constant equal to 10 if the temperature is constant
This is because, · reverSe saturation current does not depend on
rev~rse voltage but it depends only on temperature. Bat as the
. ;.---V F ----.;
_ _.....
l--1 l reverse voltage reaches the breakdown voltage value, large current
flows through the diode. . ·
a. 7 Draw Complete V-1 Characteristiqs of Silicon and
Germanium Diodes :
Ans.:.
Forward """""' (rnA)
(b) Set up to draw the forward characteristics
.(B-26) Fig. 1.7
Region B to C :
Si
As soon as the forward voltage equals the cut in voltage,
aureat through the diode increases suddenly. The nature of this
aureot is ·exponentiaL The large forward current in the region B-C · Reve""' w1tage (volts) ' . l1, In 11A )
0.2
L-,-t
0.6

~ tbe forward cb.ataeteristics is limited by connecting a resistor Si r~:~Ge--~,...,....- IIA

..,.---1 cut In vohoQes
"R" in series with the diode. Forward current is of the order of a
(ew mA. 1he forward current is a conventional current that flows .
R<!ve'*' charact.utotlca
from anode to cathode. Therefore it is considered to be a positive
c:um:ot, and tbe forward cbatacteristic appears in the first quadrant
as libown in Fig. 1.7(a). (B-Z9) Fig. 1.9 : V-I characteristics of Silicon and
CuWn voltage (Knee voltage) : Germanium diodes
The voltage at which the forward diode curre~t starts
~B r.tpidly is known as the "cut-!n" voltage of a dtode. ~s Q, t Derive expression for the Diode Current •
lbown in Fig. 1.7{a), the cut-in voltage ts very close to the ?arner Ans.:
JIOttetial. Qu--in v.oltage is denoted by Vr' C ut in vol~ge ts also The diode current 10 has an exponential shape. It is
called as kaee yoltage. Geoe.rally a diode is forward .b•ast:d above mathematically expressed as :
lhe cut in volta8e. 1be cutrin voltage for a. silicon dtode ts 0.6 V V/1\V ]
IOd that fot a gcrman.ium di.ode is 0.2 V. Io =1 e T- 1 0
[ ...(1) ·
1. ltneniie ~of a Diode : Where , 10 = Reverse saturation current
Reverse ~.6f.ics is ~ gr.q>b of reverse voltage (Va> 10 ::; Diode current (forward or reverse)
•erau. lhe reverse cwrent ({8 ) as shown in 'Pig. l .8(b).

. · laallliiMmlliiUiiiiil
 4-4
:::::00.
Electronic Devlcee & Clrcuits·l (MU)
Ana.:
V't = 11
1x> and it is called as volt equivalent Two diodes are in paralie1· - 12
. neverse saturation current, Iot 1 x 10 Amp. =
of temperature D 1 . .1" 1 10-10
_;....ration current, Io2 = X Amp.
o2 : Reverse ,...._...
ll =
l fur Gennanium ='2 for Silicon. Total current I =2 mA. ll 1. =
:. VT =26mV.
T =
Temperature in °K Assuming ' T 300oK =
and V =
Voltage across diode (forward or
Step 1 : c~ent throUgh Dt :
reverse)
Current through Dt is given by,
The constant ll in Equation (1) is called as the emission
V/ttVT ]
coeft'ldeDt or kled~ factor. Its value is 1 for Gertnanium and 2 .I - I [ e . -1 ...(1)
1 - ol
for Silicoo. ·
1. Voltage equivalent ot temperature (VT) : Step 2 : Current through Dz :
1be voltage equivalent VT at a given temperature ofT °K is Current through D2 is given by,
gi~by, V/ttVT_t] ...(2)
VT = kTvolts .. :(2) lz = Ioz [ e
Where k = Boltzmann's constant Step 3 : The total current I :
= 8.62 x 10-5 eV 1 °K . I . = II+ lz
T = Temperature in °K Substituting Equations (1) and (2) to get.
The value of VT at T = 300 °K is equal to 26 mV. The V/ttVT ]
value of vT can be expressed as, I ;;; Iol [ e -1
T T T · V/tt VT . ]
VT = (1/ k) (1/8.62 X 10 3) = 11600 ...(3) + I02 [ e - 1 ...(3)
neglecting the - 1 term in both the terms in Equation (3).
Thus voltage equivalent of temperature is dependent on
temperatureand its presence in the equation of diode . . V/TJVT V/ttVT
:. I = 101 e + I02 e ...(4)
- cum:nt indicates that the diode current is dependent on·
temperature. . . . SubstituQI1g the values to get,
Expression for the forward current (IF) : 2xl0-3 = (1xlO-t2eV/26mV)
Substituting ID =IF and V = Vp in Equation (1) to get the _ 10 V/26mV)
expression for forward diode current as·: + ( 1x10 e
. 3 V/26mV
V,ltt VT ] . 2 X 10- = e [1 X 10- 12 + 1 X 10-IO ]
fr-=10 [ e -1 - ...(4) 3
V/26mV 2x 10- 6
Ife
Vp/TJ VT
>> 1 then ·· e = l.Ol X 10- 16 = 19.8 X 10
Vp/11 VT Taking log of both the sides we get,
4- "' 10 e ...(5)
v
This expression shows that the forward current is of _ 26 x w-3 . = 16.8
exponential nature.
3. Expression for the reverse current (IS) : .:- V = 0.4368 Volts. . ••.Ans.
Substituting ID =Is and V =- VR in Equation (1) to get, As both the diodes are connected in pandlel with each
other, the voltage "V" across them will be the same.
JS = Ia[e-VR/TJVT_l]
Q. 9 Explain effect of · temperature on the V-1
But e
-v.,, VT
<<1 characteristics of PN junction diode: -
:. Is ,.,
-10 ...(6) Ans.:
This expression shows that the reverse current Is of a diode · Tbe expression for diode current is
is negative and constant, equal to 10 (reverse saturation current).
0. 8 A diode with a reve..-. saturation current of 10-
12 Io = Io [e V/'1 VT- t]
-10 -
Amp and another with 10 Am~. are connected Where , I0 = Reverse saturation current.
In parallel. If the total current of the circuit Is T i
2 mA, calculate the voltage across the diodes. VT = TI600 I
=
Auume 11 1. Refer Rg. 1.1 0. I
ll = 1 forGe diode =2 for Si diode \

r, -~;·····T t
V =
Diode voltage.
v o, 02 . v The diode characteristi ·

~~.... . .1
equation of I . Two c IS mathematically expressed by the
di~e eucre to parameters lo and VT in the expression for
is depende:t ~n te::erature dependent. Hence the characteristic

1;
<F-181J) Fig. 1.10

a '• V •, II I II I IIIII S
temperature on the V-I :mpera_~e. The effect of change in
c aractenstics are as shown in Fig. 1.l L '
,,\
 ~ Owicel & Circuita-l (MU) 4--5

T 283 o
VT = II ,600 = li,600 =24.4 mV at T =283 K ...(1)
The reverse saturation current is given by,
. I0 = K T" e-voo'"vT
Substituting m "" 1.5, fl =2 and V00 :o:: - 1.2 t for a silicoo.
=
lt is given thatl0 2 nA at T 283° K =
3
. . 2xHr9 = Kx(283)'.5xe - J.2112xZ4.4 x tc1"
:. K = 0.02473 ...(2)
Step 2 : To calculate the diode current at T =283° K :
Diode current I = 10 [e v ' " vT .:_ I)
~ flc. 1.11 : EfPeds ot taapen..re 00 v _
1 cbancteristks at T = 283° K
ofaSiBcondiode = 2 X 10-9 (e0..4/2 xZ4..4x I0- 3 _ 11
~the fig. 1.11. cbe effects of temperature are :
I. Redll<::tioa in tbe cut-in voltage takes place with increase in
.. I 1 = 7.256 x .to- 6 or 7.256 JLA ...(3)
llempeOblre. Therefore at the same forward voltage V Fl a
,_
Step 3 : To cakul.ate VT and I. at T =70°C i.e. 343° K :
~ current ~ flows through the diode at increased 343
VT = ll,600 =29.56 mV ..•(4)
ttJmpeodUre.
2. The tnakdown voltage increases with increase in ~ = KT"'re-voo'"vTJ
lliempenblre. = 0.02473 (343)1.S [ e -1.2l/2x29.56 x lc1"3)
3. Reverse satnratioo current increases with increase in .. 10 ·~ 0.2042 x 10- 6 A or 0.2042 J.1. A ...(5)
temperature. Io fact it doubles its value for every 10° C rise
in tbe tempcntu.re.
Step 4 : To atkulate diode current at T =70°C
i.e.343° K:
0. 10 Why doM Ge diode produce higher reverse lz = Jo( eV/TJVT -1)
.......aon current? Substituting I0 from Equation (5) and v; from Equatioo {4)
Ana.: to get,
Tbe four valence eleclrons of Ge are in the fourth shell lz = 0.2042 X 10-6 [e0.-4/2x29.56 x la-3- 1]
wbcreu those of a Si atom are in the third shell. Hence the force of
tttractiou berwoeo the nucleus and valence eleclrons is weak in the
1z = 1.7698 x w-' Amp.= 176.98 !lA ...(6)
IJ'UN"ium atoms as compared to that in the silicon atoms. The StepS: To calculate the % change in diode CWTeDt :
fi:JrtJiddeG energy gap is smaller in Ge than Si atoms. Therefore, at ( I2 - I 1)
the same lmlpC:OIDll'e, more valence eleclrons will jump to the %change = X 100
II
meductioo band to produce higher reverse saturation current
176.98 - 7.256
Q. 11 Why Sl diode Ia more popular than the Ge diode ? = 7.256 X lOO

Ana.:
1be ~everse saturarioo current for a Silicon diode is much
lower lhan tbaf. of a Ge diode. Tberefore even with the two fold
iaaate io 10 aftet every IO"C rise in temperature, the reverse
~ CW'1'eQt through Silicoo diodes will still remain very low.
S. It iacleued ternpeealUI'C5. tbe reverse saturation current
dlroup a Ge diode is very high. of the order of
100 ~ oc so. 1bis level of reverse saturation current is
~ ill JOC(ice. Tberefore the Si diodes are more popular
= 2339.2%
0. 13 What Is transition capacitance ? Gl:ve Ita physical
significance. ·
Ana.:
. In Fig. 1.12, a p-n junction diode is being reverse biased.
W1th rev~rse .voltage applied, the majority earners ~ve away
from the junction. Thus as shown in Fig. 1.12, the boles in the p-
side and electrons in the n-side move away from the junction.

--Ge~.
ldea!Jy dJe ctiode
cbaraCltristics should not change with
J n-elda

cb1qe io ~and practicaJJy the change in.characteristics -o:

~ be plinimom 'fbe ~cs of Ge dtode are '!lore -o:
. . .
,,,._OU~ ·dlanchalofaiJ
'licoo diode
·
-o:
-ot
0 . 12 Fot a •~ diode, the r-.veree saturation current
• 10• c a. ~ .. 2 n.,
when the v.o ltage
acrON dloOJ ._ O.A v. wtwt wtJ1 be the% change
In - CIIMftllll.,..,..,.,...,. ..
t1llMd to 70° c ?
An.. ;
 Electronic Devices & Clrcults·l (MU)
ar.ct of chalrge movement :
Due 10 the movement of majority carriers away from the
junction, lbe width of depletion region will increase with increase
in tbe reverse voltage.
Due 10 tbe movement of charge caniers there is a change in
charge (dQ) with change in voltage (dV). This increase in charge
caused by lbe change in.reverse voltage is defined as the transition
capacitance. .

~ I~ .~.(1)
0
... c.- Reverse
voltage (Volta)
- 20 - 15 -10 -5

The transition capacitance c; is also referred to as space

. (F-1025) Fig. 1.13.• Va rfation or Cr with reverse voltage .
cblqe capacitance or barrier capacitance or depletion region
capacitance. .This capacitance is not constant but it depends on the . . iOn capacitance ? 'Give Ita physical
Q. 14 What Is. dlffu s
magniiUde of reverse voltage.
· significance.
Slgnlftcance of C,. :
The basic eqUation relating the voltage o~ C, charge ~d ·Ans·. : · · 10rw
& ard b' ..~...~
·unctiol1 diode 1s 1...,..... a
capacitance Cis given by, ~en ~e .p-n . J er than t:he transition capacitance
Q = CV .. Q=CrV capaci~ce w~ch lS m~sl~pacitance is called as diffusion
Differentiating both the sides to get,
come~ . mto ~xtstWhence.. forward voltage is applied, the barrier
capacxtance '-1)· en · th 'de
~ ,.... dV . . .
potential . red d boles from p-side enter mto e n-s1 .
Is lowe an . . 'de 1 · ·
dt = "'-T X dt ...( 2) .
Similarly eIectrons from n-s;de
~ enter mto · p-st . t IS converuent ban to
~
. . . mental capacitance defined as the rate of c ge
But, mtroduce an mere · · ·tan r ·
dt = .of·injected charge With applied vol~e. 1bis capact ce '-1> ts
dV called as the diffusion or storage cavacttance.
i = Crx(it ...(3) ..@_
:. Co = dV ~..(1)
This equation shows that the reverse current "i" through the
It can be proved that the diffusion capacitance is given by,
p-n junction c!iode is proportional to the transition capaci~ce
"C,-" and the rate of change of reve~ voltage "V". Hence if a 'tl
...(2)
reverse voltage of high dv/dt appears across a diode (that means a
reverse voltage at high frequency) then a large current will flow Where, 1: = Mean lifetime for holes.
through. it, and its reverse blocking capacity will ·be lost. .Hence the From the Equation (2) , the diffusion capacitance is
maximum .frequency of operation of a diode is dependent on the proportional to the current I. In the forward biased state the val~
value of<;. of <:;0 ·is much larger than the ·transition capacitance· <;. For a
Expression for Cr : reverse bias, C0 must be ~eglected i1S compared to <;. In the
forward biased. condition, C0 appears to be in parallel with the
The mathematical expression·for transition capacitance <; forward.resistance. ·
is given by,
EA
As this resistance is very small the time
constant "rd C "
0
c; - w ...(4) will also be very small. Therefore Co will be ineffective for the
normal signals, hence it can be ignored. But for the fast signals Co
A - Area of the junction becomes effective and hence should be conside~. The variation
W = Width of the depletion region in the diffusion capacitance with change in forward voltage is as
. shown in Fig.. l.l4. . . ·
e = Dielectric constant
The value of (;. is inversely proportional to the width of Diffusion c
capacitance 0
depletion region W. As W increases, the transition capacitance
decreases.
Width of depletion region :
The width of a reverse biased p-n junction is given by the
following expression,

- 2e (V1- V)J
112

- [ qNA
w .
...(5) o--~~--~-----FoNmro
0.25 o.s voltage
Wbere , e = Permittivity of the semiconductor.= e 0 E r
E0 = 8.854 X 10- IZ F/m and <F·lOU) Fig. 1•14: Variation in C with forward voltage
0
Er ::r 16 for German.ium =12 for siUcon ..1.. ~ the .forward biased state with increase in the current level
v1 ;: Contact potential the diffusiOn .capacitance C0 becomes more predominant. But
V = Externally applied reverse voltage. for ~e reverse btased condition, C0 is negligible and c; will be
dommant as sho,wn in Fig. l.l5(a): · · .
•iiilmliiliiii
 £ectronlc Devices & Cfrcuhs-1 (MU) 4-7
1be ran~~riti"" effects ,· e r .._...
• , --.---· , • · '1' ....u Co are represented by a concentr.Uon NA of the acceptor atoms on the p
cap~C•tor m perallel wtth an ideal diode as shown in Fig. l.lS(b). aide Ia much smaller than the concentration of
· 20 I
donor atoms 11'1 the n-materlal. NA 3 x 10 /m. =
calculate the width of depletion region for an
applied reverse vOltage of 10 V. Also find the
•' .~
apace charge capacitance H croas-.sectlonal area
2
of the diode Is 1 mm • Assume: e 0 8.854 pF/m =
=
and Er 16.
Ana.:
Given :VJ = 0.2 V, NA =3 x 10'l!J/m3 , V = - 10 Volts
'=: -5
.
0 Forwartl 0.5
voltage
A= 1 mm2, E0 =8.854 pF/m, E = 16.
'(a) Effect or forward and reverse bias voltage on the 1. To calculate the width of depletion region : .
tnmsitioo and cWrosion capacitance
Cr«Co W =
•

[2e ~:V)J
112

.. (1)

. 0.
10
Where • E :: E o E r =8.854 X l0- =1.416 X 10-
12
X 16
Substituting values to get,·
112
10
(b) lndadiDg tbe effect or transition or dift'usion capacitance . 2 X 1.416 X 10- (0.2 + 10)]
W = [ 1.6 X 10-19 X 3 X 101ll
(F-1027) Fig. 1.15
= 5.48~m
a. 15 Explain how the varicap can be used in an .Lc 2. To lind the space charge capacitance (Cr ):
resonant circuit- 10 6
E A 1.416 X 10- X 1 X 1(1
Ans.: c. = w= 5.48xlo- 6

Based on the principle of voltage variable capacitance a · = 25.8pF .

special type of diode is manufac~. It is called as varactor diode Q •.17 Why is load line called as DC load line ?
and it exhibits the property · of voltage vrujable . transition
capacitance more predominantly as compared to the conventiOnal Ans.:
JHl juncti.oo diode. The circuit symbol of a varactor diode is as . The word "DC"· represents that the operating conditions are
sbown in Ftg. l.16(a). DC. No~ signal is present. .And it is called as load line because
the slope of this line . is equal to the reciprocal of the load
----·--f~( • resistance R.
Q. 18 Define Q point.
(a) Circuit symbol of a varactor diode
Ana.:
+Vee
Varactor is used as a· _T he intersection · of diode characteristics and load line is
/variable capacitance called as the Q~point. It is possible to change the position of Q
L
point as per requirement. Load line can be viewed as a· set of ·
infii:rite number of Q points.
~
' / L-~_.----~ Q. 19 What are the factors affecting the load line and Q
tankcirwtt point?
{h) How to use varactor diode in an LC tank circuit Ans.:
<F-101.8) Fig. 1.16 The factors affecting the load line and Q point are as
follows,
Varac:tor diodes are also referred . to . ~ .varicaps ?r
YOltacaps. The use of a varactor in LC tuned crrcwt ~ ill~~tt;d m l. . DC supply voltage . 2. Load resistance R
Fig. 1.16(b). Tbe resonant frequency of the tuned crrcwt 1s gtven 3. Temperature
by (without varac:tor), 4. Device to device parameter variations.
1 ...(1)
Q. 20 E~plaln piecewise lln~r model and DC load line
~ = 2n~ .
of PN junction diode. ·
Wbeo the varactor is connected in parallel wtth LC
COIDpooeoU as shown in Fig. l.16(b}, the resonant frequency gets Ana.:
moctified tot ,, The concept of the load line and the piecewise linear model
1 ...(2) can be combined together in diode circuit analysis. Considering the
f, = 2 n...ju.c + C,.) . piecewise equivalent circuit of Fig. 1.17(a) and assuming Vy =0.7
~ C,. is tbe variable tranSition capacttance offered by V and rp=O, v. =5V andR = lkn, .using the KVL,
tbc Yaractor V1 - Vy-IpR = 0 ...(1)
o. 18 ~ zero votta- .,.,.,.., height at an aThlloy
a. 02 V
Rearranging the equation to get,
.,....
germanium p-n Junction · ·
8 IR = -Vp+V1

I; ;1 : . V '• II Ill I I il II '•

 Bectronic Devices & Clrcults-1 MU) . line intersects the piecewise linear
The de • load haraCteristics at Q point as shown in
1 v. ....(2) approximated diode c oding forward diode current is IF :::: 4 3
:. I.: = - R"<Vr>+R .
Ptg. 1.1
?(b) The correspo
·
v - 07V
fun tion of v and R (as r- . olts). The
·
This is a straight line with a slope of - l/R. This is our load mA and it is onl~ the ill ~eep chan~ng when we ch~nge the values
line as shown in Fig. l.l7(b). The two extreme points A and B on position ofload line w. p· ll8(a) and (b) respectively.
tbe load line are obtained as follows : - of V• and R as shown tD tgs. .
Point A : Substituting Vi 0 in Equation (1) to obtain =
point A. It has co-ordinates of (0, 4.3 mA).
Point 8 : This point is obtained by substituting lp = 0 in
Equation (l).lt has co-ordinates of
(5V,OmA).

·V8 =5V +
.c
·:·~- ~~--· ~~~~-- - -~~·~·~.
.
· l "" ·
0.1V ·:
Ideal
diode
·...........

I····
r........
f l
......:········'1

IF
....................·...........-
j

(a) Piecewise Unear (b) DC load Une drawn on approximated circuit piecewise linear characteristics
. (F•31) Fig. 1.17
I (mA)

J.. . . L~.:~.... .... . ..!........: .........!.........~ .....Yf..c:fohs) !..?... .......J.. ... .~....:...l..... ~........! .... -~ . ..
........ J..........t... ..... ~: !:.......$.... '!.E ~'!olts)
.!......... .......

(a) Effect of Vs on load Hoe · (b) Effect of the values of R on the load tine
(F-32) Fig. 1.18

Q. 21 Give comparison of Ideal diode and real diode :

Ans. :

0.6 V for Si, 0.2 V forGe

diode
4. .Re.verse saturation current Zero Few DA for Si diode
Few mA for Ge diode
5. Equivalent circuit in the forward biased state
D .. D

(F-42)
(F-43)
~l~t-VWy-oK
·.

6, Equivalent circuit in the reverse biased state

High resistance
~
(F-45)

1: a •, 11 · s ll I II I I II II S
 -
EleCtronic DeviceS & Clrcults-1 (MU)

o. 22 calculate current "I" In the circuit of Fig. 1.19 If

both the dlodM are modeled by R1 • 10 Q and V
4-9

11 0•5 Vott. What de •ource ehould be placed 1~

eertea with 20 0 reeletor to Juet reduce I to zero ?

150 01 Co
(a) Complete equivalent circuit (b) Simpllfted equivalent circuit
+ (F-40) Fig. 1.21 : Small signal equivalent circuit. of a forward
3V 200
biased p~n jonction
,___ _ _ _ _.__ Loop 2
_:_:::__J ...i I
Fig. 1.21(a} . shows the complete equivalent circuit and
Fig. 1.2l(b) shows the approximated version of ,it Co is the
(F.St) Fig. 1.19
diffusion capacitance and CJ is the junction capacitance or
Ans. : ~ss~ng ~e voltage of the DC source ~quired to. be transition capacitance. As Co » C. when the diode is forward
~~ m ·~es WI~ 20 Q resistor is Vx. By replacing both the biased, it has.been omitted from the ~pproximate equivalent circuit
~ With their _eqwvalent circuits, the equivalent circuit are of Fig. 1.2l(b). The resistance rd is the ac incremental resistance
obtained as shown m Fig. 1.20. and the series resistance r5 accounts for the resistances offered by
neutral n and p regions.
150 100 o.sv 100 o.sv Small Signal Model·for Reverse Biased Diode =

sv~ 1711200 The small signaJ equivalent circuit for a reverse biased
diode is as shown in Fig. 1.22.Resistance r,· is the incremental
500 . • resistance when the diode is reverse biased. C,. is the transition
capacitance, The transition capacitance has a significant value only
Loop 1 Loop 2 Vx
when the diode is reverse biased.

<F-52) Fig. 1.20

1. . Apply KVL to loop 1 to write :

(F-41) Fig. 1.22 : Small signal model for a reverse bblsed diode
3 = (15 + 10 +50) I 1 - 50 I+ 0.5
.. 2.5 = 75 II- 50 I . ...(1) . Applications of Small Signal Equivalent Circuit :·

2. Apply KVL to loop 2 to write : l. It is used for obtaining t6e ac response of a diode circuit
0.5 + (10 + 20 +50) I- 50 I 1 =0 which is subjected to an ac signal superimposed on the de
signal corresponding to the Q point .
.. -50 II + 80 I = - 0.5 .;.(2)
2. For developing the small signal models of transistors,
SoJyjng Equations (1) and (2) to get, which are useful in analysis and design of transistor
I = 24.73 mA ...(3) amplifiers. .
From .Fig. 1.20, Q. 24 Discuss temperature effect on breakdown.
'3. Apply KVL to loop 1 to write : ~tentlals. I111W•U
75 II - 50 I = 2.5 .
Ana.=
But Vx is such that it will make I =0.
Effect of Temperature on zener BreakdoWn :
1.
. :. 75 II = 2.5
The diode is heavily doped. So the width of depletion
:. 11 =
0.033 Amp ...(4)
region is very small and the intensity of the electric field across it is
4. Apply KVL to loop 2 : high. If the temperature is increased, then the valence electrons will
-0.5- (10 + 20 +50) I+ 50 II - vX= 0 acquire additional energy and it will be easier for the external field
to pull such electrons by breaking the covalent bonds. Therefore a
Buti=0,:.-0.5-Vx.+5011 =0 smaller voltage is required for the breakdown to take place.
:. yx = 5011 -0.5 ={50 X 0.033)- 0.5 · Therefore the breakdown voltage decreases with the increase in
=
1.15 Volt ...Ans. temperature. ·
Q. 23 Drew and explain small signal model of a forward The zener breakdown is said to have a negative temperature
and reverse biased p-n junction diode. What Is · coefficient as V DR decreases with increase in temperature. For a

the main use of this model ?

1 10
*• 4
zener breakdown, the ·breakdown voltage decreases with the
1
increase in temperature.
Ana.: 2 Effect of Temperature on Avalanche
. The $D1all signal equivalent circuit of a forward biased p-n Breakdown:
JUnction is as shown in Fig. 1.21. In the lightly doped diodes, the depletion region is wide and
· field intensity is low theref. . for such'diodes the breakdown takes
place due to the avalanche effect.

1': a:. II '• II 1111 IIIII S

 4-1o
4co;
Electronic Devices & Circuits·! (MU)
With increase in temperature, the atoms start vlbra~ng .wi~ Ana. : · . ~- drop (VF) :
larger amplitudes. This will decrease the possibility of JOtnnSIC Forward vo·-- .
1. ode to cathode voltage measured across
electrons imparting sufficient energy to the vaJence electrons. S~ a . ~~ T -~ a
It JS •od
It is denoted by V p· YPJC Y the value Of
luger voltage is required for initialing .the process of p~er
multiplication. 'Iberefore the breakdown voltage increases Wtth
forward b~~sed di_ :·is between o.-7 V to 0.9 V whereas VP for the
i~se in temperature. The avalanche breakdown is said to have a
Vp for a Silicon diod from 0 3 to 0.4 Volts.
. diode r~ges · ·
positive temperature coefficient. For the avaJanche breakdown, the German•uro f't-- VF 4
breakdown voltage increases with increase in temperature.
Q. 25 Dltrerentiate Silicon and Germanium diodes .
Ana. :
R

. _· t . 1lo ·-''

I. Material used Silicon

2. Cut-in voltage 0.6 V (F-37(i1)Fig• 1•23 .• Forward voltage drop
3. Reverse saturation In nanoamp (less) Maximum reverse peak voltage (VRRM) or PIV:
current
· tbemaxun·urn reverse peak voltage
It 1s · that ycan be aPPlied
4. Effectof repeatedly across· It is same as Peak Inverse oltage (PlY).
Less Maximum reverse de voltage (VR) :
temperature
This specification specifies . the· ~urn reverse de
5. Breakdown voltage Higher . Lower .voltage that q_an be applied across the diode.
6. Applications Rectifiers, clippers Low
clampers, . voltage 4: VRSM:

freewheeling Low
It is ihe maximum·reverse :Peak
value of tbe nonrepetitive
voltage · that can be applied across · a diode without
temperature
applications damagmgit. · .
5. Maximum forward current (lq) :
Q. 26 Give applications of p-n junction diode :
It is defined as the maximum value of forward current that
Ans. : 1be applications of a p-n junction diode as follows : are. can be allowed to pass through a forward biased diode without
I. Rectifier circuits · 2. Clipping and clamping damaging it. This rating is also called as peak surge ~urrent rating
cjrcuits and it is specified only for 1 cycle of input ·ac waveform. It is a
3. Voltage multipliers 4. A. M. detection nonrepetitive current rating.
· 6. Reverse saturation current ~
s. Feed9ack di.odes 6. Freewhee~g diodes
The reverse saturati~n current 10 is dependent only on the
7. Log and antilog 8. Precision rectifiers using · ·temperature and independent of the applied voltage. 1 for the
amplifiers using OP- OP-AMP. 0
Silicon diodes is lower than that for the ·G ermanium diodes. Hence
AMP.
they are preferred. 10 for Silicon diodes is few hundred
Q. ZT For the diodes, ·define forward voltage drop, nanoamperes, whereas that for the Germanium diodes is few tens
maximum forward current, dynamic resistance, . of microamperes. ·
rever.e saturation current and reverse breakdown 7· Dynamic resistance :
voltage. Dec.2014. Dec. 2016 .. The_ resistance offered by a · diode to AC operating
con~tions ts known as the dynamic resistance or ac resistance of
the diode.

Chapter 2 : Clippers and Clampers

Q. 1 What Ia clipping circuit? Types of cUpping circuits :

Ana.; 1. Series clippers • In thi · . ·
· ·· . . • s configuration the diode IS
1be clipping circuits using di~s have_ the abi~ty t~ "clip" connected tn senes with the load.
2.
off or remove a portion of the input s1gnal w1thout distorting the ~~el clippers : In this configuration the diode appears
remaioiQg part of the waveform. Clippers are also known as m a ranch parallel to the load.
limiting circuits.
Q. 3 Write shon note on series negative clipper
Q. 2 What .,. the types of clipper circuits ? clrculta, working and waveforms. . .
May 06. Dec. 07
The diode clipper circuits Cllll be of the following types.

~6iai.~tikii~~i.~iibiiffi·om~ii•i••i••iii&~----------------------------~----------------------------------------
 Electronic Devices & Clroults-1 (MU) 4-11

.....,
~0~~--~---,--~

(a) A series ntgatlve cllpper

(F-1152) Fig. 2.3 : Wavefonns for the series positive cOpper with
non-sinusoidal Inputs

Output
voltage Diode OFF
-10
o~~nu~~+-~~~~+-~ 10 V~volts~
Diode ;
ON~
................. -10

(a) With an ideal diode

The basic configuration of a series negative clipper is as
shown in Fig. 2.I(a). The diode used in this configuration· is
assumed to be an ideal o~e. This clipper is called as a "series Diode OFF
negative clipper'' because it. "clips off' the negative half cycle of
the applied voltage. ,
Operation of the series negative clipper :
The series negative clipper shown in Fig. 2.1(a) is nOthing
but a simple half wave ·rectifier circuit The waveforms for the
same are· as shown in Fig. 2.I(b). In the positive half cycle of the
sinusoidal input, the diode is forward biased. Being an ideal diode,
(b) With a non ideal Silicon diode
it acts as a closed switch and connects the load directly across the
input (F-1153) Fig. 2.4 : Transfer characteristics

The load voltage is therefore equal to the input voltage in The transfer characteristics of a series positive clipper with
· the positive half cycle. In the negative half cycle of the input, the ideal and non-ideal diodes are as shown in Figs. 2.4(a) and (b)
diOde is reverse biased and acts as an open circuited switch. The respectively.
load voltage is ·therefore zero during the entire negative half cycle. Q.5 Explain biased series negative clipper :
The negative half cycle is thus "c)ipped off' or "shaved off' by the
series entire negative clipper. Ana.:
The addition of a DC supply in the series clipper is as
a. 4 Write short note on series positive clipper
shown in Fig. 2.5. This will have an altogether different effect.on
circuits, working and waveforms.
May 06. May 07. Dec. 07
.
the output voltage waveform of the clipper.

Ana.:
The series positive clipper configuratio~ is s~~wn ~ Fig.
2.2. As shown in the waveforms of Fig. 2.3, the positive std~ of
each waveform has been clipped off, because now the diode
conducts only in the negative half cycles.
D (F-1154)

Fig. 2.5 : Series cUpper with a DC supply

Operation:
The OP,eration of this circuit can be divided into three
intervals. The diode is assumed to be ideal.
Or-1151) Fig. 2.2 : Series posidve cUpper 1. Operadon when VIn is posidve but less than V :
In the positive half cycle of the input as long as VIn< V, the
diode does QOt get forward biased. Therefore from 0 to t 1 and then
from ~ to T/2 'in Fig. 2.5 the diode will remain in its OFF state and
the output voltage will be zero (Fig.2.6). · '

P.<t:>V·SIIIIII I IIIIS
 4-12
Electronic Devices & Circuita-l MU V the diode will be forward biased and the
For V1n < •
2. Opention tor V"' poslth:e and greater than V : output voltage is given_t>Y·v + V .
At the instant "t.", the positive input voltuge is exactly Vo - In • • ff d
equal to "V' Volts and the voltugc across diode D is zero. After V the diode will remam o an tbe output
When Vin >
that the diode is turned ON and remains ON until the positive input
voltage will be zero.
voltage is higher than V i.e. up to instant"~", as shown in Fig. 2.6
and the load voltage is V0 =(V10 - V).
3. Operation for V111 negative :
When VIn is negative, the diode is reverse biased and
therefore remains OFF. The load voltage is zero during the entire
negative half cycle as shown in Fig. 2.6.

v ....l...., 1 I ' Input ~tage !.. .; . ·I . [... 1. ...! ~

.,..., ...; ......... I ,_,..,.,, ................ 1.......... .... ..........! '
i ' Tf2 i !V i
;t, i JT I i !
• ... :..... . -i· ..i .. +· :i" "j

v.-~.-~ - i : ;~1 -~~H- H-=i:f=!--:1

0 '· ....:t: ~.~~.l 1~..t.~.!-.·:~.?.~-.+.:+::.~[J:.:J.:·.tj
...
Complete negative haH cycle and a part of positive haH oycle.ls clipped off
.. 'JJ. ._
(F-1151) Fig. 2.6 : Waveforms ofbiasectseries negative clipper

Trausfer characteristic : (a) waveforms and equivalent circuits Tor a biased series
TIM: transfer characteristic of tbe biased series negative positive clipper
clipper is as shown in Fig. 2.7. The output voltage is given by,
V0 = 0 ...For(Vin~V)
and V0 = V in- V ...Fot V;n > V
V0 (volts)
Diode ON

DIOde
OFF (b) Transfer characteristics
(F-1159) Fig. 2.7 : Transfer characteristics (F·3569) Fig. 2.9

Q. 6 Explain biased series positive clipper. Q. 7 For the clipper circuit shown in Fig. 2.10 sketch
Ana. : The biased series positive·clipper circuit is as shown in
Fig. 2.8.
the input and output waveform. Write
for V0 •
inFiP
• •

D
T~l----+---0+
vii
lo--_ _._.~
<F-3568) Flg. 2.8: Biased series positive cOpper (C-4823) Fig. 2.10

The diode will be off and hence equivalent to an open

circuited switch in the whole positive half cycl~ of _the input and
for a part of negative cycle of the input as shown m F•g: 2.9(a).

tis IIM'M111" 1111111

 -
EJecttoniC Devlcea & Circuita-l (MU)

A na.:
3V
4-13

V0 a V1+ 1.6V ...when 0 II ON

V0 a OV ...when D Ia OFF

-Diode ON

0~--~---------~--~~~~~
Diode OFF

1----DiodeON •14 DiodeOFF-j

(C-4815) Fig. 2.11 : Input output waveforms

Q. 8 Draw output waveform for circuits shown In o: 9 Write short note .on parallel poaltlve clipper,
Fig. 2.12. . . . .p working and appilcatlons rvla 06. Dec 07
An~.:

~u·
In the parallel clipper circuits, the clipping diode ~

,,..
. 1v T v
...s-6ftf2. connected in a branch which is parallel to the load as shown m
Fig. 2.14. ·The d,iode is assumed to be an ideal _one. Resistor R
. nttzllne+ i controls the current flowing through diode D. Thus it is connected
as a currept limiting resistance.
A
(F-4687) Fig. 2.U

AnL:
Output wavefonn for circuit
1. Output waveform for circuit
(F-1168) Fig. 2.14 :Parallel positive clipper

O~ratlon with a slnusoldallnput voltage :

1. Operation in the positive .half cycle:
In the positive half cycle of the input voltage. diode D is
forward biased and therefore conducts from rot 0 to n. Becau~ =
the output voltage is equal. to the voltage across the diode the
output voltage will therefore be zero in tbe positive half cycle of ·
2. the input voltage as shown in Fig. 2.15. the positive half cycle is
thus "c.lipped off'. ·

Output
voltage
0~~~~~~~~~~

(F..-J) (a)
(l-i69l)(b)
·rs ID +
-
A

............-
-1~.
+-
·A

-v,
l. !+
(F-11") Fig. 2.15: Waveforms and equivalent drcults
Fig. 2.13

I. 'I'. V ' II 1111 I II II '•

 4-14
Electronic Devices & Circuits-! (MU) on ·. Biased negative clipper :
Q.12
Write a short note. .
2. Operation in the negative half cycle :
Io the negative half c9cle, the diode does not conduct and Ans. : . ws the circuit diagram of a. biased negative
· therefore. acts as an open switch. The load voltage is equal to the · Fig. 2.18(a) sho . alled as the external btas. The diode is
instantaneous input voltage as shown in Fig. 2.15. Thus_ ~e ~~&
. 1be de source V JS c .
negative half cycle a~ars as it is across the load. As the pos~~ve ed o be an ideal one.
assum t . A
half cycle is "clip~ off' this circuit is called as parallel pos1ttve
clipper. The operation is mathematically expressed as follows :
V0 = 0 · ..... V1 ~0
V0 -= V1 ..... V1 <0.

Q. 10 A pOsitive shunt clipper circuit having a ±12 V

square· wave input. Sketch the output waveform
for the circuit. · · l•l§Wtj .lS(a) : Biased negative clipper
(F-1173) Fig. 2•
Ans. : The required waveform is as shown in Fig. 2:16.
Operation:
vo Mode· 1 .• For V1 positive :
• ·u· e diode D is reverse biased and acts as
Wben v . 1s pos1 v ,
I •

an open switch . . lta

The output vqltag~ is equal to the mput vo ge.
. . v. o = v.
.. I

(F-47Si) Fig. 2.16

Mode 11 : v. negativ~ but higher than V :. .
'd · a portion of the negauve
CODSI enng . half cycle. of V1, m ·
Q. 11 Explain parallel negative clipper . which V; is higher than V. So the diode remams reverse bJased.
Ans.: :. V 0 = V1
The parallel negative clipper is shown io Fig. 2.17(a). Mode 111: V1 negative and less than V:
The diod~ will ~ooduct only in the negative half cycle of As v. becomes less than V in the negative half cycle, the
the input to clip it off. The positive half cycle will appear as it is diode turns ~n. It acts as a closed switch This will connect the de
across the load. With an ideal diode, the output voltage is
source across the output terminals.
mathematically iiven by,
The output voltage is equal to ~ V
Yo = V1 • ..... forV1 ~0.
and V0 =· 0 ..... forV1 < 0.
:. vo
= - v
Fig. 2.17(b) shows the input and output waveforms with Waveforms : Fig. 2.18(b) shows the waveforms of a biased
ideal and non ideal·diodes. negative clipper with an ideal diode.
R
~-·· t
: i .
Input
vottage ~'-'-------~-+-'~----+---..i-T-:.._...,o!. t : l. l
V;

(F-1171) Fig. 2.17(~) :Parallel negative clipper

•• ••y•• .,.•• •• •• ••.••• , ....................... .. ...... . ...... " .... . . :..... l

·tj J.::
' .. ~ . . . , .
Output
i . ;

...
W-ll77) Fig. 2.18(b).: Wavefo~ of·biased ~tive·cupper _
13
Q. Explain biased positive clipper with ideal diode:
Ans.:
The circuit di:urrun 0. f . .. . .
Fig. 2.19(a). Th~ di~ .......i a btased posttive clipper ts shown JD
wavefoims for the . . s ~sumed to be an ideal one. The
along with the smu~l(lal mput are as shown in Fig. 2J9(b)
corresponding equivalent circUits.

(F-1172) FJg. 2.17(b): Waveforms or negative clipper

~6is~5~mmi-itii•i"i~i·~•imJii•m•·i•·miai~------------------------------~------------------------------------------
 Electronic Devices & Circuits-1 (MU)
4-15

·rFl.
A

(F-1180) - I J
Fig. 2.19(a) : Biased positive parallel clipper

Fig.·2.20

Q. 14 EXplain with neat waveforms,

following circuit :

I
(F-1306) Fig. 2.21

(F~1181) Fig. 2.19(b) :Input, outp~t wavefonm aiid equivalent Ans.:

circuits for a biased positive parallel clipper
The diode will conduct only from t = t1 to t = tz, when
V1 ;;::; V. When the diode is conducting the output yoltage is equal
to V. For Vi < V, the:: diode is reverse biased and turned off. So V0
=Vi as shown in Fig. 2.19(b).
Transfer cbar8c~tic :
The transfer characteristic is shown in Fig. 2.19(c).
The circuit diagram of a two way biased parallel clipper is
as shown in Fig. 2.21. It is going .to clip both th~ half cycles .of
input due to the presence of diodes D 1 and D 2 ~ the ~te
directions. Both these diodes are assumed to be tdeal diodes .
Fig. 2.21 shows Two way biased parallel clipper
1. Operation in the positive half cycle : '
In the positive half cycle, as long as vi < v I• diode Dl wiD
be reverse biased whereas D 2 is reverse biased during the entire

<F-1182) Fig. 2.19(c) : ~~er characteristics of a biased

positive paraUel cUpper
(F-1188)
. Biased positive clipper with non. Ideal diodes : . . .
Fig. 2.22 : Input and output voltages for a two way
H the diode is assumed to be a non 1'deal silicon diode then
. . 1 ·bile conducting. So the output {W'8llel clipper
voltage drop across lt IS 0.7 Vo ts W • tead of V volts as
voltage will get clipped at (V + 0 ·7>Volts ms
shown in Fig. 2.20.

e asv S OIIIIIOII S
 1
Electronic Devices & Clrcults-1 (MU)
KCL at node Vt:
It+~ = ~
V 1 -V2
9.4-Vt +Y, 6 =
:. 2000 + 50 50
-3 x 1<J 4 v, + o.o88 =0.166 v,- 0.166 v
:. 4.58 X 10 - 4· 88 . 2

.. 0.16; vl- 0.166 v2= 0.09258 ...(1)

<F-llU) Fig. 2.23 : Transfer characteristics for the two way

KCL at node Vz:

parallel clipper
2. Operation in the negative half cy'cle : 4
. . .O y -0.02 V - 0.012 =5 X 10- Vz +2.5 X 10- 3
Diode D 1 will remain OFF throughout the negative half 0.166V1 - . 166 2 - 2
cycle. However D2 will be turiled ON when Vi ~ V2·• As long as D2
.. 0.166 Vt.- 0.1865-Vz= 2.5 X 10-3 ...(2)
is. conducting the output voltage is ~qual to - V2 as shown in
. F~g. 2.22. And wben·D 1 and D2 !>9th are OFF, the output voltage is
equal. to input voltage and it is negative. The input and output Step 3 : Calculation of V 1 and V 2 :
voltage wavefonns are as shown in.Fig. 2.22. Solving Equations (1) and (2) to get,
Transfer characteristics :
v 2
=
4.394 V and V 1 =4.92~ V .

It is tbe graph of input voltage pl~tted on the x-axis and Both the diodes D 2 and D 3 will -be off. So· current through
output voltage plotted on the y-axis _as shown in Fig. 2.23.
them will be zero._
Q . 15 The cut-In voltage for each diode is 0.6 V. 9.4-V1
Detennlne V1 and V2 and ·each diode current If R1 IDI = 2050
= 2 leO, R2 = 6 ~· R3 = 2 kQ. itl§i•fi 9.4-4.922 -2184 mA
= 2050 . - · .

Q. 16 State applications o,f clippers • . ·~-

·Ans: : The applications of clippers ~ • _
I. . It is used in Waye shaping circuits and function generators.
2. To clipp off (remove). a part of input waveform without
+5V distorting the remaining waveform.
<F·l289) Fig. 2..24 3. As a diode clamp to protect sensitive electronic circuits.
This cin;uit is a combination of positive · and negative
Ana.: parallel clippers.
4. As a combinational clipper;
S1ep 1-: Mark vario-Ds branch currents :
Q'. ~7 What are clampei'S?
Ans.:
. · The "dampers" are used to clamp the input ~ignal t~ a
~erent de_ level.· ~ other words, clamper adds a de voltage to -the
stgnal_ applie~ at tts. input. A clamping circuit is made from a
" +5V
capacttor, resistor,
Tbel . .diode and . sometimes an additi'onal dc surce
o.
1F·U90) Fig. 2.24(a) · c amper CHcwts are u~ to "clamp" the input signal to a
A,Pplying KCL at nodes V1 and V2 : different dhac level. The ac input signal can be sinusoidal or it can
Step2: take any- s pe.
10-V1 -0.6 9.4- V 1 Typea of.clampers :
. II = RI+RFI 2ill+RFI' Clampers are
of ~0 types :
1. Positive clamper 2. Negative damper·
0 - V2 -0.6
= Q.18 Draw and e~plaln poSitive clamper circuit
'" RF3
5- v, -0.6 4.4
Ma 08. Ma 11 . Ma 13. Dec. 14
Ans. :·
~ = RPl R Pl '·
Fig. 2.25 shows the · . . -
v,-v2 The clamping network wi~lfCUtt diagram _of a positive damper.
13 = 60 '
namely a capacitor a diod alwa~s conSist of three elements
' e. and a resistor.
Assumptions : ·
·v2 +5 _ V2 +5 _
I, = Before analyzing the 1 · . .. .
~ - 2 k.Q following assumptions are d c amper cucu1t of Fig. 2.25.
rna e,
Assuming. Rl'l = RPl = Rr·'3 =50 .Q 1. The input is a perfect sine
waveform

1: a ~; V - S ll Ill I I f) II S
 ..
EJectrOnlc Devices & Circuits-! (MU) .4-17

:z. The values of R and C are chosen such that the time Ana.:
constant 't == RC is large enough. ·A negative damper will add a negative de level_to ~e in~ut
3. The diode is an ideal one. signal. Fig. 2.28(a) shows a simple neg~ve damper ~cwt whtc~
4. The RC time constant is much longer as compared to one adds a negative level to the AC input R 1s the load reststance.
cycle period T of the input.
c
0 RC>lOOT
~I
1)1
1
'~•t
(F-3579) Fig. 2.28(a) : A clamper ·c ircuit

(F-1200) Fig. 2.25: A positive damper Operation : ·

. In the first positive half cycle the capacitor will charge
Operation: through the forward biased diode to peak vol!_age V m.• The
In the first negative half.cycle after turning on the circUit. charging 'takes place very quickly as the diOde resis~ce ~s
tbe diode acts as a closed switch and charges the capacitor to peak negligibly small. Once the capacitor charges to "Vm", the diode tS
input voltage V m • In all the subseq~ent positive and negative half reverse biased and stops conducting. The diode is reverse biased.
cycles, due to large RC time constant. the capacitor does not lose So remains off.
much cbarge. So Vc almost remains constant. The diode is reverse The expressio~ for output voltage is given by,
biased in both half cycles, therefore it reuiains off. Vo== Vi- Vm .
The expression for V 0 is, "-r' (F-U04(a))
"---+ Negative DC shift
v0 =vi + v m (F-l20l(a)) . This shows that the negative damper adds a negative DC
-c. Positive DC shift. shift. Fig. 2.28(b) shows the waveforms for a n~gative damper.
' ""'('"'''": ···

This shows that the damper adds a positive DC shift. The . .J

input output waveforms for a positive damper are shown in !
... ·t ........~. ."'";....

••
F.g. 2.26.

c:IJ~r ·· :
II

• ..i.......(

(F-1205) Fig; 2.28(b): Input output voltage waveforms fQr a

-...... ... ... ·······:·····..(.......•.;
--~-- ..;, ,
negative damper '
:___,.:____ ;.._.....:.....;,......
Q. 21 State appUcations of Clampers.
<F·Uoz) Fig. 2.26: 'Input output waveforms of a positive
Dec.02. Dec. 04
clamper
Ans. :
0.19 A positive voltage clamping circuit ~ave a± 12 V The applications of dampers are as 'follows:
square wave input Sketch the output waveforms
for the circuit l•l§Mij 1. In the voltage multipliers, which produce ouqiut voltages
equal to. multiples of input voltage without using a
transformer.
Fig. 2.27 shows the required waveform. 2. In order to provide de shift to the input waveform.
a. 22 Sketch the output waveform for Fig. 2.29.1111MII

...:b___,
(F...f15Z)Fig. 2.27
-15Vru ~
. ~...~
Q. 20 Draw and explain negative clamper circuit.. (F·26Sl) Fig. 2.29
· · lti§Miel

1: a :. 'J ' • II 1111 I II II ~

 4-18
Electronic Devices & Circuits-! (MU)
clamper as shown m Jg. 2·
. Pi 35. In the positive half cycle V0 =12 v
Ans.:
and V =5V.
The capacitor will be charged to - 13 Volts with the "' Assuming an ideal diode.
polarities as shown in Fig. 2.30
Vo = Vm+Vc
.. 12 = 5 + Vc
.. Vc = 12-5=7V
ButVc = Vm +V
.. Ym+V = 7V
(F-2653) Fig. 2.30
. V = 7 _ vm =7 - 5 =2Volts.
H~nce the output voltage is given by ••

V0 = V1 +13V Vc=Vm+V
-... + .
Hence the output waveform is shifted by 13 V on the
positive side as shown in Fig. 231 .
R·
v.
2Volts

(D-1581) Fig. 2.35. : Proposed circuit

In the negative half cycle,

V
0
= 2 Volts. ... as per given V0 wavefonn.

In the negative half V0 from circuit is,

Vo = V 2 Volts =
... as D is on.
Thus the circuit of Fig. 2.35 produces the required output
waveform.
Q . 24 Identify the circuit and draw output waveform with
proper voltage levels. Refer Fig. 2.36. Mill

·w~f t~ I·~ r
(F-2654) Fig. 2.31 : Input output voltage

Q. 23 .Implement appropriate circuit to generate the

waveform as shown In Fig. 2.32 1MM101
<F-4714) Fig. 2.36

Ana.:
The given circuit is a biased damper circuit. The output
voltage waveform is as shown in Fig. 2.37.
.Vo = V.m - V c
(B-2644) Fig. 2.32 : Output voltage
But Vc = 7 v
Ans.: .. Vo = V~n-7V
Assuming that the input voltage to this circuit is a square
wave having zero average v,_Iue as shown in Fig. 2.33.
. . . v. o
"--·;........

...... ._.J.~-"--~-r--r--:-_.:_-H--+-+-~.
i I
...,..._....._......,.
,, r J_.,....,.._.,_....;.,i
; i
............. . .. l .
.. {
;. ! ~ f •

·:.·:!Y.. ~-~'i[--~~-~~
i
~~-~:_·.~~~.:_.~:~. -~-~-~-'~.....J::
i''""'
...:. ..a..• J
1
.. .. L..)
1·

·! --··--k; ;
... ; · f... ~' "'i.... ...~- ~ ··+. · -·t l 1
. -1'N "-·--~- '
.._....t........... ...L
. . :.. . ..,. . . . . . . . .:.t . . . .:·.__.......~····· .... :.,. :~ . . ~j .......... _!
;.....q+··--

Fig. 2.33 : Input voltage (1)-1580) Fig.l.34 (F-4'1J> Fig. l.37 : Output voltage waveform
The input/output waveforms shows that there is a DC shift
of+ 7 Volts, because the average voltage of the output waveform is
+ 7 v as shown in Fig.2.34. Hence this circuit must be a biased

e a s V · S OIIIIIOII S
 £ectronlc Devices & Clroults-1 (MU)
4-19
o 25 Explain the difference ..._....__
• onr....._n clipping clrculte and clamping ctrculte.
An.. :
~~ Parameter .
I. Components used
CUpper ca.mper f,

Diode, resistors Diode, capacitor, resistors.

2. Function
To remove u part of Input to add a de shift to the input wavefonn.
wavcfoml.
3. Frequency of input
Not important us capacitor i:; not The value of C needs to be chosen on the
used. basis of input frequency.
4. Applications
~~od~ clump, wave shaping Voltage multipliers.
CII'CUJtS.
5.

:.*+r
Configuration

~~
(B-1844)
0 I 0 .
(B-1845)

Chapter 3 : Bipolar Junction Transistor

Q. 1 Draw construction and ~ymbol of p-n-p and n-p-n transistors,

Ans.:
n-p·n Transistor p-n-p Transistor

E c
(Emitter) (Collector)

B (Base} B(Baoo}
(a) Construe~on

v
(Emitter)

B(Base)

(B-163)
C
Coll~ctor}

(b) Symbol
(Emitter)

Fig. 3.1 : Construction and symbols of tr~istors

T
E~ (Collector)
C

B(Baae)

Q. 2 Why Is BJT called as a Transistor ? 0. 4 Explain construction of BJT.

Ans.:. Ans.:
The term "transistor" was derived .from the wor~s The structure of the p-n-p and n-p-n transistors is as shown
TRANSFER and RESISTOR. This tenn was ad~pted because It in Fig. 3.2(a) and (b) respectively. The n-p-n transistor is formed
best desc ·a.:- th ration of a tiansjstor, which IS the transfer of by sandwiching a thin "p" type semiconductor between two "n"
nucs e ope . 't to a h'gh1 type semiconductors whereas ·a p-n-p transistor is formed by
an input sigDaJ current from a low resistance ctrcut
resistance circuit. sandwiching a thin "n" type semiconductor between two p type
semiconduc~ors.
Q. 3 Why Is BJT called a "Bipolar" Transistor? In both the types, base comes in between collecto.r and
Ana.: emitter region. Base is always a thin and lightly doped layer.
Emitter and collector layers are much wider than the base and are
The conduc ti.on 1.0 a bipolar junction
•
transistor takes place
h 't ·s caJied as a heavily doped. To be precise, the emitter is the most heavily doped
due to both electrons and holes. That ts w Y 1 1 ne layer because it has to emit or inject electrons and the collector
1
"bipolar" ~sistor. If the condu.ction takeths ptla.ceansi~~:r ~ ~:lie: as area is slightly larger than the emitter area. The collector area 'is
. . ·
type of earners J.e. maJon 'ty earners then e r
. device is the field largest because it is required to dissipate more heat. The transistor
"unipolar" transistor. The example of a umpo1ar has two p-n junctions namely the collector base junction and base
effect transistor (FET). emitter junction.

e a s v-s olutlon s
 4-20
Electronic OeYioee & Circuita-l (MU)
"'
Numbef of P"'f'' Junotlona and equivalent clrcutta :
. . As sbo~ in F"t.gs. 3.2(a) and (b), a transistor bas two p-n
JWIC(IOOs ~ BE (Base to Emitter) junction and CD (Collector
to Base) Junction. A p-n junction is represented by a diode.
~ the P-O-p and n-p-n transistors are equivalent to two
diodes connected badt-to-baclt as shown in Figs. 3.2(a) and (b).
. n BE p CB · n
Emitter ~Collector .
~-·_··•--~
- lt'L+~------~
•ElectiOOII
VEE
Base oHoles

(a) Equivalent for n-p-n transistor (b) consti~tion of emitter current

BE • n CB Coll&dor current

~Collector
Base
Emmer

Base
..
E
(b) Equivalent for p-n-p transistor
.......
(B-IU) Fig. 3.2
Q. 5 Explain bale principle of operation of BJT with
the help of construction, minority carrier
dlatrlbutlon and energy band diagrams.
Ma 14. Dec 15 Emitter electron current . Base elec:lron current
duato ~blnation
Ana.:
· (c) Constitution of base and coUector currents
The positi~e supply VEE will forward bias the base-emi~r
. (B-169) Fig. 3.3 .
juncti.oo and the .voltage Va:. will reverse bias the collector to base
junctioo as shown in Fig. 3.3(a). Thus the Ni>N transistor is biased 2. Some of the electrons diffuse through the base and
to operate in its forward active region. Hence 'tlie width of · out of the base connection. ·
depletion region for B-E junctiQn is very small, but that at tbe C-8 · 3. The remaining large number of electrons will pass
juoctioo is large. . through the depletion region of CB junction and
pass through the collector region to the positive end
•• --•••••• --.-.:::,,..••••••• Doplellon rogione of tbe external power supply V~ as shown in
~ Fig. 3.3(d). The coUector current Ic is much
larger than the base current (about 98% or total
E c .emitter current).

BE~ - LCBJuncllon
Fcn.d bUsj -blued e c
-v,.~+
'-------1 .,
8 - vjUt••,t-------'
+

VEE ... 8 Vee flc

- I;r·-··_. ._.•_~e_._____:-::..l•~t-•.:...__-f--~..J-
!_
_
OJ-la) Fig. 3.3(a) : Transistor (npn) biased to operate ~.....
in the active region
Eleolron collolcmr c:unant lc
Operation:
(B-t,O) Fig. 3.3(d): Operation of the n-p-n transistor
1be sequence of operation for an npn transistor is as follows : .
Step 1 : The electrons which are the majority carriers in the n- · Q, 6 State the configurations of transistor.
type emitter will start flowing towards the p-type Ans.:
lwe as shown in Fig. 3.3(b). This will constitute the
emitter cwrent Je. The common terminal can be base, emitter or collector.
~
S&ep 2 : EJcc::trom moving from tbe emitter to base have three pending on which terminal is made c~mmon to input
- and
option~ as follows:
outp~t port there are three possible configurati'ons of tbe
J. They recombine with the boles present in the base. transistor. They are as follows :
AI the base region is thin and lightly doped the
numbu of bolu is few. ~ out of the total 1. Common Base (CB) configuration
injected electronJ from the emitter a very few 2. Common Emitter (CE) configuration
recombine witb lbe bo.le.s in the baae resion. This 3. Common Collector (CC) configuration
COMtUIIta lbe bale current fa. Thua base 0.7
c.urnat now. due to recomblnadon'a of
~ ud boles. The base current ia therefore
small u compared to the emitter current {typically
2'*' of total 1£). Tbia is shown in Fig. 3.3(c).
I I ' 1 •, ltfllltil lt '•
 a.ctromc Devtcee & Circuita-l (MU) 4-21

AM.:
Current amplification factor
~ configunttioo for the n-p-n and p-n-p
"'IlK; common
Q"lll5lsron •s as shown 10 Figs. l~a) and (b). Ic ...(8)
~ Ro ~=rB

Q.8 Explain Input characteristic of 1 trlnalstor In CB

mode.
Ana.:
ea. The input characteristic of CB configuratioo is as shown in
common Fig. 3.5.
I. The input characteristics is identical to the forward I-V
(a) eo-oa base coaftgnntion tor n-p-n transistor.
characteristic of a p-n junctioo diode. This is because there
Re Rc is a p-n junction between the emitter and base of a
tTansistor and it is forward biased.
Emitter current
Ie{mA) Vca= 8V
Yca=4V .
Input .dVBE 1
f ... ........................... resistance ri = Me = Slope
(b) Ceulmoa base conftgu.ratiod'for p-n-p transistor Mt:
(B-175) Fig. 3.4 ~...................... .

1. 'Ibe collector cwrent Ic of the common base configuration

is gi\'eO by,
lc = Ic(INJ) + Icoo ...(1) 4Vae
1. 1c (INJ) : It is called as the injected collector Cllrrent and it is (B·l79(a)) Fig. 3.5: input characteristics of traosistor in CB
due to the number of electrons crossing the collector' base
junctioo. configuration
3. lao : This is the reverse saturation cllrrent flowing due to 2. Up to the cut-in voltage, the emitter current increases
the minority carriers between collector and base when the gradllally but after the cut-in voltage it increases "rapidly in
emittec is open. 1coo flows due to the reverse biased response to a small increase in the input voltage V EB·
.collector base junction. As Irno is negligible as compared 3. The input resistance "rt of the transistor in CB
to Ic (00) . It can be neglected in practice. configuration is defined as :
. . lc = lc<INJJ ...(practically) ...(2)
and fc Icoo = ...(with emitter open)...(3) ...(1)
The name JCoo shows : r; = Me constant VCB

Ice 0 (B-177) Input resistance can be obtained from the input

T..EmiUer Is open
l ColeQior to base current
characteristics. It is eqtial to the reciprocal of the slope of
input characteristics in the linear portion of the
characteristic.
Since lcao flows due to thermally ~enerated minority
l
cauiers it increases with increase m te~rarure. It : . • r; =
Slope ...(2 )
doubles• its value for every lO"C rise in temperature.
The value of r; of CB configuration is very small.
4. CllrreDt aanplifk:ation factor or current gain («etc) :
The ~ amplification factor or current gain is the ~o
4. Effect of Vca (output voltage) on the input .
~ cunem to the total input current For a CB configuratJon, characteristic:
lc~the output current and 1£ is ootal input cwrent. . As shown in Fig. 3.6, the emitter cwrent increases slightly
with increase in the output voltage VCB' 'Ibis happens due
lc<INil ...(4)
.. <Xdc "" r;- to a special phenomenon called ·~Early Effect".

..J fi CB configuration will always be less le(mA)

The value YJ <Xo~c or · because
IbM l 1bj$ lS
. of a ranges between 0.95 to 0.995
. ·
~. < f:t.. Typjcally the vaJ.ueof.&.a b~• reg~lOll Larger the thiclaless .... ..................,....
devtwting 00 tbe dlieknesi WI> - - • ~t......................... ·
~ lk base. unaJJu iJ me value of adc. Emitter current
From &,uatloo (4) • lnavaaes slightly
...(5) due to inoreaee In
lc <lHJ) • • a* 1£ . . v08 at oonllant .....-::::;;._..._"":":"'--_. V8 e{V)
Heace the expreuioo for lc u Jiven by, V8E due "> Mrty elfed
...(6)
1c .. a.ls + la-o
Bur fceo ia negligibly unalJ. (IloilO) Fta. 3.6: Effeet of Vca (Early effect)
...(7)
.. Ic .. awls
I I J ,, I II I I ,, II '•
 That is why the voltage drop across a ttansistor (V()!)~
Electronic Devices & Clrcuits-1(MU)
Q. I Explain. outpUt charactMf1ttoa of tnn111tor In CB Jar e in the active region. . .
conftgu,.tton. Sa~ratlon region : Both th_e JUn~tlons are f~ard bii!Sed
6. . rder to operate a tranststor reo;""
AM. : 10 0 . . 10 the saturation
ds C>'v...
Therefore the saturatiO? r~gton correspon to negative
Output cl:l~sdc of any circuit is always a graph of values of vCB as shown 10 Ftg. 3.7. .
output ewietlt versus oulpUt voltage. For the CB configuration, the
OUipUt cu.mmt is col.lectQt current (fc) and the output voltage is
The collector current 1c is _not constant but increases
collector to base voltage (Vco>· The output characteristic is plotted expqpentially with incr~ !n '!
CB• tow~ds ~o. The

fur a CObstant value of input current (It;). Output characteristics of a slope of output ch~actenstlcs .'s large m thts region,
n-p-a transistor i5 as shown in Fig. 3.1. Therefore the dynainlc output Ce$1Stance has_ a small value.
IcC~
That is why the voltage drop across the tranststor ( V CE) is

r. . . . . . ....... . . . . . . . . . . . . . . . .
Adlve region _ _j small in the saturation region. · .
(High output ~mle reaetanoe)--.,
In the active region, 1c does not depend on V cs· It depends
7.
only on the input current.18 . That is why the transistor is
called as a ·"current Controlled" 0C "current Operated"
I device.

~ Q. 10 With the help of neat circuH diagram, explain the

common emitter configuration of~ transistor. ·
!
Ans.: ........ ~

L A transistor can operate in my of three regions of

operation.
1be regions of operation are : · .
I. Cutoff region (trmsistor off) ·
2. Active region
3. Saturation. region
2. The biasing of the two junctions of a transistor is done as · :(a) Common emitter configuration for n-p-n transistor
........ ~

These regions have been shown in Fig. 3.7. ·

3. Cutoff region : The region below the curve for IE 0 in =
Fig. 3.7 is called as cutoff region. The input current IE= 0
Emitter Is
and the transistor is in its off state. The output current oommon
=
lc ICoo which is very small in magnitude.. (b) Common emitter confi~rati.on for p-n-p transistor
4. Adive region : In this region the collector current 1c is
almost equal to the emitter current IE md it almost remains <B-185) Fig. 3.8 .
constant. That means if IE is constarlt then Ic remains transist!!~sc~":on e~Ftt~r configuration for the p-n-p arid n-p-n
own m tg. 3.8(a) and (b).
coost.ant irrespective of the variation in the output voltage
VOJ• 'Therefore the transistor is said to operate as a curren~~r: the CB configuration , the relation betWeen the three
in
"coostant current source·~. (There i.s sligh~ change I Edue
to early effect.) R IE = lc + Ia . where 1c =adc IE + 1cao
earrange this equation to get,
$. D)'DamJe output resistance of the transistor : The lc - lcao = <Xdc IE
dynamic output resistance of a trarisistor is defined as : 1c lcao
.. a;;:- adc = IE=Ic+I8
It>. constant
...(1)
Ic[a~ -1] = I + lcao
B <X
de

.. Ic [·~:de J : :
This is nothing bui the reciprocal of slope of the output
characteri.stics in the active region. Slope of the output I +~-DO
c~s in the active region is vecy small. Therefore
o a de
tbe dynamic resistance (r0 ) in the active region is large.
f; ,1 ~. 'J ' • II I II I I IJ II S
 ~lc Devices & Cfrcults-1 (MU)
4-23

:. ~ "' la[ 1-· ~a:Jl+ (l.!coo

- ~) ...{1)
The input characteristics resembles the forward
characteristics of a p-n junction diode. The reason is that B-E
CUfTM'l Gain P. : junction is a forward biased (>:-D junction.
The base current increases rapidly as the base-emitter
. As fl.sc is tbe ratio
. of output
· cunent
· 1-c and mput
. current l , voltage crosses the cut in voltage of the BE, p-n junction, The
cal~ COIJliDOO C~tlter C~nt amplification factor or si
il IS
current gun. Thus transt~tor a~ as current amplifier. mp Y
r dynamic input resistance is defined as :

The value of fl.x Is much higher than ~· . 6. VBB

r - -- ...(l)
[1 ~ l = 1
- a:J -~ =__!c._
i - 6. 1a V constant
Assuming • aclt = _ !c Cl!
lu-lc -1 .•.(2)

'
8
Its value can \)e obtained from the input characteristics
Substituting this value in Equation (1) to get, because "rt is equal to the reciprocal of slope of tbe input

',' l
"C
:Ar_
...cit~+

~
fcso
(1 - ~ ...(3)
characteristics. The value of dynamic input resistance "rt is low
(typically 1 k.Q) for the CE configuration but it is not as low as that
of CB configuration.
But flc~c = (1 - a..t.,)
Q. 13 Explain output charaCteristics of a translatOr In
CEmode.
<X.sc adc + 1 - a~ Ans. :
. . 1 + aclc = (1- O...C)
+1=
1- CX.x
.
AD output characteristic of a CE configuration is the graph
.. 1 + flctc = 1 of output Clll'fCnt (Ic) versus output voltage (V~ fo/ various. fixed
(1. -.nctJ ... (4) values of the input current (18 ) . The typical output characteristics of
Substitute this in Equation (3) to get, a n-p-n transistor operating in the CE configuration are as shown in
Fig. :3.10.
IC = Pc~c Is+ (1 + J3ct) ICoo ...(5)
Equation (5) can t?e expressed as
lc = l3c~cis +lap ...(6)
wbere Ia;o is the reverse saturation. current for the CE
ooofiguratioo which is given by,
~oro = . (1 + l3c~c> lcso ...(7)
If a..t., =0.99 then substituting this value in Equation (2) we
get
0.99
1-0.99 = 99·
Thus J3c~cis much higher than adc. Cutoff region

Q. 11 Define .the reverse leakage current of a CE {B-t88) )fig. 3.10 : Output characteristics of a n-p-n transistor ·
configuration. in CE configuration
Ana.: As shown mFig. 3.10, there are three regionS of operation
The reverse leakage current of a lrallsistor operating in the namely the cutoff region, active region and saturation region.
CEcoofigw:ation is denoted by" Ia;o'~ and is defined as: 1. Cutoff region :
Reverse leakage current (CE configuration) : lcm =(1 + f3d.c) lcuo Both the BE and CB junctions are reverse biased to oPerate
the transistor in cutoff region. The base current Is = 0 and
Q. 12 Explain Input characteristics of a transistor In CE the collec_tor current is equal to the reverse leakage current
mode. Ia;0 . The region below the characteristics for I8 = 0 is. ·
AM.: cutoff region.
At constant output voltage V CF. the
input characteristics .of. a 2. Active region : .
n-p-~~ transistor is as shown in Fig. 3.9.The input cbaractenstic At a constant base current 18 , the B-E junction is forward
also sbows the effect of VCF.:~ biased, and C-B junction is reverse biased to operate ·the lrallsistor
.,.U OUIJ*llfe (,.A) VeE • 5V Vee "' 15V in the active region. The collector current Ic increases slightly with
80 increase in the voltage V0!: However the collector current. is
largely dependent on the base current Is· At a fixed value of VCl!• if
eo ·················· Is is increased, then it will cause Ic to increase substantially. This
M_.v;-1~ . is because le =J3c~c I8 • This relation is true only for tbe active region
of operation.
.. ~ 2D
uVCE~ 3. Saturation region : ·
~ _:__r 1.0 1.6
VIII!(Voltl)
111)111 voii4QII
The BE junction as well as tlie collector junction must be
forward biased to operate the transistor in its saturation region. The
vfltE os11to f the CE
<I-1J'7) Fig. 3.9: I.Dput ~ ot I tnt r a collocoor base junction can be forward biased if and only if VCF.
CODft radon
1: ;, ~. II •, 11 I II I I II If S

..
 Electronic Devices & Circuita-l (MU)
......... le
drops down 10 about 0.2 Volts. Because then v8 0 • 0.7 Volts will
furward bias lhe CB junction. This is as shown in Fig. 3.11. E
U5Ually the satunltlon voltage of a transistor, VCl! <•tl is between
0.1 10 0.3 Vol~
The collector cu.rrent increases rapidly with increase in Vca
as sbown in Fig. 3.10Jn this region 1c is approximately
independent of the base current and function of V01. Therefore in
this regioo the transistor is considered 10 be a semiconductor
resistor of very small value. Tile transisiOr is operated as a .switch
, in this regioo. (a) Conunon coUector configuration for n-p-n
.......·-le
T+
+ VCE = 0.2 Volts E

L
(B-189) Fig. 3.11 : Forward biasing of CB junction .
4. Dynamic output resistance ( r0 ) : Collector Is common

The dynamic output resistance ( r0 ) of a tr;msistor in CE . (b) Conunon coUector configuration tl"amistor ror p-o-p
<XIIlfiguration is defined as : transistor
6. Vrn . (F-21) Fig; 3.12
ro = 6. r ...(1)
"C constant 18 The v is input voltage and 18 is the input current whereas
v is the c:=tp'ut voltage and IE is the output current. This
· 5. Definition of Pee : co~guration is also known as "e~tter follower" con.figuration.
Ic · Fig. 3.12(a)does not show the pracucal way of.re~sentmg the CC
Pc~c = T8 . configuration. Practically it is drawn as shown.m Ftg. 3.13.
The value of f}dc <;an be obtaiD.ed from the output Current gain of CC configuration :
cbaracteristics. At any point on the characteristics w~ can calculate The current gain of a transistor in common collector
Pdc by taking the ratio of Ic and 18 at that point. AC beta of. a · configu,ration is denoted by y (gamma) and is defined as,
transistor is : IE lc+ Is
Current gain y =T =- 1- =(1 + ~de)
~Ic s . s
floc = .. I ...(2) .
... 8 V00 constant
•········ lc
r-----o+Vcc
~oc
is the slope of the transfer characteristics. Thus the
value of ac beta can be obtained at a constant value .of Vrn from the
output cbaracteristics. The values of ~de and ~ac · are nearly the
same.· Input
Volt<Jge
8. Maximum Vee and breakdown :· VBB •
Ill tbe active region the collector junction is reverse biased,
80 there is a limit on the maximum value of VCE' If V00 exceeds
this maximum value, collector junction will breakdown due to the
:-+ .
punch through effect. A large current will flo~ which will generate <F-13l7) Fig. 3.13: Practical way to draw the common collector
exce.sive beat to damage the transistor. Hence for safe operation co~ration
v0!. < vC£ (lllu)"
Q. 14 With the help of neat circuit diagram explain the
Q. 15 Draw and explain Input characteristics of n-p-n
common collector configuration of a BJT .
translator In CC configuration :
AQ8.: Ana.:·
The Common Collector (CC) configuration for p-n-p and n-
Inp~t characteristics is the graph of input voltage V~
p-n tJaD.Si.ston is as sbown in Figs: 3.12 (a) and (b). In the common
versus ~e ~nput c~nt Is at a constant output voltage VEO ~
coUcctor coofiguration, the collector is made common to both input
aod output.
shown m Ftg. 3.14. Considering the characteristic for V
The. base-emitter junctiQn is not forward biased up to v
1 V.
1.5 V.
Therefore the base current is zero up to Ysc = 1.5 v. Then it
:==
1: a •, II •. fi lii I IIIII '•
 f)eCtl'onlc Oevtcee & Clrcutta~l (MU) 4-25
1~ rapidl)' •a the Vlk' Ia lncre48ed be)'ond
beCIUIIC 8-Bjunction is more and moro forward biased.
1.' V. TJds la Ana.:
Jn order to operate the transistor as a switch, we have to
l,.,uu OUI'IWII operate it In the saturation region. In CB configuration, it is
Itt
(IIA) necessary to apply a negative voltage (VCB) to an n-p-n transistor
70 _................................... ······••·•••••·•••·•· ·•·····••·· so as to bias it in the saturation region. Moreover tbe input cwrent
(Jn) required to drive the transistor into saturation is bigb. For a CC
configuration, due to the presence of R£, a high .base voltage is
required to forward bias the BE junction and as the collector is tied
to + Va;. it is not possible to forward bias the CB junction. So a
20 transistor cannot be saturated. Due to these reasons, tbe CB and CC
configurations are normally not preferred when tbe transistor is to
be used a..s a switch.
o~----~~~~~~L--
.5 Voc (Vollll)
Input voltage
Q. 19 Write a short note on : Translator as a Current
Am~lffler:
CF·l321) Ffa. 3.14: Input characterlstks ofa transistor 1n CC,
Ana.:
con.ftguradon
When used in the CE configuration, tbe relation between
Q. 16 Expltlln output charactertatlca of a the output current Oc> and the input current (Is) of a transistor is
n-p-n
tranalator In CC configuration. given by,
Ana.: lc = ~18 • • . (1)

An output characteristic is a graph of output voltage y EC And in the CC configuration, the relation between the
versus the output current IE for constant value of input current 1 . output current (IrJ and the input current (18 ) is given by,
The ~t ~haracteristics of a n-p-n transistor in C.C. IE = (1 + f3)18 ...(2)
coofi~tJc:m, IS as shown in Fig. 3.15. From Fig. 3.15, the output The current gain is defined as,
cbaracteriStJc of CC configuration are similar to those for the CE · Output cutrent
ooofiguration. This is because Ic is approximately equal to Is:> ~urrent gain AI = Input current
OUipUI currant
IE (rnA) T
7·
.
Hence current gain of CE configuration =( = f3
e I . B
. . IE
5~--
:rj:~~=.=~~ And current gain of CC configuration =I = (1 + f3)
~ B
~s the vaJue of~ is much higher than 1, the current gain of
: -Lt~~~~~==t1~ ~ and CC configuration is large. Hence for a small change in the
mput curre~ we get a large change in output current Thus current.
amplification takes place and the transistor acts as a current
o~~~~~~~--~~~--~
2 . 3 ~ 5 Output voltage amplifier. Trao~stor does not act as C1:1I'tent amplifier when used in
VEe (Volts) the CB configuration.
Fig. 3.15 : Output characteristic of a tramistor in CC Q. 20 How transistor works as a voltage amplifier ?
conftguradon Ans. ; ·. If for a small ch~ge in input voltage, a proporti9nallarge
change m output volt:'ge.IS ~btained, then v~ltage amplification
Q. 17 Give reason : CE configuration of BJT Is preferred ha~ taken place. The ClfCU.It diagram is shown in Fig. 3.16:
over CB and CC. I.,Jyn:t Vee

Ana.:
Out of the three configubtions CB,CE and CC, the CE
configuration is the most popular and widely used configuration.
The reasons are as foJiows :
1. It bas a high voltage gain as well as a high current gain.
2. As voltage gain as well as current gain is high, it has a very
high power gain. This is .because, power gain is the product
of voltage gain and current gain.
3. The CE configuration has moderate vaJues of R1 and R0 • (.B-230) Fig. 3.16
Therefore many such stages can be coupled to each other The transi~tor is operated in the CE configuration. The
without using any additional impedance matchlng circuits. outpu~ voltage V0 1s taken at the collector with respect to ground;
Due to thl• autornatic impedance matching, maximum
power transfer will take placeJrom one stage to the other. •· Yo = VCil
Due to a small change A V11,. ~re will be a small change in
0.18 Why CE configuration I• preferred over CB and lu.
CC when UNd u a awttch. · ii4iili
... (1)

I. I ·II .II III IIIJII ' •

 Electronic Devices & Clrcults-1 (MU)
· ,!c
Hence the corresponding change in collector current is ac~c:
IE =
given by. . al nnc:itive and less than unity.
a IS ways r---

'
t:.Ic =
.
Pt:.Io
t:. vln
= PT
B • • 5.
s:.au signal current gain a.c :
. aJ ~urre
~~lit gain a.c is defined as the ratio of
Hence the corresponding change in output voltage 1s gtven Small SlgD c . .
by, t to change m eiDJtter currenl
change in collector curren
t:. yo :: lilcRL ... (2) ~ for constant collector-base
Substituting the value oft:. Ic to get, i.e. aoc = t:. 18
voltage VCB
t:. vln
liV0 = PRxRL
8
· ct is.. always positive but less than unity (very close
ac • 'th v I and temperature.
flR~ to unity). It vanes WI . CB• E .
. . t:.V0 = Rxt:.Vln ... (3) 6 Current amplification factors :
B
Thus fot a small change in Vin • a large change in V0 · is • There are two current amplification factors, the alp~ factor
obtained and the voltage amplification bas taken place. Hence the ct ·and the beta factor (.j3) defined as, the alp~a factor (a) ts known
BIT acts as a vollage amplifier. ( )current amplificat:J'on factor ·and is the ratio of collector current
as
Q. 21 Deft~ the contributing factors forwards the low ' <lc) to emitter current (Is). ·
frequency common base current gain of BJT. _ !.!c at constant collector-base voltage VCB
Hence, a - t:. IE
,...!!'llm·•--e·•
The beta factor (~) is the current g~ fa~tor (al_so known as
Ana.: the transport factor) of a common emitter crrcwt and 1s defined as
1be parameters which relate the current components are as . the ratio of collector current <lc) and base current Os)·
follows : ·
t:. Ic .
1. Emitter Injection efficiency (y) : Hence, P = t:. 18 .
1be emitter or inj~tion· efficiency 'Y' is defined as :

y
Current of injected carriers at JE
= Tot31 emitter current ·· ...( 1)
Q. 22 Derive the relation a =p ~ 1
Where, JE =
Emitter base junction. ·
In case of a p-n-p transistor , . Ana. :

y = lpE~~ = t . .( 2) Relation between a and P:

Where, Ip, = Injected hole diffusion currel!t at emitter As • p -- . ~

t:. Is
junction:
and ~ = Injected electron diffusion current at and a = ~- .t:.lc .·
emitter junction. t:. IE - t:. lc + t:. Is
2. Transport factor P* : . .. ('.' .t:.IE=t:.l8 +t:.Ic)
The transport factor is defined-as: 1 .!:. lc + .!:. Iu .!:. lu 1
Injected carrier current reaching lc or, a = .t:.Ic =1 + .t:.Ic =1 +~
P~ = Injected carrier current at JE ...( 3)
Where, l c = Collector base junction. or, la -- l±.l!
p
In case of p-n-p transistor,
or, a = _lL_
p• = i;I .. (4) . I +P ..
and p = ......£.._
3. Large signal current gain (a) : 1-a
It is defined as the ratio of the negative of the collector . . A small variation in a. corresponds to a large variation in ~­
current inCrement to the emitter current change from zero (cut off) So, It IS bette~ lo determine Pexperimentally and calculate the
· to as the large signal current gain of a common base transistor, or value of a usmg the following expression,
a = - !c.=.!w
1E ...(5) a=.JL ·
l+P
Since 1c and IE have opposite signs, then a as defined is·
Q. 23 Ust the Ideal conditions of BJT • i•MMQ
always positive. Typical numerical values of a lie in the range of
0.9 to 0.995. Ana. : The transistor has the following ideal characteristics
4. DC current gain : 1. All_the regions are uniformly doped.
2
If leo is negligibly small as compared to Ic. a · Emitter and base widths are constant
3
approximately equals to Ic I IE. This is referred to as the de current · The energy band gaps are constant
4· Current densities are uniform.
gain of the common base transistor and is denoted by adc:.
5. Low injections. '
So,
6. Junctions are not in breakdown.
'· .• ,) v s 1111111 fJ ll ~
-r:;tectronic Devices & Clrcults-1(MU)

Q . 24 List non-ldealeffecta In BJT.

Ana· : The important nonideai effect are :
1. Base width modulation
Ana.:
Early effect in tbe CE configuration :
4-27

2. High injection For • glvaJ value of VIll\• if we inatale VClllhcrl

3. Emitter band gap nanowing
4.
5.
Current crowding
Non uniform base doping
V CD incre~ as V Cll ' t .W V BB is comWll

6. Breakdown voltage
'
. • CD jllllCtloo Is IJIOI'e reverse biased

Q. 25 What Ia base width mOdulation

help of proper diagrams.
? Explain with the '
•• Depletion region extends deeper into the base

Dec. 03. May 06. Dec. 11 . May 14 '

:. Width of the nouiral region reduces.

An&:
'
. :. Gradient of minority cairier coocauratioil t 8lld diffusion current ,
The total base width is equal to the sum of the widths of the
depletion regions ·extended into the base region from the collector
and emitter.side and the width of the region occupied by the free
• > through the bose t

. . . ·~ . ,.
J :.' ·Jc.t as,..,.VCil illcreaseli.. .
)

cbaige particles. But as the EB junction is forward biased, the

width of its depletion region is very narrow (Fig..3.17). As the CB Thus due to Early effect the collector current lc increases
junction is reverse biased, the width of its depletion region is much with increase in VCE even when V BE is constant. Therefore the
larger. output characteristics are slanting upwards.
Tbus neglecting the width of depletion region at the EB The relation between Ic and V j.. is as foll.ows :
junction, lc = &J (V~ + VA)
Total base width = Width of depletion region at lbe CB Where &! = Output conductance
junction inside the base region + Width of the region · VA = Early voltage
containing free charge particles.
As VCB is increased, the reverse voltage applied to the CB Q. 27 List Applications of transistor ;:
junction increases. This widens the depletion region at the collector Ana. : The important applications of a transistor are as follows:
junction. Due to this, effective width of the base region (Fig. 3.17) 1. Amplifiers 2. Switching circuits
decreases. This will increase the charge concentration gradient in. 3. Oscillators ·4. Wave shaping circuits
the base region. Due to increased charge carrier concentration, 5. Logic circuit$ 6. Timers and multivibrator
more number of electrons ·diffuse from the emitter to base i.e. 7. Delay circuits.
emitter current increase.s. Hence with increase in Vco the input
0. 28 Determine lcao at 75° if it has a vaiue of 10 J&A at
current IE increases slightly.
The reduction in effective base width due to increase in
30" c. ·~fi.ltlttj
Va~ is called as "Early effect" or "Base Width Modulation". Ana. : ICBO doubles with every .10°C rise in temperature.
:. lcs0 (75°C)' = l.07'nlrno(30°C)
10 ~ ~ 210 ~
45
= (1.07) X

Q. 29 BC147 transistor· has very thin and lightly doped

base region. Justify. l®fi:lelel:l
Ans.:
The current gain ~ of transistor BC 147 is very high. In

-
Tolll-

(a) For smaller values ofVCB (b) For large values ofVCB
order to obtain a high value· of ~ it is necessary to keep the base
region as thin as possible. This will reduce the recombination's in
the base region and reduce 18 . It will also increase Ic for the same
value of Is· This results in increased fl as fl := Idf8 .
(F-tm) Fig. 3.17: Early effect or base width modulation .
Q. 30 Complete the sentence : The thermal reverse
Other effects of base width modulation : · saturation current of transistor - for every -
l. Since the base width decreases due to th_e early effect, ~e oc rise In the C-B junction. Hence calculate the
number of recombinations taking place 10 the base region reverse saturation current of a transistor for
will reduce. This will increase the values of both, the junction temperature of 8JOC if Ita · reverse
• r A* and the common b~ current
transportation ,actor .., · . v saturation current at 23°C ls10nA.· l~~l§W<nm:l
amplification factor a!,. with increase In the .vo.1tage CB·
2 Due . . . the charge gradient Within the base, Ana. : Doubles, l0°C.
· to mcrease m · · J'ected
more number df "minority" charge earners are m f Solution or the problem :
• . • crease the current o
across the junction. Tb1s WI11 m lo2 = (J.07)AT l ol
minority carriers. But ~T = 87-23 = 64°C, 101 10 nA =
Q. 28 Explain early effect In the CE configuration. :. lo2 = 64
(l.07) X 10 nA 759.56 nA = ...Ans•

..... _
Electronic Oevloes & Circuita-l (MU)

lysis of BJT
Chapter 4 : DC Circuit Ana

Q. 1 Expillln neceulty of bluing for BJT amplifier.

Ana. : ard active region, saturation and inverse active.
. . · namely cut-off, forw b'ased as shown in Table 4.1.
Transistor can opemte in any of the four regtons of operatio~s h ld be forward or reverse 1
To operate the lranslstor in these regions the two junctions of a transistors ou . . ·
tio0 and appJkadons
Table 4.1 : Regions of opera - '>~'
·. 1~ A~ :t·.:
·C ·
oUet*M:.b~~o •.;~ --· · · · ~
Base bitter Juncdon . · As a sWitch
Cut-off Reverse biased Reverse biased
Amplifier
Forward Active Forward biased Reverse biased
As a switch
Saturation Forward biased Forward biased
In the digital circuits
Inverse Active Reverse biased Forward biased

Rearranging the Equation _(l) to get,

Q. 2 What •re the crlt8rla to select a suitable biasing
networtt 1 I11@W•IOi
Ana. : Following are the important factors to be considered while
. Ic = [ -~Va:+
Com~g Equation (~) with the general equation of a
i: ..
(2)

designing a biasing circuit :

straight line.
I. Position of a Q point i.e. y = m.x + C ...(3)
2 Value of Ic (collector current) at quiescent point i.e.lcQ. The comparison yields the .following results,
3. Value of every stability factor shquld be as low as possible. y = ~ . x = VCE
This is essential for ensuring higher stability of the Q- m = -II~ C = Vex;/~ .
poDit This comparison sho~s that· Equation (3) ~nts a
4. Transistor should be biased in the lirie;u portion of its
straight fuie. This straight line is called as the de load line.
transfer characteristics. 1 vcc {B-2544) .
Q. 3 For a BJT ampl~r, show with the ~lp of Ic = [--R 1 Vee + ~ ·
8 c c
circuit, how to draw 8 d.c. load line ?- ~ '--r-'
....._,._...., "'--y-'-'

Ma 03. Ma 05
y=-m X+C

Ana. : To draw de load line , considering the common emitter

=
Substituting VCF. 0 in Equation (1) to get ~ Vcc I Rc =
which is lc·max or point "A" in Fig. 4.2 and substituting ~ = 0 to
CQDfi.guration of Fig. 4.l(a) and the collector circuit of Fig. 4.1(b).
=
. get Va;: V00 which represents point "B" in Fig. 42. The "DC"
word indicates that this line is drawn under the de operating
conditions without any ac signal at the input And the word load
·~-----Ic
lint is used because the slope of this line is - 1~ where Rc is the
T
VeE
+
-=-Vee
load resistance. .The de load line is drawn on the output
j__ characteristics as shown in Fig. 4.2.
lc(mA)

. . ,: . . - Adlve region ----1

v @ !
lc ... = ~ .... ~'f--------'s4 =40 pA
{a) Common emJUer conllguration
~-------Iss= 30 pA
R

·'
CutoH region •
(b) Collec:tor circuit
(J.m) Fig. 4.1
<F-284) Fig. 4.2 : DC load lint showing tile Q point on output
ProceduN to plot the DC load line : characteristics or the ~r
Applying KVL to collector circuit of the CE configuration
drawn in Fig, 4.1(b) to write, ·
... (1)
Vex;- VCE- lcRc '"' 0
1. 1 ·; ', II Ill I I II II '•
 Electronic Devices & Clrcul18-1(MU) 4-29

Q. 4 Drew D.C. load line for the circuit ahown In Q. 8 Explain the Hlectlon of a Q.polnt for 1 tranalatoi'
Fig. 4.3(a).
•••• blaa circuit and dlacuaa the limitation• on the
output voltage awing. lti§Mt.j
Ana. : Depending on the application, the position of the Q point
can be selected on the load line. This is shown in Table 4.2.
ev +
20V It;;..~.-

I:~,- ·,
. ~:~
......,..,-
Table 4.2 : Position of Q point aod •ppUcatlon

Open switch In the·cut off region

Closed switch In the saturation region
CF·I338) Fig. 4.3(a) Amplifier In the active region
The shape -of amplifier output signal depends on the
Ana.: position of Q point. Considering the three possible positions of Q
1be given circuit is a CB circuit. 1be output voltage is v point and its effect on the output signal of the amplifier
and output current is Jo CB Effect or Q point close to cut-off :
Applying KVL to the C-B loop of Fig. 4.3(b) to write , Fig. 4.4(a) shows that the Q point is adjusted closer to the
· Va:;. = lc Rc + VCB cut-off region and an input signal is applied which changes the
v v base current by 20 JAA. Due to this the positive half cycle of the
:. Ic = -ie +~ ...(1) outpufvoltage gets distorted as shown in Fig. 4.4(a) and the output
voltage swing with an unqistorted output will be limited.
This is the equation of de load line.
1 20
:. Ic =- 4~ VCB + 4k ... (2)
Substituting lc =0 to get VCB(max) = 20 V aDd VCB = 0 to
20
get lc-.: =4k =5 mA.
The load line-is shown in Fig. 4.3(c).

(F-3!14) Fig. 4.4(a) : Effect of Q point close to cut-off region

Effect of Q point close to satora~n :

Fig. 4.4(b) shows the effect of Q point adjusted close to the
saturation region. In the positive half cycle of 18 , the transistor goes
into saturation. Henc~ the collector current remains ~onstant at 1c
<sao· Hence the negative half cycle of the output voltage and
positive half cycle of Ic gets distorted as shown in Fig. 4.4(b). This
will limit the output voltage swing with undistorted output to a
very small value.

DIR>Jtlon In lc(mA)~
· · ~·· .........

(c) DC load line

waveform\
:bv ./ ,/
the oolleotor ounent
.
............ . .{;)
.a
t ../
.
··•
Q Point le oloM
k>abJra~

<F-1339> FJg.4.3 .... ........ i;}\

•t,r.;..;
.....
···~·-----
-

~~1 . l
Q. 5 Define : Quiescent Point (Q Point) •
Ana.:
1be term quiescent means quiet, still or inactive. Therefore
the Q point is a11o called as "operating point" or "bias point". Q
point is the point 00 the load line which represents the de current
through a transistor <Y and the voltage across it (VCEQ). when no
ac signal is applied at the input. In short it represents the de bias
condition. Co-ordinates of Q point are (VCEQ• ICQ). CF·39S> Fig. 4.4(b) : Effect of Q.point close to saturation region

!; a ·. v ·. n11111 1111 s
 8ectron1c o.vtoee.& Orcutta·l (MU)

o..Point In the eattYe Nflon :

The criterion of Rl«tlng qu.ieseent point t.o operate the
-
4-30

IJ'IOiillot u an ampUfler Ia as follows :

1. The Q point should not be too close to the cut-off region. ... ..T
2. lbe Q point should not be too close to the satu.ration
At Vo
reak*·
The oonditioos (1) and (2) should be satisfied in order to .L--~ .l.
..........
avoid any waveform distortion in the amplified output
signal.

•i?
. •tJ?
. J".··
~fJ/···
<F-285) Fig. 4.5 : AmpHfler circuit drawn part1ally

~--
........ . . ia~·~ lc (mA)

~:~i--~~-/~__. _·~-~ Q Point VaiUIII

Ioo•so.aA -1
Joo•3mA Slope= <Rc II RJ
tc•aM Vceo ,. 8 Voila

......
~

'<
8
(F-393) Flg. 4.4(c:):
Graphic:al representation of Fig. 4.6: AC and DC load lines
ampllftc:atiou process
Q. 8 What are the factors affecting the stability of Q
3. 'The Q point should be located at the centre of .the de load point?
line so tbat the variation in the amplified voltage is equal
Ans.:
correspooding to the positive and negative half cycles of
tbe input signal. 'This will ensure that the amplified signal The factors affecting the stability of Q point are :
will be an exact replica of the input signal. 1. Changes in temperature.
4. In Fig. 4.4(c), the component values are so adjusted that the 2. Changes in the value of ~de
Q point is situated exactly at the center of the de load line. 3. Variations of parameters f!om one transistor to the
The co-ordinates of the Q point are : other. However the Q point instability due to any
Q point = (VCEQ•Iw>= (6 v. 3 mA) reason is not desirable because it will introduce
1be value of quiescent base current i.e. 18 Q =30 JA.A.. distortion in the amplified signal. ·
Q. 7 For a BJT amplifier, ahow with the help of a Q. 9 What Is bias stabilization In BJT 1 IMfJU
circuit, hoW to draw a a.c. load line ? Ana.:
Ma 03. Ma 05
. Bias stabilization is a process of stabilizing the Q poinr
Ane.: (bias point) of the circuit. Hence there is need to design a biasing
Pig. 4.5 shows an amplifier circuit partially. The de load circuit which will keep the position of Q point stable on the load
resi.ltaoet: is Rc but the AC load resistance by considering Cc as line. ·
sbof1 aod + Vcc coonected. to ground is CRc II RJ. If a load line is Q. 10 Deflnestablllty factors of transistor.
drawn the slope of which is - 1 I (Rc II RJ the!) it is called as an Ana.:
AC load line and it is to be uJed when tbe transistm: is operating as
The stability of Q point of a transistor amplifier depends on
an~tier. the following three parameters :
The AC Joed line thus represents the AC operating
1. Leakage current leo
cood.itions of a circuit. The parallel combination CRc II RJ is
2. ~de
alway• JeQ dwJ ~· Therefore the slope of AC load line is higher
tbao m.t ~the DC 1oed line a.a abown in Fig. 4.6. 3. Base to emitter voltage

tie li&F111D11'1R
EJectronlc Oevlcee & Chculta-1 (MU) 4-31

The effect of these parameters can be e~~:pressed Rearranging the Equation (1) to get,
mathematically by defining the stabiUty factors for the three Vee- Vsa
pemneters individually as follows : .. Is = Rs
1. Stability factor,
Is
s - - A~ a
~
. A leo constant vBli and pdc or aleo ..•(1) +

~s represents ~ change in collector current due to

cbaDie m reverse saturation <;urrent leo· 1be other two parameters
dill means V BB and Pc~c are assumed to be constant. +
2. Stability factor,
Ale a~c
S' = A vBB
constant leo and pde
or -va
aa
...(2)
, •
s represents the change in Ic due to change in v at (F-289) Fig. 4.8 : Base drcuit or base lOop
ooostant leo aud Pc~c· Bli
For silicon transistors V BE = 0.7 V and for germanium
3. Stability factor, ttansistors it is 0.3 V. Therefore VBE < Vee• hence neglecting VBE ,
s" -
-
A Ic
pdc
I CODSUUlt leo an9 V BE or
aIc
apdc ...(3) Is = R
Vee
B
...(2)
This is th~ approximate expression for the base current
0. 11 Which are the bias stabilization techniques ~f corresponding to 9 point i.e. IBQ.
trMslstor ? . .
In this equation supply voltage V oc and R8 both are of
Ana. : Bias stabilization means techniques used to stabilize the Q fixed value. Therefore the base current 18 also remains cOnstant
poinL Some of them are as follows : Therefore the name or tbis biasing circuit is ''fixed bias
1. Collector to base bias circuit circuit".
2 Voltage divider bias circuit Step 2 : Ex~ression _
for ICQ or Ic :
3. Flxed bias circuit (Si~$le base resistor biasing)
The fixed bias circuit is designed to operate in the active
Q. 12 Discuss fixed bias circuit used for BJT. regiop. .
Dec 02 r.1a 0-l. l\1a 05. Dec. 05. Dec. 06. Dec. 08 Hence the collector current is given by the fol1owing
expression :,
Ana.: ~ = 13c~c Is+ lcro ...(3)
Tbe simplest biasing circuit used to bias a BIT is ca11ed as
But as, Icro << 13c~c 18 It can be neglected to get,
the fixed bias circuit which is as shown j.n Fig. 4.7. In this circuit ,
only ooe power supply (Vcc) has been used to supply power to ICQ = 13c~c IBQ
coUecror as well as base. R8 is the single base biasing resistor, Step_3 : Expression for V CI!Q or V CE :
heoce this circuit is also called as single base resistor biasing.
"" shown in Fig. 4.9. Here
Considering the collector circuit
the base resistance is assumed to be open circuited.
Applying KVL to the collector circuit to write :
Vee-~~- VCEQ = 0
VCEQ = Vee-~~ ... (4)
···········r+ lea
Vee +
+
......... .!.. +
-=-Vee

()'-ZI7) Ji"'&. 4•7 : A ftsed bias circuit for n-p-n transiBtor ··.........t
ArWyele:
Step 1 : Espn:lldoD for bale eurrent lao or •• : (F-290) Fig. 4.9: Collec:tor clreuit or collector loop·
Cooatdering tbe bale circuit shown in Fig. 4.8. Here
.t..a:.............. . ........ Uector resistaDCC Rc is assumed to be open 0.13 Give reuon: Fixed blaa circuit for BJT amplifier
~y ~ co . .
circuilt.d. ApplyiDg the Kirchhoff'• voltage Jaw~ the base CJrcuJt ylelda loweat etablltty of the de operating_point.
IOJet :
...(1)
IMN•r:ti
Voc - 18 R8 - V BE = 0

1: ···.v •.u l l l l l l l l l '·

 Electronic Devices & Circuita-l (MU)
An&. : As temperature increases, Icuo increases. So lc will Ana. : •. . as fiollows ·.
f: tor "S" ts

:~\constantV.. ondP.,
i~because,
lc • ~ Ia + (1 + P>lcuo .
n.csW>•ll: :
In the fixed bias cqcuit , 18 is constant. So lc will keep
vacying with change in temperature. The fixed bias c~uit cannot
automatically keep 1c constant and stabilize the Q pomt. Thus no . susthecban.ge in TAC due to change in the reverse
stabilization is provided by the fixed bias circuit. S gtve. nt lcso· As Icso changes by ll Jrno, the base
'll change by ll Ia and the collector current lc
saturaboln curreWt
Q . 14 Determine the following for ·the fixed blae current a
configuration of Fig. 4.10: changes by ll lc .
(a) I~ and lea For a CE configuration,
(b) Vceo
.IC
=
1-' =
~ dc IB + lcro ~de Ia + ( 1 + ~&) lcao
(c) V 8 11k1Vc
Therefore change in lc is given by,
(d) Vee-
lllc = ~de Ilia+ (1 + f:\~ ll1cso
Dividing both the sides by lllc to get, ~

' . 1 == f:\dc [~ + (l + ~~ [ ~J
1-~de[~ +~~[~J
02
--.....---t· (---- AC output .. == . (1
~de= 50 ·
. fliCao 1 - ·~de [ Ilia llllc )
:. lllc == (1 + f:\de)

lllc
. ' But, S = lllcso
(F-291) Fig. 4.10
(1+P~
...(1)
Ana.:
Step 1: Obtain IJIQ and ICQ : But for the fixed bias circuit,
Vee- VBE
. Va;- VBB 12-0.7 I-p = . RB .
IBQ = R8 240x Hr
hi this equation Vee• VBE and R8 all are fixed Therefore I a
= 47.08 J.IA ...Ans.
-6 . cannot change. :. MD= 0. Substituting this in Equation (1) to get, ..
~ = fJde X JBQ =50 X 47 X 10. . s = (1 +~de) ...(2)
= 2.35mA •••ADS.
Comment on the expression for S :
Stepl : Obtain V CEQ:
=
Substituting pde 49 in Equation (7), the value of S =50 .
Considering the collector circuit of Fig. 4.10 and applying i.e. collector current change is 50 times as large as change in the
the Kirchhoff's voltage law to it • ·
reverse sa~tion current Ieoo- Fixed bias circuit thus gives a very
Va; = VCEQ-ICQRc ...(1)
Substituting the values, poor stability of the Q point. It is the worst configuration as far as
v = 3
12-(2.35x10- x 2.2 x l0)
3 the stability of Q point is concerned.. ·
CEQ . . .Ans.
..
= 6.83 Volts. S' of
Q. 16 Derive the expression for the stability factor
a fixed blaa circuit. Also derive the relation
Step 3 : Obtain V• 8Dd Vc : between S and S' for the same. Dec. 02. Dec. 08
VB and vC are the voltages measured at base and collector
with respect to ground.
Ana. :
.. . .
The stability factor S' as,
.,.. y 8 = V8E =0.7 Volts
and vc = vCl! = 6.83 Volts. a~c
~VK : .
S' = · av
BB constant leo and pde·
= VaE- VCI!
. Vsc ...(2)
For a common emitter configuration, "·
Substituting the values ,
Vsc = 0.7 - 6.83 =- 6.13 Volts. ...Ans. lc = Pde Ia + (1 + Pde~ Iro. ...(1)
Substituting IB in terms of VBB into Equation (I). For this,
a. 15 o.rtve the axp,....lon for .tbe atablllty factor "S"
referring Fig. 4.11 and applying KVL to get,
of • fixed biM circuit Comment on the reaull
()pc 0?. Dec 08 Vee = 18 R8 + VBB .,.(2)

t: :t '. \I ' · " 111111111 '>

 •,

Electronic Devfoee & Circuha·l (MU)

...(3) Step I : Oba.tn the value of Rc :

Considering only the collector circuit of Fig. 4.12 and
apply KVL to it to get,
o - Vcx;-Voo
· 'C - lCQ ...(1)
+
Voc:-=- Substiblting the values we get,
10-5
Rc = 5x 1~r 3
= 1000 .Q or 1 kn •••ADs.

Vcc=10V

<F-m) Fig. "-11 : Bue loop l lco=5mA

t

Substiwting Equation (3) into Equation {l) to get,

Ic = ~deL-CC~ VBBJ + (l + ~ciJ lao

len and lcao are one and the same.
:. lcRs = ~de Vcc -~de Vaa + (1 +~de)laoR8 ... (4)
Differentiate this expression with respect to V88 to get,
a~c
Rsav-
BE
= o-~de+o <F·m> Fig. 4.12
:. Rg S' = -~de Step 2 : Obtain the value of Ra :
-~de Considering only the base circuit of Fig. 4.12 and applying
S' = ...(5)
Ra KVL to it to get,
Q. 17 Derive the exprualon for the •!!~~ . Vcc- Is Rs - Vaa = 0
Vex; - V,8
for a fixed bias circuit .. Rs = Ia
...(2)
Ana.:
5 mA -33 33 J.LA
The stabilitY factor S" is But Is = .!m_
~de- 150 - . ...(3)
10-0.7
.. Ra = 33.33 xlO- 6 - 279 kn •••Am.

. Step3: Selection of~:

For a common emitter configuration. The transistor to be used for this circuit should have the
lc = ~de Is + (1 + ~~ fcao = ~de Is + ~de lao+ lao following specifications :
Differentiate both sides partially with respect to ~de to get, 1. ~de = =
150 atiC 5 mA
.
a~c 2. IC (max) = 2 XlCQ =2 x5 =10 mA
apde = Is + Icao + 0
3. VCE(max) = 2 XVCEQ= 2 X 5 =10 Volts
Neglecting fcao to get,
4. = 2 XV03 (maxi X1C (mu)
a1c 1c ... (1)
Po (max)
3
S'' = a pde =18 = Pc~c = 2 x lO x lO x 10- =200mW
1bia iJ tbe required expression. 0.19 For the fixed-blued configuration given,
determine the following :
a. 11 DNign a fixed circuit ualng a alllcon n-p-n
1.
,.
~ which hU p•• 150. The do bluing lao, lea
point Ia at Vca • 5 V and lc • 5 mA. S&Jpply voltage 2. Yceo
la10Volt8.
3. v..
4. vrJC llllltl
Ani.:
GIWD: Pc~c · 150,
lal • SmA

I. 1' 'J 11 111111 1 11 •

 Electronic Devloea & Circuita-l (MU)
--------~-----+Voo
lc
R8 a 240k0
Rc=2.2k0
Voo•+12V
'·........ Is
c1 .. c2 =10k0

(F-4139) Fig. 4.13

<F-m>Fig. 4.14 : ~odifted fixed bias circuit
Ana. :
Stabilization of Q point:
At Q point • assuming that the ac input applied to the circuit If the collector current (lc) tends to increase due to either
1. '
is zero and the ac output produced is also zero. For DC analysis rise in temperature or change in Pc~c due to replacement of
therefore assume that the capacitors cl' and c2 are open circuited tranSistor then the emitter current IE also will increase.
aDd_hence do not exist in the circuit at all. 2. Due to increase in IE, the voltage drop across Re i.e. VI! ,
Step 1 : - Obtain leQ 8Dd ~ : will increase. (
Vee- Vas 12-0.7 3. But VB is constant Therefore V BE will decrease. This will
lsQ = ' RB = 240 X 103 47.08JJA ••.ADs. reduce the value of IB and therefore the increased collector
~ = Pc~c x IBQ = 75 x 47 x 10-
6
=3.525 mA •••Ans. current will be reduced towards its desired value. Thus tbil
Step 2 : Obtain VCEQ : stabilization of Q point takes place.
. Considering the collector circuit of Fig. 4.13. Applying the Q. 21 Dertve the expression for the stability
Kirchhoff's voltage law to it to get, the modified fixed bias circuit.
Vee = v<l!Q +~Rc ...(1) Ana.: As,
(l+P~
Substituting the values,
3
s = 1-Pc~c[AIB'AicJ
Va:Q = 12- (3.525 X 10- X 2.2 X 10 3 ) =4.245 Volts. ••.Ans. and obtain the value of MJMc to get the expression for S.
· Step3: /
Obtain V 11 8Dd Vc : To obtain tbe value of AI.~ Me:
VB and VC Me the VOltages measured at base and COllector l. Considering the base circuit of Fig. 4.15 and applying KVL
with respect to ground. to get: .
:. VB= VBE =0.7Volts . and Vc= Vrn=4.245Volts.
Obtain Vac:
Vsc = Vae- VCE ...(2)
= Is Rs + VsE + <lc +Is) R
Substituting the values to get, 8

VBC = 0.7 - 4.245 =- 3.545 Volts. ••.Ans. .. Is =

Vee-Yae-lcRE
...(1)
Q. 20 Dlecu11 modified fixed bias circuit used for BJT. <Rs +Rs)
Dec. 02. Ma 04. Mn 05. Dec. 06
.. Is =
Vee VBE IcRe
Ana.: <Rs+Rs) <Rs + Rs) <Rs+IY
The modified fixed bias circuit is as shown in Fig. 4.14. A
+Vee
resistance Re bas been added ~m em\,tter to the ground terminal
in the fixed bias circuit. The remaining circuit is same as the fixed
Re
bias circuit . The emitter resistor improves the bias point stability • ......Is
as below. +
Vee

<F-302> Fig. 4.1!: Base circuit

~I ifMIINIIIIIJi
 Electronic Devices & Cfrcults-1 (MU)
4-35
2. But V00 Van• Rli Rs fl
differentiation of first ' ' de • are constant. Hence Q, 23 Draw Collector to B8H Blu Clrouh uNCI for BJT.
zero. two tenns Wtth res~t to IC wm. be
ale -Ra Ane.:
·· aIC = <Ra + ~ ...(2) The collector to base bias circuit is as shown in Fig. 4.17.
The base resistance R8 is connected to the collector and not to the
~ -Ra
.. Ale = (RB + Rs) supply voltage V cc· Actually R8 is connected between the collector
and base terminals of the transistor. The current flowing through
Substitute this in equation of stabili'ty ~ fi . . He is the sum of Ic and 18 as shown in Fig. 4.17
lOf Xed btas CLICWt
to get,

- (l+ ~.0 (l+ 13 )

s- H<o[~~· t+[~\J . .(3)
Comment:
The denominator of Equation (3) will al~ays be greater
than ~· Henee S will be less than (l + ~c~c>· ThliS addition of the
.emitter resistance Rt; has improved tbe stability.
Q, 22 DetennJne Rc. R.., R8 , VCE and V8 ,
Ans.: <F-304) Fig. 4.17 : Collector to base bias clrcu.lt
Given: Va;=l2V, fc=2mA, Vc=7.6V, Q. 24 Explain Q point a~blllzatlon In collector to base
VE=2.4V, ~=80 bias circuit .
Ana.:
Step 1: Find fa, IE:
The factors that affect the stability of Q point_are change in
IC= ~IB
13deor ICo due tO change in temperature or. due to piece to piece
IC 2x w-3 variation in characteristics.
.. Is = ff = 80 =25 f.AA But ic = 13c~c Io + ICoo
I£ = ( l + ~ ) 18 = ( 1 + 80 ) x 25 x lQ-6 = 2.02 mA Therefore due to changes in ~de or Iceo. the collector
Stepl: F'md'~, Rc, ~. V CE and V 8 : current chan~es. Assuming that ~de and ICoo increase then the
sequence of events takes place as follows :
Rt; = VE = 2.4 =1.18 k.Q ...Aos.
IE 2.02 X 10-3
Vcg = Vc-Va=7.6-2.4 =5.2V ...Ans.

12V
..-....-...-ll2mA

{F-306)
Thus the value of IC is maintained constant irrespective of
changes ~n ~de or Iceo. to stabilize the Q_point.
(F-1904) Fig. 4.16 Q. 25 Calculate D.C. collector current lc and voltage Vee

...Aos.
for the circuit shown In Fig. 4.18(a) 'Khflil
Va;- Vc _12-7.6 =Z.2 k0
IC - 2X 10- 3
...Aos.
Ve +Yse =2.4+0.7.=3.1 V

.. Ra =
Va; - Vs = 12 - 3. ~ = 3S6Jal ...Ans.
Ia 25 X 10

I; a '. II s Ill II II 1111 '•

 Electronic Devices & Circuits-1 (MU)

lido= 120
Vcea=SV
Ico=SmA

(F-308) Fig. 4.19

<F-4140) Fig. 4.18(a)

Ana.: Ana. : to base bias circuit means we have

Given : p = 75, R8 = 500 0, Rc; = 2.4 W, To design the collector
to calculate the values of Rs and Rc
Rs = 600 W, Vex= 18 V · calculate the value of Rc :
To lind : 1. lc 2. VCE Stepl: V
Step 1 : To lind Ia : Vee.- CEQ ...(1)

Applying KVL to base circuit (Fig. 4.1.8(b)) to get.

Rc = ~+Is)
The value of 18 is unknown ·
V~- <Ic+·ls) Rc-Rs Is- VBE-ac+ls) Rs=O S _5 X 10- 3 =4 1.66 f.LA ...(2)
. · 'Is Pc~c - 120
=
:. Yex~(1 + (3) Is Rc;-ls Rs- YsE-:-(1 + J3) lsRs = 0 Substitute this value in Equation (l) to get,
. . Vex- Is [(1 + (3) Rc; + Rs + (1 + tl) RsJ .- VsB 0= 12-5 -
Rc; = (5 X 10-J + 41.66 X 10 II)
=1.39W ...ADs.

:. Is Step 2 : Obtain the value o~ Ra :

= R&+(l +J3)(Rc;+~
Considering the base circuit we get,
18-0.7
Vex-~ +ls)Rc-ls Rs- VBE =0
=! 600 k + (1 + 75) (24 k + 500)

. :. Is = 21.08 J.LA
OR V OlQ - 18 R8 - V 88 =0
VCEQ- VBE
+18V .. Rs = Is
...(3)

.. Rs = 41.66x
5-0.1
w-6 =103 .2 w .Ani.
..

• Q, 27 Derive the expreulon for the atablllty factor "S"

of a collector to baae blaa circuit and comment on
the reeult. Dec 02 Dec 08
Ana.:

As, ...(1)

(F-4141) Fig. 4.18(b) And substituting the value of ~ in this equation for the

Stepl: To lind lc: collector to base bias· circuit to obtain the final expression for S.
-6· To obtain the value of Ala/ Ale:
Ic = f3Is=75x21.08xl0
=
3
1.581 X 10- = 1.581 mA •••Ans. l. For the collector to base bias circuit,
Vee= Rc(lc+ls>+lsRa+VBE
Step 3·: To l'lnd Va: :. Vex = lc Rc +Is <Ra + Rc> + V BE ...(2)
Yes = Vcc-<Ic +lsHRc +Rs} 2. To find the stability factor S we take into account the
IS_ ((1.581 X 10-3 + 21.08 X 10~) (2.4 k + 500) change in Ic due to change in lao. the other two
..
=
y CB = 13.35 Volts. _
. '
~ parameters, VBE and J3dc are assumed to be constants.
3. When lcso changes by AJCao. 18 changes by Ms and Ic
26 Design 8 collector to bue blu circuit for the changes by Me- However v Ct:. and v BE do not cbange.
Q. VCEQ- v =
_ 5 ' 1CQ 5 mA, Vee 12 V and Pc.o 120. = = Therefore Equation (2) gets modified to,
Refer Fig. 4.:19. ·
O - AlcRc+Ms (RB +Rc)
:. -a lc Rc = Ms <Rs + Rc)

r.nsv - snluiro u s
 ~lc Devices & Circuita-l (MU)
4-37
• AJ.B -Rc
. . . Aic ... <Ra + Rc> ...(3) :. S' =
4. Substituting this value in Equation (l),
This is the required expression.
(1+ p~ 1+ fl

[a;!'".J "I + ~« [ R,~d ...(4) Q. 29 Derive the expression for stability factor S" Of a
S • I -fl.. collector to base bias circuit. Dec. 02. Dec 08

eomment on the result:

1. The stability factor S" is defi.ited as follows :
If you co~ th~ expressions for S of fixed bias and
_,....!_baset"~~~ cb~~ts then you will find that the value of s
coUectorfor

~·"' o uuc tas lS much less This indicate8 th S" . = aIc I

aflc1c fco and VBE constant
...(1)
point stability is better for the collectort.o base b' . • at the Q
l3S C.LIXWt.
0 •· 28 Derive the expression for S' ot a collector to base 2. From Fig. 4.20,
•. Vee = . .. .(2)
blaclrcull Dec. 02 Dec. 08
Ana. : The stability factor S' is defined as, Vee ...(3)

S' = A~ I .. . .. 3. Assuming leo and VBE to be constants, and differentiate

Equation (3) with respect to Ic to get,
1m BE and flc~c constant
(cl flc~c']
ole I ·
. . . [ l}clc-1(;\~)
or S' = av 0 = Rc + 0 + <Rs + Rc> flc~c . . .(4)
BE 1m and flc~c constant
=
As' Ic flc~c Is+ (l + flc~c> leo ...(1) af3ilc 1
But alc = S" Therefore Equati~ (4) gets modified
...........~-~-~-~~...........,
',
_

! . to,
~_,..........~ .........·iRe ,:· Ra+Rc[f3c~c-lc S"
-Rc = ~
. de
C)J
•+ .

r·............ + ........
Vae -~
-!,,':.!_Vee
.. -Rcf3~
Rs+Rc

..
1(;
S" .
=

=
1(;
flc~c- S"

f3c~c +RB +Rc

Rcfl~
'·.:::.................f .........· lc<Rs +Rc)
Base loop .. S" P&: <Rs + Rc> + Rc flc~c
2

-., .(F-309) Fig. 4.20 : Base circuit

.. S" =
lc<Ra +Rc)
z .
II considering 'the baSe circuit shown in Fig. 4.20 and apply flc1c (RB + Rc) + f}clc Rc

• KVL to this circuit to get :

.. · Vcc. =
(lc +Is) Rc + 18 R8 + VBE ...(2)
The expression for I8 in terms of V813 is obtained as below ·
;
lc<Rs +Rc)
"" f3c~c Rs + flc1c Rc +.f3! Rc
l(;(RB +Rc)
and substituting it into Equation (1). S" = ... (5)
.. Vcc. = IcRc +Is Rc +Is Rs + Vse ...(3) f3c~c [RB + Rc (1 + f3c~c)]

1c• = flc~c Is
But Q. 30 Answer the following questions for the given
Vcc. = f:lc~c Is Rc + I8 Rc +Is Rs + Vse circuit
Vcc.-Vae = IsrRs+Rc(1+f}~] 1. · What happens to voltage Vc H resistor Ra Ia
open?
Vee.- Vse
2. What ah6~d happen to Vee H p Increases
Is = Ra + Rc (1 + IJc~c) due to temperature ? ·
Substituting Equation (4) into Equation (l) to get, 3. How will Ve be affected when replacing the

= IJc~c[Rs :~(~~~J + (1 + f:lc~c) lcso

collector resistor with one whose
lc resistance Is at the lower end of the
tolerance range ?
~ and lao are one and tbe same. 4. If the translator . collector connection
f:lc~c Vee. f:lc~o: Vse + (1 + f:l~ Icso becomes open, what will happen to VE ?
.. lc • Re+Rc(l+f3~-Rs +Rc(1+f3c~c) 5. What might cause Vee to becomjf~C:1f
Ditf«.eotiate with respect to Vse to get, 18V? e•
aIc . f:lc~c o
avBI! I; o- Ra+O + f:l~Rc +
I. ••. 'J '.11 111 1 1 11 11 ' •
Electronic Devices & Circults-1 (MU)
Bias stabilization using volta~ ~~vlder bias circuit :

'~'to'ahali:e.~l£tlloei'Bi,.IUI_re'_oc:P~: .' ·.

Q
•
3~· Derive the expression for the stability factor s ot
the VC?Itage divider bias circuit. Comment on the
Dec. 02. Dec. 08
result.
Ans. : To derive the expresSion for s. , ~e same equation of "S"
(F-1389) Fig. 4.21 .
for the collector to base bias is used which IS,
Ana.: 1 + 13~ .
1. Vc = 18 v because if Rs is open then Is= o
' s = . ...(1) .
1-13dc [.Ms/Aic]
. :. Ic =Oand Vc =Vcc-IcRc= Vee·. . Ms
2. Vrn should decrease. and ~bsrltuting ~ value of Ale for the self bias circuit to
3. As Rc decreases Is, 1c and 16 will increase. So VI! will
· obtain the required expression for S.
increase.
L -0 th thr . · Vee- Vae
To obtain the value of Ala I 41c :
4. . "C - e current ough ~ wtl,l be II! = <Rc + Rs + R.J The Thevenin's equivalent circuit is shown in Fig. 4.23.
This is much lower than the originai 16 , :. VI! will reduce Applying KVL to the base circuit of Fig. 4.23, · ·
5. If lc =0 ~en Vce = 18 V. So if the transistor turns off and Vm = Is Rs + VBE + (lc +Is) Rs ... (2)
then.VCB = 18 V. ._ Considering V BE to be independent of Ic. we can
differentiate Equation (2) with respect to Ic to obtain,
Q,_31 Discuss voltage divider bias or self Bias used for
BJT.
aIs . iHs
0 = Rsalc +O+RE+~alc
Dec. 02. May 04. May 05. Dec. 05. Dec. 06. Dec. 08
a 18
Ana.: .. 0 = a~c<Rs+~+~
The cj.rcuit diagram of voltage divider bias is as shown in
Fig. 4~22. . a 18 -RE
Features of .t he circuit : ·
.. a~c = (RB +R.,)
...(3)

The resistors R1 and Rz form a potential divider to apply a MD ~

fixed voltage Vs to the base. A resistance R., has been connected in .. Me - (RB + R.,) '
the emitter circuit ·
Substitute this in Equation (1) to obtain,
+Vee
+Vee

([+Is> 1
•• .....................f+
Vee
_,....~.............t-
VTH +
<F·lZ4) Fig. 4 .23 : Thevenin's equivalent circuit for voltage
divider bias circuit
(F·316)'Fig. 4.22 : Voltage divider bias 1 + ~de 1 + 13dc
s= ...(4)
1 A [ -&__l= RE_l[
- Pl)c Rs + RJ 1 +~de Rs + ~ .

ca~v - ~ul uiiOIIS

 ~IC VV>rt'WVV ""' ...,......,,&CJ•t \MU) _

4-39
For an emitter follower, tbe collector current is given by,
lc = Pc~c Ig + (1 + p~ Icao ...(2)
From Fig. 4.24 ,
Vm - VBB
... (5) 18 = R11 +(1+P~RE
...(3)
-;i3 OertYe the
the voltage
•=ton for the atablllty factor S' for
blaa circuit. m;•·t•·''''Iii
Substituting Equation (3) into Equation (2) to get
Vm-Van_l
lc = Pc~c [ Ra + (l + p~ R;_J + (I + Pc~c) lcao
--.: 1be stability factor S' is defined as follows :
:. Ic [RB + (1 + p~ ReJ
=Pc~c (Vn1 - V8n) + ( 1 + fJ~ lcso [R8 + (1 +. p~ RsJ
l t\lc Dividing both the sides by Pc~c to get.
S = AV" ...(1) lc [Ro + (1 +P~ R~ (1+ p~
85
constant JCo and p Pc~c = <Vm- Vas>+ pdc
For a common emitter circuit . de

lc = Pc~clo+(l+Pc~c)~0 Icso [RB + (1 + Pdc> Rel

....(2)
leo and lcao are one and the same. 1 +Pdc
But~ = 1
Obtaining the expression for 18 in terms of V and
subsbblte it into Equation (2). For this referring the base
me self bias circuit shown in Fig. 4.24
l!p of ~IRe+ (1+jldJ '\:)~~~BEl~~~ ~ lcao RJ
Apply KVL to base loop to get,
·
L~. Tenn(1)
(21. (3) (-4) (5) J •.. (-4)

. (F-3l6(a))
Vm = laRs+VoE+IERE
. Considering the five termS in the above expression . and
= loRa+ VoE+(l +PjiaRB
obtain their partial differentiation with respect to Pdc·
Vm - VoE
The .terms·(2), (3) and (4).are constants so their derivative
" 18 = Rs + (1 + Pc~c Rs) · ..(3)
Will be.O.
Substituting Equation (3) into·Equation (2) to get,

lc :: Pc~c[Ro :~: ~:~ Rj + (1 + Pc~c> lcpo

... . ....·-.
~

_.. Base·.\
loop j
.............··

• uit
(F-325) Fig. 4.24: Base loop of self bias care
~de Vm Pc~c VBE + (1 + Pc~c> Icao .
= . '""B
D + (l+P~ Re Rs+(l~~.Rs v to ...(5)
• • _.,...h"IIY wtth respect to BE
Differentiating both Sldes i""'~
TermS
Considering tenn 5 of Equation (4) which is. Pc~c leBo Rn
S' = Differentiating with respect to Pdc to get, 1cso Rs
Since Icuo and R8 both are small, we can c;<tuale lcoo-Rn to

:. lcaoRn = 0 ...(6)
Hence the differentiation of Equation (4) is given by.

pdc 0 + Pdc) Rn + Pdc Rs] lc

S" [ . +"'RT
' pciQ ~-'de
Ana. : The llability factor S" is : . U~c~c Rf! - (1 + P~ Ra- Rs] = 0
...(1)
S" c aIc
a pck: coostaDt v
L :t •. \1 ·, 11 I II I l II II '•
Electronic Devicea & Clrcult8·1 (MU)

- lc [flo~e R8 - (l +Po~e> Re- R~

:. S" = Po~e (I +Po~e> Re +~ole Ro
VTH ,._. +V"t

..... ~ .. 12
R, +
l!i
- Po~e Re +(l +p~ Rs +Ro ·~12Volla

• Po~e (l +flo~c) Re + Po~e Ro Re • 88kh23.5 k.. 17Ji k

Dividing numerator and denominator by Re to get,
- Po~e +(1 + Po~e> +(R8 IRs)
S" = Po~e (l + Po~e> +Po~e <Ra IRs) Ic
1 +<RaiRs>
= Po~e [l + Po~e +<Ra I Rs>1 IC (F-361) Flg. 4•l5(c): Tbevenln's equivalent drcuft
Multiplying Nand D by (l + p~ to get
Step 4 : Calculate Ic and VCE :
. (1 + P.J [l + <Ro IRs)]
S" = (1 + p~ Po~e [l +Po~e + <Ra IRs)] IC ...(7) .. IC = pis= 180 x 12.68 xto-6 =2.283 mA ...Aas,

(l + P.J [l + (R8 IRs)] =

IE :: (1 + fl) Ia = 181 X 1Z.68 X 10-6 2.2951 mA
But S = 1 + flo~e +<Ro I R_s) Applying KVL to the collector loop to write
Hence Equation (6) can be written as, 6- IC Rc - Vcs.- IE Rs + 6 0 =
, Sic
S
= (l+P~Po~c :. Yes = 12-ICRc-IERe .

Q. 35 An ampllfter circuit Is shown In Fig. 4.25(a).

= 12 _ (2.283 X 2.5) - (2.2951 X 0.94)
Determine the co-ordinates of the operatl~t = 4.135 Volts
Q and the thermal stability factc:w S.co· ltBtD Step 5 : Calculate S1co :
For a voltage diVider: bias circuit S100 is given by,
.if. 1 + (Raf Rp)
Srco = d leo= (1 + fl) (1 + fl) + (Rsf Rs)
1 + (17.510.94)
= (1+180).(1+180)+(17.5/0.94) - 17.79 ~·
Q. 35 Design voltage divider biased circuit~
lea= 5 mA, Yceo =5 V and P=100. lrBIII
An~. :
(a) Glveo clrc:uit (b) DC equlvaient clrc:uit
Given: VCEQ =5 V, lcQ=5 mA, P= 100
(F·360) Fig. 4.25
Ana.: Step 1 : Calculate v E' ~a; rE :

Step 1 : Draw the DC equivalent clrc:uit : Assuming Vcc = 16 V

The DC equivalent circuit is as shown in Fig. 4.25(b). This
VB = 0.1 Vcc=0.1 X 16= 1.6 V
is obtained by replacing all the capacitors in the given circuit by
opeo circuit lc 5 X 10- 3
Step 2: Draw the Theveoin's equivalent cln:uit:
Ia = p 100 =50~
The Tbevenin's equivalent circuit is as shown in IE = (1 + P> Ia = 101 X 50 X 10- 6 = 5.05 mA
Fig. 4 .25(c).
Step 3 : Obtala 18 :
Applying KVL to the base loop ,
Vnt-ls Ra- Yse-l£Re +6 =0
:. - 2.92 -Is Ra -0.7 -(I+ 1})18 Re+ 6 = 0
:. 2.38- Is £Ra + (1 + fl) Re1 = 0
• 2.38
:. ls = Ra + 0 + P> Re
Prom tbe data abeet PcrnJic:al). 180 and Re 940 nor 0.94' k. =
:. ... • 17.5 k: + (~i~) X 0.94 k. = 12·68 J.l.A
(B-2653) Fig. 4.26(a)

I' .I , V '. II I II I I II II ·'

-e~eetronlo Oevfoee & Circuita-l (MU)

SteP l : cakalate Rt and Rc :

J)
•'II
• VB
18 •
J.6V
5.0!'1 mA =316.83 Q
= 2.44 Volts
Fig. 4.27(a) shows the Thevenin's equivalent circuit.

Vee- Vc +12V
Rc • lc
But Vee • VB+ VC1! = 1.6 + 5 = 6.6 V
16-6.6
:. Rc = 5 mA =
1.88 k.Q ...Ans.

(F-47l0) Fig. 4.27(a)

Vm- vllll 2.44-0.7

18- = R8 + (1 + f})R6 9.56 k + (101 X 1 k) =15·74 J.LA
.. ~· = fl 18 =100 X 15.74 X 10-<i
= 1.57 mA ...ADs.
Step 3: IE = (1 + f}) 18 = 10~ X 15.74 X 10-6
VB = VE +VB!! =·1.6 + 0.7 =2.3 v = 1.59mA ...ADs.
:. Assuming current through R 1 is I 1 and through~ is 12• Step 3 : VCI!Q and operating point :

11= =
1018 10 X 50 J.LA = 500 J.LA V CEQ = V.ee- IC Rc·- IE RE
:. ~ = =
Il-18 500-50=450 J.LA = 12- (1.5? X 2.2)- (1.59 X 1) =6.96 V

VB 2.3 :. Operating point = (VCEQ• ~

:. ~ = I ;. 450 X 10-ii = 5.lll k:Q ••.Am: = (6.96V, l.57mA)

Vee- Vs 16-2.3 Part D : DC load Hoe :

Rl = It = 500x 10-6 =27.4 W ••.Ans. The DC load line intersects the X and Y axes at points A
and 8 respectively. 1'bC:ir co-ordinates are as foUo~s :
Q. 36 For the circuit shown In Fig. 4.27, find operating
point and plot DC load line. · i!i4W A = (V00 0)=(12V,OmA)
8 = (O, Icmax) =(0, VcrJ Rc + Rs) =(0, 3.15 mA)
The DC load line is as plotted in Fig. 4.27(b).

(F-4716) Fig. 4.27

Ani.:
Part I : 0perat1ng point
Step 1 : Draw 'lbevenln's equivalent circuit : (F-mt> Fig. 4.27(b): DC load line ·

Ra = RJII ~=47 k ll12k 0. 37 .Which bluing will you use If BJT 18 to be used aa
·• conatant currant source? Juatlfy.
= 9.56~
rvl<l 0-1. r1l<1 05. Dec . 06. Dec 07 Dec 10
R. 12
Vn~ ., ~XVa;=4f+i2 X12
Rt+~

t: a :. 'J •• ulultll 11 s
 Electronic Devlcel & Circuita-l MU both are constants, the emitter current 18 also
As V8 and Ra
Ana.: 18
= Constant So collector current .IS constant
Is cons~t. oflc th• alue of Rc . Thus the self bias circuit acts as a
The collector current of the self bias circuit remains Irrespective ev
constant irrespective of the value of Rc· Considering the self bias constant current source. . -
circoit of' Pig. 4.28 and I » 18 , then expression for the base Wh 18 potential divider btaa commonly uaed for
38
voltage V8 is. Q. lh/BJT 1 I•J§i•b

... (1) An•.: . . · r, 11

The advantages of voltage divider bias crrcwt are as .o .ows :
Tbe value of V8 is constant because R1• R~ and Vee are 1. It bas the smallest value of S .among~~ ~ bi:mng circuits.
coostant. This shows that the bias pomt stability IS highest for the

The emitter voltage with respect to ground is given by, self bias circuit.
2. It is possible to avoid the loss of signRal Thig~ bdoeyconnecting
Vs = Va - VBii an emitter bypass capacitor across e· s s not have
= Ya - 0.7 ...(2) any adverse effect on the other advantages of self bias
r------voc circuit.
3. R introduces a negative feedback. This will make the self
8
bias circuit more stable. So all the other advantages of
negative feedback get attached to this circuit _
Voltage divider bias circuit is therefore the most widely
used biasing circuit.
Q. 39 State disadvantages of voltage divider blaa
circuit.
Ans.:
The disadvantages of voltage divider bias circuit are as
<F·332) Fig. 4.28: Self bias circuit
follows, .
As Va and 0.7 both are constants, the emitter voltage al~o is 1. The ratio R8 I R8 needs to be low for better Q-point
COIISbmt. stabilization. So R8 should be small and RE high. But this
Tbe emitter current is given by, reduces the input resistance.
VE · 2. Reduction in gain due to negative feedback if R is
1E = Ra =Constant ...(3) onbypassed. . B

0. 40 Compare various types of biasing techniques used for BJT. Dec. 02. Ma 08. Ma 09
Ans.:
Sr.
No.
1.
resistance
2. Negative Not used Included Included
feedback
3.

4. Poor Moderate Good

s. Configuration
(f·334) (F-335) (F-336)

Vee

Re

t. I . 'J , U Ill I IIIII

 ..
~ Oevloee & Circuita-l (MU)

The materiaJ uiCd for the diode is same as .that for the

' ,..
transistor and bas same temperature coefficient. Therefore the .
:
I'
change in voltage ocross the diode (Vp) will be exactly equal to
change In V88 due to variation in temperature. Hence the first two
. 1be collector, to b,Ue bias c~n:.uit and the volta e divider
ciJt111t .., used to mtmmu:e the vanatton In '"'· Q . g terms in Equation (4) cancel each other. Thus the change in VB£
.. --..~ b · . •uo pomt co11ector
cwneot ~ (a.-.u YVanattoos in leo V and A The . , due to temperature is compensated by an equal but opposi~ c~~e
.--a.~ o( fcodblct
.re ~ amplifiers. ' Bll t'do· SC CJI'CUJls
in VP and the collector current becomes insensitive to variatlon m
-~to (tbe' ne)gati':dedfeedback present in these circuits the VDB' Thus we minimize the Q point instability due to variations in
~ft~Pti•_...... gam proVt to the AC signals is reduced VDB by using the diode compensation technique.
~~- lf. we_annat tolerate the loss of signal due to bias 2. Diode Compen•atlon for leo :
$11bi!i1.11b0D cli'CWts then the compensation techniques sed .
<rder to minimize tbe instability of the operating po'•nt arev u ftem For tbe germanium transistors, changes in leo due to
~to..:..: • and . . . ery o n
bod!__..u~ oompen~tt.oo techniques are used to provide variations in temperature are more prominent tban changes in V BE
.,antDUtn bias and tbennal stabllJZation. due to temperature. The diode compensation circuit shown in
TypM of compensation techniques : Fig. 4.30 offers tbe stabilization against variation in leo-
1. Diode Compensation for VI!IIE : Compensation
1be.vob8e divider bias clt:cuit witb diode compensation is The diode and the transistor are of same type and material
as sbown m Pig. 4 .29. Tbe additional power supply v is Therefore tbe reverse saturation current of the diode i.e. lo will
()i«cted in order to forward bias the diode D. This diode ~ of
0
increase witb temperature at tbe same rate as tbat of current leo of
Slll)e material and type as the transistor. The voltage VP across the tbe transistor.
diode bas tbe same temperature coefficient(- 2.5 mV?C) as tbat of From Fig. 4.30,
tbe base to enlitter voltage V BE· ·. Vee- VBE Vee
C....E l!t'-clll I = R - R = Constant.
I I
Prml Fig. 4.29 , the KVL for the bS:SC circuit gives : The base current 18 =I -JO. Substituting this value of 18
Vm = Is Ra + VaE + (Ia + Ic> RE- VF ...(1) in the following·equation :
But, lc = Pc1c Ia + (1 + P«> lcso ...(2) lc = flc1c I a + (1 + flc~c) leo
:. V111 = Ia<Ra:t-RJ+VaE+IcRE-VF ...(3) = flc~c (1- Io) + (1 + P~~o> leo
Prml Equati~ (2).
.. lc = ll<t: I - llc1c lo + (1 + llcJcllco ... (5)
lc (1 + Pdc) Icno
Ia = Pc~c Pc~c . L SoEqual~cancel
opposite terms.
they other
each
If the saturation currenf of tbe diode (lo) is equal to the
leakage current leo of tbe transistor, then ~ last two terms in
Equation (5) will get cancelled.
:. lc = fl~~o I ... [Since Pc~c lo = (1 + fl«> leo 1
As I = Constant. Ic will also remain · constant and
compensation is successfully provided
From tbe last two terms of Equation (5), if Pc1c >> 1 and if
JO of D and leo of the transistor change equally over the desired
temperature range then Ic will remain constant. Thus compensation
is provided.

<F·337) Fig. 4.29 : Diode c:ompeDS8tion for Vatt

Sobltitutiog this value in Equation (3) to get. Germanium

tranlllstor
V .!c. (1 + P«> (Ra + Re) L . + V + Ic Re - V"
'111• ~- at_ + R.,) _ Pc1c "CBU BB

:. v Ra + RE (1 + ~«> 1 _ <Rs + Re} (1 + P«> 1cso

llJ. vII! - vp + p c pdc
L2._ ... (4) CF-338> Fig. 4.30 : Diode compensation for leo
1beie ~en:na are equal and
oppo~ite. So they cancel each
other-

I' · 1 ~ •• IJ I II I I 1111 ' •

 Elecbonlc Devices & Circuita-l (MU)

Q. 42 Wrtt. ahort note on : Thenn111 runaway.

Ana.:
Tbe col.lector region of a transistor dissipates heat. As we
i~ the amount of power dissipated in transistor then junction
lelllperature increases. The maximum power that a transistor can
dissipatl'l without getting damaged depends on the maximum
temperature that a collector • base junction can withstand.
Tbe rise in the coUector - base junction takes place due to
two rea.soos :
I. Due to increase in the ambient (surrounding)
temperature and <F·l43)Fig. 4.32 : Voltage divider bias circuit
2. Due to the internal heating.
Out of them the internal beating process is cumulative as ·The power ·devel~ at the collector j~ction in the
explained below : absence of ac input signal, IS gtven by,
1. An increase in coUector current 1e increases the • Pc = V csle =V CE le · ...(2)
power dissipated in the collector-base junction of 2
Substituting Equation (1) in Equation ( ) to get,
2
the transistor.
• Pc =
Veclc -Ic<Rc+Rs)
Po = Ves XIe Differentiating this equation with respect to lc-
2. This will increase the temperature of C-B junetion.
3. As the ~sistor has a negative temperature ...(3)
coefficient of resistivity, increased junction
teJ:ilperature reduces its internal resistance. The condition to avoid the thermal runaway
4. The rednced resistance wiU increase the coUector (Equation (3)) can be rewritten as:
cmrent further.
dPc die 1
This becomes a cumulative process which will fin~y ,
damage tbe transistor due to excessive internal heatiDg. This ole xorj < 9
pocess is known as "Thermal Runaway'~. , · dPc die
.. ole X;rrj X9 < 1
· 1c Increases -............ . .

/ . · Powerdl~patk.>n Increases In this expression

a~e
or.and
J
9 will always be positive. .

~~ is negative.
Resistance of ) . .
the device decreases .
There(ore this equation will .always be satisfied if
\.. This wtlllncrease the
~reof C-Bjunctlon
Hence to avoid thermal runaway.
oPe
a~e .< .o ...(5)
<F-342) Fig. 4.31 : Thermal runaway process
To al'oid the .t hermal runaway , Substituting Equation (3) into Equation (5) to get,
(1) Never exceed the collector current beyond a certain :. Vee- ile eRe+ Rn) < 0
. maximum value specified ·by the manufacturer. (2) Neve( exceed Vee
the internal power dissipation above the maximum permissible i.e. lc >. 2 <Rc + Rs) ...(6)
value. (3) Use beat sink: to radiate the heat into atmosphere.
But from Equation (1) the collector current is expressed as:
Q. 43 Prove that for a voltage divider bias clrcuh for Vee-VCE
common emhter amplifier, the condhlon for le = .<Rc + Rs) .:.(7)
• Vee
thermal 8tabllhy Ia VcE < T· Substituting !IDs in Equation (6) to get,
Vee-Yes Vee
Ans.: ~+Rs) > 2<Rc+Rs)
Considering Fig. 4.32 and ll$Sumiog that the transistor is in Vee
the active region. By applying KVL around the col1ector loop, to .. <Vee-Vc;F) > T
set. : . V CE < Vcc 12 •••Proved.
Yes =
Vee- Ic CRc; +Rs)-18 Rn H V?! is less than Veel~ then the operating point will be in
Neglecting the last term, the safe ~gt.on, where thermal runaway will not take place. But if
VCE =
Vee- Ic CRc.+Rs) ...(l) t!'e Q J>(lmt IS located such that VCE > vcc 1 2 then the transistor is
Vee - Yes likely to get damaged due to thermal runaway.
:. lc ;: <Rc + RE)

t; :t ·, 'J '. II I II II It II !,
 Electronic Devices & Circuits-1 (Eiex.-MU) 4-45

Chapter 5 : AC Analysis of BJT Amplifiers

Q.1 What Ia a linear amplifier ?
Operation of the RC coupled CE ampli.fter :
Ans.: A ~ear amp.lifie.r magnifies the input signal and produces
~ output SJ.gnal which 1§ larger in size as compared to the input
stgn~ and bas sam~ shape as that of the input signal. Amplifier
conSists 9f some active device such as BIT, FET etc.
Q. 2 Define R1, Ro, A~o Av and bandwidth for a voltage
amplifier. · biased the transistor in its active region using the biasing
Ans.:
1. Input "resisia~ <Rt> : Input resistance (R;) of an amplifier
~s defined ~ the resistance meas,\lred by looking into the
IDP_Ut termmals ~f an amplifier. The value of input
resistance R; of an Ideal amplifier should be~- . base current, proportional variations take place in the collector ·
Output resistance (RJ : Output resistllllce of an amplifier
is defined as the resistance measured ~tween the output
terminals looking back into the amplifier with its output ·
terminals open circ~ted and the input voltage source ~bort
~uited, i.e. RL =oo and V s =0. The output resistance of
an ideal amplifier is equal to 0 n.
3. Current and voltage gains : Current gain A1 is defined as
the rntio of output current of the amplifier· to its input
current
... Ax .- - ~
~
The overall voltage gain Av of an amplifier is defined as
the rntio of its output voltage to its input voltage.
. Av
.. -- ~
v.
I
When the ac input signal is absent, the value of de base
purrent of the transistor i~ IBQ which is called as the quiescent point
base current Corresponding to IBQ, a quiesc.ent de collector current
ICQ also flows tbrougb the transistor (~ = 13dc IBQ) and the
collector emitter voltage is VCEQ' All this happens because we have
components. When small ac siDusoidal signal is applied a! the_ input
of the amplifier, an alternating base current, starts flow1~g m the
circuit. This base current varies above and below the Q pomt value
of the base current (iBQ) as shown in Fig. 5.2_. Thus ~ ~ si~al is ·
superimposed on the DC current IBQ. Due to these vanations m the
=
current, because 1c j3 Ia· As· Ia increases Ic also increases and
with decrease in Ia, 1c will also decrease as shown in ~g. 5.2. Thus
I and I are in phase but lc is a magnified version of Ia· Ic varies
B C • T
above and below its Q point value IcQ· This varymg 'C passes
through the collector resistOr Rc to produce a varying voltage drop
1c Rc across it. This voltage drop 1c Rc is in phase with the
collector and base currents as shown in Fig. 5.2. .
The collector voltage is given by,
Vc = Va:-lcRc ...(1)
. Therefore. with changes in the voltage drop IcRo the
collector voltage also will vary as shown in Fig. 5.2. However Vc
and Jc Rc will vary in exactly opposite manner with respect to each
other, because as Ic Rc increases Vc has to decrease according to
Equation (1). This collector voltage is then coupled to the load
through the coupling capacitor Cz. It will block the .de part of Yc

Hence the voltage gain (Av) of an ideal voltage amplifier is and allow only ac part to pass througb as shown in Fig. 5.2. The ac
signal amplitude obtained after Cz. This is the output voltage. Its
equal tooo.
. magnitude is much higber than that of the input signal and its shape
4. Bandwidth (B.W.) : The bandwidth of an amplifi~r is is exactly same as that of the input signal. ·Thus the input ac signal
· defined as the rnnge ·of frequencies over which an amplifier.· has been successfully amplified
can amplify the input signal satisfactorily.
Q. 3 Explain the operat16n of single stage RC coupled
amplifier. .
Ans. : A single stage RC coupl~d amplifier using transistor as an
active device is as shown in Fig. 5.1. . ·
-tVcc
c1 arid c2 are
coupling capacitors

------~----~--~~~=~
(F-~> Fig. 5.1 : Single stage RC coupled cE ampll.fter I

. and C are called as the coupling

2
The capacitors cl • • led to the amplifier
capacitors. As the Load resistor RL IS . cou_p . ailed RC i :
. "t this amplifier IS c as
through the couplidg capacl _or, . . ected in the Common
18 (F-391) Fig. 5.2 : Waveforms showing the process of
COUple'rl amplifier. The transistor c:;:n plifier is called CE
Emitter (CE) configuration. Therefore IS am
ampllftcation
amplifier.

I! a •; \1· S II Ill I I fill •;

 Electronic Devices & Clrcults-1 (Eiex.-MU) .

As seen from Fig. .5.2. there is u 180° phose shill between

the ~utpu.t. and input or the output is said to be tm "inverted"
VeJ'SI.OO Of IOpUl.

Q. 4 l:xp..ln emitter follower amplifier. Why Ia lte

name emitter follower ?
Ana. : ~ co~mon collector or emitter foll~wer configurotion is
as shown m F1g. 5.3. The resistors R R and R provide de
bia~ing for the transistor. cl and <; are ili~ co~ piing c~:pncitors and
RL Is the external load resistance. ·
(F·398> Fig. 5.5: Common base amplifter
• c 1 and c2 are me coupling capacitors, and RL is the
external load.
Operation : • .. . .
The input is applied to the errutter wbJie output IS .taken
from the collector. The base is connected to ground (f~r a~ Signals
only) via a large capacitor C which acts as a short ~lfCUJt for ac
signals. Thus the base tenninal is the common t~rmma~ between
(F-396) Fig. 5.3 : Common collector amplifier ~ircuit input and output. In the positive half cy~le of t~put s1gnal, the
emitter vQltage varies sinusoidally at?ove Jts Q-pomt value. Thus
Wavetonns : , when Vbe reduces, Ib and Ic will reduce. So tbe voltage drop across .
The input voltage is applied at the base of the transistor Rc ~ill reduce. ·Hence the collector voltage will increase above its
~~ ~~ to ground and the-output of amplifier is taken from the Q-point value. · Input volta-ge
enutter With respect to ground. As the emitter voltage follows the Thus· a positive half vin
base v.oltage, the gain of this amplifier is approximately is equal to.· cycle is obtained at the output
I. A.s shown in .Fig. 5.4, the input and output voltage waveforms corresponding to the. positive
are m phase With each other. The output voltage amplitude is half cycle at the input as
exactly equal to that of the input voltage. shown in Fig. 5.6. Similarly a
vm negative half cycle is obtained
Input voltage
PA~
6,
j ~~~.~~~.:~:~~~:~)~~~:r
i ~••t
at the output corresponding to
the negative half cycle at .the

, . i~i
: vm : :
input. In this way there is no
phase shift between the input
•and output.
Q. 7 List applications of the CB amplifier.
(F-399) Fig. 5.6

Output voltage ~
o'@&:
l .• t
Ans. : The important applications of the CB amplifier are :
1. As the high frequency amplifier having large bandwidth.
l l~l 2. For the impedance matching. · ·
(F-m) Y~g. 5.4 : Input output waveforms of an emitter follower Q. 8 What do you understand by small signal
operation?
Due to the voltage series negative feedback prese'nt in ~
emitter follower circuit, it possesses all 'the advantages of the Ans: : If.the amplitude of the input ac signal being applied to the
negative feedback. Some of these advantages are very high input ~plifier JS ~mall (few mV), then the amplifier is called as a sma11
impedance, large bandwidth, low output resistance, low noise, low Stgnal ~tnplifier, at_~d the Operation of the amplifier is called as
distortion. Input impedance of the common collector amplifier is s~all s1gnal operatt~n. As the input signal is small, the transistor
high and output impedance is low. Input and output signals are in . wtll operate ?n th.e linear region of 'its transfer characteristics and
phase i.e. there is no phase reversal. · produces a. distort,i.on less output as shown in Fig. 5.7. This is why
As the output (emitter) voltage of CC amplifier is equal to the small Signal amplifiers are also called as linear amplifiers.
vo
the input voltage and in phase with input voltage it is said that
emitter follows the base. Hence the name emiiter follower.
Q. 5 State applications of the emitter follower:
AM.: The important applications of the emitter follower are :
1. As buffer amplifier.
2. For the impedance matching.
3. As the output stage (Power amplifier).
Q. 6 Explain the operation of common ~·· amplifier .
Ana. : The common base amplifier configuration is as shown in
Fig. 5.5. The resistors R 1, Rz and R1, provide the voltage divider
biasing for the transistor.
(F'-40Q) Fl · 5.7 : Transfer. characteristics
e a :; \1 · s 0 IIIII 0 II S
 !!ectronic Devices & Clrcutts-1 (Eiex.-MU)
4-47
Q. 9 Wrtte short notes on • H b
of BJT amplifier. ' y rtd ft equivalent circuit The ac resistance of a diode is given by
26mV
r.., = ~- .....(2)
AM. : A transistor can be treated a
in Fig. 5.8(a), and the small signalsha ;;o port n~twork as shown
i Where I 0 is the de current flowing through the diode. The
same equation can be used for the diode shown in the re model in
shown in Fig. 5.8(b). y nd-1t eqwvalent circuit is Fig. 5.9(b). The current 10 is replaced by I2 and r~ is replaced by rt.
26mV ·
The hybrid-n equivalent circuit consists of ;', re = -I- .....(3)
1. The small signal resistance r _two components: ·E
Here 15 is the de or Q point emitter current Thus the ac
2. A dependent current source ~ Vbe resistance of the diode in re model is determined by the de value of
r--..:..._--eC + 8 + •.!!!......• I 5 . The diode in Fig. 5.9(1)) i~ replaced by its ac resistance re to get
the final re model for the common base configuration as shown in
Fig. 5.10.

E
E
(a) Transistor as two port · (b) Bybrid-n eqUivalent
network circuit of BJT <F-1424) Fig. 5.10: Common base re equivalent circuit
. (F-1408) Fig. 5.8 . .
The small signal·resi~tance .rn is defined as, Q.11 . Draw and explaln r. model for conimon emitter.
configuration •
rn = .
.Yc.
I
b Ans. ·: The· common emitter configuration is as shown in
...(1) .
The alternative expressions for rn are : Fig. 5.ll(a). The input is connected between base and emitter
terminals and BE junction is forward biased. The output is
. ~VT YL obtained between the collector and emitter and the CB junction is
.
rn I = L_
BQ "
=
-cQ
...(2) · reverse biased. The BE, junction is replaced by · a diode and a
. r,. is called as the diffusion resistance or base-emitter input controlled current source appears between the collector and base
reststance. The_value of r, depends on the Q-point parameters. (I~Q terminals as shown in Fig. 5.ll(b): The controlled current source ·
and :fw). The output side of the transistor is represented by a
dependent current source marked "g,., Vbe"• where g, is th~
.
. terminals has a value of I and
between collector and base
I. = Pib .....(1)
.
transconductance of the transistor which is defined as : The current through the diooe in Fig. 5.ll(b) is given by:
Ie = I. + Ib = ( 1 + t} ) ~ ..... (2)
ICQ
8m - - ...(3)
. - VT
The small signal transconductance is also a function of the
Q-point parameters and it is directly proportional to the de bias
cnrrent
Q.10 Draw. and explain '• model for common base
configuration .
Ana. : Jk common base configuration of a transistor _is shown .in
Fig. 5.9(lt). The base emitter junction· is forward bt~ while (a) A common emitter (b) Approximate model for
collector base junction is reverse biased. Th~ forward btased EB configuration the CE conftgn;.tion
junction ·can be represented by a diode m the re model of (F-14l5)F1g. 5.11
Fig. 5.9(b). For the output side , But as the value of Pis much hi~ than 1 ,
• . aI
I · = . . .....(l) le "" t} Ib . , .....(3)
Thus a con;oJled c~nt source appears on the output side . The diode in the approximate model of Fig. 5.ll(b) is
as shown in Fig. 5.9(b). replaced by the ac resistance re and the re model for the common
emitter configuration is drawn as shown in Fig. 5.12.
C·

It= Ib
······•
8~---..,....~
+
(b) remodel oftbe CD
(a) A common base traJ]Sistor
configuration
configuration E E
(F-1423) Fig. 5.9 <F·14l6>Fig. 5.12: r. model for the CE configuration

f: a !. 'J · S II I II I I 0 II S

•
 4-48
ters associated with this model are input
The four param~ current gain and output conductance.
0.12 sate merha and demerfla of r. Model. impedance, voltage ratio, letely different from each other, this set
Ana.: . th . units are comp
Smce elf . . 11 d as hybrid parameters. . .
Merits otre Model are , of parameters IS ca e . -
h parameter model of CE ampiHier.
1. Tile 'pllJ'Ilmeters of r. model can be determined for any a. 14 Explain the •
tegioo of operation within the active region.
2. lt is a simple and less elaborate model of a trnnsistor. Ane .: . . the simple CE configuration of Fig. 5.15 (a).
3. These parameters can be obtained easily from the "h" Constdenn? th four variables are as follows :
For this configuration . e ·
parameters which are specified by the manufacturer.
1. Input'current li =lb
Demerits ol' reModel , .2. 'Input voltage Vi =Vbe
I. re model does not account for the output impedance level of 3. Output current lo =Ic
a device and feedback effect from the output to input.
4. Output voltage Vo =Va:
2. This model is sensitive to the de level of operation of the
amplifier. Therefore the input resistance will vary with the
de operating point. '
Q.13 Explain hybrid model of BJT.
Ma 09,Ma 10.Dec.10· ®
'ij;"+
..
:p•.,O port Output LEmittor ls ~
between input and wtpul
active
device.
port (a) CE confi~ration (b) b-parameter equival~nt for ·
transistor in CE configuration
1 (F-414) Fig. 5..15
<F-410 ) Fig. 5.13 : Transistor as a two.port system Applying KVL to the input loop of h-parameter equivalent
circuit of Fig. 5.15(b) to get,
The bybrid equivalent circuit consists of four quantities
caUed the hybrid Parameters which are hn, h12, h21 and h22• These ybe = hje lb + hre vee . ...(l)
are tbe components of a small signal equivalent circuit. Fig. 5.14 Applying KCL at the collector node of Fig. 5.15(b) to get,
shows the h-parameter equivalent circuit of a two port network. lc = bre lb + hoe V ce . ...(2)
· h11 . 1
0 Expressions for h-parameters for CE configuration can be
2
obtained from Equations (1) and (2) by letting Vee or lb equal to 0.
b-parameters for CE CC?nfi.guratioi,l are :

~
1 2 \
(F-41 I ) Fig. 5.14 :
b-parameter equivalent of a two port network
Table 5.1 lists the h-parameters, their expressions and their ·
names along with their units.
TableS.l

8r. .... Name

No.
1. hu Input Ohms
impedance vi I
hu=T hoe ;::: ~
I V0 =0 v ce
2. hl2 Reverse 0 ·15 Draw hybrid equivalent model for common base
voltage ratio v.
h12= v configuration. . · ·
0 i-=0
, I
Ana. : h·parametera of common base configuration :
3. ~~ Current gain
I
~~ = i. hib = ~
I
v0 = 0 .I
I
- .• Vcb=O
hn, = t
e Vcb = O
4. ~ OUtput Siemence
conductance 1._
h21= v
0 11= 0 hrb =~
v cb hob= V
I
I. = 0 cb I.= 0

e :t '. II '• II I II I I II II S
 _:Iectr.onic Devices & Circuits-! (Elex.-MU)
~49

conditions. The parameters of other equivalent circuit <re model)

can ~ determined for any region of operation within the active
region and are not limited by the single set of parameters provided
by the specification sheet.
· Q. 19 For CE amplifier with bypassed Re .d erive the
. expre8slons for Av, " , Z. and Zc,.
(May 07. May 14
(a) Circuit {b) Hyb 'd ..
n eqwvaient circuit Ans.:
(F-416) Fig. 5.16 : h-parameter • al
equav . ent circuit" The CE ampiifier with bypassed Re is shown in
Q.16 Draw hybrid equivalent mOdels for ~om Fig. 5.18(a). R., ~and Rs form the voltage divider biasing circuit
collector configuration. . mon to bias the transistor in the forward active mode. The coupling and
bypass capacitors are assumed to be large enough so that they are
Ans. : .h-parameters of eommon coll~t

t IV==O
. replaced by short circuits in the_ac equivalent circuit
Analysis:
0. = .. h,. ="';flgu-., Step 1 : Draw the ac equivalent circuit :
The ac equivalent circuit, obtained by replacing all the de
Vc,;=O sour~s and capacitors by short circuit is shown in Fig. .5 .19.

I
h.,., = v-
ee ~=0

Fig. 5.18 :CE amplifier Fig. 5.19:AC equivalent circuit

(a) Circuit (b) Hybrid equivalent circuit
with byp35Se4 RE
<F-417) Fig. 5.17 : h-paramerer equivalent circuit and .
Step 2 : Draw the hybrid-1t equivalent circuit :
expressions for CC configuration Replacing the transistor in ac equivalent circuit_ by the
·a .17 State the typical values of h-parameter for the CE, hybrid 1t equivalent circuit is shown in Fig. 5.20. .
CB and CC configurations.
Ans.:
Table 5.2: Typical values o~ b-parameters for different
configurations

(F-1474) Fig. S.20 : Hybrid'-n equivalent circuit

br 50 Step3: Expression for voltage gain ( Avs> :

=~
4
by. 2.5 X 10- 1 ...(l)
. Avs Vs
4. b0 25 ~ 25 flAIV ·0.49 fJ.AIV
Q.18 State merits and demerits of hybrid model · But V0 = Voltage developed across (r0 II Rc II ~)
due to current gm V11•
Ana.: MeritS of hybrid model are ,
1. h plU'3llletecs ~ be easily measured. · . . .. vo = - ~ Vx (roll Rc.ll ~) ...(2)
2. They can be calculated fiom the static cbaractenstlcs of .
transistor. . . beets
Manufacturers pr~vide h parameters ~ tberr _data s. . · :
And v" = Voltage across R.'I wflere R.'I = ( R 8 II r,J.
3.
easily and convemently m crrcUlt
4. h parameters can be u sed
(Ro II r,J
analysis and design. .. vfl. = Rs + <Ro II rx) X Vs
Demerits of the b-paramere~ are ,
. The hybrid parameters suffer from a major disadvan~ge
that they are defined only for a partic~lar set of operating ... (where R 8 = R 1 II~)

casv-solutiOIIS
 4-50
z::::::o
~lc Devices & Circuita-l (Elex.-MU) . _ 8m V" X (r0 II Rc )
...(7)
...(3) . Io = (ro II Rc) + RL

From Fig. 5.22(a) •

, Substituting Equations (2) and (3} into Equation (1) to get,
V11 =
•
It, r~~
the principle of current diVtston at Node
. . . .
But It, is obtained by ustng
Avs = - 8m V' (ro II Rc II RtJ X ( Ro II r,J B.
£Rs +<Roll r,J] v" '
(RRII r,J . :. It,
' Avs ,.. - &n (ro II Rc II Rt.) X Rs +(Roll r") ...(4 )
This is the required expression fur voltage gain. The . V
.. 11
= Ru r.
R8 + r11
X I; ·= <Roll r,. ) I; ...(8}
negative (-) sign of Avs shows that V0 and V8 are 180° out of
pbase with respect to each other.
. . th
Substituting e ex · " ·
v
pression of into expression for 10 to get,

4:Exprealon for tbe input resistance R: : _ -L<rall(iex(R llrn >I;

Step lo - .Rt_ + (ro I R:c) . . B . .

From Faa. 5.20, me ex,pressioo for R; is, I gm (r0 II'Rc ) <Ru II r,) ·
...(9)
Current gain AIS= 'J. = Rt. + (r0 II Rc) ·
~ = <Rs II r"> = <R, II Rz II r.J ...<~>
" I

This is the required expression for the current gam.

•

Also R; = r" the given circuit as shown In Fig. 5.23,

Step 5 : Expression for output resistance R:·: Q.20 For
d8termlne Z1, Zc,, Av·
May 15. 10 Marks
The output resistance R' is obtained by setting the
0
independent source Vs to zero. As Vs =0, V" =0 so g.,. V, =0 ail<:l
the hybrid-n circuit gets modified as shown in Fig. 5.21.

<F-1415) Fig. 5.21 : Equivalent circuit to calculate R:

· So the output resistance looking back into the .output

tenninals is, (B-2645) Fig. 5.23
, Ans.: .
R0 ' = ...(6)
Giv.e n :~ = 150, Assunie VA =·oo
R, = Type of circuit: CE amplifier with bypassed RE
Step .6 : Eq»ression for current gain (Am) : Type of mOdel : Hybrid - n
Part I : DC analysis
AIS = ·~I j
Step 1 : Thevenin's DC equivalent :
Io Fig. S.22(b) , OutPut current 10 can be obtained by Rz . 16 .
coosidering the current division at Node A. The current gm V, gets Vm = R 1 +Rz xvcc_
=68 + 16 x12=2.29V
divided between (r0 II Rc> and R._. . R = R II '.,'2
D = 16 x 68
B l 16 + 68 =12.95 k.Q

,.----Nodile
.~......

(a) (b)
<F-147'> Fig. 5.22

Hence using dle current division principle to get. <B·l64') Fig. S.24(a) : Thevenln's de equivaient

1: a :. 1J •, II I II I I II II S
 £!ectronlc Devices & Cltcults-1 (Eiex.·MU) 4-51
Step 2 : Find ~ :
In Pig. 5.25(b) , the resistance r0 has been assumed to be oo
Vm-VI_IB
and we have used the tU11 current source and not Sm V" .
Is = R 8 + ( 1 + ~ ) Ru I

. 2.29 - 0.7 • Step 1 : Obtain tbe expression ror R, and R1 :

= 12.95k + ( 151 X 1. k) =9.71J.A From Fig. 5.25(b),
.. lcQ = ~ .18 =150 X 9.71J.A =1.46 ntA ~ = Vtflt, ...(1)
Step 3: Find rK, &nand r 0 : But vb = ~r.+J.,Re=lt,t,c+(1+f.\)lt.Re
.. Vb = Ib(r.+(l +f.\) Re] ...(2)
v ~ .
Assuming, VT 26 mV r = It
= _.!__ _ 26 x 150
lcQ - 1.46 =2.67 Jc.q
Substituting Equation (2) into Equation ( 1) to get,
lt,[r,+(l+f.\)Rg]
=3 1.46 .. R1 =- It,
8m VT =26 X w-3 =56.15 mAN. .. Rl = rlt+(l +~) R£ ...(3)
v ,
ro = f:!:.=oo s·mce VA is .not specified. · And R.I · = Rs II R; =CRt II~ II [ Gt + {1 + ~) Re 1
"CQ ...
...(4)
Part II : Small signal analysis Step 2 :Th.e expression of voltage gain Avs :
St,ep 1 : Draw the smaU signal model : ~
Avs = Vs
+o----.--~
8 c Referring to·the partial output circuit shown in Fig. 5.26.
r---o----+
8 -·"+
"'
+
lllb

r-
Vs Re b

. ~
-l R'
0
Ac f\. Vo
r r
A;'
A; Ae ·
(B-2650) Fig~ 5.24(b) : SmaU ·signal model (without load)
(a) Circuit to obtain V0 (b)
Step 2 : R., R 0, Av witboot load :
- <F-1478) Fig. 5.26
R; =. · r" = 2.67 k.Q
R~ I
= R8 II R; =2.67 k II 12.95k =2.21 k.Q •••Ans. V0 • = Voltage developed acroSs (Rc II RJ
Vo -gm V,.Rc .. V0 = - ~~<RciiRJ . ...(5)
.Av = v.= V I It
-gm~ Referring the input circuit shown in Fig. 5.26(b).
= - 56.15x3.3= - 185.3 ...Ans. Vb = ~R; or ~=Vb/R; ·
. Substituting this into Equation (5) to get,
R0 = oo
, = - f.\Vb<Rc.ll&2
R0 = Rc=3.3W ••.Ans. Vo R; ...(6)

Q. 21 For CE. amplifier with unbypa$sed Re, derive the R.

expressions for Av, A, , Z, and Zc,. But , xVs
R.+Rg
···~~ijiitl:l•l§Wmlf~~l!'IMI•IMfMd 1

Ana.:
The CE amplifier with unbypassed Re is shown in
Fig. 5.25(a) and the bybrid-1t ~u~valent ~ircuit is · shown in
Fig. 5.25(b). The bypass capacitor~ ts not bemg used. .~ =
.. Vs Avs

:. Avs ...(7)

This is the exact expression for Avs·

,
But if Rj » Rs and (1 + ~) » r" then Avs is
approximated to,

Avs "" (l+ f.\ ) Re

.(b) Hybrid-1t equivalent
(a) CE.ampUfter with
circuit If ~ =. (1 +f.\) then,
unbypassed ~
(F-1477) Fig. 5.25

easv-s oluii OIIS

 4-52
~
Sectronlc Devloes & Clrcuits·l (Eiex.·MU)

Avs• - CRcRt;II RJJ ...

(8)

This is the required expression for the approximate voltage gain.

St!!p 3 : Output resistaate :
The output resistance is ·obtained by letting V s 0 in =
Fig. 5.27. Assuming that a source v. is connected between the
output terminals ~ the current supplied by this source is 1.:· .
'• ..
r,.
...(2)

. '

flo'
<F-1479) Fig. S:J:T : Orcwt ·to obtain output resistance

. =
As Vs 0, It, will reduce to zero. Hence j}Ib = 0 so the
depeodeot current source is replaced by .an open circuit, as shown ...(3)
in Fig. 5.27.
. ...( 9)

Q. 22 Draw circuit diagram. ~~ an emitter follower. Derive

expressions f.o r current gain A.. Input resistance
Where R.
I
= R8 II [rn + (1 + j3) REI
.

At, output resistance ~. voltage gain A~. Stat8 Its Substituting,..the expression for Vb to get,
Important applications. Dec. 03.Ma 06. Ma 12 R'
Ans.: V0 x [rn .f.. ( 1 ~ ~) (r0 II RE)] =(1 + 13) (ro II RE) X (R~ + Rs ) V s -
I
. . I
The CC . amPlifier (emitter follower) is shown iD. ,.
Fig. 5.28(a) and the hybrid-1t equivalent circuit is, shown .in Ya_ 0 . + 13) (rc. II RE ) R.
Fig. 5.28(b). : .. Avs = = x '
Vs r,.+(1+j3)(r0 11~) (R.I +Rs) ...(4) .
Step 1 : Redraw tbe bybrid-n circuit : .
The hybrid~1t circuit of Fig. 5.28(b) can ~ redrawn in a · ~s iS the exact
.
expression
. .. for voltage gain.
simplified manner as shown inFig. 5.29. · Approximate expre&slon :
. If rlt <<. (1 + 13 ) (r0 II RE) and R~ >> Rs then
I

. - (l+.j3)(roll~)
c . ;'-;_.,JAvs - . (1 + j3) (ro II RE) = l
+
v, < ·. The positive sign is associated with the expressions for
v Cz - gam. It shows that the phase shift between input and output is 0°. ·
~0 ..

Step 3 : Input resistance :

Re
In Fig. '5.30 • applying ~VL to fue input loop ,
. Vb = lbr~t+le~ ..
But .le - (1 + j3) Ib
(a) Emitter follower ampUfter (b) Hybrid-n equivalent circuit
· • Vb = ~ rlt + (1 + j3) It, R6
{F-1480) Fig. 5.28
:: ~[r~t+(l+j3)RE)
8 r,. E -
.
..
~ .
R, = ~ =rlt+(l +j3)'Rs ...(5)
lifi Thi~this the
+
·
amp er w& unbypassed. Rs·
required
expression. It is·same as that for the CE
.

R; = Rail ~=Rail [ rlt + (1 + j3) R6 ] •••(6)

c ,
(F-1481) Fig. 5.29 : SlmpWled bybrtd..n equivalent drcult

1: :1 ~;11 S IJIIIIIIIII ~•
 Electronic Devices & Circuits-! (Eiex.-MU) 4-53

-- ~
········• B
• • le
Ru
= (1 + p) • RB + RI X~
A = 1.. _(l + P> Ru
t . .. I Ii - Ra +R;
R8 b If R; >> R8 then the expression f01: A1 gets' approximated to,
A1 ~ (l + P> ...(9)
AI' a. 23 Calculate the small signal voltage gain for the
emitter follower circuit shown In Fig. 5.33(a).
Assume that P ; 100, VBE (on) 0.7 V and =
VA=100V.
<F-1482) Fig. 5.30 : Circuit for obtaining ~ and a; Vcc = 6V

Step 4 : Output resistance :

Setting Ys = 0 to ob¥xt the values of R, and R' .. The

0
equivalent circuit to obtain the outpt~t resistance · · h •
F~g. 5.31. ts s own m
· · Ro = <Rs II Rs) + r"
and R: = (1~ j3) II (ro II Rt,) ·- ._..(7)
__&__ . . . .
wbere (l + j3) represents th~ reflected resistance froin base- to.
emitter.

(F-1504) Fig. S.33(a)

Ans.:
Part I : DC analysis
. Step 1 : Draw Thevenin's equivalent circuit :
The Thevenin's equivalent circuit is as shown in
Fig.5.33(b), ·•·
· Current 80UI'OO . R~ = R[ II~ =40kl(40k'=20k
act8;8$.oj)fin cil;cuit.
. &
CF-1483) Fig. 5.31: Equivalent circuit to calc~te R., and R: ~rn = ..Rt +Rz
. -40k
~ Vcc .
.
' ~ CRsiiRa)+r~t
:. Ro - . (1 + j3) . II (ro IJ REJ ...(8) = 40k+40k x6V=3V •
+6V
The first term in the above expression represents a very low
resistance. It will further decrease· due to the paralleling effect.
Hence the output resistance of an emitter follower is very low. ·
Step S : Small signal current gain : ·
The small signal current gain is defined as
A1 =
I/11 where . Ie OUtput current =
Referring Fig. 5.32 t:O·calculate Ar

(F-1505) Fig. S.33(b) : 'Theveoin's equivalent ckcuit

Step 2 : Calculate 18 and 1c :

Vrn- VaE 3-0.7
= Ia Rs + (1 + j3) ~ ·:- 20 k + (101 X 2 k) =1?·36 J.lA
At
And ~ = (3 Ia = 100 X 10.36 X 10- 6 ,.; 1.036 mA
<F-1485) Fig. 5.32: Equivalent clrcult for obtaining A,

But Ie = ( 1 + j3 ) It, ... (neglecting r0 )

and. It,= RR!R x~ where Ri = r11+P +13)Rs

B I

r.a s v · s nlutt uus

I 8ectronlc Devices & Clrcults-1 (Eiex.-MU)

Part II : AC analyat8
Avs =
(1 + P) <ro II Ra ) x 0.9732
R,
4-54
4co;

Step 1 : Cakulate r.lllld r. : 101 X (95.525 k 11 2 k} X 0.9732

~ l00x26mV = 2{)().366k
r,. = ~ = 1.036 mA = 2.509 W 101X 1.959k x 0.9732 : . Avs 0.961= ...Ans,
= 200.366k
= .!A. 100
r., ~ .. 1.036 x w-:1 =95.525 w Ste 8 . O~tput resiStance : .
Step l : Draw AC equivalent circuit :
P ' . v
Settmg s ·
=
0 for calculating the output resistance. The
· · h
. . 't to calculate the output resistance 1s s own in
The ac equivalent circuit is shown in Fig. 5.33(c). eqwvalent cJfCW · .
Fig. 5.33(e). · ·
.---+e-.--.. v. E

· v ..
• v, +

(F-1506) Fil.5.33(c): AC equivalent circuit '\'

step 3 : Draw tbe bybrid-K equivalent circuit : <F·~) Fig. s.33(e): Equivalent circuit to obtain the outp~t
The bybrid-n equivalent circuit is obtained by replacing the resistance
transistor by its bybrid-n model as shown in Fig. 5.33(d).
As 8 It, · rx E fe ·
~~y-~-
···~
····~~+~~~~~--~~~ ..·~~~+
---~ [(Rs II Ru ) + r" J II (r II R )
(1 :1" J3) o - E

~ The (1 ~~)term is used for reflecting the resistance from-

base to emitter.
. . R: = [(0.51!2~dl+ 2.509] II (95.525 II 2)
~· At
<F·15Cr7) Fig. S.33(d): Hybrid-n equivalent circuit = 2·~~ k 111.959 k
= 0.02922 k.Q or 29.22 Q ••.Ans.
Step 4 : Calculitte R. and a' :
I.
Q. 24 For a common . base · amplifier with potential
~ = ~~~ . divider biasing, derive expression for :
Applying KVL to the outer loop ofFig.5.33(d) to get,
1. Voltage gah'l : Av
vb = ~ r,. + (1 +a>~ <ro II~-> ..
2. Current gain At
.• Vb = ~[r.+(l+fl)(ro11Ra)1
3.. Input .resistance R1
.. ~ = ~ [r" + (1 +~ )(r0 II Rg )] 4. Output resistance Ro Dec. 05. May 08
Ans.:
= rn + (1 +.f3) (r0 I~RE.)
.. ~ = 2.509 k + 101 (95.525 .k lf2 k) The circuit diagram of a CB amplifier is as shown in Fig. 5.34.
~ G, . . ~
= 200.366k.Q
'i!l!t-----...-~1------0V
I
:fo 9
and R.I = ~· II ~ >II ~ =20 k II 200.366 k ~-·

= 18.18 k.Q
Step S : Calculate output voltage :
V., = (I} It,+ Jb) X (r0 II iy =(1 + f3) ~ (r II Rll)
0
...(1)
Step ' : Calculate vb :
Applying KVL to the Oute[ loop of Fig. 5.33(d) to get,
vb =
Jt,r.+(l +P>Ji,.CroiiRs> <F·l486)'Fig. 5~: C~on base amplifter
=
.. vb It, [r.+(l + p)(ro II Rs )] =Jt,RI . ...(2)
Step 1 : Draw the ac equivalent clttuit : "'
..Ya. (1 + P) I,. (r0 II Rg ) _ (1 + p) (r0 II Re ) . As .
, :. Vb = It, X R, - R, ... (3)

Step 1 : Calculate voltage p1n :

..Ya...Ya.~
Avs • · V =
s Vb x Vs
...(4)
,
~
= Rs +a; =O.S + 18.18 =0.9732
R, 18.18 (5
But Vs ... )

Subltituting Equations (3) and (5) into Equation (4) to get, (F-to481} Fig. 5.35 : AC equivalent circuit
t; : 1 ~. 1J '• II Ill I I IJ II S
-~lc Oevicee & Clreutta-~ (EtelC.·MU)

s -p l : Draw the hybrid« equivalent drwlt :

Tbe bybrid-tt eq~ivaJ~t cin:uit of CB Ainpliftet is shown in
But &m r,.
[-•- i!.!.ID. +
v ~to+r
= IJ
tJ - - :is_
-R
4-55

Ag. S.36(•): Here the stmphfiod hybrid-It model of the transistor .'S " s
(withoUt t 0 ) IS used. ·
-V
.. .v" = ...(3)

Assuming i = ~ +(
1
~ ~ + ~E
~ceR=Rslt (l :fj)ll~.
•
:. ·v" = -~s xR=- R! [Rs ll(l~f3)11Re]
(a) Slftr..... bybrkl« drcolt (b) Stnall signal equivalent Substituting Equation (4) into Equation (1) to get.
ol • traDslstor drcui_t for CB conftguration
_ Vo =
. v [
-<RciiRtJgmx-~ Rsll---r;-IIRE
(1 + IJ) J
' <F-1481) Flg. 5.36
v =. Avs =+ gm <RcR~
:. V; II R, ) [ (1 + 13>
Rs II r. II Re
J (5)
···
This is the required expression for the voltage gain.
Approximate expression ror.Avs :
Assuming that Rs = 0, the ~el combination of Rs. (1 + f3}1r.
and RE approaches to Rs.· .
· · Rs II (1 ~ (3) II _
RE = Rs
· gm<Rcii&Jxo
. . Avs = Rs . ~'S
:.Vo = -(RciiRdgmVn :.•.(1) . · : . Avs = gm <Rc II Rt) ...( 6)
In Fig. 5.37 , applying KCL at node E to write, Step 4 : Exi»ression for smaU signal current gain :
~+'-e =~ Sinau signal current gain A18 = I., I I;
Applying KCL at the emitter node of Fig. 5.38,
As E I.
•·····
........
G
+

'
<F-1489) Fig. 5.37 (a) (b)
(F-1490) Fig. 5.38.

~+Jb+gm V"-IRB = 0
But ~ =
~ ~
:. ~ +. r. + &m v. + Rs = 0
Ie =
:. v"[:" +gm+ ~ = -~

= tl
But 8m r"

... v. = [~ • ...LJ -\[a..u <t:'pi] ...oJ

~ R .
.•.(2) Referring Fig. 5.38 (b) and writing the expression for
cum:nt (0 using the principle of cunent division. Current (g. V• )
get& divided betw~ Rc and R.. at node A.

I • . • • li I II I I · ' II '•
 Electronic Devices & Clrcuits-1 (Eiex.-MU)
-&: Q.25
:. l, = Rc + RL X gm Vrr. •••(8)

Substituting Equation (7) for Vtt into Equation (8) to get,

I, = -&.,&; [ r
Rc+RL X -~ REII~
J
•• A .
. .'IS
= ~ -
~ -
&m Rc
(Rc+RL) [u
"'E 11--.!L.._]
(l+f\) ...
(9)

This is the required expression for the small signal current

gain. ·
Expression for input resistance :
Assuming ~ = Resistance seen betwee~ emitter
and ground and
I
R1 - Resistance seen by the voltage SOUJ:Ce (F-J..S al) Fig~ 5.41
Referring Fig. 5.39 to obtain the values of~ and R' .
. . I Ans.:
~ = Resistance between emitter and ground Given : VEE=-4V, p =150, ~ =3.3 k,
= r,. reflected from base side to emitter .Rc=7.lk, . Va; =lOV.
D
: . ~'i
= ___!a__
(1+ ~) =re
. ...(10) . Type of amplifier : C. B. .
Model used for analysis :.hybrid 1t
Part I : DC aDalysis
E
Step 1· : · DC equivalent circuit :
The DC equivalent circuit is .as shown in Fig. 5.42,.
Applying KVL to base loop to get,
v~ = V~;~E +IE Rs•
V £ili- VsE 4-0.7
+ :. IE = RE = . 3.3k =1 mA
IE 1 X 10:- 3
Is - 1 + 13 = 151 . 6.62 ~
I
(F-1491) Fig. 5.39 : Circnit to obtain Rt and R 1
~ ,; Pis = 150 x 6:62~
The resistance looking iDto the emitter with grounded base
is usually defined a8 rc which is e](tremely sinall due to the = 0.993 mA ...(1)
presence of ( 1-t: (:\) term in the denominator. ·
Thus R; of a CB amplifier is very small. .
, · ~

Ri = RsiiR;= Rsll (l+P) ...(11)

Due to paralleling the input resistance is reduced further.
Exp~on for output resistance :
For obtaining the expression of output resistance, we have
. to set Vs= o·and-assume that a source Vx is connected between the
output terminals.as shown in Fig. 5.40. · (F-lS49) ·Fig. 5.42 : DC equivalent circuit

• . Step 2 : Calculate riP r 0 and &n :

_ . VTP 26mV x 150

r" - icQ = 0.993 mA =3.92 k
...Assllilling VT =26 mV
icQ 0 .993 mA I
Ro g
m
=V-,
- 26 x l0-3 =38.19mAN
(F-1492) Fig. 5.40 : Equivalent circuit to calculate R., VA
' . ' · ro = icQ = oo Since VA is not specified.
. •• •
= =
As V5 .o, V" 0, hence &mV11 = 0. So the depen~ot
current source in Fig. 5.40 can be replaced by an open circuit.
;, R0 Rc = ...(12)
...(13).
And R'
0
= Roii~=<RciiRJ
t; a ~. II S II IIIII 1111 S
 Electronic Devices & ClrC:uits-1 (Eiex.-MU)
=-
Pa_rt n : AC analysis 0.27 State and explain the Miller's theorem.
Step 1 : Draw the hybrid n equivalent circuit : Ana.:
Fig. 5.43 shows the hybrid 1t equivalent circuit. · Considering an arbitrary circuit configuration with N
distinct nodes I, 2, 3 ..... N as shown in Fig. 5.44(a).
Assuming the node voltages are v •• v2. v3 .... VN where VN = 0
which means N is being treated as a reference node or ground
n~ .

7-
-,-~
z
(F-1550) Fig. 5:43·: SmaU signal equivalent circuit

Step 2 : Calculate the parameters :

· Vo -gmVx Rc • (a) A circuit conftgoradon with (b) A network having
1. Voltagegam Av=-v _ =g 'D
· . i -~ m~ N different nodes identical node vo~ges. Note
:. Av =
38.19 X 7.1 =270.936 ••.Ans. that 11 =- 12
2. Input resistance
r,. 3.92k {F-458) Fig. 5.44
R; = O+~) =T+15Q =25.96 n ••.Ans.
Assuming the impedance Z is connected between nodes N 1
R; = R; II RE = 25.96113300 ~ 25.76 n ••.Ans.
and N 2 and the ratio of voltages V.j V1 is denoted by K, wh:e.re K
3. Current gain is a complex number. The circuit configurations drawn in
Figs. 5.44(a) and {b) give identical resuJts in Other words they are
~ = .&m [ REII I : p] equivalent networks.as shown below :
Stepl:
3
= 38.19 X 10- X R~ =38.19 X 10- 3 X 25.76 . Disconnecting terminal-! from Z and connect an
I ,
impedance Z1 = Z I (1 - K) between terminal 1 and ground as
~ = 0.9836 ...Ans.
shown in Fig. 5.44(b). . The expressions for ''I... for both the
4. · Output resistance
arrangements in Figs. 5.44(a) and (b) are obtained as below:
~ = 00 ·From Fig. 5.44(a), ·
R'0 = Rc =7.1 k.Q •••Ans. V 1 -V2
•
I, = z ....(1)
Q.26 Compare common base, common collector and v
common emitter BJT amplifiers. But as K = VI
,substituting V = KV in Equation (1)
2
. 1
Dec. 02. Dec. 07. May 08. May 12, May 16 V 1 -KV 1 _ Vdl - K)
Ans.:
.. II = z - - z
v
Sr. .. I, = Z I (1 - K) ....(2)
NO. Con~idering Fig. 5.44(b) to wiite,'
I. Input tenninal Base Emitter Base .!J.. v
2. Output tenninal Collector Collector Emitter · .. I, = Z1 = Z I (1 - K) · ...(3)

3. Common terminal Emitter Base Collector Comparing Equations (2) and (3), they give the same value ofl •
1
4. Input resistance (R;) Medium Low High Step2:
5. Output resistance Medium High Low Disconnecting terminal 2 from the· impedance "Z" and
(RJ 4 ' pedance ~ = (i(:"i)
connect an tm ZK between terminals 2 and
6. Current Gain (A1) High Less than High ground·as shown in Fig. 5.44(b).
1
. The expressions for "~" from the two configurations shown
7. Voltage Gain (Av) High ' High Less than m Figs. 5.44(a) and (b) are obtained as belbw :
1 Considering Fig. 5.44(a)
Low Buffer _ _ V2 - V 1
Applications AF
noise pre- amplifiers .. ~ - - 1•- Z ....(4)
voltage v . .
amplifiers · amplifiers But K =~hence substitute V1 = V2 1 Kin Equation (4) to get,

- "'''*i'•m•''''"
---------
lis
 ~~~~~~~~~~~~----------~~--~---~~::==~~~~:;::~~~~:~~
~ OevloM & Clreultl-1(Etex.·MU)
V1 - <Va I R)
a~ .gi~e same Val-: . .. Comparing Equations (5) (6) ' they the
us the identical nodal equatJons are obtamed from two the
l2 • z of Lz· Th .
8
of Figs. 5.44(a) and (b) therefore we conclude that
V2 ( 1 - 1 /K) v: (JK _ 1) configuration ,~ are equivalent. This theorem is useful to m.,~..
12 -- z - • "-Zk - these· two
. networ....
·r d only if it · poss1'ble to find
· 1s 1 the value of -K by
- calculations 1 80 s The transformation of network sh...·- ·
v · d pendent mean · uuwu tn
11 • ZK /(K - 1) . .. (5) ~roe 10 e to Pi 5.44(b) is known as Miller's theorem. Tbe
F1g. 5.44(thea) •~·used for the ana]ysis of circtrits such as CE
Prom fttl. 5.<4-4(b), Miller's orem 1 .
ampHfier with collector to base bias.
~ v

-
. • 12 • l.a • ZK I (K - 1) .. . (6)

Chapter 6 : Field Effect Devices ·

in Fig. 6.2(a). On both sides of ~-type bar,. bea~ly doped ( p )
0. 1 Juetlfy : FET la a voltage controlled device. · h been 1&ormed by alloymg or by diffusion to create a I>-
reg.~ons ave ' · ected ·
Ana. : The voltage applied between gate and source (V05) controls · ction Both these p regions are conn · together and VIa an
lbe drain current 10 • ~fore FET is a voltage controlled device. ~~=c co~tact the gate terminal is brought out. ~ supply voltage
'The drain cu:n-ent (lo) is known as the controlled parameter while is connected between the drain and source termmals of a JFET
gate to source voltage (V05) is called as the controlling parameter. hence current is cau.sed to flo~ ~ong ~ len~ of.the ~-type bar.
This current is due to the maJonty earners which m this case are
Q. 2 Justify : FET la a unipolar device, electrons. Fig. 6.2(b) shows the symbol for then-~ JFET. The
Ana. : FET is a unipolar device, that means the current flowing arrow on gate terminal indicates the convenbonal cmrent
tbrou&h it is. only due to one type of charge particles, boles or directions.
elecuoo.s. 1be conduction taken place only due to electrons in the n
c:bmnet FETs and only due to holes in p channel PETs.
Q. 3
Ana.:
St8tll ttdvantagea of JFET over BJT .
~~~
1be PET enjoys several advantages over the conventional
bipolar junction transistor. Some of them are as follows :
n
. ~Source(S)
1. It is a unipolar (levice so its operation depends on the flow
of majority carriers onJy. Source (S)
2. It is relatively immune to radiation.
3. fET has a very high input resistance (typically few (a) Structure ofn-cbannel (b) Symbol of n-cbannel
megaobms). . JFET JFET
4. FET is less noisy as compared to BIT. It produces less
internal noise. (B-263) Fig. 6.2
QA What are disadvantage of JFET ? Channel :
Ana.: Disadvantage of JFET are as follows, Channel is the n-tyj» material between the two gate·
I. FET amplifiers have lower gain. . regions. The majority carriers (electrons here) move through this
2. It bas a relatively small gain-bandwidth product as channel from source to drain. Since the channel is made of n-type
COIDp8I'Cd with that of a conventional transistor. material, this FET is called as n-channel JFET. The electrons enter
3. It can not be used as a current amplifier. the channel through the "source" terminal and leave through the
4. Tbe value of transconductance &, is small. "drain" tenilinal. . ·

Q. 5 Gtve clualflcatlon of Field Effect Translators • Q. 7 Draw and expJaln construction of JFET. umLi
AM. : 1be f.eld effect transistors are classified as follows : Ana. : ·
Drain (D)

p-channel
er&in (D)
Gate (G)
Gatf
(G)
<J-%0) Jl'l&. 6.1 : CIMdllcation of FETs
Sourc8(S)
p
Q. t SUtch and explain the conatructlon of JFET.
(Jt·r. 11J f.l.t·; 1? lJ Pt. 13 [J1ily 1!J. De c 1!)
Souroe (S)
Nil.: (It) Structure of p-cbannel (b) Symbol of p-claaDDcl
Tbe wucwre of an o-duumel field effect transistor is aa JFET JFET
&bowo iJ1 Fis. 6.2(a). A .emiconductor bar of n-type material is
LakeD and ohmic oonliCI.II arc made to the ~wo ends of the bar, (8-2545) Flg. 6.3
'Jbete are tbc t.enninals named dtain (0) .and ~ (S) ua ahown

lii1***11•D111ll
 Electronic Devices & Circuits-! (Eiex.-MU)
---- The construction of. a p-cbannel JFET •
· fig. 6.3(a) and its symbol is as shown in Pi IS as shown in 3. Operation or n~bannel JFET ror lal'l• value or
difference between the p-cbannel and n-cban g. 6-3(b): The only negative VGil .: As the negative volt.ugc V011 ill fUrther
type semiconductor bar is being used with twnelJFETs ts that a p- increased, the depletion regions spread more Into tho n-typo
In p-cbannel JFET, current flows due to the ~ ~-type ~a~e regions. bar. At a certain value of negative V0 8, the depletion
bOles are majority carriers in a P- . 0 es. This ts because regions touch each other as shown In Pig. 6.4(c). AI' thl11
c;baDDel JFET current flows due to fl~osefIDllconductor bar. In n- point the channel width is zero and therefore the drnlo
- e ectrons.
current lo =0. This gate to source voltage ut which the
Q. 8 ~ketch and eXplain the working of JFET. Dl4Wii diain current is cut off is called as Vos toll')'
Ans.: · Thus with increase in the negative gate to source voltaac•
've.Tvolt_ageVis a~plied_between the drain and source
. alA pofsitiJFE the channel becomes more and more narrow and drain current 10
tetJJlln s o a • I.e. 05 1s positive and · · -reduces. For Vos = 0, maximum dmin current I0.9s will flow
. be th a negative voltage is
applied tween e gate and source tennina1s . V . . through JFET. The drain current then reduces with increase In the
· f JFET · I.e. GS IS negative
The operation o IS explained for different a1 · · negative gate to source bias. Thus JFET is a voltage controlled
' foIIows: v~~Vosas device. Cutoff Voltage V0 s <o« > : The vaJue of Vos that makes the
1. Operation of n-clumnel JFET with v _ 0 The drain current 10 approximately equul to zero is called ll8 cutoff
GS- : effect
of gate JFET
to source voltage VGS on the operati'on of a n- voltage and it is denoted by Vos <om·
.
channe1 IS as follows ; In Fig. 6.4(a) in which gate is Q, 9 Define pinch off voltage for JFET.
connected to source making v GS -- 0• Due to the supp1y
Dec. 14. Ma lh
voltage V , current starts flowing through th h
The drain 05 e c anne1. Ans.:
, current is con~olled solely by the resistance of
the semtconductor matenal between drain and sourc Th The pinch off voltage VP is defined as the value of V03
'al h e. e
n-~ maten . as a finite resistance. Therefore the drain beyond which the drain current becomes constant. VP is defined
current flow. causes a voltage drop a1ong the channel. This a1ways for Vos =0.
~ol~e drop will reverse bias the gate to source· p-n
JUDCbOn. Q. 10 Sketch and explain the charactertatlca of JFET.
Dec.10.Mn 12.Mn 14. Mn l!i.Ucc.l!>
Ans.: Drain characteristics is a plot of drain current 10 (on Y-~is)
versus drain to source volt.uge V00 (on X-axis) at different values
of gate to source voltage V0~.

(a) Operation (b) Operation with (c) Operation with

with no bias a small negative a large negative
voltage gate source bias · gate source bias
~~~,~0--1~
5--~~--------------V~N*l
Fig. 6.4
(B-Ui7) . V,(lar Voa • CN)

The depletion region of the reverse biased ~n. jw;tction (B-172)Fig. 6.5 : Drain characteristics or an n-cbannel JFET
·· penetrates more into the n-type bar because 1t ts hghtly The characteristics has been divided into three regions viz.
doped as. compared to the ·heavily doped p-type gate. The cut off, saturation and ohmic region.
penetration of the depletion region into n-type bar depends 1. Cut off region : With increase in the negative Vos voltage,
on the magnitude of reverse bias voltage. Due to _the the channel width available for conduction decreases. At a
dePletion regions the width of ~e "~banner• available for certain voltage called "Vos (om" the depletion regions touch
conduction is reduced, as shown 1n F1g. 6.4(a). . each other to close the channel completely. Hence the cut
- Source saturation current IDSS : The value of dram off region corresponds to 10 =0 and Vos > Vas (off!· In the
. - . ' din to v _ ov is called as ·the source cut off region 10 =0 and there is no effect on its value even
current correspon g .GS -: · b I I
saturation current and tt JS denoted ~ nss· nss if we change the drain to source voltage (V00). The JFET
- ds
C91Tespon
.....vimum
to the ll-U&A-0 •
drain current because ~e• operates as an open circuited switch in this region.
channel is widest for VGS =OV· ti v 2. Saturation region : As shown in Fig. 6.S, saturation
2. Operation of a n-cbaDDel JF.ET for small nega ve csd·• region is that portion of the characteristics where 10
. lied between the gate an remains fairly constant and does not change with changes
A small negative voltage ~s app .4(b) Due to the reverse in Vns· This "saturation" is entirely different than the
6
source teroiinals as shown tn Fig. so~e junction, the . "saturation" in a transistor. In order to use the JFET as an
voltage applied across ~e ga~n into n-type · material amplifier it is operated in the saturation region.
. penetration of the deplett~n reredgt the channel width
. forth This wtll uce 3. Ohmic region : The: drain current 10 varies with variation
mcreases er. 'dth less number of
1 in the drain to source voltage Vos• in ~ ohmic region as
further. Due to reduced cha::n ;,m source. Therefore
electrons can pass through t6 . v shown in Fig. 6.5. The JFET is therefore said to be
drain current Io reduces with incre~ .m - os· operating as a. voltage variable resistance (VVR) in the
ohmic region. It is equivalent to a closed switch in this

P.:lS\1 - SO I II II O il S
 Electronic Devioee & Clrcuits-1(Eiex.-MU)
region. The resistance offered by the JFET decreases with
decrease in the value of negative gate to source bins
voltage i.e. negative V 011• The FET resistance in the ohmic
loee ···············
J0 (mA)

8
-
4-6()

region is given by.

Ros = Vp /loss
4
where. Vp == Pinch off voltage and

4.
loss =
Maximum drain current.
FET bl'\'akdown : When a JFET is operating in the
..... ..t. . . . . 2

saturation region. 10 does not change with change in V os . . ........i··········~···· ·······

upto a certain ·value of V 05. If V 05 is increased further Yos (vol18) -2 -1 0
beyond this value, the gate channel junction breakdown
due to avalanche effect and the drain current shoots up . . Transfer characteristics of a JFET
suddenly as shown in Fig. 6.5. This can damage the device. (B-275) F Jg. 6•6 •
The value of breakdown voltage does not remain constant. . Th the two extreme points on th~ characteristics. The
In fact it decreases with increase in negative values of V 05• ese are ,. . 'th red . .
ti haracteristic grows exponential1y WI uctlon m the
The operation in the breakdown region should be avoided trans .er cV The transfer characteristics defined by tbe Shockley's
in order to protect the JFET against damage. . negative as· 1c: • hi
· affected (remain same) by the networ m w ch the
5. Effect of negative VGS bias : With increase in the negative eqJFEuaTtl~n are un ted The transfer curve can be obtained using
ts connec . . .
V05 bias the channel width decreases and drain current ID Shockley's equation or from the drain charactenstlcs
~ces proportionally. A family of curves for different
values of V05 is as shown in Fig. 6.5. With increase in the Q.13 :Draw the structure of p-channel JFET.
negative V 05 bias, the breakdown will take place at lower Ans.:
values of V 05• ·
Drain (D)
6. Pinch off Voltage (Vp) : The "pinch off' voltagds the
p-channel
value of V os• at which the drain current reaches its constant
· saturation value. Any further increase in Vos does nOt have
any effect on the valu~ of 10 . Do not make a confusi~n
between the cut off and pinch off. The pinch off voltage is
denoted by V p·
Q. 12 Sketch and explain transfer characteristics of
JFET. Dec. 10. May 14. May 15
Ana. : Transfer characteristic is the plot of output current In Source (S)
versus the input controlling quantity which is Vas in this case. For (a) Structure. of p-channel (b) Symbol of p-channel
a BIT the transfer characteristic is a graph of 1C versps IB: ·
JFET JFET
For a bipolar transistor the relation between output current
Ic and input controlling quantity Ia is given by, (B-254~ Fig. 6.7
1C =
f}dc Ia ...(1)
Where , f}dc is considered to be a constant. Q.14 Draw drain characteristics of a JM:hannel JFET.
'Therefore the transfer characterjstic of a transistor is a Ans. : .Fig. . 6.8 shows the drain characteristics of a p-channel
straight lioe indicating a linear relation between 1C and lB. JFET. .
However the relation between 10 and V00 is not linear. The
relationship between In and V05 is defined by Shockley's equation .
which states that,
2

Vas]
lo = loss [ 1 - Vp ...(2)
where, loss =
Maximum drain current or source
.... ........
FET•clau
~

saturation current
VP =
Pinch off voltage
In the Equation (2), I~ and V" are considered to be the
CODStaD1 quantities. The relation between 10 and Vas is therefore a
squared relatiOD.Ship. which produces a curve whic~ is growing (B·l78) Fig. 6.8 : Drain characteristics or a p-cluumel
.
JFET
expooentially as shown in Fig. 6.6. As seen from Ftg. ~.6, when . . .
= = =-
v 0 volt. 10 = foss and when Vas Vp 4 the dram current
05
The shape of this characteristics is.same as that for tbe n-
channel JFET except for the reversal of polarities of V OS .and V os·
.
~=~ ~
Q.15 Draw transfer characteristics of a p-channel JfET.
Ana. : The transfer characteristics of a p-cbannel JFET is shown
in Fig. 6.9. It is mathematically expressed as foUows :

1: a •, V '• II Ill I I II II S
 Electronic Devlcoa & Circuita-l (Eiex.-MU) 4-61

Q, 19 Give reason : JFET can be uHd u a voltage

variable reeletor. ltl§Mtlj
Ane.:
8
The field effect transistor can be operated as a voltage
variable· resistor (VVR). Refer to the drain characteristics of a
JPET shown in Fig. 6.10. The region before 1'pinch off' is called as
ohmic region. In this region the JFET acts as a variable resistor.
The drain .to source resistance R08 in this region is dependent on-
tl1e gate to source voltage. As V08 becomes less negative, more
drain current flows and R05 decreases.
For higher negative gate voltage; 10 decreases and Ros will
I 2 3 Vas (voila) increase. Thus the JFET acts as a vo1tage variable resistor (VVR).

(8.1?9) Fig. 6.9 : Transfer characteristics of a p-channel JFET 10 (mA)

. Even though lo. has reversed its directi'on as compared to i -- Loous of pinch - off values
that tn n-channel devtce, we have not tak .
Th· · beca en 1o as a negative
~~ . 1 IS IS use lo and loss both have reversed their loss -··:..; ·' -;·······' :/ v08 = ov
directions. VGS and V P are going to be positive for the p-channel I
JFET. .. ~-------------- V08 : - 1V
Ohmic region
Q . 16 Define drain resistance for a JFET and state It's

Ana. :
typical values. I•J§MtJ ---+-
FET acts
as VVR
Voo= - zv
V08 = - 3V

Dynamic drain resistance is an AC resistance of a JFET is -::-1~---------- v08 (volts)

defined as ~ ratio of ~hange in the drain to source voltage to the
(B-1634) Fig. 6.10 : Ohmic region in which FEl' acts as VVR
corresponding change 10 the drain current, at a constant value of
gate to source voltage. It usually lies in the range of 50.kQ to few
Q. 20 Compare BJT and FET. Dec. 10. Dec. 15
hundred kQ. '
:The rnlmnlln~or'\11

.. rd =
1!1 Vos I
1!1Io constant Vas
~"'-~

Q. 17 Define transconductance for a JFET.

Ana.:
The transconductance gm is defineq as the ratio of change in
drain current to the corresponding change in gate to source voltage,
at a constant value of drain to source voltage. It is calculated at a
particular operating point. (No
.1. Io
·g.,- - -
.. - .1. V GS constant V vs
0.18 Define amplification factor and give relation
between gm , J1 and rd.
Ana. : Amplification factor "J.L" is defined as the ratio of change
in the drain to source voltage, to change in the gate to s?urce
voltage, at a constant value of 10 . It is calculated at a particular NPN

operating point.
.1. Vos ...(1) (B-283) (B-l84)
j.L = -
.1. Vas 10 constant
Q . 21 What are the applications of JFET ?
Relation between the parameter• : ...
Equation 0 ) can be rearranged as follows : Ane.: The applications of JFET are,
1. JFET can be used as an amplifier.
avi>S ~ 2. JFET can be used as a switch.
·· IJ. = A 10 x A Vas
...{2) 3.. It can be used as analog switc~ in cin:uits like sample and
.. J.L= rd x 8m d .
Thus amplification f..ctor J.tl~ equal to the product of raJn
hold, amplitude modulation, ADCJDAC (analog to digital
or digital to analog) converters.
resilltance rd and transconduc!JUlCC Bm· 4. As a voltage variable resistor (VVR).
A&"J.L" is the ra tio of two voltases hence it is unitJess. 5. . In di ital ci.rouits.

ea ~ v s nlul tfl ll li
 Electronic Devices & Qirculta-1(Eiex.·MU)
Q: 22 An A-Channel JFET hu to.. • a mA and Vp • - 4
--
4-62

Votta.
1. If 10 • 3 mA calculate the value of V08•
2. Calculate Y08 (-') for lo • 3 mA.
Ana. !
Gl"'ftl : loss = 8 rnA, Vr = - 4 Volts und J0 =3 rnA. ss
(~a&e}
I. To <ablate Vcs:
2

As. lo "' lnss [ 1 - Vr:J

·· Vas = vr[t -·~J[iJ Source

(B-1635) • .• Construction ofn~bannel depletion type

Fig. 611
.. VGS = - 4(l -..JY8] = - 1.55 Volts ...Ans. MOSFET
l. To calculate Vos <•> :
VOS (Mil = Vas - Vp= - l.55+4=2.45Volts .•.Ans. Effect of the Insulating Si02 layer :
Due to the presence of the Si02 layer between ~ate ~al
Q. 23 For a n-channel JFET with loss =8 mA, Yp =- 4 V _ · hannel the input impedance ofMOSFET ts very high.
=
tf 10 3 mA calculate the value of Vas
1. and n type c • high ·
This is a desirable feature of a MOSFET. ~e to .. mput
Calculate V06 (SAl) for 10 =3 mA
2. impedance, the gate current IG = 0 for the de operatmg conditions.
3.
Calculate transconductance (g.,)
Q.26 Explain working principle of D-MOSFET. ·
May 16. Dec. 16
Dec. 09. May 10. May 14. Dec. 15
Ana. : Transconductance ,
Ans. : Working principle of D-MOSFET
VGs]
8m = gmO [ 1 ~ Vp ...(1) Operation with VGS =OV :
- 2 loss - 2 x 8 x 10-3 Fig. 6.12 shows that the gate, sourc~ and substrate
Where, &no = terminals are connected together tO the ground _potDl Thus V GS =0
Vp - 4
3 ·volt. A J)ositive voltage V 00 is applied between drain and source.
= 4x10- =4mAN Due to the positive voltage applied to the drain terminal,
Substitute this value into Equation (1) to get;
free electrons from the charinel are attracted to the drain and the
Transconductance, gm = 4 x 10-
3
[ 1- (-l1~)J drain current starts flowing as· shown in Fig. 6.12. The drain
current at VGs ·= 0 V is called as loss· This- is the maximum
= 2.45 mA ..•Ans. possible value of 10~
Q. 24 What are the types of MOSFET ? ·
AM.:
•••••
MOSFET is the short form of Metal Oxide Semiconductor
Field Effect Transistor. MOSFETs are different from the JFETs in
construction and they are of f.o~owing types : .
1. Depletion type MOSFET
2. ~ment type MOSFET
3. Power MOSFET
Q. 25 Explafn .vucture of MOSFET.
Dcc.08.Dec. 10.Ma 14.Dec. 14

AM. :
Construction (structure) of the depletion tyj>e.MOSFET is
as mown in Fig. 6.11. A ~type of semiconductor material (Silicon)
is u6ed as a substrate. Usually the substrate is internally connected
to tbe source terminal. But sometimes it is taken out as a separate
tcnniDaf termed "SS". The drain and so~rce terminals are
~ to the o-type regions through the metallic contacts as
shown in Fig. 6. J J. These n-type regions are linked wit~ ea~h
other by a n-cbannel as shown in Fig. 6.11. The gate termmal 1s
insulated from then-channel by a thin Silicon di-oxide layer (Si02) • .
(B-1636) Fig. 6.12 : n-cbannel depletion tjpe MOSFET
With
.
VGS =0 and applied voltage V DD
Operation of depletion MOSFET with negative VGS :
In Fig. 6.13, due to negative voltage applied between gate
and cathode terminals, the gate will tend to repel the free electrOns
towards the p-type substrate and attract the holes from the
substrate. These electrons and holes will recombine inside the
channel as shown in Fig. 6.13. This will n!duce the number of free
electrons available for conduction. Therefore the drain current will
~ecrease with increase in negative value of V 05• Thus as - VGS
mcreases, 10 decreases for a constant value of V os·

f: :t ~. V !, U Ill I I II II s
 ~ronic Devices & Circults-1 (Eiex.-MU)
....
Q. 27 Draw the drain characterlatlce of D-MOSFET. ·
Dec 03. Dec. 08. Dec. 09 May 10
Ana.:
Fig. 6.15 shows the drain characteristics of a n-cbannel
depletion MOSFET.
Io<mA>

...,..._...;.._______ v- =ov
08

(B-1C7) Fig. 6.13: Effect of negative gate to Depletion

source voltage on drain current mode

'!'be number of ~omb~ation taking place inside the 0 type

cbaDDCI depends on the ~gnitude of negative bias Vos· As we
~ tbe value of negative V GS• the number of reconibi.Dation ·
will increase. This will reduce the number of free electrons in the <F·IfilO) Fig. 6.15 : Drain cb~racteristies of an ~-channel
n<baJmel available for conduction. · .
depletion type MOSFET
Tbe higher the negative bias, the more the recombination
and the less is the drain current. This is as shown in the tr.msfer Q . 28 Draw symbols of n and p..type depletion
characteristics of Fig. 6.14. This mode of operation with negative
v6S is called as depletion mode. MOSFETs:
Elfect of positive gate to source voltage : Ans.:
If tbe gate voltage is made positive with respect to source
tbeo the positive Vas will ·attract additional· electrons
(free electrons) from the p-type substrate .due to reverse leakage
CUJieDl Gate
J0 (mA) (G)

-·
. -r-..
·--~--. . Enhencernent mode (a) Symbol oro-channel
depletion type M()SFET
· (I)) Symbol ofp-channel
depletion type MOSFET

·················-~·-·········t·········· ·~
Fig. 6.16
·····g· ·········r········ '~
Vas(Volla)---:=::::::::::~--l.--l:t->:--;t--'1--
Gate Gate
Vp (G) (G)
2

(B-1638) Fig. 6.14 : Transfer characteristics of an n-cbannel

depletion MOSFET
, 'UJmotch out more electrons (a) n-cbannel (b) p-clwmel
These accelerated electrons WI th drain current will
due to cOllision in the n type channel. Tbusv e This rise in drain (B-1fi42) Fig. 6.17: Simplifted circuit symbols for depletion
· 'ti VO1tage GS' MOSFETs
lllcrease as we increase the pos• v,e fore be aware of the·
~t will be very rapi~. We must ~~~~t exceed Io above that.
!llaUmum drain current rating and sbou .. nbanced" due to the Q.29 State appliCations of DMOSFET •
1'00s the level of free electrons bas bee~e~fore the region of Ana.:
application of positive gate volta~~· ate voltage is called as DMOSFET can be used as an amplifier. It can be used as a .
OJleratioo corre""""Aing to the positiVe g .on between cutoff
..eahancement" ...I:"'.....
region of opera
u·on and the regJ
.
h
· 0 This is as s own 1
.n switch.
and saturation iS referred to as deplebon regJthaO.t I has a non-linear a. 30 Explain construction of enhancement mode
. tics show o . MOSFET.
Fig. 6.14. The transfer cbaraetenssed thematically llS.
relation with vas· It can be expres ma · Dec. 08. IVlay 09. Dec. 10. ~ 1\.tln rks. 1\lny 11 .
2
...(1) 1\lay 12. Dec. 14
I : : I [ 1 -~] .
~
(j;-
D~~;~~~~V;:p~~~:S~h~OC~~~e:y·~s~~~u~a~h~OD~·
1:
Tbis equation is )mown tbe
:t ~. II ~. 11 I II I I 0 II ~
------j_-----------------------------------------
88
 Electronic Devices & Circuits-! (Eiex.-MU

Ans.:
The basic construction of an n-channel enhancement type ~::2.---v-----~- Electrons ~JIIracted
by positive gate
MOSFET is as shown in Fig. 6. J 8. A slab of p-type semiconductor (Induced n-ohannet)
(silicon) is used as substmte. The substrate is sometimes connected
L------It--Region depleted of
to the source or it is brought out as the fourth terminal. The drain p·type earners (holes)
and source terminals are connected to the o-type doped regions
through the metallic contacts. The "channel" is absent here. The
insulating Si02 layer is present (similar to depletion MOSFET)
which isolates gate terminal from the substrate: Thus the
construction is very similar to that of the depletion type MOSFET, t - - - l - - t - - Holes repelled by
but the channel is not present. positive gate
(0)
m::o:r-----..,__,-·n-l)rpe doped region

(B·l644)·Fig. 6.19: Formation ofindnced

channel in n-cbannel enhancement MOSFET
Gate(G)
3. Effect of increase in the drain to source voltage :
In Fig. 6.20, .the positive gate to source ~oltage. V?Sis kept
constant and the drain to source voltage Vas ts mcreased
n-type dope.dregion gradually. Due to this, the gate te~al becomes less and
~ (S) Jess positive with respect to the draJD. So less number of
electrons are attracted towards gate terminal and the
(B-1643) Fig. 6.18 : Construction of n-chaooel enhancement "induced channel" becomes narrow as shown in Fig. 6.20.
MOSFET Eventually, the channel width will be reduced to a point of
pinch off i.e. it remains constant and the .saturation region
Q. 31 Write short . note · W()rking of n-channel will be region, which is same as that in a JFET, or
enhancement type MOSFET. depletion type MOSFET. That means any further increase
,Die.. OB, ·May·n, May·12 in V08 at the fixed value of Vas ·will not affect the value of
In unless breakdown takes place.
Ans.:
The operation can be explained with two different
operating conditions : ~1----4-Pinch off (begiMing)

1. Operation with Vcs = 0 volt : If VGs = 0 and a positive ·'+---+------+- Depletion region
voltage is applied between its drain and source (positive
Vns), then due to the absence of the n-type channel, a zero
drain current will result. This is exactly opposite to what
· happens in the depletion-type MOSFET, where II? = Inss at
Vas=O. .
2. Operation when Vcs is positive : In Fig. 6.19, both VGS
and Vos are positive. The positive potential at the gate
terminal will repel the holes present in the p-type substrate
as shown in Fig. 6.19 This results in creation of a depletion
region near the Si02 insulating layer. But the minority
carriers i.e. the electrons in the p-type substrate will be (B~t645). Fig. 6.20: Effect of change in vDS a t
attracted towards the positive gate terminal and gather near fixed V cs on the channel width
the .swface of Si02 as shown in Fig. 6.19.' As we increase
the positive Vas• the nutpber of electrons gathering near the Q. 32 Explain characteristics of ·enhancement mode
Si02 layer will increase. The electron concentration near MOSFET.
Si02 layer increases to such an extent that it creates an
induced n-channe1 which connects the n-type doped Dec: 03. Dec. 08, May 09. 4 Marks. May ·11.
regions. The drain current then starts flowing through this
induced channel. 1be value of Vas at which this Ans.:
conduction begins is called as the ''threshold voltage" and
· The drain charactenstJcs
· · and transfer characteristics of a n-
iB indicated by VT or Vos <THr For an n channel E- channel e~hancement M0SFET are as shown· F 6 21(b) and.
M OSPET the threshoJd voltage is denoted by V.rn whereas (a) respecttvely. m tgs. ·
for a p channell!-MOSFET it is denoted by VTP·

e a S V- s 0 Ill f I 0 JI.S
Electronic Devices & Circuits-! (Eiex.·MU) 4-65

2. The gate current of a MOSFET i!l almost zero. So the

loading oo the source is considerably reduced.
3. MOSFETs consume very small power. So bau.ery operated
devices like caJculators, watcheb etc. prefer MOSFLITs.
4. MOSFETs can operate with positive as well as negative
gate to source voltages.
a. 36 Write a short note on : Input protec1Jon In
MOSFET. Ma 04. Dec. 12

Ans.:
If we increase the gate to source voltage of a MOSFET
above approximately 30 to 100 Volts, then breakdown will occur.
Breakdown means the Si02 layer beneath the gate layer gets
(a) Transfer characteristics (b) D ram· ch aracteristics ruptured. This will lead to a permanent damage to the device. The
<F·"') Fig. 6.21 : Characteristics of ... · · e1 e nbancement
..0 n-chann gate of an ~ represents one plate of its input capacitance (CP).
·The charge introduced at the gate will remain stored on this plate
MOSFET of the capacitor and will not leak off. Stray electrostatic charge can
The drain current is zero for V Gs s; VTN· For an n-channel easily develop very high voltage on this capacitor which can result
E-MOSFET the threshold voltage is denoted by vTN and for a p- in· the breakdown. It is interesting to und~rstand that a person
channel E-MOS~ v Th walking across a Jab floor is capable of ge!lerating a static voltage
. . the threshold voltage is denoted byTP.e which is as high as 10 kV. under suitable conditions. lf this person
tran_s_tier Vcharac~nsticsd shown in Fig. 6.2l(a) is totally in the
posttive os. regton an remains zero till v Gs -- v m· The re1au·on touches the gate of FET then the device will be easily damaged.
0
between drain current and VGS is given by the following equation,
I . 2
o =
k(VGs-Vm) ... (1)
~ere k is a constant and its value depends on the
construction of the device.
a. 33 Draw symbols of enhancement MOSFET :

~ (a) n-channel
s
(b) p-channel
(F-1627) Fig. 6.24.:
s
Diode protection circuit for MOSFET

This type of breakdown is avoided by using the d1ode

(B-1649) Fig. 6.22: Circuit symbols of enhancement type prot.r.ction circuit as shown in Fig. 6.24. This circuit is constructed
MOSFETs by the manufacturer at the input of the FET.
~i s typically of 250 Q to l.S kQ. 0 1 and 0 2 are acLUally

G~ G~
present, but 0 3 is formed as a result of the fabrication process of
R5• However 0 3 does not contribute in the protection of gate.
Operation of the protection circuit :
. If the input voltage is positive and excessively large, then
0 1 is forward biased and it "clamps the gate voltage to the drain
(c) n-channel (d) p-chaonel
voltage . Thus the maximum positive gate voltage is restricted to
(B-1650) Fig. 6.23 :. Simplified symbols for enhancement + Vg(m:tx) = (V0 + 0.7) Volts ...(1)
MOSFETs If the negative input voltage exceeds a particular value then
0 2 is forward biased and it clamps the gate voltage to the source
0.34 State applications of EMOSFET : voltage. Hence the maximum negative gate vol.tage is restricted to
- Vg lmax> = (Vs - 0.7) Volts ...(2)
Ana.:
Thus the diode protection circuit will protect the MOSFET
Applications of EMOSFET are , . from breaking down.
I. EMOSFET can be used as a linear amplifier.·
2. As an inverter.
a. 37 Compare MOSFET and FET.
3. As an active load (in integrator circuits). Dec. 09. Lila 10. fJia 11
4. CMOS inverter. . Ans.:
~ In the digital circuits. .
Sr. JFET MOSFET
a. 35 State advantages of f!!OSFET over JFET • No.
Ana.: 1. JFET are of two types, MOSFETs can be of depletion
Advantages of MOSFET over JFET are • . . JFET p-channel and n- type or enhancement type.
l. MOSFETs have a higher input reststance than · channel JFETs.

ea s v · S O I IIIIOII S
Electronic Devices & Clrcults-1 (Eiex.-MU)

Sr. J'FET Ana.:

MOSFET EMOSFET
,&, · Sr. DMOSfET
2. The symbols of JFETs The symbols of MOSFETs are No. · Symbols of enhancement
are as follows : as follows : l. Symbols of depletion
MOSFET:
MOSFET :

(B-1658)
3. JFETs do not have the MOSFETs have the insulated (B-1657}
insulated gate. gate structure.
4. Input impedance is Input impedance is higher than 2.' An insulating oxide layer The insulating oxide layer
lower than that of the that of JFET due to the (Si02) is present ~tw~n is present between gate and
MOSFEI's. insulated gate structure. gate and channel. substrate.
5. Drain resistance is Drain resistance is higher than 3. n or p type channel is Channel is not present. At
lower than that of a that of a JFET. present. the time of operation, an
MOSFEI'. induced channel gets
created.
0.38 Give comparison of JFET and 0-MOSFET.
4. For an n-channel For an n-channel
~:
DMOSFET, the V Gs can be EMOSFET, V Gs will be
negative for depletion only positive.
mode and positive for
1. Symbol of n<hannel Symbol of n-<:hannel enhancement mode.
JFET : depletion MOSFET :
5.

G~
For an n-<:hannel For an n-cbannel •

G~
DMOSFET, 10 decreases EMOSFET, 10 increases as
as VGS becomes more and V Gs becomes more and
more negative. more positive.
6. For an n-<:hannel
(F-lUS) For an n<hannel
DMQSFET, EMOSFET,
2. The oxide layer is absent The insulating layer of Si02
hence gate is not isolated is present between the gate
from the channel. and channel.
3. Drain current decreases Drain current· decreases as
with increase in the negative VGs is increased. Currentlvoltege controlled Voltage
negative V voltage. device
controlled
4. Reduction in drain current Reduction in I 0 is due to the 2. Unipolar/bipolar device Ulipolar
is due to the narrowing of recombination process 3. Symbol :
the channel width with taking place under the
increase in - V GS' influence of negative V
s. Drain characteristics are Drain characteristics are
drawn only for same as those of JFET
V GS S 0 volts. except for the part 4. Input resistance
corresponding to positive Low or High Very h9l
moderate
5. Noise produoed Hi!jl Low Very loW
Q. 39 Differentiate between enhancement MOSFET and
6. Swilching a,...,.. Lo
""""" w· ,Hqt ,H~ _,
deptetlon MOSFET.
Dec 03. f>'l<~ 07. M<~ 08. f>'l<t 16. Dec. 16 Q. 41 Explain difference between N-channel and
P-channel JFET. UfiiiD

t: :t :. V <; II III I Ill II s

 £!ectronlc Devices & Circuits-! (Eiex.-MU)
4-67

Q. 42 Aa a switch JFET 11 preferred over BJT justify·.

Symbol
IDiml
Ana.:
.JFET as a switch is preferred over BIT due to tbe following
reasons:
l. ~T is a voltage controlled device. So the switching
s1gnal should be a voltage signal. This is easy to implement
in p~tice.
Substrate 2. JFET can. switch on and off at a much faster rate than a
P type substrate ·
(F-1581) N type substrate BIT.
Voltage
polarities and <F-1581) JFET is less noisy than a BIT.
cwrent - JFET turns off very quickly bec;:ause, it is a majority carrier
directions device. So no time is wasted in the recombination process
at the time of tum off.
On state resistance is low. • •
.The state change from ohmic to off and vice versa is easier
and faster than the state change from saturation to cut off in
BIT. • .
Negative Positive

Chapter 7 : DC Circuit Analysis of FET Circuit

Q.1 Which are different methods ·of f:>lasing for JFET · Ans.:
and MOSFET ? . l•l44f.j The given MOSFET is a depletion type MOSFET and the
Ana.: Fig. 7.1 shows the classification of biasing circuits for JFET type of biasing is self biasing. · ·
and MOSFETs. , . •
Biasing drcuits Step 1 : Find IDQ :
I
+ + + Vos .,;· - 10 Rs = - 2.4 10

•
ForJFET For 0-MOSFET

•
For E-MOSFET 2
+
1. Axed bias 1 . Fixed bias 1. Feedback biasing Io = loS&[ 1 - v~:J
2. Self bias Z. Voltage divider 2. Voltage divider .2
3. Voltage divider bias biasing [
(-2.410 )]
bias
= 8 1- -8
<F-1650) Fig. 7.1 : Classification of biasing circuits .1
.. Io = 8 (8 - 2.4 10 ]
2

2
Q. 2 Which blaslng method cannot be used for
Dec. 09. Dec. 11
.. 8 In =· 64-38.410 + 5.7f> I 0
D-MOSFET and why ? 2
Ans. .: The self bias circuit cannot be used for D-MOSFET : . .S.16 I~- 46.4 In+ 64 = 0
because it cannot provide the positive V,GS r~uired for th~ . I _ 46.4 ± ')/,..<46-.4_,[,.._-4_x_5-.7-6_x_64_
operation of a n-channel depletion MOSFET J.D the enhancement " n - . 2 X 5.76 .
~ = 6.29 mA or In= 1.77 mA
Q. 3 Determine following for the circuit shown In Selecting IDQ = 1.77 mA ...Ans.
Fig. 7.2: (1) loa and V0 so (2) Yo- Step 2: Find VGSQ: .
VOSQ = - 2.4 IDQ =- 2.4 X 1.77 = - 4.24 V •••Ans.
Step 3 : Find vD : .
· V0 = V0 n-10 R0 =20-(l.77x6.2)=9.026V...Ans.
Ioss=BmA
Q. 4 State the regions of MOSFET Operation •
Vp=-6~
Ans.:
Depending on the demand of an application we have to
operate the MOSFET in any one of the following regions of
operation : ·

(F-J97l) Fig. 7.2

I! a :, V · s 0 I II I I ll II S
 ·s... No. tlon
l. Cutoff As an open switch
2. Saturation As an amplifier
3. Ohmic region As a closed switch
Q. 5 Wrtta short note : DC Load Une of a MOSFET.
Ana.:
The DC load line is helpful in identifying the region of
operation of a MOSFET. Considering the biasing circuit of
Fag.7 .3(a). The drain-source loop of this circuit is shown in
Fig. 7.3(b). Applying KVL to the drain-source loop to wii.te,
Voo = IoRo+Vos
l Voo
:. lo = -Ro Vos+ Ro . . ..(l)
Q.6 Write short note on : Various biasing schemes
Comparing this equation with the equation of a straigh~ line • used for EMOSFETs.
y =
mx+C
Equation (l) represents a straight line with a slope
l · Voo Ans. : The biasing circuits used for the enhancement type
m =-
Ro and y-intercept C Ro . · =
MOSFET are as follows :
As Ro is the de load reSistance, and the slope of the line · 1. ·. Feedba~k biasing arrangement for enhana:m~nt
represented by Equation (l) is inversely proportional to the de load MOSFET : This is one of the most popular btasmg
resistance, this line is known as de load line. The de load line is a.rrapgements for the enbance~ent type M<?SFETs. The
plotted on the drain characteristics as shown in Fig. 7.3(c). The two feedback biasing arrangement-Is .as shown m Fig. 7.4(a),
extreme points A and B on this line (Fig. 7.3(c)) are obtained by · and the de equivalent network is as shown in Fig. 7.~(b).
=
substituting Vos 0 and 10 =
0 respectively into Equation (1). When we use · feedback biasing for an amplifier the
feedback resistance ~ will connect a pcpt of output signal
Hence ~rdinates of point "A" .are A (o. ::) and those of "B" back to input. Hence this circuit is called a feedback
are B {V00, 0) . biasing. This arrangement is similar to collector to base
biasing in transistor. The resistor~ of Fig. 7.4(a) brings a
suitably large positive voltage to the gate to turn the
MOSFET "on". Due to the presence of Si02 insulating
Io . =
layer, the input impedance is very large. Hence Io 0 mA
=
and V RG 0 Volts. Therefore the drain (D) and gate (G) are
· equipotential points.
i.e.V0 = ·v 0 and Vns=Vos ...(l)
Therefore, a direct connection (short link) appears between
drain and source terminals as shown in Fig. 7.4(b).
+Voo

(a) Given biasing circuit (b) Drain source loop

<F-134) Fig. 7.3

The Q-point and transition points also are plotted on the

DC load line as shown in Fig. 7.3(c). The dotted curve corresponds
(a) Feedback biasing (b) DC equivalent network of
to the V DS(aal) curve .and the point of intersection of this curve with arrangement the feedback biasing
de Load line is called as the transition point. The transition point arrangement
separates the saturation and non-saturation ·regions as shown in
(F-136) Fig. 7.4
Fig. 7.3(c). The three regions marked on the load l.ine are as
2. Voltage divider biasing for enhancement type MOSFET :
follows:
1. Cut off 2. Saturation 3. Non saturation. The other most popular biasing arrange ment for the
enhancement type MOSFET is voltage divider biasing as
If the gate 10 source voltage V0 s is less than VT• the shown in Fig. 7.5.
MOSFET is in the cut off region.
Analysis of voltage divider biasing circuit :
Step 1 : Obtain the expression for VG :
As Io =0, referring to circuit of Fag. 7 .S ,
(;;tS Sll llll IIIIS
 £ectronic Devices & Clrcuits-1 (EiexA-AU) . '

Step 2 : Calculate IDQ :

...(2)
SteP 2 : Obtain expression for vcs : Vas = Va - Ir>Q Rs=~XVoo - IDQRs

ApPlying cbe KVL to the loop shown by thevarrow i~ Fig. 7.5 6.8 '
:. Vas= 10 + 6.8 x24 - 0.751DQ=9.7 - 0.75IDQ . ...(1)
r----..
+Db
:. IDQ = k [Vos - VOSCI'hl]
2 .
=0.55 [9.7 - 0.75 IDQ - 3]
2
2

:. IDQ = 0.55 [6.7- 0.75 IDQ]

: . 1.82IDQ = 0.56 ?OQ - 10 IOQ + 44.89
2
:. 0.56 I DQ- 11.82 IDQ + 44.89 = 0
11.82 ±yr(l-l-.8-2)....,2---4-x-:-0-:.56-=--
x -:-44:-:.8::::9
·····r·· " IDQ = 2 X 0.56
1
Vo R2
.. IDQ = 1. 8~-~26·26 =1~.14 mA or 4.96 mA
.....!..... IDQ = 16.14 mA will result in neg~ve V0 SQ
:. · Selecting IDQ 4.96 mA =
(F-139) Fig. 7 .S: Voltage divider biasing for a n-cbannel Step 3 : Calculate V0 and Vs :
~nhancement MOSFET . V0 = V00 -IDQ R0 =24 -(4.96 x2.2)
= 13.088 Volts
VG = Vas + VRS =VGs +Is Rs ...(3) · V5 = IDQ R5 = 4.96 x 0.75 = 3.72 Volts ...Ans.
But Is =Jn ·· VG =· VGS + lo Rs Q, 8 In the circuit shown In Fig. 7.7, find value of Ro H
:. VGs = Va-I~Rs ...(4) V050 =3V . . ·
Step 3 : Calculate IDQ : Transistor data:· Vm =1 Volt, 1<n = 160 J.IA I Y
loQ = k (Vas- VGs(Tht ..
,.~m·a~.,,..,

In this expression substituting V GS obtained in Step 2 and

the values of k and Vas (Th) to ob~ the value-of IDQ.
Step 4 : Obtain the expression for VDSQ :
Considering the output side of Fig. 7.5, applying KVL to
this side to write,
Voo IoRo+Vos +VRS .
= 10 R0 + Vos + 10 Rs =Vos +Io <Ro + Rs) ·
· V
•• OS
= . VDO - .I0 (R0. + R, S ) ...(5)

0.7
(F-t73)Fig. 7.7

· A~s.:
. N2
Given:Vrn = 1 Volt, k;,=l60~
10Mn To find : R~, V os

Step I : Calculate Vcs:

2
IOQ = k(Vos- VT)
2
160 X 10- 6 = 160 X 10- (VG5 -1 )
6
6.8MO
2 160x10~
(VGS- l) ·= 160 X 1006

.. <Vas-1)2 = l :. Vas- 1 =
(F-4718) Fig.7.6 :. V GS = 1 + 1 =2V
Yoso ,;, Voo """ IOQ Ro
Ana. : 3 = 5 - I~R0
Step I : Obtain k : 5 - 3 = l2.51dl
Yoo- Voso ... Ans.
:. Ro = IOQ 160 X 10=6
k = (VGS (oo) - V GS (Th)J
Write a note on the following : NMOS driver with
Q.9
= 5 rnA -0.55 mAJVz
[6 - 3] i enhancement load.

Cti S IJ · 'i iiiiiiiiiii S

 ,_
Electronic Devices & Clrcults-1 (Eiex.-MU)
V -V ==0 -VT=--VT
Ana.: VOS (Ill) =
= OS T b . .
V
05
0 becaUse gate and source are s ort crrcwted.
If an enhancement load device is connected as a load with
another M<?SFET as shown in Fig. 7.8, then the circuit can be used •.. ~~<~~·· · · r··· ···r·····r ····· · ·-··· ·-····· ·······-········· ··-····-. ......
~ ~ ~lifier or as an inverter in the digital logic circuit. In the
~~tt di~ of Fig. 7.8 . MOSFET M1 is the load device which
!·-·-· .......L.-...J......i , vDS(.., -.vos- Vr•-Vr

E:~J=li~:dJ)j'
ts biased m saturation and MOSFET Mz operates the driver
MOSFET which operates either in saturation or noosaturation.
+Voo 1 ~ i : ~ ~ ~ i ~ t t
·....-----....... ~ lo1 L ........L. . .vOS(aat) .. "'!........';. _...1L ...J....
.·-o ' i v n~
OS\·alta)

Load
.(a) A depletion (b) Output cbaraderistics 8Dd
NMOS with gate source connected together

<F-163) Fig. 7.9

Considering the circuit shown. in Fig. 7.10 in which the D-

Vos2 Driver
MOSFET is used as a depletion load device. .The D-MOSFEr can
be biased in the saturation or non satlll'ation regions, depending on
the parameter values ~d V00 and R5 • The D-MOSFET.biased in
. this manner can be used as a resistor. It can replace resistors in the
(F-161) Fig. 7.8.: NMOS driver with enhancement load ' M:OSFET integrated circuits.

Expression for the transition point :

The 1raosition point is the point that separates the non
saturation and saturation regions of a MOSFET. The expression for
the transition point of the driver MOSFET Mz in Fig. 7.8.
Vos2(at) = Vos2- Vn
Q.10 Write a note on the following: Depletion MOSFET
as load device.
Ans.:-'
Fig. 7.9(a) shows a 1)-MOSFET with ·its gate and source
terminals connected together. Fig. 7.9(b) . shows the drain <F-164)Fig. 7.10: A depletion load device
characteristics of this device.
The D-MOSFET can be biased in the saturation or non
saturation regions. The transition pOint is shown in Fig. 7.9(b). The
threshold voltage VT of an n-cbannel D-MOSFET is negative.
Hence VDS <at>will be positive because, . ·

Chapter 8 : Small Signal·Analysis of FET Amplifiers

Q. 1 What are the three basic conflgur,aflons of Fig. 8.l(a) shows a typical ·cs amplifier. The input and
MOSFET amplifiers ? output voltage waveforms are ·180° out of phaSe with respect to
each other. The voltage divider biasing (VDB) is used for biasing
Ana.: the MOSFET in saturation region. .
The MOSFET is a three terminal device. Depending on
which terminal is used as signal ground. there are three basic
configurations of the MOSFET amplifiers as :
1. Common souice configuration.
2. CollllllPn gate amplifier.
3. Common drain configuration (source follower).
Q. 2 Wrtte a short note on ~e following : CS MOSFET
amplifier
Ana.: In cs MOSFET ampUtler configuration , the source (S)
terminal acts as the common terminal for input as well as output.
· The input signal is applied at the gate <<:J> tenninal wi!h
respect to source and the llJllplified output is obtatned at the drain (a) CS MOSFET ampllfter (b) Input outpu' waveforms
(D) with respect to source. (F..c852) Fig. 8.1

e a :. v - s n11111 1111 s
r ~ Devices & Ciroultf-1 (Eiex.-MU)
4-71
API"~:
1be CS amplifiers Q.U find applications In the - .
1. As a pre-amplifier. fullowtng areas:
2. As a voltage amplifier.
3. [n tbe radio and TV amplifier circuits
fNCU"M of CS •mplthr : ·
1. H'lgb voltage gain. 0
:z.. LowR.,
3. Modentely high ~n
4.. Out of phase input and output.
0. 3 Write • ahort note on the foil ·
tmptlfter. owing :CD MOSFET

Ana.: . ''"•MI
The CD configuration of MOSFET · · . (a) CG MOSFET ampUfle~ (b) Input output waveforms
cbe CC or emitte£ follower conh~·-tt'
sbown tn
. ';!t!
2(
ampflifier ts sunilar to
'"6~... on o a BIT amplifi
. • a). 'lbe input voltage is ap lied er, as
(F-4854) Fig. 8.3 .
output is from the . P to the gate and The voltage divider biasing is used to bias the MOSFET in
..:-it, tbe drain (D) · soun-:e termmal. In the ac equivalent the saturation region: The input and output waveforms are ·as
...._. ts connected to ground Th .
ac voltages are measured with · . us ~put and output shown _in Fig. ·8.3(b) which shows that they are in phase with each
· respect to drain terminal Hence the other. CG amplifier is a wideband amplifier. It has a large
DIPIC ~ dmin (CD)_amplifier. The voltage divid~r biasing is
used to bias tbe MOSFET m the saturation reaion Th ·
bandwidth.
_........,_ wavefonns b . o- • e mput output Features of CG amplifier :
..~._"' . are ass own m Fig. 8.2(b). They are in phase
wttb each ocber With voltage gain less than 1. 1. · FJigh voltage gain (Av > 1)
+Voo 2. High output resistance.
..---+ 3. Low input resistance.
· 4. It has large bandwidth.
5. No phase shift between input and output
·Applicatf~n: .
• In the high frequency (RF) amplifiers.
Q. 5 Compare the three amplifier configurations of
MOSFET amplifiers.

(b) Input output Ans.: Comparison of MOSFET amplifier configurations :

(a) CD or source follower
Coofiguration waveforms ·

(F~) Fig. 8.2

Feelurea of CD amplifier
l. Low voltage gain (Av < 1). . 2. · Gate Gate Source
2. Very high input resistance
3. Drain Sowce Drain
3. Very low output resistance.
4. lao pbase shift between input and output voltages. 4.
AppHcatlone
1. As the output amplifier stage. 2. As a buffer.
5.
0. 4 Wrtte a •hort note on the following : CG MOSFET
6.
amplifier.
7. Output resistance Low Low
Ana.:
The Common Gate (CG) MOSFET amplifier is as shoW? in Q. 6 Draw and explain small signal equivalent circuit
Pig. 8.3(a). The input signal is applied to the Sour~ (S) ~nmnal of CS amplifier with voltage divider blas.18@jl0i
with respect k, the Gate (G) and the output voltage 1s obtruned at
tbe ~=- .(D) . ..a. pect to n<>t~. Thus all the voltages are
•.~uw.t WJ.w res &-- . . a1 He the name Ana. : The basic CS amplifier using MOSFBT (n channel) is
measured witb respect to the Gate (9) tetmJD · nee shown in Fig. 8.4.The type of biasing circuit used here is the
Common Gate (CG) ampJjfier. voltage divider biasing. 'Resistors R 1 and~ will bias the MOSFET
in its satumtion region.

1: ;; •. II '• H I II I I II II '>
 Eleclronlc Oevioes & Cfrcults-1 (Eiex.-MU)
Ana. : PBrt I : DC •n•lyala
+tOV Step l : Calculate V<:80 :
V • y _ y9 • v0 slnce V11 • 0
...
OSQ 0. O
, y
.. OSQ
•
R, + ~
R:2 x 5 V • 20: 30 X 5 2 Volts =
Step l : Calculate 100 : 1
IOQ =
K(YosQ - V,i= tOO x 10...(1(2 - 1)
... lr>Q = 100 J1A
Step 3 : Calculate &n and r 0 :

8m = 2K(Vos - VT)
= 2x l00 X l0- 6 (2 - 1) =200 ~A/V
- 1
r0 = 'I
[11. IDQ)
Since A. is not given, assuming that it is equal to zero.
<F-IIU) ttlg.. 8.4 : CS am.plUitr with voltage dlvtder biasing
.. r0 = oo
SIMI 8lgnal equtwient circuit :
Part II : AC analysis
Step 1 : Draw the smaU signal equivalent clrcult :
@ . ......
ld
v0 + +
• @
RtiiR2 Vgt Om VIlli ro Vo
RL

(F-1~ Fig. 8.7 : Small signal equivalent circuit

Input resistance : Step 2 : Voltage gain:
R; = Rtll~ .. ... (1) vo-- 8.n vg. (Ro II RL)
Vollage gain : Av = V1 - V85
Av = v;v.. .. Av = - gm (Ro II RJ
But V0 = Voltage across (r II Ro) ...(2)
:. V o = - &. V p (ro II Ro>
0
= - 200 X 10 -6 X (20 X103 X 47 X 10
3
3
)
. .(20 + 47) X 10
R; =- 2.8
aodVP = R.;+R; x vin ...Ans.
Step3: ~and Ra:
R;
:. Vo = - &. (ro II Ro> •~ + R; X V 1n R; = Rtll ~ =20 k 1130 k 20
5~ = 12 k.Q
30
...Ans.

vo - ~·R; 20 47
:. Av = V itJ =<R,. + R;) · (ro II Ro) ... (3) Ro = Ro II RL =20 1147 k - k ;, = 14 kQ ...Ans.

Q. 7 For the amplifier circuit shown In Fig. 8.6, .derive Q. 8 ~or the circuit shown In Fig. 8.8 ,Find Ay, R1 and
the e..,...aons for Ay, R1 and R0 • Compare this
amplifier with C.E. amplifier. I•J4Me1Cj Ans. :
o· • ·'fflh"l'
+6V
30V

47k

VGS(Itl) ,., 3V'

-3
K•0.4 x 10
rd•40k0

O"·Wf> f1a. 8.6: Glvea amplUier CC-4816) Ftg.8.8

f• . 1 . 0 ·. o I II I I It II ~.
 ..
Electronic Devices & Circuits-! (Eiex.-MU)

Ant· :
4-73

pert 1: DC analyala : = - 1.33 (40 k 113.3 k) =- 1.33 [ : : ~:~]

S#P 1 : Find VGSQ : .. Av = - 4.054 ••.Ans.

VGSQ = Vo- Vs = Vo -lDQ R5 Step 4 : CakuJate R. :

~ R0 = (rd II R0 ) =40 k IIJ.3 k
and Yo= R I +R2 x Voo
= 3.048 k.Q ••.Ans.
10
= 40 + 10 X 30 = 6 V Q. 9 For the given E-MOSFET amplifier, determine
R., Av and R0 • Refer Fig. 8.1 0. I®GiiiOj
.. VGSQ= (6-1.21~
Step 2 : Find IDQ :
IDQ = K(VGSQ -VT)2
= 0.4 [6- 1.2 IDQ - 3]2
IDQ = 0.4 [3 - 1.2 IDQ1
.
2
2
··~
IDQ = 0.4 [9 - .7.2 IDQ + 1.44 ~ ]
2
.. 1.44 ~ -9.7 IDQ +9 = 0
Solving the quadratic equation to get,
2
-9.7 ±y(- 9.7) - (4 X 1.44 X 9)
IDQ = 2 X 1.44
VGS(Th) = 3V, IO(ON). = 5mA, VGS(ON) =&I
= 5:62 mA or 1.11 mA (B-2648) Fig. 8.10
Selecting IDQ = 1.11 mA
:. VGSQ = 6 - (1.2 X 1.11) = 4.668 V Ans...:
Given·:VGS (Th) = 3 V, Io(on) = 5 mA, VGS (on)= 6 V
Step 3 : Find &u : Type of circuit : E-MOSFET CS amplifier.
g, = · 2K(VosQ:....vT) To find : . }\, A v, R0 •
= 2 X 0.4 (4.668- 3) =1.33 mAN DC AnalysiS :
Part 2 : AC analysis _
; Step .1 : Draw the DC equivalent circuit :
Step 1 : Draw the small signal equivalent circuit : The DC equivalent circuit is shown in Fig. 8.11.
Step 2 ; Calculate value of K :

@
(C-4828) Fig. S.9: AC equival~nt circuit

Sttp 2 : CalcuJate llt :

R; = R 1 11 Rz =40 111°
40X 10 -S MO .•.Ans.
= so -
(B-2651) Fig. 8.11
S&ep 3 : Calculate Av :
v0 . Step 3 : Calculate VGSQ :
Av = V io But V in =V GS VosQ = Vo - Vs
But V0 = Voltage across (rd II Ro) y 0 = Rl ~ Rz x V00 = lO } 6 .8 x 24 = 9.71 Volts
6

= - g, V GS (rd II Ro)
v Vs = IDQ Rs=0.75IDQ
:. ~ = - 8m (rd II Ro) :. VosQ = (9.71- 0.75 I~
OS

I!:J~>IJ - !;O IIII IO IIS

 Electronic Devloee & Circuita-l (Elex.-MU) V

Sttp • : Calaalate lOQ :

+Voo
K (VGSQ - V~ ('11\/"' 2.5[9.71 - 0.7S IDQ - 3]
1
ioQ "'
= 2.5 [6.7 l - 0.7S IDQ12
• 2.5 [45 - 10 too +0.56 ~]
2
· · loQ • 112.5 - 2S I1lQ + 1.4 IOQ
1
:. 1.4~ - 26 1{)Q+ll2.5 = 0
Solving we get,
loo = 26 ±:Jr-<2-6-.)2--....(4_x_l-.4-.x-11-2.-5) _ 26 ± 6.78
2 X 1.4 2.8
.. ~ =
11.7 mA or 6.86 mA
Discard too = 11.7 mA because it produces a (F-1826} Fig. 8.13 : Source follower amplifier
negative V 05 ·
So selecting I~ = 6.86 mA
... l{)Q = 6.86 mA
:. VGSQ = 9.71-0.75x6.86=4.57Volts

Step S : Cakalate g., r • :

&.. = 2 K (VGSQ- VTn) =2 x 2.5 (4.57- 3) = 7.85 mA!V
r0 = [A ~~-
1
=oo

AC..tysls:
SIJep 1 ~ Draw small signal (!quivalent circuit : Fig. 8.14: AC equivalent circuit

Fig. 8.15 shows the small signal equivalent circuit.

Rsl v .
· -- ---1......-----o ~......---1----~-~ .

(8-:wl) F1g. 8.12 : Small signal equivalent , <F-1827) Fig. 8.15 : Small sigDal equivalent circuit
. Expression for voltage gain (Av) : .

Av = ~
v o -~ID va Rll V;
Av = VID vgs
=-g;,RD .
But Vo = Voltage across (r0 11 Rg)
.. Av = - 7.85 X 2.2 =-17.27
:. vo = gm vgs (ro II Rs) ... (1)
R• = R 1 11~= 10.MOII6.8Mn

4.05Mn •••Ans.
and vio = vss +Yo ... (2)
=

...Ans.
vgs + gm v gs (ro II Rs) =v 8S [1 + 8m (ro II Rs)]
vio
Q. 10 Anetyze the CD MOSFET a.mpllfler ualng Ita amall .. v.. = ... (3)
.tgnal equivalent circuit.
AM.: But V -~X V1
io- Ra~+~
lrJ CD MOSPET amplifier • tbe input is applied to the gate
IIDd output is obtained at tbe source. The source follower amplifier .. v = (R/(Rli +~)]VI
usiog MOSPE'f islbown in Pig, 8.13. . 11 1 + &m(roll Rs)
Tbe .-c equivalent circuit i1 shown in Pig. 8.14. In the ac
tJqu.ivaleol cl.rcuit tbe diJin gets connected to ground and all the Substituting this into expression for V0 to get,
volrages are measured with respect to tbe drain. Hence the circuit is V :; + &m [Ri I (Rt + Ra~)J V1(r0 II Rg)
... (4)
1 + g, (ro II Rs)
9
c.a1led u common drain circuit.

t· ,, · 'J ' II Ill I I II II '•

 eteetronic Devices & Circuits-! (Eiex.-MU) 4-75
.......-
Vo + 8m lR/<Rt + ~)] (ro II Rs>
Ana.:
:. Av = V; 1 + &m (ro II Rs>
Part I : DC analysis
= + g, (ro II Rs> [ R;_1 Step 1 : Expression for VGSQ :
1 + g, (ro II Rs> R;+'RJ ... (5)
'Ibis is the required expression. VGSQ = V0 - V5 =V0 -IDQRs
Input resistance (R.) : ~ 460
and V0 = R +~ x V00 : 160 + 460 x 12=8.9Volts
R; = <R.II~ ... (6)
1
output resistance (RJ : :. VGSQ =
(8.9- 680 I~
Step 2 : Cakulate IDQ :
R~ucing V; to zero. The equivalent circuit to calculate o
is sboWD m Fig. 8.16. . ·'D 05
3
IDQ . = K (V Q- Vi=4 x 10- [ (8.9-680IDQ-I.48) i
3 2
' Nodi A = 4 X 10- [ 7.42-680 IDQ]
3 . 2
lo
..... . ... = 4 x 10- [55- 10091.2 IDQ + 462400 IDQ]
+
.. I~ = 1849.61~ - 40.36 IDQ + 0.22
2
. . 1849.6 IDQ 2
- 41.36 IDQ + 0_.22 = 0
~~~------------~---
2
41.36 ±y(- 41.36) - (4 X 1849.6 X 0.22)
. ' IDQ = 2 X 1849.6
= 13.64 mA or 8.72 mA .·
<F-1828) Fig. 8.16: Circuit to obtain R. Selecting IDQ =
8.72 mA as the other value yields
a negative VosQ
Assuming that a voltage source of V 0 volts has been
connected between the output source andthe current supplied by Step 3 : Cakulate GSQ : v
this source is ~· Then, VGSQ =
(8.9-680 x 8.72 x 10-~= 297 Volts
Step 4 : Cakulate g, and r • :
~ = Vo/Io =
8m = 2K (VGSQ- VT) 2 X 4 (2.97 - 1.48) = 11.92 mA/V.
1
and r0 = (A~~- 1 = (0.01 X 8.72 X 10-
3
Applying KCL at node A to get,
f =11.467 ill
Part II : AC analysis
lo+g,.,Vss = l,+IRS Step 1 : Input resistance :
But lr = V /r and IRS=VJRs
0 0
160 x 460
R1 = R 1 liR2 - 460 + l60
= vo[t+~
118.7 ill ...Ans.
:. lo+8m v ..
Step 2 : Voltage gain :
As the current flowing through Rsi and (R1 II ~ is zero, the
voltage drop across it will also be equal to zero. Hence gate (G) 8m (ro II R,) [ R; J
Av = 1 + g, (ro II Rs) ~ + RJ
·will be connected to drain.
:. v, = - v 'Ml =- v 0 = 11.92 (11.467 11 o.68) [ 118.7 ]

vo[t+~ +gm Vo = vo[g,.,+t+~J

1+ 11.92 (11.467 11 o.68)· 10 + 118.7
.. 10 = 11.92 X 0.6419
c 1+ (1 1.92 X 0.6419) X 0.9222 =0.8156 _.Am.
vn- 1
~=- J Step3:0u~ut~:
" 10 • [ g,.,+:o +~J 1 ' 1
Ro = &m llroiiRs 1 1.92 X 10-J 0IL467kll0.68k
:. ~ =
7
-:l II Rs II ro· ... < > :. R0 = (83.89 k 1111.467 k II 0.68 k) = (10.08 k II 0.68 k)
8m
This is the required expression for Ro· :. R0 = 0.63702 ill= 637.02 Q ...Ans.

0.11 For the source follower circuit shown In Flg.8.17. Q. 12 For the CG ampiHier shown In Fig. 8.18, calculate
calculate the small signal voltage gain, Input the voltage gain Av, R1 and R0 • The MOSFET
resistance and output ntSistance. parameters are VT =1V, K = 1mAI'I and A 0. =
+12V Also calculate the output voltage H the Input
·1
~ =0.01 v voltage Is 100 sin mt mV.
2
• K=4mAIV
VT= 1.48V

CGfio
. 1--r-:··
3.9k. ~f\"'~
+5V

(F-1834) Fig. 8.18: Given CG ampllfter

(F.tm>Fig. 8.17: Given source follower

e a s v-s nluJJun s
 4-76
Electronic Devices & Clroults-1 (Eiex.-MU) '
Step 2 : Calculate Av :
Ana. :
Part I : DC Anelyal8 am<Roll RJ = 2.J)+9(2.J9
p.9ll8.2}
Av = 1 + gm R~l X 1)
Step 1 : Calculate v GSQ :
2.19 X 2.642 =1.8144
= 1 + 2.19

Step3: Output voltage :

vo =
Av x y 1 =1.8144 x 100 sin w t m V
:. VGSQ = 2.095 Volts ... (1)
sin w t m V
= 181.44
,
Step 2 : Calculate g., : Output resistance :
Step 4 :
&., = 2K (VGSQ- VT) = 2 X 1 (2.095- 1) Ro II RL =3.9 ldlll 8.2 ldl =2.642 ldl •••Ans.
= 2.l9m.AIV ... (2) R0 =
Part II : AC Analysis

Step 1 : Calculate~ :
l 1
R
. -; -8m
- X l0-3 456.4 n· ...Ans.
2 19
Chapter 9 : Special Semiconductor Devices-1

The forward biased zener diode behaves identical to a

Q. 1 Write short note on : Zener diode : Principle.
forward biased diode. The forward biasing of a zener diode is
Dec.02. Dec.OB shown in Fig. 9.l(b). The zener diode is generally not used in the
Ans. : "Zener diode" is a special type of p-n junction forward biased condition. ·
semiconductor diode. Its construction is similar to that of .a
cooventi.onal p-n junction diode. However in constrUcting the Reverse biasing of zener diode :
zeoer diodes, the reverse breakdown voltage is adjusted precisely When the cathode is connected to the positive terminal and
between 3 V to 200 V. anode is connected.to the negative terminal of the de source, the
Its applications are based on this principle hence zener zener diode is said to be reverse biased. The operation of zener
diode is called as a breakdown diode. _ diode in the reverse biased condition is substantially different from
The doping level of the impurity added to manufacture the . that of a diode. The reverse biasing of a zener diode is shown in
zeoer diodes is controlled in order to adjust the precise value of Fig. 9.l(c). Zener diode in the reverse biased condition is used as a
breakdown voltage. voltage regulator.
Q. 2 Clear1y describe the phenomenon which governs Q. 3 Write short note on : Zener diode VII
the working of zener diode. Dec. 02. Dec. OB characteristics. Dec. ·oa. Dec. 16
Ans.: Ans.:
The cin:nit symbol of a zener diode is as shown in The V-1 characteris~cs of a zener diode can be divided into
Fig. 9.l(a). It is a two terminal device and the terminals are anode two parts: ·
and cathode. The arrowhead in the symbol points towards the 1. Forward characteristics
cooventional direction of current through the zener diode, when it 2. Reverse characteristics
is forward biased
Forward characteristics :
T+
rn:-~
,~
rn
Curmnt limiting mslslor
The forward characteristics of a zener diode is shown in

•
J Calhode

Anode

(a) Circuit
V-
-
IF
............/

(b) Forward
;
v
.

(c) Reverse biasing of

Vz
.L
·
~ig. ~.2. I~ is almost identical to the forward characteristics of a p-n
JUnction dtode.
Reverse characteristics :
. The reverse characteristics of a zener diode is substantially
dtfferent from that of the p-n junction diode. As we increase the
reverse voltage, initially a small reverse saturation current "I "
symbol of a biasing of a zener a zener diode which is in !AA will flow. This current flows due' to the thermallY
generated · ' t ·
zeaerdiode diode mmon Y earners. At a certain value of reverse voltage,
!he_rev_erse current will increase suddenly and sharply. This is an
(e-42)Fig. 9.1 : CircuJt syinbol and biasing of a zener diode mdicati~n that the breakdown bas occurred. This breakdown
voltage ts called as zener breakdown voltage or zeoer voltage
Forward bluing of zener diode :
and it is denoted by V•• The value of V can be precisely
Wben the anode of the zener diode is connected to the c_ontrolled by controlling the doping levels ofp ~d n regions at the
positive terminal of tbe de sour~ ~~ the. cathode is conne~ted to time of manufacturing a zener diode. After breakdown has
tbe negative terminal, the zener diode IS swd to be forward btased. occurred, the voltage across zener diode remains constant equal to

P. a s 11 •, IIIII I JIJ II !i

....
 3ectronic Devices & Circuits· I (Eiex. ·MU)
4·77
v•. Any increase in the source vo.ltage will result in the increase in atoms and impart some of the kinetic energy to the valence
reverse zeoer current. The zener curre
bfeakdown must be controlled b con . nt aft?r the . reverse . electrons present in the covalent bonds.
with the zener diode. This is es~nlinln:J~ng.: reststor R to series Due to this additionally acquired energy, these valence
device due to excessive beating. vot any damage to the electrons will break their covalent bonds and jump into the
conduction bond to become free for conduction. These newly
zener Region end Its Importance :
generated free electrons will get accelerated. They will knock out
After reverse breakdown, the zener di . ·some more valence electrons by means of collision. This
region called zener region, as shown in Fig 9 2odie tho~rat~s m a
voltage across zener diode remains constant · ·b · t n IS reg10o the phenomenon is called as "carrier multiplication".
~.,.A;nn on the su 1 v 1 U current changes
In 11 very short time, a large number of free minority
~·......'6 • • .PP y o tage. Zener diode is operated in this electrons and holes will be available for conduction, and the carrier
regton when tt IS bemg used as n voltage re 1 . multiplication process becomes self sustained. This self sustained
V-1 characteristics is as shown in Fig. 9.2. gu ator. The complete
·multiplication is called "Avalanche Effect". A large reverse current
Forward current · starts flowing through the zener diode and the avalanche
breakdown is said to have occurred.
!
8l'ellkdoWn YOiage A current limiting resistor should be connected in series
v. with the zener diode to protect it against the damage due to
~ 11011age •-"t--------}ro---i(-~F~o:rw~ ard vol1age excessive heating. The breakdown voltage in the avalanche
....
l J
·,~ 1......................: ::::::0 breakdown increases with increase in the junction temperature. The
TZene( >
,
Knee point
. Zmln. . Cut In vol1age V-I characteristics in the reverse biased region with. avalanche
breakdown is shown in Fig. 9.3(b), which shows that the
region characteristics bas a gradually increasing nat.ure.
1 . . . . . . . . . . .... ......... Jzmax.
. -- - - BI1MII<down vcll!lga - - - - - .

Reverse current
(B-44)Fig. 9.2: V-I characteristics ofa zener diode
Q. 4 Write short note • on : Avalanche · and zener
breakdown mechanism.
-I
Dec. 03 May 06. May 07. May 16
Ans. : In zener diode, there are two different -breakdown (a) Zener breakdown (b) Avalanche breakdown
mechanisms. 1bey are :
. <B-4')Fig. 9.3
1. Zener breakdown 2. Avalanche breatdown
1. Zener breakdown : The zener breakdown is observed in Q . 5 pifferentiate between zener and avalanche
the zener diodes having Vz less than·5 V or betw~n 5 to 8 breakdown.
Volts. When a reverse voltage (5 V or less) is applied to a Ans.:
zener diode, it causes a very intense electric field to appear
across a narrow depletion region. This intense electric field
is strong enough to pull some of the valence electrons into
the conduction band by breaking their covalent bonds. This is observed in zener This is observed in zener.
These electrons. then become free electrons which are diodes having V z between diodes having V z greater
available for conduction. · . 5 to 8 Volts. than 8 Volts.
A large number of such free electrons will constitute a 2. The valence electrons are The valence electrons are
large reverse current through the ·zener diod: and pulled into conduction pushed into conduction
breakdown is said to · have occurred due to the Zener band due to very intense band due to the energy
effect". A current limiting resistance should.be co~ected electric field appearing imparted by colliding
in series with the zener diode to protect tt agamst the . across the narrow accelerated ~ority
damage due to excessive heating. In zener bn!akdown, the carriers.
bieakdown voltage depends on the tempe~~ of P:n 3.. V-I characteristics with The V-I characteristics
junction. The breakdown voltage decreases WI~ l.ncr~ase m. the zen~r breakdown is with the avalanche
the J·unction temperature. The V-I charactenstt.cs m the very sharp. breakdown increases
· . . · p·g 9 3(a) whtch shows
reverse biased regton IS shown m 1 · • • · h gradually.- It is not as
that the characteristics after breakdown IS very s arp, sharp as that with the
almost vertical. · 1 b zener breakdown.
2· in Zener Diodes : The ava anc e
Avalanche Breakdown . · diodes having Vz 4. The breakdown voltage The breakdown voltage
breakdown is observed to the zener . f breakdown decreases with increase in increases with increase in
higher than 8 V. Even though the mechamsm odiode In the
has cbangi.d. the device is still called ~ zene~ll tak~ place
~: · the c.onduetton WI Q, 6 Give comperlaon of zener diode and p-n )unction
reverse biased conwtton, . As we increase the
· ' t earners diode
only due to the mmon Y · d' -~A these minority
l 'ed to the zener IVIW•
rev~ voltage app J te Therefore the kinetic energy
earners teod to accele~ · . While travelling. these
associated with them ~re~ · llide with the stationary
11
6

accelerated minority earners WI co

 . 4-78
Electronic Devices & Circuits-! (Eiex.-MU) ~
lain the principle of operation • of varactor
Ans.: Q. 9 Exp
Sr. · p-njonetion diode diode·
Zener diode
No. Ans.:
1. Symbol : (B-47) Symbol : (B-48)
The varactor diode is basicall~ a p-n junction_ diode which
. ted in the reverse biased regton. The two stdes of a p-n
Ao 1>1~'1----oo K A o ~:Mf----0 K ~s o~ra will act as the conducting plates and the depletion region
JUDCbOn · between tbem to fionn the
the dielectric matenal
behaves as · r Thi · h
2. This is operated in the Zener is operated in the junction capacitance or transition ca~cttance '-T' s. ts s own in
forward biased condition. reverse biased condition. Fig. 9.5. This is the principle of operabon o~ varactor diod~.
3. V-1 characteristics: Refer V-I characteristics: Refer Thus the transition capacitance extsts at the p-n Junction.
Fig. A Fig.B The transition capacitance C,. of a p-njunction diode is given by,
4. Applications of p-n A
junction diodes are in the
Applications of zener c,. = e wd ...(I)
diode is in voltage
rectifiers, clippers, regulators. voltage limiters where, A = Area of the p-n junction area.
clampers, voltage. etc. and Wd = Width of the depletion region.
multipliers. As the reverse voltage increases, the width of depletion
Forward current (mA) region incre.ases. This will reduce the transition capacitance C,..
Forward
characteristics The characteristics of varactor diode is as shown in Fig. 9.5(a).
Ge
Capaci1ance CT (pF)
Si ., ... ,_ , .......!
Reverse Forward
CT decreases wi1tl increase
voltage +:;;::=-:;::;;==r-;:'f-"""":;':'!;-- voHage
(Volts) . : I, in nA j 0.2 0.6 (Volts) in reverse voltage

(Io in""
--~

Si.
JGe "" 40~
Reverse .. ·'
Characteristics , Reverse current (!lA) ~--

(B-49) Fig. A ............. ''"' 20

Forward current
"' "~ ·~
- ;

Reverse
voltage M -16 -12 -8 -4 0 '

(a) Variation of C,. with reverse voltage

Depletion
region
p sde
Reverse c~nt · ~· n side
(B-50) Fig. B 0 0 0 e • • •
~
Q, 7 Write short note on Zener diode application. - 0 0 0 e <!> · • • r-
. I•J§Mel:l 0
0 e6 • • •
Ans.: Zener diode applications are,
0
0 e6 • •
1. As a voltage reference in emitter follower type voltage 1+----t
regtllator. . wd
2. As a regulated power supply.
(b) p-njunction and depletion region
3. In the protection circuits for MOSFET and .OPAMPs.
4. In the clipping circuits , pulse amplifier. (F-221S)Fig. 9.5
Q. 10 S~te ap.pllcatJons of Varactor Diode
Q. 8 Draw symbol of Varactor (Varicap) Diode.
Ans.: Diodes made especially for the applications·which are based Ans. :Vanous applications of a varactor diode are as follows:
on the voltage-variable capacitance are called as varactor diodes. 1. FM modulator.
2. Automatic Frequency Control (AFC) t'n d' .
3 A t · . . ra to rece1ver.
A A . u omabc tuning circuits.
4. In TV receivers • Automobile radios .
Q. 11 Explain construction and working of tunnel diode.
Dec. 14 . Ma 16
Ans.:
K h · "I?e. operation of a tunnel diode is based on a special
c ar_actensttc known as . the negative resistance The
(F-:UI4)Fig. 9.4 : Symbols of varactor diode semtcon_ductor materials 'used for constructing the tunnel di~es are
Gel1llaDlum or Gallium Arsenide. ·

tea easv - so IUIIOIIS

 ~lc Devices & Circuita-l Elex.-Mu
ConstruCtion of a tunnel diOde is . . 4-79
R _ AV..f
F - AIF
AVF is Positive but A lp is negative. Hence Rp is caJJed as a
~egative ~esistance. The decrease in Ip with incr~ in Vp
ts oppos!te. to. the Ohm's law. The negative resistanCe
cbaractenstlcs ts utilized in the applications of tunnel diode
such as oscillator and microwave amplifier.
5. ~egion Z onwards : At point Z, the current starts
m~easiog with increase in voltage. So this is a positive
reststance region and the tunnel diode acts as the
conventional diode.
Q. 13 Draw structure of tunnel diode.
Ans.:
The material used for the construction of a tunnel diode is ·
Germanium or Gallium Arsenide. Fig. 9.7 shows the basic
construction of a tunnel diode:
As doped
ball
Dec. 13. Dec.14.May16
AnS.:
The volt ampere characteristics of a tunnel . . .
in Fig. 9.6(b) and its symbols are shown in Fig. 9.6(~ode ts shown
FOIWard
current IF

Kovar pedestal
<'B-1759) Fig. 9.7 : ConstructiQn of a tnnnel diode
Q. 14 What are the applications of a tunnel diode ?
Ans.: Application of Tunnel Diode are,
- 1. One of the important application of a tunnel diode is in
(a) Circuit symbols of (b) Volt-ampere characteristics of a high speed computers where the switching times of the
·order of nanoseconds or picoseconds are desirable.
taooel diode tunnel diode
2. 'Tunnel Diode is used as an Oscillator .
(B-1760) Fig. 9.6 3. In the digital networks.
4. As a high speed switl:h.
Reverse characteristics : 5. As a high frequency oscillator.
Due to heavy doping of p and n sides, the depletion region
il extremely narrow when the tunnel diode is · reverse biased. Q. 15 Give comparison o' tunnel diode and p-n junction
Therefore the reverse blocking capacity of the junction is lost and . diode.
reverse current will start flowing as soon as a very small reverse Ana.:
voltage is applied. Thus the tunnel diode allows the re~erse
cooductioo to take place for all the reverse voltages. ~ere ~s no
breakdown effect as observed in the conventional rectifier diode.
The:retore we cannot use the tunnel diode as a rectifier.
less than 0.1
Fonrtard characteristics : volts
I. Forward characteristics can be divided into three regions 2. Breakdown It bas a large reverse Breakdown
namely X to Y. Y to Z and Z onwards. y is breakdown voltage. does not take
2. D....c~- X to y .. In this reuion the forward voltage F • Breakdown due to place.
~ • o- · ill take place m avalanche or zener effect
e~mely smaJJ. But heavy con~uctJo~..wthrough the pn Can not block
Conventional diode can
;:;:~~JI~~tr=s ; : : as a resolt of heavy 3. Reverse
blocking block high reverse · the reverse

doping. . oint y the forward

3. Reaiou X
Y to Z : In this regto?• at the forward current 4. Doping
voltaee begins to develop a b~er::; 1·ncrease in Vp· This levels
ltaiU decreasing inspite of conunu eifon. 5. Symbol
region is called as the oegadve. ~~~:mathematically
4. The diode resistanCe in the regJOo to
expressed as,
 Electronic Devices & Clrcults·l (Eiex.·MU) 4-80
due to the "majority carriers" o~ly. No mino~ty carriers :;:'
Q. 16 State actvantligea and disadvantages of tunnel • d · the process of conductton. Due to th1s heavy flow of
diode . mvo1ve 10 • h · ·
. to metal a region gets created near t e JUnc~on surface
.Ana.: e Iectrons m . h
which is depleted of carriers I;" t ~ Sl con. mat~a ·d.~s IS very
·u t · 1 Th' ·

Advantages of tunnel diOde are aa follows, similar to depletion . region m t .ell p-n tJunc .~on ~~ el. These
. ddi · a1 earners in the metal w1 crea e a nega 1ve ayer or
I. Low cost. ·' uon . . f I d .
2. wall" inside the metal at the b.ou~darr. orfmetab an. ;~ID.Jbeconductor
The peak point voll.nge and current ( Vp and Ip ) are not materials. The result of n:Jl thiS ·~ a su are arne tween the
dependent on tempemture. two materials, which prevents any further current. ~en w~ aPPly
3. Tunnel diode needs a small number of external components a forward bias voltage, the str~~gth of tb~ ne~ative bamer wiU
and a de power supply for its opemtion. duce because the external pos1t1ve potential wtll attract electrons
4. It consumes low power. . ~om the p side (metal). Due to this, a heavy flow electrons across
Disadvantages ·the junction w111 begin. This f?rward current can be controlled by
the level of applied bias potential.
l. No isolation between the input and output.
2. Low output voltage swing. So amplification is required. Q. 19 Write short notes on Schottky diode-
characteristics Dec. 07.Dec. 12. Dec·. 15
Q . 17 Write short note on: Schottky Diode Construction
Ans. : The I-V characteristics of a schottky diode is shown in Fig.
Ma 04. Dec. 04, Dec. 07, May 08,
· 9.9. The characteristics of a schottky diode is very similar to that
Ma 11 , Ma 12. Ma 15 a
of p-n junction diode. But it has a very low cut-in voltage (of the
Ans. : order of 0.2 Volts). ·
The construction of a schottky diode is as shown in . . ... . : .
F Oiward ciineni
., ......, ·:·
F~g. 9.&. It is q~te different from the conventional p-n junction . . -··. ; ;
I.

d1ode. A metal semiconductor junction is formed between a metal . t· . ;-

·· · · · . . ·'··j·"·····. - ..
and n-type semiconductor as shown in Fig. 9.8. Eventhough n-type : ~; p-n ll..aion
dodo ; diode
se~conductor . is normally used; sometimes a ·p-type .. ; · __
;
selll_Iconductor JS used. The metals used are molybden!Jm, .. . ... --; - :

platmum, chrome or tungsten. The characteristics for the device .. --- ~-: i
Re~rse !: : FOIWard
will be depende!)t on the technique used for the construction of th~ ~~ ~~~~~~--~~~-'~~~~-----. ~
:... .J..
schottky diode. The metal side ·acts as the anode and n-type i
semiconductor acts as cathode of the schottky diode. ....... ~ .-..~.........;... .

• . 'i . -~-

' ·· Reverse chataci;:~ .,.... ..... .;............. . .

..... .• ....!. ... -~~.~ryt.; - ·~· ·-··-···-···
(B-1662) Fig. 9.9 : I-V characteristics of a S~hottky diode

The reverse breakdown voltage of a SGhottky diode is less

than that of a p-~ junction diode. Typically it is about 50 V as
n-lype silicon Metal semiconductor compared to .150 V f~r a ~-n junction diode. The leakage current in
junction
the.reverse b1ased reg10n 1s higher than that of a p-n junction diode.
Metal contact The _rev~rse leakage current flows due to the electrons in· metal
Cathode(-)
-passmg mto the semiconduclor material.
(B-788) Fig. 9.8 : Construction of Schottky barrier diode
Q. 20 Draw equivalent circuit and circuit symbol of a
Q. 18 Write short note on: Schottky Diode: working. schottky diode :
May 04. Dec. 04. Dec. 07, May 08, Ans.:
Ma 11 . Ma 12. Ma .15
· Anodeo
Ana. : o cat~ode

Inside the metal which acts as the anode as well as inside

the n-type semiconductor which acts as a cathode, "electrons" are
CJ '
the majority carriers. Inside metal, the level of minority carriers Cathode
(a) Approxlotate equivalent circuit
(holes) is not significantly high. When the metal and (b) CirCuit ~boi of a
semiconductor are joined to form the junction, the electrons in n- of ll schottky diode
schottky diode
type material will flow to the metal side. This ·will establish a
heavy flow of majority carriers. Fig. 9.10
Since the injected carriers have a very high kinetic energy, Q. 21 List advantages, disadvantages and applications
compared to the electrons of the metal, they are commonly called of a schottky diode (iMMfJ
as ~bot carriers". Jn the conventional p-n junction the minority
Ana. :
carriers get injected into the adjoining region. But here the
electrons are injected into a region (metal) where eJecuons only are Advantages :
the majority carriers. In this aspect the schottky diodes are different
I. Lo~ on state fo.rward voltage drop.
from the conventional diodes. Jn schottky diodes, the conduction is

ll:t ~. V S IJ IIII J OJI S

 ,

Electronic Devices & Circuits-1 (l;lex.-MU) 4-81

2. Higher speed of switching. These d.

frequencies in the gigahertz (GHz) r~~:s can be used upto
[l GHz =109 Hz}. . · g .
3. Total power dissipation taking place in . .
is less than conventional. diodes. the schottky dtode
[)isadvantages :
1. Low reverse breakdown voltage. th f
inverse voltage) as compared to p'-n ~re ~re lo:-v PIV (peak
JUnctton diodes
2. High leakage current. · ·
Applications :
1. Switching Mode Power Supplies (SMPS). (a) Construction of selenium (b) Array of
2. AC-to-DC converters, Radar systems. photovoltaic ceU photovoltaic cells

Q. 22 Differentiate between Schottky Barrier Dio <F-1034) Fig. 9.12

p-n Junction Diode. · de and

Ans.: Q. 25 What is the basic working principle of solar cell ?

Ma 14. Dec. 15

Ans.:
l. A solar cell is basically a p-n junction device and no
A~K voltage is directly applied across the junction. In other words we
(F-969(a)J (F-969(a))
can say that it is a large photodiode designed to operate as a
"photovoltaic" device and gives as much output power as possible.
2. Forward Typically 0.7 V Between 0 to 0.2 V
The solar cell converts solar energy into electrical energy.
voltage drop for silicon diodes
The construction of a solar cell is shown in Fig. 9.13(a) and the
3. Peak inverse High . (typically ):.ow (typically 50 simplified construction·has been shown in Fig. 9.13(b). Wf! can use
voltage 150V) V) it_.to explain the operation of the solar cell.
4. Leakage Low (in nano High (in
current amperes) microamperes) Ughtenergy
Condudion ~es Conduction takes @ ' ........
5. Carriers
llll r p-type
place due to place only due to · ;.
majority and majority carriers. "-''":". ....c.~-~:::;;...-
h' , _1+--p-n junction
minority carriers. Load j ·.·.-:.r:=> . rift , n-type
Q.23 Give Classification of Optoelectronic Devices.
Ana.: -rEJ dlrectlon of electron flow
rfY direction of hole fl~w
Optoelectronic devices
(a) Construction of a solar ceU
I
l l
. Opto lsOiatorsfoouplers
Space cha:rge
Light detectors region
I l
1 l l
Pholotranslstor Sohircells
LOA Photodlode
p n
photo current
<F·2713) Fig. 9.11 : Classification Qf optoelectronic devices
~~~_j .......
· The ~ptoelectronic: devices can als~ be .classified as
photoemissive, photoconductive and photovoltruc devtces. Photo currsnt
·.................. ......................•
Q. 24 Write a short note on : Solar cell : characteristics
+
I•N••tirnfi•'""•l4M•ti•I4•,.i v
(b) Simplified diagram
Ana.:
The photovol.taic cell generates a voltage across it w~ch is (F-1035) Fig. 9.13
proportional to the intensity of incident lig~t. The phorovoltruc cell
. . w_hen the light strikes the space charge region around the
thus operates on the principle of photovolwc effect. . . .
The construction of a selenium photovoltal~ cell IS as p-n JUnctJO?,. the electrons and holes are generated, due to the
shown in Fig 9 l2(a) and the practical way of connec~mg a nu~ber
photons stnking the valence electrons and imparting energy t0
· · . F. .., 9 l2(b) The selentum them. The optically generated electron-hole pairs are quick!
of &olar cells is as shown JD 1g. · · . 00 sep:uated and sw~pt outside the space charge region (depleti~
Photovoltaic cell consists of a base plate made from 1 ~ or stee.l, regiOn) due to the mfluence of the external electric field.
Which acts as the positive electrode of the cell: A sel~n.JUm lay~rhiS
Placed above the base plate. Selenium lpyer ~~ senslt~ve to bg 18 .t.
Above this, an electrically ·conducting cadmiUm oxide layer
i!ed, as shown in Fi . 9.1 a·
easv- s olutlnns
 4·82
Electronic Devtcea & Clrculta·l (Eiex.·MU)
Pig. 9.14(b) shows how to connect a gr<>U:P of ~lar cells. Seve-;'
These eled:roos and holes now to constitute the ceiJs in series and/or parallel. connected 10 senes to produce the
photocun-ent u shown in Fig. 9. t ~(b). This photocurrent produces required output voltage and . several of these series connected
• voltage V across tbe load resistance Rt_. Thus solar cell supplies groups are connected in parallel to supply the required output
power to the load. .. ·
current.
Q. 21 eq,laln chantcterlatlca of aolar cell and alao Q. 27 State advantages and disadvantages of SOla-;
expWn what Ia the need to connect aolar cells In
..n..
of In pt~rallel fuhlon.
cells.
1\1;~ ' 14. Dec. 15. 1\1;~ 14. Dec. 15 Ans.:
Ana.: Advantages,
1. Th~y respond very well to the incident light over a wide
.n.e typical output characteristics of a power photocell is as range of incident wavelength.
sbown m Fig. 9.14(a).
2. No need of external de source for <>J>eration.
~r-n::-:--,---.----~--~
3. Can produce an adequately large ph_otocurrent.
~ ··-····'-·
Maximum .! _I_ ..
7'0 \ power ; Disadvantages ,
paint ·i·:;i"-" 1. Slow operation. The solar cells cannot change their output
~+--1-'-:-!-.....Y~-r \ft;_f·- 2. ·
rapidly if the light intensity changes rapidly.
Solar cells are temperature.sensitive.
H~~:.:-+-~....J 3. Low output voltage and current.
1:i
COl
a. 28 What are the applications of solar cells ?
Ans.:
Applications of solar cells are as follows,
1. Solar cells.are used to power the electronic circuits used in
satellites and space vehicles.
10 2. Power supply to calculators , for charging the batteries.
3. For powering the cars run on solar eitergy. Typically a car
o~~~==~=t~UIIJD . needs about 8 m 2 of solar cell arrays that can produce 800
0 .1 0.2 0 .3 0 .4 0.5 0 .6 0 .7 v W of pciwer on a sunny day at noon.
OUtput voltage
a. 29 Write short note on : Photodiode.
(a) Typical output characteristics of a solar cell
Dec. 06. Dec. 14. Ma 07. Ma 12. Dec. 13. Dec. 16
Ans.:
: · !fte photodiode is a p-n junction semiconductor diode
which ts. always operated in the reverse biased condition. The

-r
. ~on~trucllon of a photod.iode and its circuit symbols are as shown
m F1gs. 9.15(a) and (b) respectively.
Photona
13--

~. -~-TI
0011-*'d
c.a.
v
..

(b)
(F-1037) Fig. 9.14
(a) Construction of a pbotodiode (b) Symbols of a pbotodiode
2
Wbeo the incident illumination is 100 mW/cm • If the cell
is lbort circuited. then the output current is 50 mA but the output
(B-lOSO)Fig. 9.15
vo~t.a&e iJ zero_ Hence the output power is zero. If the cell is open
cin:ui1ed, then tbe output voltage i.s 0.55 V and the output current is Conatructlon and Operation :
zero. Tberetore the output power is zero. For muxlmum output
.powet', tbe cell nw.&t be operated in the knee region of the The light is always focussed throu
junction of the photod.iode. gh a glass lens on the
charaderiitics, as shown in Pig. 9.14(a). Like other devices the
• utpUt power mu.st be derated at increued temperatures. 't~the photod.iode is reverse biased, the depletion region is·
qut e ' penetrated on both side of the junction as shown in
WI
A photovoiUic cell i.J capable of generating a voltage upto
o.•N aod can supply current In IJ. A range. Therefore in practice
~g. 9.~(~). The photons incident on the depleti~ region will
ampart . etr energy to the ions present there and generate electron
~Yare cooneaed in ~Cries and parallel as shown in Fig. 9, l4(b),
hole.pairs.. The n~ber of electron hole pairs will be dependent on
an order to iooruse their tenninal voltage 311d the current sourcing the mtensaty of hght {number of photons). These electrons and
capability. The ICiies coonec.tjoo inaeues the voltage while
parallel connoctioo will increate the current IIOW'Cing capacity.
L I •. J •. tl Ill I I II II '•
 aectrOnic Devices & Circuits-! (Eiex.-MU)
......- 4-83
bOleS will be attracted towards the positive .
respectively of the external source, to consti:d negative tenninals 3. In the fiber optic receiver.
With in~rease in the light intensi te the photo current. 4. In light intensity meters.
_,..,.trOD bole paus are genemted and th hty, more number of
"""" · e P otocurrent · Q . 32 Give comparison between LED and Photodlode ·
'Jbus cbe photocurrent 1s propoJ:tional to the 1• h . . Increases.
tg t mtens1ty Ans.:
PflOIOdlode Charactertstlcs : ·
The photodiode V~I characteristics
Fig. 9.16(a) and the variation of photocurrent
as shown in Fig. 9.16(b). . WI
:UCth. as .shown in
11ght mtensity is
Sr.
No.
LED .
.
'Pbotodlode.
'
'
..
c
.~

,.
/,

I
l. It is a light emitting It is a light detecting device.
device.
2. Electrical energy is Electric current proportional
VF converted into light. to light intensity is
(Vohs) produced.
3. LED is always forward It is always reverse biased.
biased.
4. GaAs or GaP or GaAsP Silicon is used.
I._(Reverse CUIT9nt) are the materials used.
(IIA)"
5. Due to recombination .of Due to generation of
(a) V-I characteristics of a photodiode
electrons ·and holes, electron bole pairs, the
Photocunent ligh~ is emitted. pbotocurrent will flow:

,.-
(!lA)
6. Circuit s mbol : Circuit symbol :
Anode

·~ Cathode
.

caU,~
(B-2083) (B-2084)
'
(b) Variation of photocurrent with Q. ~3 Write a short note : p-i-n Photodiode .
intensity of light Ans.:
(B-208l)Fig. 9.16 The construction of a p-i-n diode is as shown in Fig. 9.17.
A nearly pu.re (lightly doPed) "n" type of semiconductor layer has
Dark cnrrent : It is the current flowing through a been inserted between the heavily doped p and n layerS.
pbotodiode when there is no incident light on the device.. ( Fig. This layer is called as the "intrinsic"· (pme) layer i.e. "i"
9.16(a)). Dark current flows due to the thermally generated as
layer and the device is"called the p-i-n flhotodiode.
minority carriers, and hence increases with increase in temperature.
The reverse current I (photocurrent) depends only on the
intensity of light incident on ~e junction. It is almost independent
of the reverse voltage as shown in'Fig. 9.16(a). ·
0. 30 List advantages and disadvantages of
~ Swept minority carrier
photodiode. . e--
Ana.: Advantages, . .
L lligb sensitivity : This means, a large change . m . the
. mall change m light
photocurrent will take place fior a s External bias
intensity. . · LDR (Light
2. High speed of operation as compared to ·. (L-831) Fig. 9.17 : Construction of p-i-n photodiode
Dependent Resistor). The intrinsic layer is made thicker so that almost all the
Dlaadvantages of Photodlode : photons which pass through the junction are absorbed within this
1. Dark current increases with temperature. layer.
2. Poor temperature stability· . Operation of p-l·n photodlode :
3 . tial for operatton.
· Extem.aJ bias voltage IS essen t current is of small L The light which is to be converted into electric signal is
4. Amplification is required, as the outpu · made to fall on the junction of the photodiode. The
magnitude. I!MMII photodiode is reverse biased.
Q. 31 State application~ of photodlode • · 2. Photons enter the depletion region and encounter with the
atoms within the depletion region, They generate electron-
An . . . t.odi.ode are as foiJows,
a.. Applications of pho . b'ect counting hole pairs inside the depletion region.
I· h0 todiode IS an 0 ~
Popular application of the P
system.
2. In the cameras for sensin
r: :t S V · S IIIIIIJOJI S
 4-84
Electronic Devices & Circuits-! (Eiex.-MU)
te p-1 n and avalanche photo diodes .
3. Due to the reverse voltage applied across a photodiode. a. 35 Dlfferentla •
these electrons and holes are drawn across the junction and
leakage current proportional to intensity of incident light
starts flowing. Thus light is converted into electric current.
4. Due to wider "i" layer, a more complete absorption of
photons takes place and a larger photocurrent gets
l.
Construction -rm:G-
produced. The sensiti_vity of p-i-n photodiodes is therefore (L-835)
higher than that of a p-n junction diode.
s. Due to the addition of ''i" layer, the electron-hole pairs
Biasing
Reverse Reverse biased
generated due to photons have to travel a longer distance. 2. biased
Hence p-i-n diodes are slightly slower than the p-n junction
diodes. Higher Very high due
3. Sensitivity
than p-n to ·avalanche
Q. 34 Describe construction, working and characteristic
of avalanche photodlode. Dec. 13. Dec. 16 photo effect.
Ana. : The construction of an avalanche photodiode is as shown diode but
in Fig. 9.18. It has a p-i-p-n structure. Light enters through a thin .lower
"n" layer which is heavily doped.
than
APD.

4. Dynamic·response Slower Slowest due to

than p-n increased
photo transit time.
diode b~t

faster
External bias
(L-832) Fig. 9.18 : Construction of avalanche photodiode than
APD.
Operation of avalanclie photodiode :
1. As negative voltage applied to the diode is increased, the 5. Avalanche Multiplication Absent Present
intensity of the internal field increases proportionally. 6. Noise in the output Very High due to
2. The internal field intensity then reaches a threshold so that
the electrons which are being accelerated . through the low random
junctiqri region will generate secondary eleetron-bole pairs fluctuations of
due to collision. avalanche
3. The number of carriers generated in this manner will
generate many more electrons due 'to collisions. This is multiplication
called as "avalanche effect". · factor
4. In avalanche pbotodiodes, the electrons generated due to
the light are accele~ and made to pass through the Q. 36 Write short note on : LED construction, working.
junction region. They give rise to avalanche effect and a Dec. 04. Dec.09
large current starts flowing through the device. .
Ans.:
5. Due to the avalanche effect a sort of "current
amplification" takes place inside the device to yield a much An LED emits light when electrical energy is applied to it
higher current. Thus the sensitivity of this device is much The construction and biasing of LED is as shown in Fig. 9.20(a)
~~ .
higher than that of a p-i-n diode.
6. The p-i-p-n structure helps to concentrate the internal field
·near the junction in a better way. ·
Frequency response :
Silicon p-i-n and avalanche diodes typically h~ve a
. frequency response that extends from about 0.6 J.l.m to about 1.2
J.UD as shown in Fig. 9.19.

o.e

0.4 (a) Construction (b) LED biasing (c) Circuit symbol

and principle of .. ofLED
operation of a
LED
, Wavelength ).o(J.IIT1)
0. 1.
CL.&Jl) Fig. 9.19 : Spedral response of pin and avalanche diodes (F-1039) Fig. 9.20
ea s v SOIUliO IIS
e~nic Devices & Circuits-! (Eiex.-~)
P# ,uvctlon of LED : 4-85
COf1 1be construction of LED is same as th
·conductor diode and the LED is operated . at of a p-o junction
::on asTbeshown in Fig. 9.20(b). R is the CUrren~ :~rw~ biased
LED operates on the Principle Wbi g reststor.
l. Gallium Arsenide ( Ga As) Infrared (IR)
recombination of electrons and holes tak cb states that when 2. Ga AsP Red or Yellow
~eased in the fonn of light. One of the po~lace, an energy is
re sUUction 'is to deposite three semiconduc methods of LED 3. Gallium phosphide (GaP) Red or Green
~..-.H>. as shown in Fig. · 9.20(d). The t?r laye~ on the Q. 37 What are the advantages and disadvantages of
su~-- d . . Th active re,on .
~n the p an n regiOns. e light emerges fro o • . eXtsts LEOS?
n ooi... rec
.10 all the directions when electron hole ..,....., mb. the active side
om me. Ans.: Advantages of LEOs are as follows ;
~ 1. LEOs are of small size and light weight. Therefore it is
. possible to pack a large number of LED, in a small space
while manufacturing a display.
2. They are available in different spectral colours.
3. They have longer life as compared to the lamps.
(o~~,.....,,.,.~~.,..-.1 } l\ctive region Disadvantages of LEOs : '
~""'~~~ri:t~-n'"fegion
1. ' Output power is affected by changes in temperature.
2. Over current can damage it easily.
Substrate
3. They need larger power for their operation.
<F-1040) (d) : Construction of LED
Q . 38 State applications of LED Dec.04. Dcc. 09
Fig. 9.~
Ans.: The typical applications of LED are :
Principle of LED Operation : l. In the optocouplers.
When the LED is forward biased, the electrons in the n- 2. In the infrared remote controls.
regioo will cross the junction and recombine with the holes ui the 3. As indicators in various electronic circuits.
p-type material. These free electrons reside in the ·conduction band 4. In seven segment and alphanumeric displays.
and hence at a higher energy Level than the holes in the valence Q. 39 Differentiate PN Junction Diode and LED .
band. When the recombination takes place, these electrons return
back to the valence band which is at a lower energy level than the Ana.:
conduction band. While returning back. the recombining electrons Sr. Parameter PNlunt!ttOil· ~ _"\ LED
give away the excess energy in' the fonn of light. This is shown in No Dlbde' . - ~
Fig. 9.2L. This process is called as electroluminesceoce. In this l. Symbol //
way an LED emits. Light. This is the principle of operation of LED. o---{>f------o
.. .. ........ ...... ...... ....... . .... ~
..... .. ::i.b~J~~J~
.i:=~~ii~: ~J ~ ~ ~ ~ 11 ~ .~
......... ............. (F-1048)
(F-1049)
-
Forbidden! Z • Ught output 2. Material used Silicon or Gallium Arsenide
energy gap Germanium
~~--+-~~~~------
-.~~1
'< 3. Capacity to Cannot emit light Can emit light
·.'·~Cl emit light when excited
Valence band electrically.
Recombination
of hole and electron 4. On state 0.7 V for silicon Ranges between
Fig. 9.21·: Principle of operation of LED voltage drop diode 0.3 V for 1.2 to 2 Volts
germanium diode
Colour of the emitted light : . clec"ded by its 5. Reverse High Very low
• ted l"ght IS 1
1 bre~down
The colour of the ellllt . • ererit materials are as
wavelength. The colours associated wtth diffi . voltage
follows. Applications Rectifier, clippeJ:, As a light source
6.
damper etc. in optical fibre
applications. As
indicator, in 7
segment displays.
 Electronic Devices & Clrcults-1 (E:Iex.-MU) &:::

Q .• 1 Draw the block diagram of regulated power

Chapter 10 : Rectifiers & Regulators
at.q)ply.
<B-163) Fig. 10.1 : Block diagram of a regulated power supply
Q. 2 Oeftne rectlfter and rectification.
Ana.: ~edification .is the process of converting the alternating
~tage or current mto the corresponding direct {de) quantity
(direct voltage or cw:rent).The input to a rectifier is an alternating
(ac) voltage whereas 1ts output is unidirectional or de voltage.
1be electronic circuit which carries out rectification is
called as rectifier. Rectifier is an electronic device which is used
~ ~~ning an alternating (ac) voltage or current into a
unidirectional (de) voltage or current
8. Hence the diode is forward biased and starts conducting. As the
diode starts conducting, the secondary voltage V AB appears almost
-
as it is ·across the load resistance (as the voltage drop across a
conducting diode is very stnall).
The load voltage is thus positive and almost equal to the
instantaneous secondary voltage V AB' ·The load current has the
same shape as that of the load voltage since· the load is purely
resistive. The waveforms for HWR are . - shown in
Fig: 10.4. The instantiuleous load current i1- is equal to the ratio of
instantaneous secondary voltage (VAB) and total resistance (Rg + Rp
+RJ.
VAB
IL = (R +Rp+RJ ...(l)
8
Operation in the negative half cyde of ac supply (11: to 2,.;) :
In the negati,ve half cycle of the ac supply (1t to 2n),
secondary voltage V AB is· negative, i.e. A is negative with respect
to 8. Hence the diode is reverse biased and offers a very high
resistance. Hence we can replace it by an open circuited switch.
The load is disconnected from the secondary. Hence the
load voltage and load current both are iero and the voltage across
the diode is equal to the instantaneous secondary voltage VAB· The
waveforms are shown in Fig. 10.4.

Q. 3 Claaalfy rectifiers.
Ana.: .
1be classification of rectifier configurations is as shown in
Ftg. 10.2 . . .
Aacafter clrcul18

tW Wow Railer (HWR) Ful Wave R9cllfler (FWR)

FWR with oenter FuR wave bridge

tapped tnmlllormer roollfler

(B-88)Fig. 10..2 : Classiftcation of rectifiers

Q. 4 Explain the operation of Half. Wave Rectifier

(HWR).
Ana.:
. In balf wave rectifier, the rectifier is on only during one.
half cycle of the ac supply. So output is produced only in that half
cycle. The output is suppressed (zero) in the other half cycle.
0

T1
(Input transformer)
8

<J-1') f1&. 10.3 : Half wave reedfter <B-91) Fig. 10.4 : Waveforms fo~ the HWR

Operlllort of IN HWR : 0.5 Derive ILdc • VL rma .IL rma ,Vt.Ato , RF , PLdc p and 11
ofHWR. · ' .c
Opendoe la the polltlve ball eyde of~ supply '<O-n) :
.. half . ~ycl.e. (O--n>, of ~e ac supply, the
wrond•In vthe posiUve.
ry oltage VAll 111 JlOSltive. t.e. A 1s pos1t1ve with respect to

lit I :t ' \.1 ', II I II I I II t1 •,

. ~ronic Oeyjces & Circuits-! (Eiex.-MU)
4-87
Ana.: HWR:
1/2

*{
·1• DC or A verkge Load Current (ILd ·\ • By d fi ..
1
average value of a periodic fun . ~ •
ction ts gi
e nttion the
b
under one cycle of the functio di . ven Y the area = ; [ n; -!sin 2n;) J
(period). Considering one n rl(;led by the base But sin 2rc =0
O>t =0 to rot =27t of the load c comp ete cycle from
Fig. 10.5. . . urrent waveform shown in = I,.
2
...(6)
4. AC or RMS Value of Load Voltage (VLnat): Since the
load is purely resistive, the rms value of load voltage is
given by, .

= ILnnsxRL = 2I.n xRL

L This portion of load current wavefonn vm ... (Exact)
ts
Itself. So oonslder It for~latl rapea
average and rms value. ng But {Rg + Rp) <« RL
vm
T ...(Approximate)
• <B-93>J!ig. 10.5 : Load current waveform • • VLrms= . .. .(7)
7t 5. Ripple Factor (RF) : The rectifier output consists of AC
' 1 _.
.. lav = IL de = 27t J~ sin rot drot =~
0 27t
[cos rot]
.
11
0 •••
(
1
) •
as well as DC components. The ripple factor me3sures
percentage of AC component in the rectifier output.
Ripple factor is denoted by "r'•.
where, Im = Peak amplitude of the loa4 current Ri · RMS v~ue of the AC component of output
-I, . . -I, PP1e fac~r = . DC or average value of the output
.. lUc = 271; [COS1t- COS 0) = 2
7t [-1-ll 112

.. Iuc = -;
I,
...(2) . [V~nns- V ~de ]
r=
.
VLdc
v Substituting the approximate values to get,
where, Ia. = Rs + R; + ·~ , it is the peak load current 2 2 112
[<Vm/2) :... (Vm/1t) ]
~ = Di~ forward resistance,
Rs = Transformer secondary·resistance r = Vm/1t
· V m = Maximum or peak secondary voltage r = 1.21 or 121 % ...(8)
2. DC or Average Load Voltage (V...J : As the load is 6. DC Output Power PLdc : The de or average output power
purely resistive the average load voltage is given as : delivered to the load is given by,
2
VLdc = Il.dc x ~ ... (3) · • [I.n]
Pl.dc = ~ xRL = -;
2.
RL ~ .1t
-ll! RL
r ...(9)
Silbstituting the value of Il.dc to get, .
Substituting the expression for ~ to get,
VLdc· = I,xR
7t L
· v2 . .
= v
xRL ...Exact ...(4)
7t( Rs + Rp + RJ
· v2
Usually Rs and Rp are.small as compared to RL If RL » (Rg + Rp) then, P =~
Ldc 1t~L

.. <Rs+Rp+RJ == RL ·v2
Hence Equation (4) can be approxiiJlated as, But V.Jrc = Vl.dc, Pl.dc"'~ , ..(10)
L
~: . AC Input Power (P.J : Th.e ac input power to a rectifier
VLdc "" 7V ...Appro~
m .....t.. .. .(5) 7.
is the power supplied by the seconrulJ:y winding ~f the
where V =
Peak secandary voltage . transformer. It is given by,
3. , AC or RMs
Load Cun:ent (IL em) : Considenng ~b~ Pac = . Isnns x(R8 +Rp+Rd
2
...(11)
complete cycle of the load current waveform (0 - n; Where I.mu =RMS value of the secondary current
shown in Fig. 10.5 , l/2 For a HWR, the secondary current is same as the load

~llDI [in j I~ dolt] current. Hence RMS vatue of the secondary current is same
as the RMS value of load current.
= ;in' rot
Im
..
= [ ~1c~ oo;z )do'l
0 1/2 I.nns = ILnns = 2 ...(12)
2

OlJ_ ... Pac = ( ; ) (Rs+Rp+RJ

 Electronic Devices & Circuits-! (Eiex.-MU)

·r' 2
= 4m <Rs + Rp + RJ ... (13)
a. 10 Where are HWR are used ?

Ans.:
-
4-88

. A HWR is used in the eliminators for pocket radios ·or

8. Redifkation Efficiency or Power Conversion eliminators for walkman or in the low cost power supplies.
Efficiency :
Rectification efficiency is defined as, step down transfonner having turns ratio 10 ;-;
a.11 A
DC output'power Pl.dc and input 230 V, 50 Hz Is used In 8
'll = .AC input power = Pac half-wave rectifier. The diode forward resistance
Substituting Equations (9) and (13) to get, Is 15 ·o hms and reslsta.n ce of secondary winding
2 2 Is 10 ohms. Fo.r a load resistance of 4 k-ohms,
'll = :z . ~oc RL =__<.;.,}n~'n...;.)_R....:L::.-_ calculate average and rms values of load current
Is rms (R8 +RF + RJ ( ~ /2 ) ( Rs + RF + RJ and voltage, rectification efficiency and ripple
4 Rr factor.
=·;( (Rs+Rp+RL)
Ans.:
If~ >> <Rs + R.,), then we get the maximum rectifiCation Given: N1 / N 2 = 10, Vin ·= 230 V, RF = 15 .Q, Rs = 10 Q,
efficiency as, · ·
4 RL =.4 k.Q, Circuit : HWR.
'llmax = ;? = 0.4 or 40% ... (14) To find : Il.dc, I~..nns, VLdc' VLnns' 11 and ripple factor.
Q. 6 Define : Voltage Regulation . . l.Rms secondary voltage
. N2 . 230
Ans.: v. = 230xN
I
=23V. =w
Voltage regulation is defined as :
Peak secondary voltage
Voltage regulation =
VNL....:.VFL
V . x 100 %
FL
.
2.

3.
Vm = ....{2 X
Average load current ·
v> ....[2 ?< 23 =32.53 Volts
Where , VNL = . Average load voltage at no
load i.e. when RL ::: ~·
vm
ILdc = 1t (Rs +RF + RJ
vm
·· VNL = 1t .. . (ForaH.W.R) 32.53
10 + 15)
1t (4000 .+
a. 7 Define Transformer Utilization Fac;tor (TUF).
=
3
2.57 x 10- A or 2.57 mA •••Ans.
Ans.:
~ vm
The transformer utilization factor (TUF) indicates how well 4. Rms load current ILnns = 2 2 (RL +Rp + Rs)
the input transformer is being utilized. It is deflned as the ratio of
de output power to the ac power ratings of the transformer. 32.53 .
TUF iS defined as : ··
= 2 (4000 + 10 + 15) =4.04 mA ••.Ans.
5. Average load voltage VLdc = ILdc RL
TUF _ DC output power (P.,J
- A C. power rating of the transformer =. 2.57 x w- 3 x 4 x to 3
. VI"' lx 4c = 10.28 Volts •••Aos.
= Vsrmsfsrms 6. = =
Rms load voltage VLnns ILnnsRL 4.04 X 10- x 4 X 10 · 3 3

a. 8 Define Peak Inverse Voltage {PIV} • = 16.16 Volts •••Aos.

7. Rectification efficiency
2
Ana.:
PIV is the maxi.mlim. negative voltage which appears across 'll = 2 ~oc RL
a nonconducting reverse biased diode. In HWR , the maximum .Il.fms ~+ Rs + Rp)
negative voltage across the diode is -Vm Volt, when the diode is = . (2.57x 10-?x4 X IQ3
not conducting. · · ·
(4.04 X 10- 3) 2 X 4025
.•. PIV = Vm Volts = 0.4021 or 40.21 % ••.Aos.
a. 9 State advantages and··disadvantages of Half Wave · - V )
[V
2 2 112
[(16. 16)2 .:_(10.28)z.,tn .
·Rectifier • · 8. . Ripple factor = 'm• '4s J
. VLdc = 10.28
Ans. : Disadvantages of HWR are , = 1.2129
. or 121.29 % ••.Ans.
1. Ripple factor is high (1.21). Q.12 Explain 1he operation of full wave rectifier and-
2. Low rectification efficiency (40 %). draw the output waveforms for V and I
:3. Low TUF (only 28 %) which indicates that the transformer Ldc Ldc •
is not being used effectively. Dec. 09. Ma 10
Advantages of HWR Ans.:
1. Simple constivction. The_ full . wave rectifier configuj:ation is as shown in
2. · Less number of components are required to be used. Fig. 1.0.6. It conststs of a step down center tapped transformer 'I\,
3. Small size. two diodes and a purely resistive load RL.

£!~1 $ \1-SOIIII!OIIS
-
Electronic Devices & Circuits-! (Eiex.-MU) ·

. Q. 13 Derive expressions for lm ' IL de'

4-89

vl.dc. IL rme. vL.....

L ,RF,PI.dc. Pac: and TJ for FWR•
1+ 'v
2SOV,AC ·· Ans.:
N
·1. Peak load current lm
...(1)
Peak load current, I., = (Rs + RF + RJ
where, Vm = Peak secondary voltage for half the
(B·97) Fig. 10.6 : Full wave rectifier
secondary (OA or OB).
In the HWR the load current flows in 0 1 h
the supply but in the fuii wave rectifier it fl~ ':\o:- ~cleof
Rg = Resistance of half the secondary
cycles ofac supply. · e half (OAorOB)
RF Forward resistance of a diode.
operation of FWR :
2. Average Load Current (t de) :
Operation in the ~tive half·cycle (0 -n) :
In the positive· half cycle of ac supply v .8 . . . d Load
. . • AO 1 posttive an current
v80 is negative. Due to the centre .t apped secondary v dV
· ' AO an BO
are alway~ equal and o~postte to each other. Hence diode n is
1
forward btase<l; and D 2 Is reverse biased. ·The load current starts
flowing from A, through D 1, load resistance RL back to point 0.
_The instantaneous load voltage is positive and.
approXlDlately e<_IUal to V Ao· As the load 'is purely resistive, the
·This portion of load current waveform repeats
load current iL has the same shape as that of the load voltage. The
itself. So consider it to calculate
voltage and current waveforms are as shown in Fig. 10.7. average and rms values. •
Operation in the negative half cycle (7t - 2 n) :
(B-102) Fig.,10.8: Load current for FWR
In the negative half cycle of the ac supply, VA~ is negative
and V80 is positive. Hence D 1 is reverse biased and D2 is forward Considering the load current waveform extending from 0 to
biased. So D 1 acts as an open circuited switch and D 2 carries the 1t because this portion repeats itself again and again.
entire load current. The direction o~ load current ~ is same as 1t .
that in the positive baif cycle. That means even in the negative
half cycle, the load current continues to be positive. The
J
. . Average load current IL de = ~ I., sin rot dc.ot
.- 0
instantineous load voltage vL ·is positive and almost equal to
I., 7t
VIIO. -; [-cos c.ot ]
0
Wavefonns : . -I.n -I.n .
The voltage and c~rrent waveforms are as shown in Fig. 10.7. -[cos1t-cos0] = - [ - 1-1]
1t ·" 1t
21...
1t ...(2)

where, ~ =
vm
(R8 +RF+RJ
·3. Ave~age Load Voltage (VuJ :
As the load is purely resistive, the average load voltage of a
full wave rectifier is given by,

Diode
VLde =
ILde X RL
oonent lp1 Substituting the value of IL de to get,
1&£~~":--~-IT.~T"":S.-:---"'' ~
VLde := 1t X RL
Substitute the value of I.,. to get,
2V
VL de = 1t {Rg + R; + RJ X RL ...(Exact) ...(3)

=
n[l + (Rs;LRp)J

t Assuming that ( R 8 + RF) << RL to get,

... ' . ... · ·· ···· ·iv L;;w·· · .
Vu, =·
ZVm
1t ... (Approximate)
d rrent waveforms
. ' - m .•.(4)
<a-tot) Fig.10.7: Voltage an cu
for a toll wave rectifier

ea s v- s olntton s
 Electronic Devices & Circuita-l (Eiex.·MU)
4. RMS Load Current (IL ~ : ·
Considering the load current waveform(Fig. 10.8)
Substituting the value of lm to get,
Vz (Rs+Rp+RJ V
2
-
. 4-90

.
• . ...(9)
pK .. 2m(Rs + Rp + Rj i = 2 (Rs + Rp + RJ

~:.[~y:.~ ;:r~J:~~:~r· 9. RectHier Efficiency :

=[ fJ (l - cos2oK)don r 112
As,

= -~[*(rot)~- 2~(sin2rot) ~J
112 . ' • 11 = (Irrf\lil (Rs + Rp + RJ
=
I,. [ 1
...f2 ; 1t- 2n1 <O> J I,.
= ...f2 ...<s> 8 R1 ..:(10)
.. 11 =n2 <Rs + Rp .f. RJ
Compared to HWR, the value of IL mu for FWR is higher by This is the required expression for rectifier efficiency.
20.7%. Assuming (Rs + Rp) · << RL we get, the maximum value of
5. RMS Load Voltage (VL mJ : efficiency to be,
'The nos value of load voltage is given by,
· = ~ =0.812 or 81.2% ...(11)
VL,_ = llrma X RL 11max 1t
. '
I,. a. 14 Give reasons : PIV of a FWR with cent~
:. VL,...= ...[2 X RL
. transfoJmer Is 2 Vm· II!Bi1l
Substitute the value of I,. to get,
y. Ans. :
m X R To obtain the value of PIV, referring Fig. 10.9, which is
VLIDII = "\{i(Rs+Rp+RJ L
:th~ equivalent circuit of FWR in the positive half cycle.
VMJ
... (Exact) A o1 oN
Assuming {Rg + Rp) « Rv

6.
~
vL,.,. = ...[2
Ripple Factor (RF) :
·...<Awroximate>

2 2 112
...(6)
0~+ ~A
· [VLnns- v Lde] 1---vBA-...j
Rippfe factor {RF) = VL de e I $
Peak value ol
Substituting the values to get, · VIlA 1& -2Vm
112
( (V Mi - (2V m/ 1t)2] . [1t2 ]112 (B-103) Fig. 10.9 : Peak inverse voltage for FWR
RF= 2Vdn 8 -_1 Diode D1 is conducting and it is assumed to be equivalent
to a closed switch. Let us obtain the PIV of D 2 which is no~ OFF.
= 0.48or48% ... (7)
Fig. 10.9 shows that in the positive half' cycle (0 - ~) the
7. DC Output Power (P~ :
instantaneous voltage across D 2 is V BA· As shown in the
The de output power is given by, wavefonns the mllximum negative value of V BA is - 2Vm·
PLde = (de X RL .. PIV =
2 Vm Volts
21,. vm
Substituting , ILde = n and Im =-Rs+ Rp + R1, to gc::t. Q .15 State advantages, disadvantages and applications
of Full Wave Rectifier .
2
4V Ana.:
.. PLde = 1?(Rs+R:+RJ2 x RL ...(8)
Advantages :
1. AC Input Power (P80) : 1. Low ripple factor as compared to HWR
The ac input power is given by, 2. Better rectification efficiency
P~ • J; lllll x (Rs + Rp+ RJ
2
3. Better TIJF
Disadvantages :
= [ ~] x(Jts +Rp+RJ 1. Since PIV of the diodes is 2 Vm' size of the diodes is larger
and they are more costly.
I; (Jts +R,+RJ Cost of the center tapped transfonner is high.
p~ = 2 2.

1: :1 '. \1 ', II I II I ! II II ~.
 ~rontc Devices & Ctrcuits-1 (Eiex.-MU)
4-91
APPlications of FWA :
}.
Laboratory power supplies. OperaUon of the Bridge Rectifier :
2. High current power supplies. 1. Operation in the positive bal( cycle (0 !: c.ot !: n) :
3. Battery chargers. .
In the positive half cycle· of the ac supply the secondary
4 Power supplies for various electro . . . voltage VAD is positive. Therefore diodes D 1 and D2 are
..:-- mc cJrcwts.
a. 16 A full wave rectifier Is used employing . ·forward biased whereas D3 and D4 are reverse biased. The
1. Centre tapped transformer • reverse biased diodes D3 and D4 act as open switches. The
2. Bridge configuration. • load current and load voltage both are positive as shown in
To give an output of 9 v peak f the waveforms iii Fig. 10.11.
50 Hz supply, compare the tw rom 220 V AC, 2. Operation in the negative half cycle (n !: cot!: 2n) :
reference to the rms ou ut c 1rcults with
transformer turns ratio
voltage to be o 7 Volts 0' 1
•
0
A:
voltages and
.ume diOde cut-In
• scuss relative me Ita 1
In the negativ.e half cycle of the ac supply_the secondary
voltage V AB becomes negative. Diodes D3 and 0 4 are
forward biased and start conducting. 0 1 and 0 2 are reverse
the two configurations · r o biased , hence do not conduct. The waveforms of the
. 1
-·14••!1
Afl$.: bridge circuit are as shown in Fig. 10.11.
Given : Peak output voltage V 0 {peak) =9 v;
Primary voltage =220 V . rms
1. Centre tapped trausfonner FWR :
= 9v
v o (pelk)
:. Peak secondary voltage (112 winding)
= 9+0.7 9.7 v =
RMS secondary voltage
= 9.7 VI =6.86 V~lts.
Vl
. . NJ 220 .
:. Transformer turns ratio : N = .86 = 32
.
6 . 2 .
The ratio is of primary to half the secondary. Hence the
ratio of primary to full secondary is 64. · · ·
l Brid~ rectifier :
vo(pcat) = 9v
:. Peak secondary voltage = 9 +. (2 x 0.7) =10.4 V '
.. RMS secondary voltage = 10.4 ·v r./2 =7.35 V
N 1 220 ·
.. Transformer turns ratio = ~=7.35= 29.91 .••Aris.

Q. 17 Explain bridge rectifier circuit. IMfi•€1 (B-109) Fig. 10.11: Waveforms for the bridge rectifier

Ani.: . Q.18 Whatarethe advantages of bridge rectifier ?

The circuit configuration o{ bridg~ rectifier is as sbo~ in Ans.: The advantages of bridge rectifier are as follows,
Fig. 10.10. It consists of four diodes c_?nnected ~ :rm~r::=~ I. It requires a smaU size transformer. Center tap transformer
The center tapped input transformer ts not reqwr · is not required. This ·makes the bridge rectifier cost
transformer T shown in Fig. 10.10 is a step down transformdert.
. I tifi ti The diodes con uc effective.
B
. ridge rectifier offers full wave rec. ca on. · of diodes either 2. High average output voltage
1D pairs i.e. at any given instant of tune, one patr
3. Rectifier efficiency TJ is high
DJ D2 or D3 D4 will be conducting. · 4. Transformer utilization factor TUF is high.
Q. 19 State disadvantages of Bridge RectHier.
Ana.: Disadvantages of bridge rectifier are as follows ,
1. The number of diodes used is four instead of two for FWR.
2. As two diodes conduct simultaneously, the voltage drop
across them increases and the output voltage reduces.
a. 20 List appllcaUona of B.rldge Rectifier •
Ana.: Applications of bridge rectifier are as follows,
1. Laboratory de power supplies.
tiller ctrcult 2. High current power supplies.
(8.107) Fig. 10.10: ~ brid&e rec ·3. Battery charger.
4. DC power supplies for various electronic circuits.
 Electronic DeVICes & Circuits·! (Eiex.-MU)

Q . 21 Give compariao~ .of HWR , FWR and

rectifier. ·
Bridge 3.
AC input power,
Pac == 152rms X (R5 + 2Rp + RJ
2
-
4-92
I

Ana.: .- (1,.1..J2) (Rs + 2Rp + RJ

-3)2
·The com~son of the three rectifier circuits is as foiJows,
.. i 20·2 X2 lO X 2012-- 410 mW ...(5)
Pac ==
' Sr. ' .. ~ter .· lJWR . FWll .Brldae :·.•
- No. ., .
.. ··/ l
J'eCtHiet .:·
.. % efficiency =
~
p
liC
X
331
100 =410 X 100 = 80.73 %••.Ans.
I. DC or average I,. 2 lm !1m
load current (IL de) Vm- Ve.

2. Maximum average
load voltage VLde ·
vm
1t

1t
__
2Vm,
1t

1t
2Vm
1t

1t
4. % regulation == V
FL
X 100

2Vm ~ 2 X 40.65 25 .87 V

1t - 1t ...(6)
VNL ==
-3 13
3. RMS load current I, 1m
Im
VFL == ILde X RL =12:86 X 10 X 2 X 10
ILnns 2 ~ ~ 25.72 v
= ...(7)
4. RMS load voltage Ym
'2
vm vm
~
.. % regulation == 7
i;
25·8 ; 5 ·72 x 100 = 0.5832% ...Ans.
VLnns ~ -
2
5. DC load power pde 12 41 R 2
41 R-L Q. 23 What is a filter ?
: : RL ~ Ans. : Filter is connected after. J]Je rectifier to obtain a ripple free
1t ~
1t or pure de voltage whereas voltage regulators are used to deliver a
6. Maximum 40 % 81.2% 81.2% constant d.c. voltage to the load. ..
rectification · Q ; 24 What are types of filters ?
efficiency (11)
Ans.: Filters are classified depending on the components used'and
7. TUF 28.7% 69.3% 81.2%
depending ·on the configuration in which they are
8. Ripple factor 121 o/~ 48% 48%
connected. The important filter types are as follows :
9. Ripple frequency 50Hz 100 100Hz
Hz 1. Capadtor input filter (shunt capacitor filter)
Two Four 2. Choke input filter (se!ies inductor filter)
10. Number of diodes One
used 3. LC filter
4. 1t type filter.
Q . 22 A bridge rectifier Is applied with input from a step
5. RC filter
do~ transformer having turns ratio 8:1 and input .
230 V, 50 Hz. If the diode forwar(J resistance is Q. 25 Draw a circuit diagram of a f ull wave reetlfler wtth
1 0, secondary resistance is 1~ Q and load C filter. Derive expression for ripple factor and
resistance connected Is 2 kQ find : also explain the basic rectifier operation.
1. DC power output Dec. 08. May 10, May 11
2~ PIV across each diode Ans::
3. % efficiency T~e capacitor input filter ·is used to reduce the ripple
4. % regulation at full load. con~ents· m th~ output oi a. rectifier to obtain a pure de voltage. A
full wave rectifier along Wltb a capacitor input filter is as shown in
Ana.: -
Fig. 10.12."C" is the filter capacitor which is connected across the
Giyen : ~oad· resistapce R.
C<tnllttoe> IIIIP
(a) RMS secondary voltage, down trllnolormot .. -~v
-o:
(..· ·~ -.§.)
A.
1 ...(1) . ,..,_ L _Q_
V5 rms = gX 230 = 28.75 V N - 1 5 Z4tN, "'II .

(b) Peak secondary voltage,

Vm = ..J2 V 5 nns = -{2 X 28.75 = 40.65 V ...(2)
(c) Peak load current,
(a) Connection of filter (b) FWR witil capacitor input
vm 40.65
20 2 ...(3)
lu, = <RS + 2Rp +RJ = .(10 + 2 + 2000) = · rnA capacitor filter
(d) · D.C. load current,
(F-1093) Fig. 10.12
ILdc = 21m = 2 X 20.2 - 12.86 mA ....(4)
1t 1t
!be fil~r capacitor is connected ·across (in shunt with) the
1 D.C. load p<)wer, load, this filter ts called as shunt capacitor filter.
2 -3 2 3
PLdc = ~dcxRL=( 12.86xlO ) x2x10
= 331 mW ...Ans.
2 PIV across each diQde = Vm =40.65 V •••Ans.

eas v -so luJtons

 r:rectronic Devices & Circuits-! (EI
"'
.......- ex.-M U)
operation of FWR with a Shunt Ca 4-93
Fig. 10.13 shows the waver. P&cltor Filter :
various intervals have been shown. ~rm ~ load voltage with th
0
.
V perauon of the FWR w·th e c~acttor filter. Along with the waveforms the equivalent circuit:> for
1
o capacitor filter is given in four different intervals.
Voltage
across C or load voltage

l
Cctwges
0-A throughD2
Ccharges
through o1
c discharges
o--+--...J - through RL

A-B
(F-l094) Fig. 10.13: Load voltage wavefonn and equivalent circuits ofFWR with a capacitor filter

OperatiOn in the interval 0 to A :
The initial voltage on capacitor "C" is assumed to be zero.
IIi the first positive half cycle of the supply, D 1 is forward biased
and starts conducting. 0 2 is reverse biased and acts as an open
switch. Diode 0 1 supplies for the charging current of the capacitor
and the load current.
Capacitor starts charging through D 1 and at the end of this
interval i.e. at "A" it charges to the peak value of secondary
voltage i.e. "Vm".
:. At "A", voltage on C i.e. V c = V m
After point "A" the instantaneous secondary. voltage s~s
reducing as shown by the dotted wave~onn of rectifier ~~t~.ut tn
Fig. 10.13. This will reverse bias the diode D 1• hence a~ A • ~e
diode D is blmed off. The equivalent circuit for this mterval IS
1
shown in Fig. 10.13.
diode 0 2 starts conducting at instant B. The capacitor charges
through 0 2 and at the end of this interval i.e. at point "C", the
voltage on capacitor is again equal to +Vm· Due to this D 2 is
reverse biased and stops conducting at point "C" as shown in
Fig. 10.13. The equivalent circuit for this interval is shown in
Fig. 10.13.
Operation in the interval C to D :
The pperation in .this interval is identical to that in the
interval A to B.
Expression for the I.Upple Factor :
To obtain the expression for ripple factor of the output
voltage using a capacitor filter, refer to the two waveforms drawn
in Fig. 10.14(a) and (b). To simplify the mathematics , assuming
that ripple has a triangular shape.

Operation in the interval A to B : OutpUt

During this interval voltage on the capacitor is higher than voltage
. ' · ) H nee D and D both
rectifier output (shown by dotted lines · e . 1 2 ·..,._ Reotlfler
remain off. The capacitor discharges exponentially through the \.,_ OU1put
load resistance Rr_. . ~~·· .
her than R the capacttor Q•L-~~T
~,~.:~,---T-2~~:~~--~----------~----.
dischar
A$ the value of RL is roueh hig . "R
1 1 o· h o1ng time constant 1s L •
C"
y alue of C
:.-T/2-l
. ges sow y. tsc aro~· , bar ·n time constant as
IS very large in order to make the diS~ gtC:ntent in the output (a) Load voltage waveform for a full wave rectifier with
1
large as possible. This wil~ ~uce the. nrz:rval is shown in Fig. capacitor input filter
Voltage. The equivalent ctremt for this
10.13. (F-1097) Fig. 10.14contd•••••••
Operation in the interval B to C : · equal to the
_ ,.u'fied voltage ts
At "B" the instantaneous.:~ . v
r than c· Therefore
Voltage on capacitor and after "B tt IS greate

'Cis·eas v- s olut• o n s
 Electronic Devices & Clrcuha-1 (Eiex.-MU)
A-t- the RMS value or ripple voltage (V___ , •
Step 2 : T 0 ObUIUI • XIIIIY •
triangular ripple voltage shown m Fig. 10.14(b),
For a..__. formula which states the RMS value of ripPle
Using a StanUlUu
voltage. It is given by,
v, ...(10)
V RMS = 'J:\[3
· Substituting the expression for V, from Equation (9) to get,

V RMS -
-
Jj "'
4 3fCR
..
(11)

(b) Triangular approximation of ripple voltage Step 3 : To obtain the ripple ractor :
(F-10J7) Fig. 10.14 VRMS VLdc
RF = Y;:' 4~fCRVLdc
The capacitor charges linearly during period 1 1 aild 1
- _,.; ...(12)
discbarges linearly during the period 1 2 as shown in Fig. 10.14(b). .. RF - 4v3fCR
The balf cycle period is ''Tfl" which is equal to the sum of 1j and · This is the ripple factor for a full wave '!f bridge ~fier
T2• T 1 <<<T2 tbelefure (1fl) =(1 1 + 1 2 ) =12• circuit. For the half wave rectifier the expresston for RF ts as
Peak to peak ripple voltage is V, Volts. follows:
Derivation : 1
...(13)
The ripple factor is defined as, · RFforHWR = l~fCR
RF = VRMS ...(1)
The ripple factor is denoted by "r''·
VLclc
Q, 26 Explain HWR with shunt capacitor filter •
Where VRMS =
RMS value of the ripple voltage
and V Lclc =
Average value of the load voltage. Ans. : The circuit diagram of a HWR with capacitor filter is as
shown in Fig. l0.15(a) and the load voltage waveform along with
The steps to be followed are as follows :
the equivalent circuits is shown in Fig. 10.15(b).
Step 1 : To obtain peak to peak ripple voltage Vr :
Operation and waverorms :
Capacitor discharges through load R during the time For the intervals 0 to A, B to C the diode is forward biased
interval 1 2• The charge lost by the capacitor during this period is and the capacitor charges through the diode almost instantly. For
given by: 1 the intervals A to B, C to D etc. the capacitor voltage is higher than
Q = cv, ...(2) the instantaneous secondary voltage. Hence the diode is off and tbe
The discharge current capacitor discharges through RL slowly. The discharging time with
i = ·!!Q
dt ...(3) HWR is longer than that with the FWR. Hence the capacitor
discharges to a lower voltage [point B or D in _Fig. 10.15 (b)].
T2 Hence the ripple increases. So the. ripple factor of this circuit is
... Q = f idt=ll..dc 12 ...(4)
higher than that of the capacitor filter with FWR.
D
0
This is because the integration gives you the average i.e. de
value. Substituting the value of Q in Equation (2) to get :
1uc T2 = C V,
1L.x T2
...(5)
p='.:c LON
-~N ·.· . ."II
Hence v, = c ...(6)
~~~----~----~~~
But T1 << T2 , therefore substituting 1 2 =(T/2) B

.. 1z = I2 (a) HWR with capacitor filter

1 . Fig.to.ts
But T =f where f is the supply frequency.
1
:. T2 = 2f ...(7)
Substituting this value in Equation (6) to get,
ILc~c T JLdc
v, = c-x2 =uc ...(8)
But the average load current
,Yu;
JLc~c = R

..
.
Vr =~
2fCR ... (9)

This ~ tbe required expression for peak to peak ripple OloA ;.. loB.
voltage V,. (F-1101) Fla. lO.lS(b) : Waveform and equivalent circui~ for a
HWR with capacitor ftlter
1: a!, v •, u11111 1111 s
~ic Devices & Circults-1 (Eiex.-MU)
4-95
Q. rT Wlult .... advantage.
capecttor Input ftltw ? and dlaactvantagea of
.,.._:
1be .tvantages of a capacitor input filte
. Easy to design r are as follows :
1 R(load)
2. Rcductioo in tbe ripple COOte
wavefoml nt of the output voltage
3. locrease in the average load voltag
4. Small size aod low cost e.
02
~ (Umltatlona):
1be diSIIdvantages of a capacitor input filte . <F·IUI8) Fig. 10.17: Full wave rectifter with tbe inductor ftlter
1. Ripple factor is dependent on the ~ are· 1
2. Regulation is relatively poor. · Operation of the Circuit :
The diodes D 1 and D2 conduct alternately in the positive
3. Diodes have to handle large peak currents.
and negative half cycles to jlroduce a unidirectional current through
the load. Due to the inclusion of inductor L in series with the load.
the current ripple reduces to a great extent and the load current is
smooth as shown in Fig. 10.18. Higher the value of inductor is,
lower will be the peak to peak ripple in the load current waveform.
The load voltage waveform is same as .the load current waveform.

(F-lU)9) Fig. 10.18 : Output current.waveform for the inductor

filter
<F-1140) Fig.10.16
EXpression for the Ripple Factor :
Ans.: Ripple factor on oo load :
On no load, load resistance R.= oo and load current is zero.
~usc
VLdc = Vm-4fc 4oh}
:. ~ ~o
100 X 10- 3 ·
= 20 4 X 50 X 1000 X 10- 6 20-0.5 = 2 .
.. RF on no load = 3 '\[2 =0.472 =47.2% ...(1)
:. vLdc= 19.5 v
Ripple factor on load : 0
VLdc = Iuscx ~ l R
vl.dc 19.5 .. RP = 3-/2 OOL ...(2)
~= lusc = 100 x 10... 3 195 n
Q. 30 State ·advantages and disadvantages of series
vl.dc
V, = 2fCR Inductor filter.
!9.5 Ana.:
= 2X50.X 1000 X 10- 6 x 195 Advantages of series Inductor filter are as follows,
V, = 1 v This is ripple voltage at the output. 1. Low ripple factor at heavy load currents.
1 1 ~ 2. No surge current through the diode.
R.p· -- -
4.../3fCR-4xv3 xSOx l
ooo x 10-6 x 195-67·54
- r;
3. Reduces ripple in the output
R.P. :: 0.014 or 1.48 % Disadvantages :
This is the ripple factor. 1. It is bulky.
Q. 28 Explain operation of full wave rectifier with the 2. It is more costly.
Inductor filter and give the expression for the 3. Ripple factor is poor at light loads (small load current).
4. Audible noise (bum) is produced.
ripple factor. .
AM. :Tbe inductor filter is as shown in Fig. 10.17. An mductor Q. 31 Draw a circuit diagram of a full wave rectifier with
• _ ----A•AA in series with the load R. The LC filter. Derive expreaalon for ripple factor and
(choke) L 15 ~ •
. is that it opposes any change m an output voltage. Explain the bale rectifier
property of an inductOI' . -·--" be to reduce current operation.
current through it is beang uac;u re
ripple iD the outpUt of the rectifier. . Dec 03. Dec. 05. M<1y 06. 10. r,1<ly 08. Dec 10
 4-96
E1ectronlo Devtces & Circuita-l (Eiex.-MU) sea
2V 4Vm
AM.: ___!! - - 3 cos 2 c.ot ...(2)
vln == n n
The cimlit diagram for an LC filter used with a full wave
Rlctifier is as shown in Fig. 10.19. This is a combination of Ste 2 : To obtain the de voltage acroa the load :
inductor filter and a capacitor input filter. Inductor filter is P The de current in the circuit is given by,
pre&rmd for low values of R and the capecitor input filter is 2Vrrf1t
~ for high \'alues of load resistance. The L.C. filter can give IL de = <Rc + Rp) ...(3)
low ripple factor irrespective of the load as it is a combination of
cbe CWO filters. Where , Rp = R II Ra
Therefore the de voltage developed across the load is given by,
· 2Vm
VLdc = ILdc X Rp =1t (_Rc+ Rp) X Rp
rc ...(4)

1\: .. oc .........""" ol L
== n[ l +~]
Ae .. a-lar reelllance But Rc « Rp therefore Equation (4) gets modified to,
<F· Ill'l F1g. 10.19 : FuU wave rectifter with LC filter 2Vm
... (5)
The series connected inductor offers a high reactance to the V Ldc =7
t.mooic components (ripple) ·in the output and attenuates them
Step 3 : To obtain the RMS value of ripple :
and die parallel capacitor provides a low reactance by pass path for
diem. This wiU reduce the ripple further. From Equation (2) the peak value of second harmonic component
Role of the bleeder realstance (Ra) : ofVin is given by,
Peak value of second harmonic,
The resistance Rs connected across the capacitor is called
4Vm
as bl.eelb resistance. It is used to maintain a continuous current vm2 = 31t ...(6)
through tbe filter inductance L. H the current through L is not
cooti:nuous i.e. if it is interrupted then a large b;u:k emf (L di/dt) Therefore the peak value of second harmonic current is given by
will be developed across the inductor. This voltage may exceed the vm2
PIV rating of the rectifier diodes and damage them. This voltage l,a = z;.- ....(7)
may exceed the maximum rated voltage of the capacitor as well.
Reoce lbe induced back emf is dangerous for diodes as well as the Where Zz = Impedance offered by the filter circuit at second
capacit«. 1be back emf wiU not appear if the current through L is harmonic frequency.
cootiDUous. Rs will maintain a continuous current through L. .
WfNeforrna:
Zz = Rc + j2o:IL + G2~ II ~ J ..(8)

1be input output waveforms of the LC filter with full wave But j~C « Rp and Rc << j2o:IL. Therefore the above equation
Jrdifier are as shown in Fig. 10.20. ·
can be written as :
Zz = j 2IDL ...(9-)
Substituting this value in Equation (7) to get,
4Vm
~ = 31t X j 2roL ...( 10)
Therefore the second harmonic voltage across the load is,

Second harmonic voltage across load =1ua x G~ J

11 Rp

1
<J'· lll1) Fig. 10.20 : Input output voltage waveforms of But j2<oC « Rp. Therefore their parallel combination is
anLCftlter . 1 1
approxunatc y equal to j roC .
2
Exp eeelon for the Ripple Factor :
Second harmonic voltage across load =I.ta x .~
Stet 1 : To nprea~ the lo8d voltage In fourier series form :
1be output voltage of a fuU wave rectifier which acts as an Substituting the value of ~ to get, J
iJipul voltage to lbe filter can be expressed using the fourier series Second harmonic voltage across the load
u!oUow• : 2Vm 1 V
zv. 4V. 4Vm = 3;t(;)L x 'iroC =3 1tO);LC ...( ll)
Via • 7 - "3,t' eo& 2 wt - IS 1t cos 4 Cl>t ...(1)
But this is the peak value. To calculate the ripple factor we need
Wbete V• I;< maxiowm value of half secondary voltage. rms value.
1be tint term io Bquatioo (I ) repre~ents the de or average value of
tbe ouapw. IC008d ttnn repteaents the sec.ond harmonic, third one · · RMS second harmonic voltage across load = ~21tm"LC
V•.
~ tbe fowtb barJDoQic and 10 oo. Nesloctina aU the hiaher
order ~y romponeatl except the second harmonic , ...(12)

,. 'I ' , ~ ', II 11111 11 II ',

 gectronic Oevlces & Circults-1(Eie>c.·MU)
4-97
seep 4 : To obtain exp~n .,_
•vr the ripple factor .
r "" ~[
RMS
RF = StX'Ond harmonic voltage across lou~ I Jn
3 4 alLC
VLdo:
vm Here n =2 (number of L section)

= ~ [4 x (2~f);::cJ
-1.'2 2 X ~-
= JV I
.dtm LC 2 Vm- 6 -{2. ro2 LC ...(JJ) .. r
Sta.. ltdvantagea and dl · ·
~[4
Q, 32 ·
. &advantages of LC Fllte
A~: ~ X 47t2 X 50z! 2 X Z7 X 1000(;1
3
Actventagea ~f LC filter : .. r = 1.038 X 10-
I. Very good load regulation 2. DC load voltage
2. Ripple factor is low and d~s n0 t d 2 vm
.3. This filter is suitable for light e r;end on the l~d. VL = 'It -Il...dcR
4 Diodes do not h as we1 as heavy loads. Where R =(Rs + Rp + Rc)
. ave to cany surge currents.
Disadvantages of LC Filter : But the values of Rs, Rp and Rc are not known.
I. Audiable noise (hwn) is produced b th . 2Vm _2.J2x100
2.
Du
e to the use of large value L d C
Y e mductor
. .. v" = 7t 7t
circuit becomes costly. . an components the VL = 90Volts
3. Due to the USe of inductor the filter is bulky
4- Bleeder resistan · · .· 3. AC ripple :
ce mcreases the rating of rectifi : ·
5 Power loss tak I er cucwt. ._ AC rlpple
. . es p ace in the series inductor L due to its de Ripple factor r
resiStance. v~..
-3
a. 33 Draw double section LC Filter. What Is the ripple :. ACripple = r X V L =1.038 X 10 X 90
factor of a two stage LC filter? 0.09342 Volts
. ' ~
Ans.:Tbe double section L.C filter is shown in Fig. 10.21. The value of L is sufficient if Lc = 3(1)
. 500
:. Lc = x 27t x 50
... . . .. . l.
~
:. Lc =
3

0.5305 ii
RL · Vo The given value of Lc = 2H. Hence the inductance is sufficient.

L...,;~-__._--+---'·········...J.. a. 35 Draw a circuit diagram of a full wave rectifier with

7t filter. Derive expressions for ripple factor.
(F-1123) Fig. "10.21
Explain the basic rectifier operation. 16@d•fi
1be double stage is being used in order to improve the
quality offiltering. · Ans. : The 'It-type filter which is a combination of capacitor input
1be ripple factor of a two stage LC filter is · filter and LC filter is as shown in Fig. 10.23. It consists of
2 two capacitors C1 and Cz along with the inductance L.
r = f [(li~c] .... L 1 =L2 , C 1 :::;C2 Generally both the capacitors are of same value.
This shows that ripple factor reduces i.e. gets improved due
~~-
. - ' - - FWR---+-- Ftlter---41~
to the use of two sections instead of one. L .
a. 34 In the circuit shown In· Fig. 10.22 determine the de.
load voltage v'-'
ac ripple in the output and verify
that the given Inductance value Is sufficient.
Derive necessary expressions. ·

(F-1128> Fig. 10.23 : n type filter with run wave rectifier

A 'It-type filter can be considered as a combination of shunt
capacitor filter and LC filter. This improves the effectiveness of the
c, • c2 • 27,F 'It-type filter as far as filtering of ripple is concerned. Due to the use
()1'-UU> Fig. 10.22 of thre~ filtering elements (C 1, Land C2), the ripple factor of the 'It-
type filter is very low as compared to the other filters. The
capacitors C 1 and G.z provide a low reactance path for the ripple
Ana. :The .gJVeD
).
. . 't 's a multiple section LC filter. Its ripple
CJJ'CU1 I . whereas the series inductor L provides a high reactance to the ac
factor is given by, ripple. The combined effect of this is the reduction in ripple, and
improvement in the output waveform.

1: a ~. II s U I II I I ll II S
 ...
Electronic Devices & Circuits· l (Eiex.-MU)
ll..de 1
--
4-98

tnput •nd Output Vottege Wavefonna : But -VIAe =RL

Vollagot 801'00111 Cor loed vollnQe :. Ripple factor,
1
. AecUIIed
'····./output

I . .(
\ •.. Rearrangjng,
\\
oL---------~w~--------~2.~--------~~~ 1 10)
r = 4 ..j3f(w:LC 1 C2 RJ ForFWR .
<F-1131) Fig. 10.24 : Input and output waveforms of n ftlter . . h pre·ssion for ripple factor w1th a full wave
This JS t e ex . · 1 f f
. . . 1 the expresston for the npp e actor o a half
El(J)I'eSSlon for Ripple Factor : rectifier. Sulll1ar Y
The nns value . Qf ripple voltage at the output of th~ wave -rectifier is :
capacitor input filter C 1 with a full wave rectifier is given by·: .

v
y .
--j:;
.....
= 2 -v 3
... (1)
1·
I ForHWR .
...( 11)

h t are the advantages and disadvantages of n

Where v r =
Peak to peak ripple. Q. 36 W a .
type filter ?
The peak to peale ripple voltage for a fu]J wa~e rectifier is
given by, . Advantages . of n type fitter are as follows ,
Ans..
lLdc 1. Same as those of shunt capacitor fi~ter.
v. = 2 fC 1 .:.(2)
2. In addition to that the ripple facto-r IS very low.
Substituting Equation (2) into ( 1) to get, 3. High de voltJ,ge (approxirruitely V m>
ILclc Disadvantages :
v
""' -- 4V3 fC, ...( 3)
. 1. . It is bulky due to use of inductance.
This is the ripple voltage at the input of the L-C filter. 2: Costly due to more number of components.
Tbe rms ripple voltage. at the output of the LC filter LC2·is 3. Current rating of choke needs to be high.
given by: Q. 37. In the ·circuit shown ·in Fig. 10.25 determine
v =
·Xo
vi'Dl$
:..( 4)
d.cJoad voltage VL, an ac ripple In the output,
""' XcXo verify that the given filter .is sufficient low ripple
.. v =
v rms
...( 5)
· voltage. Derive necessary expression. lli!JJN•EI
rms (XL/Xo) - -1

But XL = w, L and XC2 = w,1r'-'2., considering

.
the second
·...,
harmonic frequency w, = 2 w.
Substituting these values and the value of V rms from
Equation (3) into Equation (5) to get,
ILdc . .
v -
rms - 4...{3 fC1 [w, L x w, ~ -1]
where ro, is the angular ripple frequency. That means
(F-im>Fig.l0.2S
w, = 2 1t f, where, fr= 2 X 50= 100Hz
Ans.:
= 4-../3fC1 [w .LC:z-1]
2 . ...( 6) .
Step I: To find DC load voltage :
2
VLdc = __2Vm
for w LC2 >> 1 ,
1t
JLdc
v,.. ... ( 7) 2 x...J2 x50
VLdc .=
1t v Ldc =45.0158 v
The ripple factor is defined as Step II: To derive expression for Ripple factor ;
Rms value of the ripple voltage across the load vr . .
r = Average vol~ge across the load V rms = 2 "./3 (for a ca~acitor filtt:r)

...( 8) = Ildc
Vr 2 fC
1
I~
I

Substituting lhe expression for V from Equation (7) to get

nns .. v rms = 4 "./3 rc,
ILdc
r = is the ripple at input ofLC ftlter.
The rms ripple voltage at output of LC filter L<; is,

r. .t ,, II • Ill II II fillS
_:!ectronic Devices & Circuits-! (Eiex.-MU)
4-99

Ana. :
The block diagram of a regulated power supply is as shown .
in Fig. 10.26.

~.....___Unregulated _ _ _ . . J
~power supply-.,

(F·10l3>Fig. 10.26 : Block diagram of a regulated power supply

Q. 40 Deflne : Load regulation :
Ana.:
.. vrms
' ILdc
= The load regulation (L.R.) is defined as the change in
4V3 fC 1 w2 L~ output voltage when the load current is changed from zero {no
v'nns. load) to maximum (full load) value. ·
Ripple factor = VNL-Vfl.
VLdc ·%L.R. = V X 100
fl.
ILdc
.. R.F, = Q. 41 .Define: Output Resistance (RJ of power supply•
4V3 fCI (~2 L~) v Ldc
ILdc Ana. :The output resistance of a power supply is defined as the
But = .!..
RL ratio of change in output voltage to the change in load
VIAe
.current, if. input voltage V in and temperature are held
. R.F.=
4
V33 fw LC
1
c; RL
2 constant
1

llF. V3 2 1 .
ll Vol . . .
4 3 X 50 X (21t X 50) X 47 X 10- 6 x 47 X 10- 6 x 1 X 1000 ll IL Constant V in and constant temperature
=0.0132
Q. 42 Define : Source Regulation
R.F. = 1.32%
Ana. : The source regulation (SR) is defined as ~ change in
Q. 38 Compare L-sectlon LC filter , Choke Input fitter ,C
regulated .load voltage due to change in line voltage in a
filter and 1t type filter. {I•AIM specifiedrange of 230 V ± 10%.
Ana.:
Q. 43 State types of voltage regulators :.
Ans.:
'l'be two' most widely used types of voltage regulators are :
Place of Across the In series N;ross the 1. Shunt voltage regulator . ·
• lOad with the
load.
load

All loads
2. · Series voltage regulator
Q. 44 Explain characteristics of zener diode. Explain
Slilable for light load Heavy load Ughtas
applications applicatiOnS. well as ·zener diode as voltage regulator.
heavy
loads Dec. 10. May 11. May 15. Dec. 12. May 16. Dec 16
Low and Low ·Ana. : The voltage across a zener diode remains constant equal to
&.ge Veryhigl Low and
CUTent and must need not be· need not Vz when it is operated in the "zener region" Qf the reverse
controlled. be
llrot9l be
controlled. characteristics (Fig. 10.27(a)). This fact is utilized in the
cildes controlled application of the zeiler diode as a voltage regulator.
RF= r=
ExJlreaeion RF= RF=
R
brp _lL
fN2oAc 2-/31
1. 2
(ro LC1 Cz RL)
taca 4-.fi fCR ~rol ForFWR

Size oilier B~ BulkY Bulky

l ~ ~ ~·· ~· t
~ High current DC poWer
DC power supplies
T,. . . . .... . . . . . . . . . ...... J..
---
Cel
charger, de power suppHes ....(Ytol
___ _.__..;.J.. . . .
smal supplieS
ellrmlators lated de power (a) Reverse cbarac:terlstks .of a (b) Regulator dmlit using.
Q. 39 Draw the bloCk dJ«tgram of a regu . · zeuer diode zener diode
aupply <B·136) Fig. 10.27

f: a ~. II · '• II Ill I I II II ~
 Electronic Devices & Circuits-! (Etex.-MU)

Operation of the z.ner rwgulator :

Regulating Action with • Val)flng Loa~ (VJn Constant) :
4-100
-
Assuming that the input voltage IS .constant and load
The input voltage V1n is an unregulated de voltage which is resistorRL is variable. IfRL increases then IL wlll decrease. But the
obtained from a rectifier filter combination. R, is the current
total current I is constant as :
limiting resistor and ~ is the load resistor. The input voltage V1n
V10 - Vz
sbou.ld always be higher than the breakdown voltage V,. Tbe
circuit diagram of Fig. 10.27(b) shows tlmt the zener diode is
I = ...(1)

reverse biased and operates in the zener region of the reverse Therefore. with decrease in IL, the zener current ~ win
characteristics. lf Vtn is higher than V• and if the zener current I. is increase. This can continue without damaging the zener. diode, as
between l z lllln and ~ max then the voltage across the zener will long as ~ is Jess than. I.. max• and the output vol~ge ~Ill remain
remain constant equal to V • irrespective of any changes in V1n and constant. If RL is reduced, 1L ipcreases. But as 1 IS constant, the
~· As the output voltage is constant and equal to V •' to get a zener current will decrease. The output voltage will remain
regulated output voltage. Zener current ~ should not be higher than constant as long as 1, is higher than I.. min' ~us the output voltage
I.. m~a· otherwise excessive power dissipation will damage the zener remains constant as long _as the zener current IS between ~min and ~
diode.
max'
I.. should not be less than ~min either because then the zener Q. 45 Whatare the limitations of zener regulators ?
diode cannot operate in the zener region and cannot maintain a
constant voltage across it. The regulator should keep the load Ans.:
voltage constant inspite of changes in input voltage and load Even though the zener diode provides a very simple means
current. of ·voltage regulation, these regulators have following
Regulating Action With a Varying Input Vohage disadvantages : _
(Constan~ 1J: i. · The output voltage of zener regulator is equal to V•. This is
Assuming tha~ the load resistance RL is constant and V in is a constant voltage. Therefore these voltage regulator
vazying (Fig. l0.28(a)). As RL is con,s~t, IL is also coiistailt cannot.provide as adjustable regulated output voltage.
because IL =
V/ RL. But supply current keeps changing due to 2. Large power gets dissipated in the series resistor R_,.
change in Via as, .
Q,46 State merits of zener regulator .
Vm- V,
I = Ans.:
R. Merits of zener regulator are as follows ,
Also I = ~+IL
1. Simple circuits~
Rs 2. Only 2 or 3 components are required to be used.
····• 3.. Low cost. .
IL (constant
Q. 4? State applications of z~ner regulator :
Ans. :Applications of zener regulator are as follows ,
1. In the emitter follower regulator.
2. · As a low cost, regulator with a small load current range
(a) Regulation action with a varying input voltage over which V 0 remains constant.
I( constant) Q. 48 Design a zener voltage regulator for the following
····• . =
specifications, V1n 20 ± 2 Volts, Output voltage
=
Yo ·6 V, Load current IL :: 50 mA, 1z (min) 5 rnA, =
vin =
Zener wattage Pz 0.5 Watts.
constant)
Ans.: Given : V in (min) -18V
- ' vin (max) =22V•vo =6V•
IL =50 rnA, I.. (min>= 5 mA andJ>, =0.5 W
(b) Regulation action with a varying load resistance

(B-137) Fig. 10.28 Step 1 : To calculate Is (max) :

If Via is increased, then current I will increase. But ·as V• is
::._ 0.5 .
c.oostant an(J RL is also constant, the load current IL wili remain 1z(max) = Vz = 6 = 83.33 mA ...(1)
constant. Naturally the increase in current "I" will increase the
zener current ~· This can continue Juumlessly as long as 12 is less Step 2 : To calculate £'1(mln).
v •
than Jzmu· If V.u, is decreased, I will decrease causing Jz to decrease . When ~ = R s (min)• the source current .J can become
as V.._, and IL are constant. The load voltage will continue to be maxtmum =
corresponding to V in v in (owi>· As the ioad current is
equal to V1 as long as It is higher than Iz min· The zener regulator · constant, this .increased source current will flow through tbe zener.
with variable input voltage is shown in Fig. J0.28(a). Thus the '!herefore the value of .R, <min; should be such that even when
output voltage V 0 will remain constant as long as tb~ zener cu~nt vin = in v
(max)• the zener current ~ ~I.. (max).
is maintained between Jzmill and lz 0111 • As soon us tt goes outstde vin(max) - vz
these limits, the output voltage will not remain co nstant. '' J\
(min) = [I T
L +": (max)
) •••(2)

I!:ISV-SIIIIIIIOIIS
£!eotronlc Devices & Circuita-l (Eiex.·MU)
4-101
''
Rl(IDII\)
ae T.s~~~~--
21 - 6
( 0 + 83.33] X 10" ~ • 120 .Q ...Ans. Tran•former tum• ratio :
SteP 3 : To calculate D. .. .. (1111•).•
vnnn• = 12 Volts given
When R" =
R, <max) the source c But VOntiJI = Vml-{2
...inimum corresponding to v y urrent I can become
u• In "' 1 As [ ·
should be taken to ensure thut 1, ~ 1 " <1111"'' • t. 18 constant, cure
where V., = Peak secondary voltage
V • t.(mln)' .. vm = -{2 X Vorms = 12 -{2
,
••
R. . .
emu)
= [I + 1
V.,
ln(mln) -
] .. v.rm.= secon!lary rms voltage
...(3)
= Vmt-{2 = 12~1-{2 Volts
l. '1- (111111)
R = 18 - 6
[50 + 5] . . Primary to secondary turns ratio
•• a(max) · X to-·;-:r· = 2LS.i8.0. ...A·OS,
Nl = VI nns ~ 230 = 19_166
Thus R ;::: 120 0 and R !:0 218.2 .0.. So, select R = 180 .0.. Nz Vtrms 12
Q. 49 Give comparison of rectifier and regulator. .. Tninsformer turns ratio = 1~.166 .•.Ans.
Ana.: PIV of diodes:,
Sr. R.edltler ' lteaulator · PIV = 2Vm=2x~xv.rms
'' ....An5.
No. = 2·x-{2 x 12 = 33.94 Volts
l. Its function is to convert Its function is to maintai~ Selection of zeoer diode :
ac input to de output. the output voltage constant. The zener diode vqltage be Vz = 6 V.
2. Output voltage waveform Output voltage waveform is · Assuming the maximum zener power dissipation Pz = 500 m~.
is pulsating de. pure de. .. P~ = V~ Iz <max)
"z max) = p z 1 Vz =500 mW/6V = 83.33 rnA
(8·~43) (D-144)
.. T<
Vo Vo
Assuming lz<n~n) = 5 mA
·V'\r(''' Resistance R8 :
Curreni through Rs = Iz (min) + I~ =Is
1

. . Is = 5 mA + lO mA = 15 mA
3. Poor voltage regulation. V~ry g~ voltage Average output voltage of the rectifier
regulation. 2Vm
4. Made of _
diodes. ContaitJS devices such as = 1t
transistor, zener diode. 2 ..J2 X 12
= 10.8 Volts
5. Types : HWR, FWCT, Types : Series or shunt 1t
Bridge rectifiers. · regulators.
= ~~ ~ =320 Q
8
:. Rs ...Ans.
6. The output voltage varies The output voltage remains
to a great extent with constant irrespective of Selecting the nearest but lower standard value.
changes in vln• ll. or changes in vin• IL and Rs = 290Q ...Ans.
temperature. temperature. Power dissipation of
Rs . = I~ R8 =(15 X 10- ) 2 X 320
3
Q, 50 Draw a center tapped transformer configuration to
proctuce - 12 V rms Volts at the output of a full .. Pas = 72mW ...Ans.
wave. rectifier. Connect a zener diode clrpult to . Hence selecting R8 as 1/4 Watts resistor.
the o~JWut of this circuit to SU!)PIY a load current .
of 10 .m A at 6V to a load resistance. Calculate
a. 51 A full wave rectifier employing a center tapped
transformer has an output voltage of 15 volts.
values of all the components shown In your
circuit.
. . l•l§•t.l Input supply is 240 Volts, 50 Hz. Load resistance
Is 750 0. Calculate transformer tums ratio. If a
Ana. : Part 1: Full wave rectifier circuit . . · zener regulator Is connected to this output to give
The ce~ter tapped transformer configurauon With full wave 9 Volts at 10 mA calculate values of circuit
rectifier·is shown in Fig. 10.29. components. lfud•h
Soln.:
G'ven : V01 (av) = 15 Volts, Supply voltage= 240 V,
RL =750.0., V0 =9 Volts, IL =lOrnA

Step 1 : Draw the circuit diagram :

230V Vz::6V The circuit diagram of the rectifier with zener regulator is
50Hz shown in Fig. .10.30.
L-----41---- +

Dz
m.. 10 29 1 Requited circuit
(li'·l:l71) .....• . . .

t: a :. V 'i 11 Ill I I II II S
 Electronic Devices & Circuhs-1 (Eiex.-MU)
Ant.:
1be transistor shunt regulator as shown in
4-102

Pig. 10.31. The transi~r Q acts as a shunt control element It is

- "
operated in its active reg1on.

Regulated
output voltage
vo
(F-U71) Fig. 103o

Step l : c.Jcalate transtonner turns ratio : ·

Rectifier average output voltage \'01 <••> = 15 V ... given
__ _ 2Vm (F-2045) Fig.10.31 : Transistor shunt regulator
But V ol (av)
Jt
Operation:
where Vm = Peak secondary voltage From Fig. 10.31 ,the output voltage is given by
:. 15 XJt = 2 Vm vo = vz + VBE ...(1)
Vm = 15 Jtl2 = 23.56 Volts Vin is the unregulated de power supply sending a current I;
rms secondary voltage l:brough the current limiting re~istor R.
V, rms = Vm!..J2=23.56/...[2 Regulation action : ..
The relation between input current, collector current and
:. V,rms = 16*66 Volts
load c~nt is as foUows :
N, 240 .
Thms ratio = N = 16.66 = 14.4 ...Ans. ~ ·= lc +IL
2 If the output voltage decreases due to any reason, then (Vz
Step 3 : Cakolate PIV of diodes D1 and D1 : ·+ V0~ will also decrease. But V,. is constant so V8 E wiD decrease.
.This will reduce base current 18 of the transistor. This wiD reduce
PIV of each diode = 2 Vm =·2X 23.56 Volts
the coUectOr current lc· So more current will flow througp the load
= 47.12 Volts
and the load voltage will increase. This will continue till the load
Step 4 : Select:ioo of ~ner diode : voltage reaches the desired level. If .the output voltage increases,
then exactly opposite action will take place to regulate the output
AI. the required output voltage is 9 V, we select the zener
voltage.
diode of V,_ = 9 V. Assuming the maximum power dissipation in
zeocr diode is P ,_ (IDaxJ =500 mW. Q. 53 What are the advantages and disadvantages of
ButPz(mu) = VzX~(max) transistor shunt regulator ?
T SOO X l0-.3
p:t(max) 55.55 mA Ana. :
•• A.z(max) = vz . 9 Th¢ advantages -and disadvantages of transistor shunt regulator
~(laiD) = 0~ 1 ~emu) = 0.1 x 55.55 = 5.55 mA are,
1. It is possible to provide temperature coJDpensation without
Steps : Selediot.of Rs : . My additional circuitry. .
Total current through Rs =Is= ~<min>+ IL 2. Output resistance ~ is of low value. This is an imPortant
advantage. ·
• But Ji_ = V,_/RL=9V/7500=12mA
3. Better regul~on as compared to the simple zener
.. Is = 5.55 + 12= 17.55 mA reg~ll~tor. !1'1s IS because, due to presence of transistor, the
¥ 01 -V,. 15 - 9 vanations m 1z will be smaU.
HenceRs = Is - 17.55 x w- 3 4. The only disadvantage is the high power· dissipation taking
place in the series resistor R, zener diode and transistor.
. . Rs = 341.88 Q This reduces the efficiency of the circuit.

.. Rs '"'
Selecting tbe nearest smaller standard value
3300
.
...Ans.
Q! 54 Determine the regulated voltage and circuit
currents for Fig. 10.32 as shown In shunt
Power dissipated in regulator.
Rs ::: ~ Jl., =(17.55 X 10- 3)2 X 341.88 =0.105 W
Hence chooie Rs to be 1/4 W resistor.
Q. 52 Explain the operation of tranelator ehunt
regulator.

1: a :. 'J ', U Ill I I II II~

Eectronic Devices & Circults-l (Eiex.·MU)
4-103
I5 330
This will increase the collector to emHter voltage VCE
across the transistor and V0 will be reduced till it reaches the
desired value. This is because,
v = vin - vt.E
0 ...(2)
If the output voltage decreases, then exactly opposite action
will take place and the output ~oltage is increased till it reaches the
desired regulated value.
Q. 56 What ·are the limitations of emitter follower
voltage regulator .
<F-2053) Fig.10.32 Ans.: The limitations of emitter follower voltage regulator are as
. follows, .
Ans. : 1. The output voltage is not adjustable.
Step 1 : Output voltage : 2. There is no protection for the transistor if an accidental
short circuit takes place on the ·output side. Such a short
Vo = Vz+VoE=10+0.7=10.7V circuit will damage the ·transistor due to excessive power
...Ans.
Step2: dissipation.
3. The output voltage is Vz .: VBE' Since both these voltages
are
temperature dependent, the output voltage will vary
...Ans. with tempera~.
V;-Vo 15-10.7 - Q. 57 Determine output voltage and zener current for
Is = R = 33 == O.l3 A ...Ans. the circuit shown In Fig.10.34. Ufi•Q
Is = IL + IC + Iz 13 =50

ButJC 13Iz = +
.. Is == IL + (l + 13}1z
:.· 0.13 = 0.107 + (1 +50) Iz ...Assume p =50 1k
:. Iz =
0.45 mA ...Ans.
And IC = 13~ =50 X 0.45 mA =22.5 mA ...Ans.
Q. 55 Explain the operation of serieS voltage regulator
(Emitter Follower Regulator). (F-1143> Fig: 10.34
Ans.: The basic series regulator (emitter follower regulator) A.n s.:
circuit is shown in Fig. 10.33. 1. Output voltage:
The transistor Q acts as a control element. Because it is Vo =Vz + V8 E =:= 8.2 + 0.7 = 8.9 Volts...·.Aos.
connected in series with the load. this circuit is called as series 2. Output current 10 =IE :
regulator. The transistor is operated in the active region and it ·is
call~ as series pass transistor. The circuit shown in Fig. 10.33 is
v 8.9 .
10 = -R;_ =lk =8.9 mA
also called as emitter follower regulator. .

R
. . IE = ?.9 mA

··~'"''''' '"":'""f
3. Base current :
.l 8.9x w-3
Regulated . Io = 1+13- 51 =174.5~
UnregiAated JAB f\ output voltage
Vo 4. Current through 200Q resistance :
YllltageVIn

'---___._~--·" ' " "' " .1

V;.- V, 22-8.2
IR = 200 200 = 69 mA
5. Zenercurrent:
(F·:ZOSS>Fig. 10.33 : Emitter follower regulator
IR = IB+Iz :. 69 = 0.1745+Iz
Operation of the circuit : . . Iz = 68.83 mA ... Aos.
The series pass transistor operates ~n ~e emitter follower
configuration. Therefore the output voltage IS g•ven by, . Q. 58 Differentiate series and ,hunt regulators •
...(l) Ans.:
vo = V,-VBE .
V" is the zener voltage therefore it is assumed . to be
constant Therefore if the output voltage varies, then there will be a
Serles
. . ftgulator
change in V BE> because V, is constant. . .
Regulation action : If the output voltage mcreases due to In parallel with load In series with
some reason, then vBE decreases ·(refer to' Equation (1)). Due to transistor in the load
reduction 1·n v the base current . decreases. Therefore the regulator ·.
BE• · ·
collector cuirent decreases.
I! a:; V · s 0 Ill II II II S
 Electronic Devices & Clrcults-1 (Eiex.-MU)
I,
Sr•
.N~····· of Active
Power High power Low power 6. Region
dissipation in dissipation in R · dissipation in transistor
current limiting R operation
resistance o. 59 What Is the maximum reverse voltage (PIV)
3. voltage stability r, across a diode In :
factor Sv=[+R
r, +~e z 1. HWR
(l + hre)R + (r, + ~J Sv is low 2. FWR with center tapped transformer
Sv is high which is which is bad. 3. Bridge type rectifier. ·
Dec. 09. May 10. Dec. 10. Dec. 11
good.
Output ~·= Ans.:
resistance
(r, +~JR r.+~e I. HWR =Vm
(1 + hre)R+ (r, + ~J . (l+~J ·· 2. FWR with center tapped.transform.er= 2Vm
~ is, low which is ~ is high 3. . Bridge type rectifier. =V m
gbodo · which is bad.
5. Output voltage

Chatper 1.1 : Design of Electronic Circuits

0.1 Design a single stage RC coupled CE amplifier ·I A i ·= h,~ <&: II R1)
using the transistor with the following . Y . ~e ·
apeclflcationa of an amplifier . hht · - · 220, But Rr_ =oo :. Rc II RL =Rc..
. ht. = 2.7 leO, ~oe = h,.. = O.The amplifier mu~ ~
have : . :. I Ay I = ~
lAy I ~ 180, ~ -~ 10,' V0 =3 Volts. Vee= 18 V, But .I Ay 1 ~ .1 80
fl!520 Hz. . .
.~·
Calculate Ay. ~ and Ro of the amplifier you ~e ·~ 180
designed. . 3
.> 180Xl\c · 180 X 2.7 X 10
Ana.: :. Rc bee .. Rc -~ 220
1. ~ons of the transistor: :. Rc ~ 2209Q-
flte = · 220,hie=2.7kO,hoe=~=O · . Selecting the.next higher standard value of Rc·
2. Specifications of the amplifier_: Rc =
2.3 k.Q. ·
I Ay I ~ 180 V0 =3 Volts. Srep 2 : . . Emitter resistor RE :
S;ro ~ 10, Vex;= 18 V . · I. For Va; > 10 V, the value of V E should be 5 _v.
fL!::20Hz. :. VE 5v . =
2. Applying KVL to the output loop of Fig. 11.1,
The single stage RC coupled amplifier is as shown in
Fig.ll.l. Due to high gain requirement, the emitter resistor Re is Vex; = ~Rc+VCEQ+VE
bypassed . Va;-VCEQ-VE
+Vee
. . ~ -~ • Rc

3. Assuming the Q-point is at the center of load line.

:. VCEQ = V cc-:- VC5 <sao 18 - 1

0
2 =~
:. VCEQ = 8.5 Volts
4. :. 1cQ =
Vc;c-Vcyp-Ve _ 1~-8.5-5
Rc,' - 2.3 X 10 3
= 1.956mA . ...(2)
Io
Q
!w
hcc
= 1.956 mA
200 =
9.78 J..LA ...(3) =
(F-Ull) Ff&.ll.l: Siape stage R.C. coupled ampUJier .. IsQ = lcQ + loQ = 1.956 mA + 9.78 J..LA
5. . . lao =
1.9657 mA
6.
Step 1 : Value of Rc : :. The emitter resistor
The expreasioo. for gam, RB =..!Ji.l~n
........
-
- 1.9657 x
5
w- 3
-
Electronic Devices & Circuits-! (Eiex.-MU)
:. Rt, = 2.5436 kQ
10 10
4-105

Selecting RE = 2.7 kQ ... (4)

:. 2 7tfLR; ~ ct or c. 2: 2 7tfL R ;
Step 3 : To calculate the biasing resistances a and ~ : ~ _ 2.7 X 25.45
1 But ~ = ~II Ra =b. + R 8 - 2.7 + 25.45
Fig. 11.2 shows the Thevenin's equivalent circuit f the
amplifier of Fig. 11.1. . 0 ••
. :. ~ = 2.440
RB = RtiiR2 to
and V = R2 :. CI >
- 2 7t X 20 X 2.44 X 10J
m <Rt + Rz) x Vee ... (5)
:. c 1 2: 3.26 x 10 -s or C 1 2:32.6 ).IF
.Selecting the standard value C 1 = 47 ~ 125 ~..
Selection of c2 :
c2 should ~ such that,
Xo ~ 1~ <Rc II RJIAt f = fL
~ut ~ = oo

.. Xcz ~ RcflO
VTH .. Xcz ~ 2JOO /10 i.e. 230 Q
1
~ 230
:. 2 7tfL Cz
1

(F-1522) Fjg. 11.2: Tbevenin's equivalent circuit

:. Cz 2: 2 7t X 20 X 230
The expression for stability factor of the voltage divider
bias circuit is given by, :. Cz :::: 3.459 x w-$ or C2 2: 34.59 ~­
Selecting the standard value of Cz =47 ).IF /25 V ·
... (6)
Bypass capacitor Ce :
But S ~ 10 ...(Given) ~ should be such that

..
(1 + 220) (RB + 2.7) < 10
Rg+(1+220)x2.7 - .
:. 221 ~ + 596.7 ~ 10 R8 + 5967
:. Ra ~ 25.45 kn . ... (7)
. Xa; ~ ~1101

< 2700
- 10
Atf = fL
-
l
1
Applying KVL tO the base loop of Ft~. 11.2 • :. CE 2: 2 7t X 270 X 20
Vm = IaQRa+VaE+VE

'
. 3
:. C 5 2: 29.47 ).IF
:. Vm = (9 .78 X 10- 6 X 25.45 X 10) + 0.7 + 5 Selecting the nearest higher standard value i.e. 47 J.&F I 25
: .. Vm = 5.95 Volts V. The designed circuit is shown in Fig. 11.3.
-~ X~
But V 111 = <Rtltz
+Rz) x Vcc-R 1 +Rz Rt

RR xVa; = 25.45x 18
. . Rt = Vrn 5.95 0

. = . 77 kJ). ., . .._. .(8}

.. Rt . R, Rz
. But Rs = 25.45 kO = (RI + Rz)

:. 25.45 X 77 + 25.45 Rz = ?1 Rz ...(9) 47!1f=

.•. 0nz = 38 k.O acitors c 1 cl and I"'-'E ••

Step 4 : Calculate the coupling cap '

Selection of C1) . uld be such that. <F-1523) Fig. ll.3 : Designed CE ampllfter

.
The coupling capacttor c. sbo

. Xc. ~
~I
10 At f
.= .
fL
Step 5 : Av, ~ and R,. of the deslgued amplifter :

~ 220 X 2.3 X 103

IAvl = ~ 2.1 x 103
1
IAvl = 187.4

lis '*'"''4jli@liijiiJ
 Electronic Devices & Circults·l (Eiex.-MU)
Thus voltage gain is higber than 180.
·R; = ~II R0 = 2.7 k lj25.45 1c
R; = 2.44 k.Q
Step 2 :
r0 (mA) '
:. Rc .. 2.1 k.O
Decide tbe Q point :
4-106

-
and 1\, = Rc = 2.3 k.Q
Q. 2 O..lgn alngle stage BJT CE Amplifier for the v
following requirements. . Ac
00
Av:?! 100, Z. >3 kQ, Vee= 18 V Dec. 09. Mny 10
Ana.:
Spectficatfone are :
1. Voltage gain I Av I~ 100 2. ~>3k.Q
3. Vcc=l8V 4. Assume fL = lO Hz
Assumptions : Ycecsat)
The .type of biasing circuit : Voltage divider bias. The
emitter resistor Re is bypassed. The CE amplifier circuit to be Vee - Vcecaat)
designed is as shown in Fig. 11.4 ·
<F·l566> Fig. U.S

vo (peale) = vCEQ - v CE(sat)

Assuming Vce (satJ = lV

Vo(p-pJ = Vee.- Vce<.oat)- Vce<w>
= Vee.- 2 Vce(aat)
But VCl!'(sat) = lV
:. Vo(p-p) Va::. '-2 =18-2
16V
. . Q points S : 16 Volts, 5.5 mS
Step 3 :. Selection of emitter resistor RE :
1. For Va:.> 10 the value of Ve should be 5 V.
Assuming Ve = 5V
2. Applying KVL to output loop to wrjte,
<F·IS65) Fig.ll.4
Vex; = ' lCQRc+VCEQ+Ve
Vee.- VCEQ - Ve
Selecting transistor BC 147 B because it has higherh;e· :. ICQ Rc
· Specfftcations of transistor BC 1478 :
~=4.5.0 . ~=2x10
' -· 3. Assuming the Q-point is at the center of load line

.. VCEQ . =
. Va:.- VCE(sat) 18- l
2 =~
he., (miD) = 240 h fe (typ) = 330 h fe (max) = 500
hfE(IIIia) = 20() hFE(typ) = 290 b PE (max) =450
. . VCEQ = 8.5 Volts
Design procedure : L_· Vcc-VCEQ.-Ve_ 16-8-5 rnA
The steps to be followed for the amplifier design are as follows : 4. " "CEQ = Rc 1.8 X 103 - 1.6
Step 1 : Collector resistor Rc : = .1aL. 1.6 X 10-3 5 05 "A
The expression for voltage gain is, InQ bee (typ) 330 · ,.....
IAvl =
hce<RciiRJ 5. Ii>Q = · lCQ + IBQ = 1.6 X lO - J·
+ S:05·X lO-6
But~ = oo •.• IEQ 1.60 mA=
hceRc 6. The emitter resistor is given by,
:, I Av I = hie Vi, 5
Because required 1Av 1~ 100 ,so substituting the mi~imu~ Ro ' = IBQ = 1.60 X w-3 =3.115 k.Q
value of 11,.,. so that under running.conditions the voltage gam wrll Selecting R8 = 3.2 k.Q
be~ dlan 100. Step 4 : To calculate tbe biasing resistances R and R, :
1
:. I Avf ~ 100 Thevenin's equivalent circuit of the amplifier of Fig. ll.6.
bee (Jaiol) Rc R8 = R 1 IIR2
~ ~ 100 ~
3 andVTH = R +~X Vee
4.5 X 10 X 100 1
:. Rc ~ 240 The expression for stability factor of the voltage
:. Rc ~ 1.87 ill divider bias circuit for good stability is given by,
SeJecting tbe next higher standard val.ue for Rc S ~ 5 .Substituting hPB = hi'B(tYPJ =290 and
remaining values, to get,
L ;1 •, 11 '. 1J Ill I I ll II '•
Electronic Devices & Circuits 1(
. . - Elex.-MU)
+ 107

. c1
••
:0:: 10
21t X 10 X 3.32 X 103 =47·9 J.lF •••Alii.
Selecting the standard value C 1 =47 J.1F I 25 V
Selectioo of C1 :
'1 should be such that,

But~
Xo s
=
1~ <Rc II RJ
oo
I at f =fL
.. XC2 S Rc/10
1.8 X 103
.. X C2 S 10

. <F-1567) Fig. 11.6

5 S (1 + 290) (RB + 3.115)

1
.. C1 :0:: 27t X lO X 180
Rg + (l + 290) X 3.115
5 <Ra + 906.46) . = (291) <Ra + 3.115)
. . C2 • :.:: 88.41 x w-6
· · C 2 2: 88.41 J.1F •••Ans.
5Rg + 4532.32 = 291Rg + 906.46
4532.32-906.46 = R a (29 1 _ 5 ) Selecting c2 =100 JJF/25 v
RB 12.67W = Bypass capacitor C£ : <;; should be such that,
Applying KVL to the base loop of Fig. 11.6 to get, Xa; S ReI loj at f =fL
Vm =
IBQ Ra + VaE + VE 1 3.115 ~ 10
3

:. Vm
6
(5.05 X l0- X 12.7 X 103) +0.7 + 5 · · 2n fL Cs s 10
: . V 111 - 5.76 V . · lO
. . <;; 2: 27t X lO X 3.115 X 103
.~ R1 ~ Vex;
ButVm = R +v x Vcx;
1 .'2 (Rl +~
x-
R1
•• CE 0!: 510.93 X 10-
6

Vee = 18V
Rs
: . V 111 = R x Vcx;
I

• • _R1 = -v--= 12.75.7X 16

Ra Vex;
11{
35.64 w

R,~
Ra - R,+~
.. R 1 R8 +~R8 = R,~
.. R,RB = ~(R, ~ Ra)
R 1 R8 35.64 x 12.7
:. R:z = (R1 - R8 ) = 35~64- 12.7
••. Ans.
~ = 19.73 k.Q
Step S : Coopting capacitors C 1 and Cz :
The coupling capacitors C 1 should be such that ii:s reactance Xct " Flg.ll.7 •

should be at least (1/10) of R; at the lowest frequency. :. <;; = 510.93 J.1F •••Alii.

:. .XCt s R~
10
,
I at f::; fL
Selecting C =470 J.1F 1147 JJF.
Step 6 : Av, Rt and R. of the deslgued ampli&r :
hc<(cyp) X Rc 330 X 1.8 X 1if
~ I Av I = ~ 4.5 x 103
.. 1
21tfL Cl
:s; 10
.. I Ay I = 132 (Greater than 100) •••Alii.
••
.. lO
, s c, .. R: = ~liRa
21t fL R, 4.5 X 12.7
lO , R' = 4.5 + 12.7
.. c, 0!: T1tfLRi
I

.. ·R'I = 3.32 W (Greater than 3 W)

~Ra
4.5 X 12.7
But R'I =
-
h~c iiRo=(h~e+Rs> 4.5 + 12.7 and Ro = Rc= 1.8W ••.ADs.

R: = 3 .32W

lis '*"**i''lt''''''"
 Electronic Devices & Circults-1 (Eiex.-MU)

Q, 3 DMign a single stlloe CS amplifier for audl~

Using the typical mutual transfer characteristics of Fig,
d assuming us obtain the value of IDQ corresponding to
4-108
-
11.38 an
frequency appllcationa suitable for operation upto v =_1.87 Volts. ·
low frequency of 20 Hz. Uae JFET type BFW-11 to os As shown in Fig.ll.8, the value ofiDQ is given by,
give output voltage of 2 Volta and voltage gain I ·JDQ =
1.2 mA . . .
Av I • 10. For dealgn u. . mutual characterletica of Thus the co-ordinates of the Q-pomt are,
Vae- loa (typ) given In the data sheet. Design two 1 )
Q (VGSQ• DQ
=
(-1.87 V, 1.2 mA) ... (2)
clrculta: ' ' . "t sed . If b'
Assuming that the type of b1as1.11g crrc~. u 1s se J.a.S.
1. To give zero-temperature drift of the Therefore the bias line wiD pass ~ough.the ongm and through the
operating Q-polnt and Q-poiot. The slope of the bias line eq~ to (1/Rg ).
i{
1
2. To give 10 = 108 = i 1088•
·· Rs = Slope of bias line
Ana.: 1.87 v - 1 558 lc.Q .
.. Rs . = 1.2mA- ·
Gi'ftll :fL =20 Hz, I Av I = 10, IFEI' BFW-11, Yo = 2 Volts
(rms) Seleeting the nearest standard value of 1.5 ill.
Part I : Circuit design to give zero-temperature drift : .. Rs =
1,5ill
Steps to be followed : .lo -
•-"*' an=0.5V
Step 1 : Calculate V GSQ : Y- "*1an=1mA
10
The condition for zero temperature drift as :
I vp 1- 1vGS I = 0.63
.. Vp = V 08 +0.63
The expression for 10 is, .

:. . Io

.·. Io
• [ Vas] .
But g. 1- Vp =g,
(F-1798) Fig. 11.8 : Mutual characteristics of BFW-11

Step 3 : _Calculate the value of vDSQ : .

gm The transconductance of JFET ·is given by,
· · lo = T[Vp- VQs1
= VGS + 0.63 to get, .. [ v ]
SubstiJuting Vp ~ - = &no 1- v~
8m
lo = T CVos +0.63- Vos1 Substi~ting the typical s~ifi.ed values fot: BFW-11 to get,
. . Io = 0.315 &o . &m 5 >< w-3
=
.
[1 .(-1.87) ]
(- 2.5)
Substituting the expressions for 10 and gm in the above
" gm = L26mS .
expresiioo to get,
2 For ensuring that the output of the amplifier is not distorted..

Ims[l~:;J = ·0.312[g~ (1 - ~:9] But V 0

VDSQ ~ VP + V0
(nus) = 2Y.
(peale) ... (3)

...G'1ven

• •
L ..
"08$
[t-
Vp
Vos]2 =
0.312·[-2Ioss]
. Vp
... (1)
..
:. Vo (peale> = 2 ..J2
=2.828 Volts
VosQ · ~ 2.5.+ 2.828 =5.3284 Volts
from the wec;ifications of JFET BFW-11 given in the data · · Select, V05Q = 6 Volts . . ..(4)
~beet we bave tbe typical values as follows : Step 4 : Drain resistance (Ro) :
Io.sc 7 mA. v, = - 2.5 V, rd =50 ill and gmO =5 m mho. The required voltage gain is 1 A 1 = 10. For a CS
Subldb!Cing lbele valuel in Equation (1) to get, amplifier with bypassed Rs. v
VasQ =-
1.87 Volts .~Ans.
I Av I = - 8m R~ ...(5)
Step l : 8ourf.e ......oc:e Its ;
where R'D rd Ro
The ~ mutual cransfer characteristic of the JFET = r11 IIRo= rd + Ro
BPW- 11 iau 1bowD iD fig. ll.S.
.. 10 = -s.n~

t :t'. r1 '.ll ftlllfJII l•

~lc Devices & Circuits-! (Eiex.-MU)
4-109
.. ~ "" lQ__ 10
8..,- 1.26 X 10:"]' =7.93 k.Q
7.93W

7.93 k:.Q = SOk X Rn

50k+R0
Solving for R0 to get.
. R0 = 9.424 kQ
Selecting tbe nearest highest value .i.e. 10 k.Q. Ra 1MO
:. Ro = IO.kQ
... (6)
Seledion of~:
Tbe value of Rm of the JFET is about 10 u n .
lv~. Hence too
small valueof o&'G will decrease R;.. and very
. high al . .
cause 1=.t.llge
~'-ft problem.s. v ue of~ will (F-1799) Fig. 11.9 : Complete designed_CS amplifter
':. Selecting Ro < 10 Mn . . I
:. . Ro ·= 1Mn .. ~(7)
Part II : Circuit design to give 10 =T :
StepS: Supply voltage Vnn : The procedure to be followed is as follows :
Applying KVL to the outpu~ loop of self bias circuit-CS amplifier Step 1 : Obtain VGSQ:
to get. Given that IDSS(typ) =7 mA. Therefore we ha'Ve to design the
amplifier circuit for IDQ = 3.5 inA. ·
Voo :::: VRS + VDSQ + VRD .
Referring the typlt~>mutual characteristics of Fig.11.8 and
.. Voo :::: IDQRs + V00q+IDQRD finding the value of VGSQ corresponding to IDQ = 3.5 mA. From
.. VDD :::: IDQ <Rs + RO) + vDSQ Fi~. 11.8,
.. Von. :::: 1.2 (iO + 1.5) + 6 =19.8·Volts VGSQ = -0.8 Volts . ... (13)
.. Voo =20V ... (9) Therefore the co-ordinates of the Q-point ~•
Step6: ~piing capacitors (C1 , Ci) : Q2 (VGSQ• I~ = (- 0.8 v. 3.5 mA) ... (14)
The input coup~g capacitor C 1 is _selected to satisfy the following . Step 2 : Obtain the source resistance Rs :
Draw the second bias line passing through the Q-point Q2
condition,
. 3 and the origin. -The reciprocal of the slope of this bias line is Rs·
Xcl = 0.1 R;, = 0.1 X 1 M.Q =100 X 10 1 0.8V
1 3 · · Rs = Slope = 3.5 mA
.. 21tfLCI = 'wo x 10
.. Rs = 228.0
But fL = 20Hz
Selecting the nearest standard valu~ of 220 .Q.
1
·· Cl = 2nx20x100x10 =0..1 JJF/ZSV .. Rs = 220.0
Step_3 : Tranconductance &. :
c,
= 0.1 J.LF /25 v ....(10)
Similarly, we
coupling capacitor ~ is selected to satisfy the ~ = g~[ 1- V:sJ
following condition, , But gmO = . 5 mS, • Vp = -2.5 V and VGS = -0.8 V
Xo = OJ. Ro
1 .. ~ = 5 X 10-
3
[ 1- (~:~)]
.. 2nfLCz = 0.1 x7.93W
.. gm = 3.4 mS ... (16)
r 1 =9.5S J.lF Step 4: .Calculate Q-polnt draiil to source·voltage VDSQ:
.. '-'2 = 21t fL X 793 For undistorted ()utput voltage,
... (11)
:. Cz =10 J.LFI2S V VosQ ~ Vp+Vo(pcak>
Step 7 • Bypass capacitor (Cs) : · .. VosQ ~ 2.5 + 2 x-{2 .. Vorms= 2 V
• • ,_....aA satisfy the following condition,
ByPass capacitor C5 JS &eRN..,.. to . . VnsQ > 5.32 V
Xa = 0.1 Rs . . Select VosQ 6V = ...(17)
1 =
0.1 X 1500 Step 5 : Drain resistance R 0 and biasing resistor Rc :
2n.fLC5 The required voltage gain · IAv I = 10
.. 1 =
53.05 J.LF
'
/. C 8 =
2 x n x 20 x ISO But IAv I = gm R
D
• hi"""'r s· --"ft,..~ value.
Selectiog the nearest &>- WJUA~U ...(12) Substituting the values to get,
. <; = 68 J.lF!2S V ' ~ 10
.. . · shown in Fig. ll.9. Ro = gm = 3.4 X 10-3 = 2.941 ill
1be complete circwt JS as
Bectronlc Devices & Clrcults·l (E1ex.·MU)
rdx R0
-
4·110

But R~ • (r11 II Ro) "' ;-:;:R" and rd =50 k.O

d 0
50k XRp
:. 2.941 k = (50k + Ro)
Solving for R0 to get,
R0 =
3.12 .k n
Selecting a higher standard value . 1MO
Cs=470)1F
.. Ro = 3.3 ill ...(18)
Assuming the self bias circuit used for the amplifier biasing
to get,
'Ro 1 Mn = <F-1800) Fig. 11.10 : Complete designed circuit for part ll
The selection criterions are same as those used in part I of
this design assignment a. 4 Design. a c.s.
amplifier using FET type BFW ·- 11
Step 6 : Supply voltage V DD : to meet the following specifications :
In Part I , =
Av ~ 10, V0 3 Vac , R, better th~n 1 M.O, flbetter
IOQ ( Ro + Rs) + VosQ
Voo ~ than 25Hz.
.. ~ 3.5 ( 3.3 + 0.22) + 6
V DO • Assume the ·external· load connecte~ RL 33 kQ =
.. V00 ~ 18.32 Volts. · between the output a~ ground. Assume suitable
. . Selecting , V00 = 20 V ... (19) supply potential Voo·
Step 7 : Calculate the coupling capacitors (C1, <;> : H~w- will you proceed for above design If zero
temperature drift Is necessary ?
FOI' seledioD of c 1 : · ·
Dec. 03. May 09
R;..Ro
Xcl = w=w Ans.:
The required circuit diagram is as shown in Fig. 11.11.
1MQ s
.. 27tfLCI
= ---w-=1 x10
But fL = 20Hz
1
.. cl = 27tX20x1x105
cl = 79.57nFn5 v ... (20)
For seledioD of<; :

~
Xo = 10
0 rd xR
50x3.3
But ~ = ( rd + R0 ) =(50 + 3.3) 3.o95 k.Q .
.. Xo = 309.5 .a
_1_
.. 2mLc;
= 309.5
• <F·1857) Fig. 11.11 : CS JFET amptifter
1 . '

•• C:z = 27t X 20 X 309.5 = 25·7 ~ Step 1 : Selection of FET :

Selecting FET BFW-11 wifh the following specifications :
Selecting , C:z= 33 ~I 25 V ...(21)
loss =7 rnA VP =- 2.5 V V DS(max) -'
- 30 V
Step 8 : CakJalate the bypass capacitor Cs :
~=5.6mAIV rd=50kn
For ldedloa of C8 :
Step :Z :Selecting IDQ.:
Xes = -fg =22 .0 ... atfL =20Hz A reasonable minimum drain current level can be assumed
to be 1 rnA.
Step 3 : Cakulate vGSQ :

•
<; = 2 7t X 201 X 22 =361.7 } J.lF As,IOQ = .loss[l- V~oJ2
. 2
Select tbe nearest highest value.
: . C8 • 470 J.LF/25 V ... (22) .. 1 = 7 [·~ -~]
-2.5
The complete dealgned circuit is as shown in Fig.ll.lO.
·. V 0 SQ =- 1.56 Volts

Step 4 : Calculate VD8Q and V8 :

As, VDSQ<mln>:: Vp+lV-V08 = 2.5+1+1.56

t: ' I ' 'J II Ill I I II II ·,
.;leetronlc Qevloes & Clroulta-1 (Eiex.·MU) 4-111
= 1.~ Volts
Step 5 : Cakulate 1m : .. x0 = 5 · 21~ k := 526.1 n
8m = sm0[ 1- v~ '' C2 =
1
2n X 25 X 526.1 = 12 ~ •••ADS.
But gmO = 5.6mAJV

.. .
&,, =
(- 1.56)]
•5
.. Dealgn for a full wave rectHier, an L type LC filter
J~hlch glvea a de output voltage of 1OV at a load
5.6 [ 1 - -2.5 =2.1 mA/V
current of 100 mA. The allowable ripple factor Ia
Step 6 : Calculate R0 :
• 0.02. Dcc.09. Dec. 10 Dec 11
Gain IAvl = 8m (rd II Ro II Rl)
Ana. :
:. 10 = 2· 1 (50 II Ro II 33) = 2.1 (19.88 11 R )
19.88 R0 0
.
Given: LC filter, v l..dc =10 V, Il..dc = too·mA, r = 0.02.
... 19.88+R0 = 4.76 Assuming supply frequency is 50 Hz.
Step l: Circuit diagram :
·• R0
6.26 k.Q = ...Ans.
Step 7 : Calculate V ~ R8 and v00 :
Assuming Ro = = 6.26 kn
R8
· · Vs = IOQRs =1 X 6.26 =6.26 Volts
Applying KVL to the drain source circuit to write,
Voo = l~o + VDSQ(min) + Vs -·
= (1 X 6.26) + 1.94 + 6.26 <F-1144) Fig. ll.U
•• Voo = 14.46 :Y
Step 2 : . Calculate RL , Land C :
Assuming . V00 = 15 Volts ...Ans.
VLdc 10
Step 8 : Calculate VG, R1 and R1 :
RL = -1-= 100mA =IOO.Q
Required , R1 :2:: 1 MQ l..dc
1
•. CRt II Rz) ; : : I MQ

..
RJ Rz
CRt + Rz)
..,
~
1 ,..n
lVL)ot. ...(1)
2
0.0 = 6 Vz X 41t2 X (50)2 X LC
Also VG = Vs + VGS =6.26- 1.56 =4.7

Va· =
R2
Rt +Rz xVoo=4.7
LC = 6Vz X 41t2 ~ (50) 2
X 0.02
LC = S.97 X 10-~
Rz Step 3 : Bleeder resistance R8 :
• • Rl +~ X 15 = 4.7
VLdc
Rz ·...(2)
RB = -~- ·
•• 1) = 0.3I33 b
Rt + ..'2 . Assuming bleeder current Ib is 10 % of the load current
Substituting Equation (2) into (1) to get, . ·· :. Ib - 10 mA -'
R 1 X 0.3133 :2:: I MQ 10
:. Rt ;;::: 3.19 M.Q ... RB = 10 1 k.Q =
. . Select R 1 3.39 Mn = •••Ans. Step 4 :· Calculate·Lc and selection ofL :
3
Substituting this value into Equation (2) to get, R8 1 X 10
. ~ :::= (0.3133 X 3.39) + 0.3133 ~ Critical inductance Lc ; 00 _3 x 21t x 50
•••Ans. =
:. Rz = 1.55 MQ f.06H . ~
Step 9 : Coupling capacitors : Step 5 : Selecting L = 2 H (Higher than Lc)
. Xct =
.& -
... at fL - 25 Hz LC = 5.97 X 10-S
10 5.97 X 10 -S
3.39 X 1.55
But ~ = Rt II ~ =3.39 M 111.55 M =3.99 + 1.55 ,. c = 2
.. C =
2.98 x 10-S
I
.. c =
29.8 J.lF
Xct= 106.3 w =21tfL cl Step 6 : Rating of the diodes :
Each diode conducts for · one half cycle of the rectifier
1 output Hence the average current through each diode will be half
Ct= 27t X 25 X 106.3 X 10 of the maximum load current.
...Ans.
C 1= 59.88 nF ll..dc
Selcctiog C1 = 100 nF . . Average current through diode 2 50 mA = .=
(R0 II RJ (6.26 k !l 33k) .. 11¥1 = somA
Sinillar1y Xc = 10 = 10

·cis I! a :. II •, II Ill I I II II !,
 Electronic Devices & Circults-1 (Eiex.-MU)
. hi h barges to
The load voltage is the voltage across C w c c .
Vm volts. With a very small value of r, Assuming that the npp1e
voltage.is small. .. so= 2xso xCJ
:. Vl.dc "t Vm = lo'V 1 -2xl0-
4
J.if
PIV of each dibde = V = tOV . · .. C1 = 2xsox50
Hebce selecting. the diode ~ving a PIV rating higher than 10 V.
Step 7 : ~tings of transfonner : ••
cJ = 200 J.IF
. •
. al
th 1t section filter to be symmetri« ,to get,
Assunung e ..
vm ~ =
c1 200 J.lF= ···Ans.
Secondary.nns voltage Vsnns =_r;:, =7.071 . .. C and r into Equation (4) to get
. v2 Substttuttng 1 "-'2
. Nt 230 -9
• • Turns ratto N
2
= 7.071 = 32.52 3 X 10 0' 0.075 H
L = (200 X 10- :) .
...Ans,

Q. 6 A tuU wave rectifier using a center tapped Thus the filter components are
· transformer with two diodes gives output voltage c. 1
=
~ = 200 J.lf, L = 0.075 H
of 250 V to a resistive load, the current being Step 3 : Ratings of diodes :
75 ± 25 mA. H the ripple factor is 0.001, cai.culate · The PIV of each diode will be 2 Vm'
the specHication of the devices and components . . For a n ~ filter ,
required If the filter used is n-fllter.Draw comp18te ILdc (max)
circuit diagrams In each c~~- Vl.dc = Vm- 4fC ... (6)
3
Ans.: 100x 10-
Given :Vl.dc = 250 V, Il.dc = (75 ± 25) rnA, r = 0.001 .. 250 = Vm- 4x50x200X 10- 6
Step 1 : Cakolate the range of RL : .. Vm 250V =
For a full wave rectifier with ·a 1t type filter the expression . . PIV · =
2 Vm =500 V
for ripple factor is givt)n by , . · Step 4 : Transformer ratings :
1 rms secondary voltage
r = ...(1)
. 4-..f3 f ffi, L C1 c; RL vm 250
ro, = 2nf:;;2x3.14 x 100=628.31 ... (2) v.(nns) = -../2 =-../2 =176.7 v

Considering the worst case condition RL =~~ Nl 230

· v;..., 2so · .. Turns ratio N2 ·= .176.7 =1.3
Ruru,; = -y - = 100 mA = 2.5 k.Q
l,.dc(max)
... (3)
rms secondary current
Ste., 2 : Calculate L, C1; C2 : . = ILdc(max) =100 mA
Substitute Equations (2) and (3) into Equation (1) to get, 01 L
. . 1
1
0.00 = 4-.,J3 X 50 X (628:31l L C1 C2 X_2.5 X 103
L C1 ~ =:.. i.92
X 10- = 3 X 10-
9 9
••• (4)

Calculating the value of C1 with an ass.umption that the

peak to peak ripple voltage across it is one fifth of the average de
voltage.
. · Ripple voltage ~ . . 02 ·
. 1
ll VJH = j XYu: (F-2672) Fig. 11.13 : Circuit diagram of n type filter
. 250
='·j=50V ._..(5)

[J[J(J

ea s y SOIUliOIIS

. \
., ______• --- --------- ------------- -- ... ~ .