FACULTY OF ENGINEERING, SCIENCE & TECHNOLOGY

Assignment # 02
Subject: FPGA Based System Design Instructor: M. Amin Qureshi & Syed Rizwan
Allocated Marks: 10

Topics Covered: Verilog Coding – Behavioral Modeling

Objective: Design a seven segments decoder for common anode seven segments in Verilog.
Simulate your designed code with test-bench and Complete given table:

Decimal Binary code Hex Code Output

Value (4 bit input) (7 bit =
gfedcba)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Hint: Use behavioral modeling to perform the task accordingly.