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A Ku-band CMOS LNA with transformer feedforward gm-boosting

technique
I l l l l l i
Weiqiang LU , Chenxi Zhao , Yiming Yu , Zhengdong Jiang ,Yunqiu Wu , Huihua Liu and Kai Kang
I
University of Electronic Science and Technology of China, Chengdu, 611731, P.R China
Email: kangkai @uestc.edu.com

Abstract - This paper presents the design of a Ku-band


Voo
CMOS low noise amplifier (LNA) with noise reduction and gain
improvement. A transformer feedforward gm-boosting technique Ro Ro
is employed in a single-ended common-gate LNA to reduce the
noise figure (NF) and improve the gain simultaneously. A single
vy
cascode is the second stage of the LNA. Fabricated in 0.18um RF
CMOS process, the LNA exhibits a minimum noise figure (NF) of
3.6 dB at 17.5 GHz and a highest power gain of 18 dB at 17.5GHz 4kTV/gm�f -
-
Vin
-
in measurement. The LNA only consumes 7mA from a power
2
supply of 1.8V and the total area of this design is 0.6*0.8 mm • -
Index Terms - CMOS, lower noise amplifier, gm-boosting, (a) (b)
transformer, Ku-band

Fig. 1. (a) A conversional common-gate stage (b) Noise analysis


I. INTRODUCTION ofM1·

With the development of communication and radar, the achieve gm-boosting technique in microwave low noise
operating frequency of components trends toward higher amplifier, this paper presents a Ku-band CMOS LNA based
frequencies with a high data-rate capacity. Extensive research on transformer feed forward gm-boosting technique.
on single-chip integrations in several GHz has been This paper is organized with following section. Section II
demonstrated in wireless communication applications [1]-[3], analyses the common gate stage with transformer feedforward
but few works have been done on Ku-band applications. In gm-boosting technique including the effect of gain and noise
this frequency band, there are some important applications, figure. The measurement results of the designed LNA and a
such as satellite communications and phased array systems. comparison with other designs are presented in Section III.
More work should be done in this frequency regime.
It is possible to design microwave circuit for good
II. LNA WITH TRANSFORMER FEED FORWARD
performance with the advance of silicon semiconductor
GM-BOOSTING TECHNIQUE
technology, because the short scale CMOS devices exhibit
good electrical properties including high fmax , ft and A conversional common-gate stage with inductive loading
low NFmin. In the past few years, many microwave circuits is widely used in LNAs at several GHz frequencies for its
fabricated with CMOS technologies have been reported [1]­ superior matching and linearity. But it suffers from the
[3]. The ft ofTSMC 180nm process is about 60GHz. it can contradiction of input match and noise performance. Let us
be used in this Ku-band design. consider a circuit topology as Fig.l (a). At the resonance
CMOS low-noise amplifiers (LNA) with low noise figure frequency, L1 resonates with C1, and RD is the loss of L1. If
and high gain are among the most critical and challenging channel-length modulation and body effect are
components in RF and mmWave IC design. In order to neglected,Rin l/gm. thus the dimensions and bias current
=

1
improve the performance of microwave circuits, some novel of M1 are chosen so as to yield gm l/Rs (500)- for
= =

configurations proven useful at low frequencies have been input match. As for noise analysis, modeling the thermal noise
applied in microwave frequencies regime. Recently, gm­ of M1 as a voltage source in series with its gate, V;1 =

boosting technique applied on LNA has been reported [3]. The 4kTy/gm, where y is the "excess noise coefficient", and we
gm-boosting technique technology was firstly proposed to have
efficiently improve the gain of a relatively low frequencies
low noise amplifier in [3]. However, according to the author's
knowledge, no LNAs with gm-boosting technique operate
VZ-I
n,Dut M1 = VZ
n1
(A v ) 2 =
4kTy
Bm
( )
RD

Rs + 1
2

=
kT
Y
RD

Rs
2

(1)
8m

more than 10 GHz have been reported until now. In order to

978-1-5090-2017-1/16/$3l.00 ©2016 IEEE


(a)
(a) -
Fig. 3. (a) The fabricated LNA with transfonner feed forward gm­
K1 boosting stage and cascode stage (b) The ill icrophotograph of the
proposed LNA.
vpEf€v, the Fig.2(b) is
1:n
(c) -9mRDVn1
Vn,out 1M1 -
- (5)
(1+nKl)9mRs+ 1
Fig. 2. (a) The LNA with transfonner feedforward gm-boosting If the input is matched, Rin =-1/(1+nK1)9m= Rs and
technique (b) Noise Analysis of the transformer feedforward gm­
boosting LNA (c) the model of transformer.
Av=(1+nKl)9mRD/2, than
( -9mRoVnl) 2+4kTRD
to obtain the noise figure, �I
n ,out Ml+ 4kTRD 2
NF = 1 + = 1+
NF = 1+�IMl 4
+ kTRo =1 y+_4_
+ (2)
4kTRs(Av)2
4kTRs C1+nK�9mRo ) 2
kT Rs (Av)2
4 9mRo 4
=1 + Y + (6)
From the equation, it is obvious that a higher gm yields a (1+nK1) (1+nK1)9mRD
lower NF but the 9m is determined from the input match.
A novel topology is proposed the common gate stage with Compared with the equation (2), The equation (6) reveals that
transformer feed forward gm-boosting technique [3] as the the NF caused by Ml can be lowered (1 +nK1) by
Fig.2(a) showed. Let us review transformer topology Fig.2(c) transformer feed forward gm-boosting technique.
at first. For a ideal transformer,the coupling coefficient Kl = 1,
and
III. FABRICATION AND MEASUREMENT RESULTS

�1 The designed LNA as the Fig. 3(a) includes two stages. The
Vs: It" =n: 1 = �L;: (3)
first stage employs the transformer feed forward gm-boosting
technique based on common gate stage. A cascode stage is
Where VP' Vs is the primary and second voltage, n is The turn used as the second stage. The transformer plays a important
ratio of the transformer, n > 0, Lp' Ls is the primary and role on noise reduction and gain improvement. In order to
second inductance. In fact [4], 0 < Kl < l.So the gate voltage achieve a high quality factor, the primary and secondary rings
of Ml in the Fig.2(a) is Vg =-n Yin K1, We get !::,.Vgs = of the transformer are implemented in the ultra thick top metal
-n KlYin - Vin· As we all known, gm!::,.Vgs =-Vout /RD' Than layer. The thickness of the ultra thick top metal is 4.6 f.!m.
Vout This LNA was fabricated in a standard CMOS 180nm
-=9m(1+nK1)RD (4) process. Fig. 3(b) shows the microphotograph of the LNA ,
Vin
which occupies 0.6*0.8 mm2, including the pads. The chip is
Compared with the gain of common gate stage, the equation mounted on a printed circuit board (PCB) and measured by
reveals that the gain is improved (1+nK1) by transformer chip-on-board technique. The measurement and simulation
feedforward gm-boosting technique since nKl > O.
results of the gain, and the input/output matching is showed in
As for noise, the source noise voltage of Mlin the Fig.2(b)
Fig. 4. The gain is 18 dB at 17.5 GHz, and the input/output
is Vn,s =- Vn,out Rs/RD .This noise voltage is added to the
matching is below 10 dB at 17.5 GHz. the measurement result
gate by the transformer, So the gate noise voltage of Mlin the
is agree well with the simulation. The simulation results of the
Fig.2(b) is v,.,9 =Vn,out RsnKdRD +Vn1. As we all known,
NF is 3.6 dB at 17.5 GHz as the Fig. 5 showed. The measured
9m!::" Vgs=-Vout / RD' Than the output noise voltage of Ml in PldB is -12 dBm for various input powers.Table I provides a
Table I K-band LNAPERFERMANCE COMPARISION
20 Process Frequency Gain NF PDC Reference
_simulated 511
-+-simulated 521
15 �simulated 522
(GHz) (dB) (dB) (mW)
130nm 25 27.5 3.88 16.8 EuMIC2015
10
CMOS [5]
CD 5
"0
N 65nm 22.45 20.46 3.4 12 ISCAS2013
N 0
U)_ CMOS [6]
N -5 130nm 18 22.4 4.1 36 ISSCC2008
U)
;: -10 COMS [7]
U)
-15 130nm 24 14.7 4.3 20.2 RFIC2009
-20 CMOS [8]
14 15 16 17 18 19 20
180nm 17.5 18 3.6 12.6 This work
CMOS
Freq(GHz)

consumption. The measurement results show a gain of 18 dB,


(a)
an NF of 3.6 dB, an PldB of -12 dBm, and an input matching
(S11)/ output matching (S22) of less than 10 dB at 7 rnA
power consumption with a 1.8 V supply voltage.
_simulated NF
6.5

6.0
REFERENCES

5.5
[I] Kang, Kai, et al. "A 60-GHz OOK receiver with an on-chip
antenna in 90 nm CMOS." Solid-State Circuits, IEEE Journal of
� 5.0 45.9(2010): 1720-1731.
u. [2] Vi, Kai, et al. "A Q-band CMOS LNA with noise cancellation."
Z 4.5 Wireless Symposium (lWS), 2014 IEEE International. IEEE,
2014.
4.0 [3] Li, Xiaoyong, Sudip Shekhar, and David J. Allstot. "G m­
3.5
boosted common-gate LNA and differential Colpitts
VCO/QVCO in 0. 18-f.!m CMOS." Solid-State Circuits, IEEE
14 15 16 17 18 19 20 Journal of40.12 (2005): 2609-2619.

Freq (GHz)
[4] Long, John R. "Monolithic transformers for silicon RF IC
design." Solid-State Circuits, IEEE Journal of 35. 9 (2000):
1368-1382.
(b) [5] Dang, J., et al. "A K-band high gain, low noise figure LNA
using O. 13-f.!m logic CMOS technology." Microwave Integrated
Circuits Conference (EuMlC), 2015 10th European. IEEE,
Fig. 4. (a) Measurement (red line) and simulation (black line) 2015.
results of the SII,S21, S22 vs. frequency. (b) simulation (black line) [6] Xu, Jianfei, et al. "A 3.4 dB NF k-band LNA in 65nm CMOS
results of the NF vs. frequency. technology." Circuits and Systems (lSCAS), 2013 iEEE
International Symposium on. IEEE, 2013.
performance summary of the proposed LNA and gives [7] Cao, Yiqun, Vadim Issakov, and Marc Tiebout. "A 2kV ESD­
comparisons of this work with other k-band LNAs fabricated Protected 18GHz LNA with 4dB NF in O.13f.!m CMOS." Solid­
in CMOS process. It shows that the LNA of this work has a State Circuits Conference, 2008. ISSCC 2008. Digest of
Technical Papers. IEEE International.IEEE, 2008.
relatively high gain and low noise figure under low power
[8] Yeh, Jin-Fu, et al. "A 24-GHz transformer-based single-in
consumption. differential-out CMOS low-noise amplifier." Radio Frequency
Integrated Circuits Symposium, 2009. RFIC 2009. IEEE. IEEE,
2009.
IV. CONCLUSION

In this paper, a low noise amplifier is presented based on the


transformer feed forward gm-boosting technique in Ku-band
in order to reduce noise figure and improve gain. The
proposed LNA was fabricated with a 0.18 f.!m CMOS process
and measured. The measurement frequency was 17.5 GHz.
Results demonstrated excellent performance with low power

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