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Obsolete Product(s) - Obsolete Product(s) : STI10NM60N
Obsolete Product(s) - Obsolete Product(s) : STI10NM60N
Features
TAB
VDS RDS(on)
Order code ID PTOT
12
3
STI10NM60N
@TJmax
650 V
max.
< 0.55 Ω
( s
10 A ) 70 W
ct
I2PAK
• 100% avalanche tested
d u
• Low input capacitance and gate charge
r
• Low gate input resistance o
Figure 1. Internal schematic diagram
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'7$%
l t
Applications
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• Switching applications
s o
b
Description
*
) -O This device is an N-channel Power MOSFET
ct
MDmesh™ technology. This revolutionary Power
MOSFET associates a vertical structure to the
6
d u company’s strip layout to yield one of the world’s
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ........................... 6
4
s )
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
(
4.1 2
ct
I PAK package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
u
o d
5
r
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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1 Electrical ratings
VISO
r
Insulation withstand voltage (RMS) from all three leads to
o V
TJ
external heat sink (t = 1 s; TC = 25 °C)
Operating junction temperature
e P
Tstg Storage temperature
l e t - 55 to 150 °C
s o
2. ISD ≤ 10 A, di/dt ≤ 400 A/µs, VDS peak ≤ V(BR)DSS, VDD = 80% V(BR)DSS.
O b
) -Table 3. Thermal data
t(s
Value
Symbol Parameter
u c I²PAK Unit
Rthj-case
o d
Thermal resistance junction-case max. 1.79 °C/W
Rthj-amb
P
Rthj-pcb
r Thermal resistance junction-ambient max.
Thermal resistance junction-pcb max.
62.50 °C/W
°C/W
e t e
ol
Table 4. Avalanche characteristics
bs
Symbol Parameter Value Unit
O IAS
Avalanche current, repetitive or not-
repetitive (pulse width limited by Tj max.)
4 A
2 Electrical characteristics
ID = 1 mA, VGS = 0
Drain-source
V(BR)DSS ID = 1 mA, VGS = 0, 600 V
breakdown voltage 650
TC = 150 °C
(s)
Zero-gate voltage
VDS = 600 V 1 µA
IDSS drain current
(VGS = 0)
VDS = 600 V, TC = 125 °C
c t 100 µA
Gate-body leakage
u
od
IGSS VGS = ± 25 V ± 100 nA
current (VDS = 0)
VGS(th)
Gate threshold
voltage
VDS = VGS, ID = 250 µA
P r 2 3 4 V
Static drain-source
e t e Ω
RDS(on)
on-resistance
VGS = 10 V, ID = 4 A
o l 0.53 0.55
b s
- O
Table 6. Dynamic
Symbol Parameter
ct
Ciss Input capacitance - 540 - pF
du
Coss Output capacitance - 44 - pF
VDS = 50 V, f = 1 MHz, VGS = 0
Crss
r o
Reverse transfer
capacitance
- 1.2 - pF
e P Equivalent
Ob Qg
Qgs
Total gate charge
Gate-source charge
VDD = 480 V, ID = 8 A,
-
-
19
3
-
-
nC
nC
VGS = 10 V
Qgd Gate-drain charge - 10 - nC
1. Coss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss
when VDS increases from 0 to 80% VDSS.
e
ISD = 8 A, di/dt = 100 A/µs
let
Qrr Reverse recovery charge - 2.12 µC
VDD= 60 V
IRRM Reverse recovery current 17 A
trr Reverse recovery time
s o - 315 ns
Qrr Reverse recovery charge
O b
ISD = 8 A, di/dt = 100 A/µs
VDD= 60 V TJ = 150 °C
2.6 µC
IRRM Reverse recovery current
) - 16.5 A
t ( s
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
u c
o d
P r
e t e
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b s
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1µs
10
10µs
is
R rea
)
on
100µs
S(
ax a
D
m this
by n
1
d ni
1ms
ite io
m at
Li per
O
10ms
0.1
Tj=150°C
Tc=25°C
( s )
ct
Single
pulse
0.01
0.1 1 10 100 VDS(V)
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Figure 4. Output characteristics
AM03947v1 ID
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Figure 5. Transfer characteristics
AM03948v1
ID
(A)
14
VGS=10V
(A)
14
l e t
6V
s o
12
VDS=20V
b
12
10
O 10
( s )- 8
6
6
4
c t 5V
u
4
2
o d 2
0
0 5
P r 10 15 20 25 30
4V
VDS(V)
0
0 2 4 6 8 10 VGS(V)
e t e
Figure 6. Normalized VDS vs. temperature Figure 7. Static drain-source on-resistance
o l
VDS AM09028v1
RDS(on)
AM00891v1
b s (norm)
1.10
ID=1mA (Ω)
O 1.08
1.06
0.56
1.04 0.52
1.02
1.00 0.48
VGS=10V
0.98
0.96 0.44
0.94
0.92 0.40
-50 -25 0 25 50 75 100 TJ(°C) 0 2 4 6 8 ID(A)
8
100
6
Coss
4 10
( s ) Crss
ct
0 1
0 5 10 15 20 Qg(nC) 0.1 1 10 100 VDS(V)
e P AM03954v1
1.10
ID=250µA (norm)
2.1
l e t ID=4A
s o
1.9 VGS=10V
1.00
O b 1.7
1.5
)-
1.3
0.90
t ( s 1.1
0.80
u c 0.9
o d 0.7
Pr
0.70 0.5
-50 -25 0 25 50 75 100 TJ(°C) -50 -25 0 25 50 75 100 TJ(°C)
e t e
s ol
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3 Test circuits
Figure 12. Switching times test circuit for Figure 13. Gate charge test circuit
resistive load
VDD
12V 47kΩ
1kΩ
100nF
RL 2200 3.3
μF μF
VDD IG=CONST
VD Vi=20V=VGMAX 100Ω D.U.T.
VGS
RG D.U.T.
2200
μF 2.7kΩ
( s ) VG
PW
47kΩ
c t
1kΩ
d u
AM01468v1
PW
r o AM01469v1
O b L
)-
FAST L=100μH VD
G D.U.T. DIODE 2200 3.3
μF μF VDD
25 Ω
S
B B
B
D
t (
μF
s
3.3 1000
μF
VDD ID
G
u c
RG
o d S
Vi D.U.T.
P r Pw
e
let
AM01470v1 AM01471v1
so
Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform
O b VD
V(BR)DSS
tdon
ton
tr
toff
tdoff tf
90% 90%
IDM
10%
ID 10% VDS
0
4 Package information
( s )
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P r
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(s )
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O b 0004982_Rev_H
A 4.40 4.60
A1 2.40 2.72
b 0.61 0.88
b1 1.14 1.70
c 0.49 0.70
c2 1.23 1.32
( s )
ct
D 8.95 9.35
du
e 2.40 2.70
e1 4.95
r o 5.15
E 10
P 10.40
ete
L 13 14
ol
L1 3.50 3.93
L2 1.27
b s 1.40
- O
(s )
c t
du
r o
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l e t
s o
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5 Revision history
( s )
ct
16-Nov-2012 6 Inserted new package and mechanical data: I²PAK
18-Jul-2013 7
Updated Section 4: Package mechanical data.
Minor text changes.
d u
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Part numbers STD10NM60N, STF10NM60N, STP10NM60N,
02-Dec-2015 8
P
STU10NM60N have been moved to a separate datasheet.
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e
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