Latches:

Storage elements that operate with signal levels (rather than signal transitions) are referred
to as latches; those controlled by a clock transition are flip-flops. Latches are said to be level
sensitive devices; flip-flops are edge-sensitive devices. Latches are the building blocks of flip-flops.

RS / SR Latch with NOR:

Note: If any-one the inputs of NOR gate is “HIGH” then output will be “LOW”.

Logic Circuit: Function Table

Conclusion:

SR Latch with NAND:

Note: If any-one the inputs of NOR gate is “LOW” then output will be “HIGH”.

Logic Circuit: Function Table

Conclusion:

SR Latch with Control input:

Logic Circuit: Function Table
D Latch (Transparent Latch):
Logic Circuit: Function Table

Draw the graphic symbol for the following:

SR Latch with NOR gates SR Latch with NAND gates D Latch

Clock Pulse:

Find out Level (Positive & Negative) and

Transition /edges (Positive & Negative) for the
given clock pulse.

Block diagram of D Flip flop (Master – Slave):

D Flip flop (Master – Slave):

Comment
If Master is Positive latch and Slave is Negative latch?
If Master is Negative latch and Slave is Positive latch?
If Both are Positive /Negative latches?

Is it Positive or Neative D Flip flop?

JK Flip flop :

T Flip flop:
Clocked Sequential Circuit or Synchronous Sequential Circuit:

There are two types of problem:

(i) Logic Circuit to State Diagram
(ii) State Diagram to Logic Circuit

Procedure for Logic Circuit to State Diagram (Analysis of clocked sequential circuit):
(i) Logic Circuit
(ii) State Equation / Characteristic Equation
(ii) State Table
(iii) State Diagram
P1.1: Consider the below problem (Logic Circuit to State Diagram)
(Note: It is a Mealy Machine because Output (y) depends on present state
output (A,B) and Input(x))

Step 1: Logic Circuit Step 2: State Equation:

(or)

(or)

Step 3: State Table (Using State Equation and Step 4: State Diagram
Characteristic table of the Flip flop)
P1.2: Consider the below problem (Using JK Flip Flop)
(Note: It is a Moore Machine because Output depends only on present state
output)

Step 1: Logic Circuit Step 2: State Equation:

Step 3: State Table (Using State Equation and Step 4: State Diagram
Characteristic table of the Flip flop)
P1.2: Consider the below problem (Using T Flip Flop)
(Note: It is a Moore Machine because Output (Y) depends only on present
state output (A, B))

Step 1: Logic Circuit Step 2: State Equation:

Step 3: State Table (Using State Equation and Step 4: State Diagram
Characteristic table of the Flip flop)
FSM:
Procedure for State Diagram to Logic Circuit (Synthesize Problem):
(i) State Diagram
(ii) State Table along with Excitation Table
(iii) State Equation
(iv) Logic Circuit

P2.1: Consider the below problem (Using D Flip Flop)

(Note: It is a Moore Machine because Output depends only on present state
output)

Step 1: State Diagram Step 2: State Table with Excitation Table :

DA DB

Step 3: State Equation (Using Excitation Step 4: Logic Circuit

Table of the F/F )
P2.2: Consider the below problem (Using JK Flip Flop)

Step 1: State Diagram Step 2: State Table with Excitation Table :

Step 3: State Equation (Using Excitation Step 4: Logic Circuit

Table of the F/F )
P2.3: Design a 3-bit up counter using T F/F
Step 1: State Diagram Step 2: State Table with Excitation Table :

Step 3: State Equation (Using Excitation Step 4: Logic Circuit

Table of the F/F )
P2.3: Counter with unused state using JK F/F
Step 1: State Diagram Step 2: State Table with Excitation Table :

Step 3: State Equation (Using Excitation Step 4: Logic Circuit

Table of the F/F )
(NOTE : After the K-map)

00 01 11 10
( B C ) ( B•C ) (BC) ( B•C )
0
0 0 X 1
(A)
1
X X x x
(A)
 P.S or Q(t) I/P N.S or Q(t+1) O/P F.F I/Ps
A B X A B Y DA DB
0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 1
0 1 0 0 0 0 0 0
0 1 1 1 0 0 1 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 0 0 1 0 0
1 1 1 1 1 1 1 1

00 01 11 10
(B  x) ( B•x ) (Bx) ( B•x )
0 0 1
0 0
(A)
1
0 1 1 0
(A)

DA  A  x  B  x