Part – A

Q1: The access time of cache memory is 100 ns and that of main memory is 1000 ns.
If cache hit ratio is 0.85, determine the effective access time of the system.
Ans: - Access time(EAT)= (Cache hit ratio * Cache access time) + (1- Cache hit
Ratio) * Main memory access time
EAT = (0.85 * 100) + (1- 0.85) * 1000 ns
EAT = 85 + 0.15 * 1000 ns
EAT = 85 + 150 ns
EAT = 235 ns
The effective access time is 235 nanoseconds.

Q2: A digital computer has memory unit of 64K x 16 and cache memory of 1K
words. If direct mapping policy is used, determine the number of bits in:
(a) Main Memory address
(b) Cache Memory address
(c) Tag and Index fields
ANS: 1). Main Memory address: -
The number of bits in main memory address = 64 * 1024 * 16 bits
= 65536 * 16 bits
= 1048576 bits
2). Cache memory address: -
The number of bits in cache memory = 1 * 1024 bits
= 1024 bits
3). Tag and Index fields: -
The number of bits in Index fields = 10
The number of bits in Tag fields = 6
Q3: Direct Memory access is an efficient way of implementing I/O transfer. Prove
that point by giving importance of DMA

ANS: Direct memory access (DMA) is a feature of modern computers and

microprocessors that allows certain hardware subsystems within the computer to access
system memory for reading and/or writing independently of the central processing unit.
Computers that have DMA channels can transfer data to and from devices with much less
CPU overhead than computers without a DMA channel. Similarly a processing element
inside a multi-core processor can transfer data to and from its local memory without
occupying its processor time and allowing computation and data transfer concurrency.

Without DMA, using programmed input/output (PIO) mode for communication with
peripheral devices, or load/store instructions in the case of multicore chips, the CPU is
typically fully occupied for the entire duration of the read or write operation, and is thus
unavailable to perform other work. With DMA, the CPU would initiate the transfer, do
other operations while the transfer is in progress, and receive an interrupt from the DMA
controller once the operation has been done. This is especially useful in real-time
computing applications where not stalling behind concurrent operations is critical.
Another and related application area is various forms of stream processing where it is
essential to have data processing and transfer in parallel, in order to achieve sufficient
throughput.

Importance of DMA
DMA allows a peripheral device to read from/write to memory without going through the
CPU. DMA allows for faster processing since the processor can be working on something
else while the peripheral can be populating memory.

Part – B

Q4: Differentiate between synchronous and Asynchronous data transfer techniques

along with the circumstances in which each can be used.
ANS:

Asynchronous data transfer Synchronous data transfer

1. Asynchronous transmission uses start 1. Synchronous does not use start and stop
and stop bit. bits but, clock pulses that the signal built.
2. The two units are said to be
asynchronous to each other if the internal
timing in each unit is independent from the
other in that each uses its own private clock
for internal registers and that data transfer
is called as asynchronous data transfer.
This approach is widely used in most
computer systems.
2. The internal operations in a digital
system are synchronized by means of clock
pulses supplied by a common pulse
generator . Clock pulses are applied to all
registers within a unit and all data transfers
among internal registers occur
simultaneously during the occurrence of a
clock pulse.

3. Asynchronous data transfer between two
independent units requires that control
signals be transmitted between the
communicating units to indicate the time at
which data is being transmitted
3. The transfer of data between the two
units is said to be synchronous if the
registers in the interface share a common
clock with the CPU registers.

Q5: Write a program in assembly language to perform data transfer from registers
and memory.

Q6: List various addressing modes available in latest Pentium processors.

Ans: Intel architectures only support 1 addressing mode. It looks (something like) this:

Effective address = base reg + (index reg x scaling factor) + displacement

where
base reg is EAX, EBX, ECX, EDX or ESP or EBP
index reg is EDI or ESI
scaling factor is 1, 2, 4, or 8

The syntax of using this (very general) addressing mode will vary from system to system.
It depends on the preprocessor and the syntax accepted by the assembler.

SOME ADDRESSING MODES

Register mode: The operand is in a register. The effective address is the register
(wierd).
Example instruction:: mov eax, ecx
Both operands use register mode. The contents of register ecx is copied to register eax.

Immediate mode: The operand is in the instruction. The effective address is withithe
instruction.
 Example instruction: mov eax, 26
The second operand uses immediate mode. Within the instruction is the operand. It is
copied to register eax.

Register direct mode: The effective address is in a register.

Example instruction: mov eax, [esp]
The second operand uses register direct mode. The contents of register esp is the
effective address. The contents of memory at the effective address are copied into
register eax.

Direct mode: The effective address is in the instruction.

Example instruction: mov eax, var_name
The second operand uses direct mode. The instruction contains the effective address.
The contents of memory at the effective address are copied into register eax.

-- Base displacement mode --

The effective address is the sum of a constant and the contents of a register.

Example instruction: mov eax, [esp + 4]

The second operand uses base displacement mode. The instructio contains a constant.
That constant is added to the contents of register esp to form an effective address. The
contents of memory at the effective address are copied into register eax.

Base-indexed mode (Intel's name): The effective address is the sum of the contents of
two registers.
Example instruction: mov eax, [esp][esi]

The contents of registers esp and esi are added to form an effective address. The
contents of memory at the effective address are copied into register eax.

Note that there are restrictions on the combinations of register that can be used in this
addressing mode.

PC relative mode
The effective address is the sum of the contents of the PC and a constant contained
within the instruction.
Example instruction: jmp a_label

The contents of the program counter are added to an offset that is within the machine
code for the instruction. The resulting sum is placed back into the program counter.
Note that from the assembly language it is not clear that a PC relative addressing mode is
used. It is the assembler that generates the offset to place in the instruction.