Syn1588 User Guide

syn1588® User Guide
Version 1.7 – May 28th 2011
Oregano Systems – Design & Consulting GesmbH

Mohsgasse 1, A-1030 Vienna
P: +43 (676) 84 31 04-200 / 300
F: +43 (1) 89 00 940 15
@: contact@oregano.at
W: http://oregano.at
W: http://syn1588.com
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syn1588 User Guide
0 Legals
Copyright © 2006-2011 Oregano Systems – Design & Consulting GesmbH
ALL RIGHTS RESERVED.
Oregano Systems does not assume any liability arising out of the application or use of any
product described or shown herein nor does it convey any license under its patents,
copyrights, or any rights of others.
Licenses or any other rights such as, but not limited to, patents, utility models, trademarks or
tradenames, are neither granted nor conveyed by this document, nor does this document
constitute any obligation of the disclosing party to grant or convey such rights to the receiving
party.
Oregano Systems reserves the right to make changes, at any time without notice, in order to
improve reliability, function or design. Oregano Systems will not assume responsibility for the
use of any circuitry described herein.
All trademarks used in this document are the property of their respective owners.
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0.1 Versions
Version 0.1, May 13th 2009
• Document created
Version 0.2, May 20th 2009
• Document extended.
Version 0.3, June 10th 2009
Version 0.4, August 4th 2009
• Added syn1588app utility description. Added frequency option to Linux driver.
• Moved data from API AN to this UG. Added description for synchronizing the system
clock (currently Linux only)..
Version 1.1, December 22nd 2009
• Chapter about the syn1588® PTP Management Tool extended.
Version 1.2, January 14th 2010
• Added info about new release of syn1588® in Q1/2010.
• Section about the FreeBSD driver included.
Version 1.3, January 14th 2010
• Re-formatted
Version 1.4 July 15th 2010
• Re-formatting
• Chapter 7 updated
Version 1.5 September 22nd 2010
• Expanded syn1588® VIP Chapter
Version 1.6 October 28th 2010
• Expanded syn1588® LiveCD Chapter
• Introduction of chapter about the syn1588® PTP Stack protocol version 1
• Update of procedures to synchronize the system clock
Version 1.7 May 28th 2011
• Update of PTP Stack features
• Several enhancements
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Contents
0 Legals.............................................................................................................................. 2
0.1 Versions .................................................................................................................... 3
0.2 List of Figures ........................................................................................................... 9
0.3 List of Tables........................................................................................................... 10
1 syn1588® Product Overview .......................................................................................... 12
1.1 syn1588® Network Interface Cards.......................................................................... 12
1.2 syn1588® Gbit Switch .............................................................................................. 13
1.3 syn1588® Clock IP Cores ........................................................................................ 15
1.4 syn1588®VIP ........................................................................................................... 17
1.4.1 A Fully Integrated Single Chip IEEE1588 Solution ............................................ 17
1.5 syn1588® Software .................................................................................................. 19
2 syn1588® Application Scenarios .................................................................................... 21
2.1.1 syn1588® in SoC Designs ................................................................................. 21
2.1.2 syn1588® in µC/µP Board Designs ................................................................... 22
2.1.3 syn1588® in Ethernet Network Component Designs ......................................... 23
2.1.4 syn1588® in Automation Systems ..................................................................... 24
2.1.5 syn1588® in Measurement Systems ................................................................. 25
2.1.6 syn1588® in Communication Systems .............................................................. 25
2.1.7 syn1588® in Many Other Systems..................................................................... 27
3 syn1588® PCI NIC ......................................................................................................... 29
3.1 Features.................................................................................................................. 30
3.2 Functional Description............................................................................................. 31
3.3 Technical Specifications .......................................................................................... 32
3.4 Installing the syn1588® PCI NIC Hardware.............................................................. 33
3.5 Testing the syn1588® PCI NIC with the syn1588® Live CDROM ............................. 33
3.6 Installing the syn1588® PCI NIC Software ............................................................... 33
3.6.1 Linux OS ........................................................................................................... 34
3.6.2 Windows OS ..................................................................................................... 34
3.7 Register Map........................................................................................................... 35
3.7.1 Register Description ......................................................................................... 37
3.7.1.1 Version Register (SYN1588_VER) ............................................................. 37
3.7.1.2 Receive Timestamp FIFO Data Register (TSFIFO0_RX) ........................... 37
3.7.1.3 Transmit Timestamp FIFO Data Register (TSFIFO0_TX) ........................... 38
3.7.1.4 Transmit Timestamp FIFO Data Register (TSFIFO1_RX) .......................... 38
3.7.1.5 Transmit Timestamp FIFO Data Register (TSFIFO1_TX) ........................... 38
3.7.1.6 Timestamp FIFO Status Register (TSFIFO0_STATUS).............................. 39
3.7.1.7 Timestamp FIFO Status Register (TSFIFO1_STATUS).............................. 39
3.7.1.8 Interrupt Source Register (IRSRC) ............................................................. 40
3.7.1.9 Interrupt Enable Register (IREN) ................................................................ 41
3.7.1.10 Time Control Register (TIMECTRL)............................................................ 41
3.7.1.11 Event Control Register (EVENTCTRL) ....................................................... 42
3.7.1.12 Shadow Pure-Step Register (SHDWSTEPPU_L) ....................................... 43
3.7.1.13 Shadow Pure-Step Register (SHDWSTEPPU_H) ...................................... 43
3.7.1.14 Shadow Time Register (SHDWTIME_L) ..................................................... 43
3.7.1.15 Shadow Time Register (SHDWTIME_M) .................................................... 43
3.7.1.16 Shadow Time Register (SHDWTIME_H) .................................................... 43
3.7.1.17 Time Register (TIME_L) ............................................................................. 44
3.7.1.18 Time Register (TIME_M) ............................................................................ 44
3.7.1.19 Time Register (TIME_H) ............................................................................. 44
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3.7.1.20 Time Register (TIME_E) ............................................................................. 44

3.7.1.21 Event Time 0 Register (EVENTTIME0_L)................................................... 45
3.7.1.22 Event Time 0 Register (EVENTTIME0_H) .................................................. 45
3.7.1.23 Event Time 1 Register (EVENTTIME1_L)................................................... 46
3.7.1.24 Event Time 1 Register (EVENTTIME1_H) .................................................. 46
3.7.1.25 Trigger Time 0 Register (TRIGTIME0_L) .................................................... 46
3.7.1.26 Trigger Time 0 Register (TRIGTIME0_H) ................................................... 47
3.7.1.27 Trigger Time 1 Register (TRIGTIME1_L) .................................................... 47
3.7.1.28 Trigger Time 1 Register (TRIGTIME1_H) ................................................... 47
3.7.1.29 Period Time Register (PERIODTIME0PU_L) .............................................. 48
3.7.1.30 Period Time Register (PERIODTIME0PU_H) ............................................. 48
3.7.1.31 Period Time Register (PERIODTIME1PU_L) .............................................. 49
3.7.1.32 Period Time Register (PERIODTIME1PU_H) ............................................. 49
3.7.1.33 PWM Control Register (OSZPWM_CTRL) ................................................. 49
3.7.1.34 Clock ID register (low word) (CLOCKID_L)................................................. 50
3.7.1.35 Clock ID register (high word) (CLOCKID_H)............................................... 50
3.7.1.36 Control Register for setting the IO Matrix (IOMATRIX) ............................... 51
3.7.1.37 Input Clock Frequency Register (CLKFREQ) ............................................. 52
3.7.1.38 Time Register (TIME2_M) .......................................................................... 52
3.7.1.39 Time Register (TIME2_H) ........................................................................... 53
3.7.1.40 Time Register (TIME2_E) ........................................................................... 53
3.7.1.41 Control Register for Time Stamping Unit 0 Transmit (MIITS0_TXCTRL) .... 54
3.7.1.42 Control Register for Time Stamping Unit 1 Receive (MIITS1_RXCTRL) ..... 54
3.7.1.43 Control Register for Time Stamping Unit 1 Transmit (MIITS1_TXCTRL) .... 54
3.7.1.44 Control Register for Time Stamping Unit 0 Receive (MIITS0_RXCTRL) ..... 55
3.7.1.45 Pattern & Mask Memory for TS Unit 0 Receive (MIITS0_RXMEM) ............. 55
3.7.1.46 Pattern & Mask Memory for TS Unit 0 Receive (MIITS0_TXMEM) ............. 56
3.7.1.47 Pattern & Mask Memory for TS Unit 1 Receive (MIITS1_RXMEM) ............. 57
3.7.1.48 Pattern & Mask Memory for TS Unit 1 Receive (MIITS1_TXMEM) ............. 57
3.7.2 IEEE1588 Register Layout................................................................................ 58
3.8 Diagnostics ............................................................................................................. 59
3.8.1 Verification of Installed Driver ........................................................................... 59
3.8.2 Controlling the syn1588® PTP Stack ................................................................. 59
3.8.3 The syn1588app Utility ..................................................................................... 59
3.8.3.1 Convenience Commands ........................................................................... 60
3.9 Using the syn1588® PCI NIC ................................................................................... 66
3.9.1 Interoperability .................................................................................................. 66
3.9.2 1PPS Output..................................................................................................... 66
3.9.3 Frequency Output ............................................................................................. 67
3.9.3.1 Example ..................................................................................................... 67
3.9.4 Changing IO Functions ..................................................................................... 68
3.9.4.1 IOMATRIX Register .................................................................................... 69
3.9.4.2 Example 1 .................................................................................................. 71
3.9.4.3 Example 2 .................................................................................................. 71
3.9.5 Timestamping User Defined Packets ................................................................ 72
3.9.5.1 Introduction ................................................................................................ 72
3.9.5.2 MII Timestamp Control Register ................................................................. 74
3.9.5.3 User Timestamping Demo Design .............................................................. 76
3.9.6 Synchronizing to GPS: ESYNC......................................................................... 80
3.9.7 Synchronizing the System Clock: LSYNC ......................................................... 82
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4 syn1588® PCIe NIC ....................................................................................................... 85

4.1 Features.................................................................................................................. 86
4.4 Installing the syn1588® PCIe NIC Hardware ............................................................ 86
4.5 Testing the syn1588® PCIe NIC with the syn1588® Live CDROM ........................... 87
4.6 Installing the syn1588® PCIe NIC Software ............................................................. 87
4.7 Register Map........................................................................................................... 87
4.8 Diagnostics ............................................................................................................. 87
4.9 Using the syn1588® PCIe NIC ................................................................................. 88
4.9.1 1PPS Output..................................................................................................... 88
4.9.2 Frequency Output ............................................................................................. 88
4.9.3 Changing IO Functions ..................................................................................... 88
4.9.4 Timestamping User Defined Packets ................................................................ 88
4.9.5 Synchronizing to GPS....................................................................................... 89
4.9.6 Synchronizing the System Clock ....................................................................... 89
5 syn1588® VIP................................................................................................................. 91
5.1 Features.................................................................................................................. 91
5.3 The syn1588®VIP node ........................................................................................... 93
5.5 Serial Logging ......................................................................................................... 94
5.6 Remote Configuration ............................................................................................. 95
5.6.1 Example 1: Indentifying syn1588®VIP Nodes .................................................... 95
5.6.2 Example 2: Reading syn1588®VIP Registers .................................................... 96
5.7 Defining the output frequency ................................................................................. 97
6 syn1588® NIC Driver ................................................................................................... 100
6.1 Features................................................................................................................ 100
6.2 Installing the syn1588® NIC Driver ........................................................................ 100
6.2.1 Linux OS ......................................................................................................... 100
6.2.1.1 Clock Device Driver .................................................................................. 100
6.2.1.2 Synchronization Driver ............................................................................. 101
6.2.2 Windows OS ................................................................................................... 107
6.2.2.1 Network Driver.......................................................................................... 108
6.2.3 FreeBSD OS................................................................................................... 115
6.3 Diagnostics ........................................................................................................... 116
6.3.1 Linux ............................................................................................................... 116
6.3.2 Windows ......................................................................................................... 116
6.3.3 FreeBSD ......................................................................................................... 117
7 syn1588® PTP Stack ................................................................................................... 119
7.1 Functional Description........................................................................................... 119
7.2 Features................................................................................................................ 119
7.3 System Environment ............................................................................................. 120
7.4 Calling Convention ................................................................................................ 121
7.5 Diagnostics ........................................................................................................... 122
7.5.1 Diagnostics without Logging ........................................................................... 122
7.5.2 Diagnostics with Logging ................................................................................ 122
7.5.3 Diagnostics with syn1588® PTP Management Messages ............................... 125
7.6 Software Interface ................................................................................................. 126
7.7 Directory Structure ................................................................................................ 127
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7.8 Building the syn1588® PTP Stack:......................................................................... 127

7.8.1 Building for Windows ...................................................................................... 127
7.8.2 Building for Linux ............................................................................................ 127
7.8.3 Building for the MC8051 ................................................................................. 127
7.9 Installation ............................................................................................................. 128
7.10 Management Interface .......................................................................................... 128
8 syn1588® PTP Stack for Protocol Version 1 ................................................................ 129
9 syn1588® PTP Management Tool ................................................................................ 130
9.1 Command Syntax of the syn1588® PTP Management Tool .................................. 130
9.2 Command Reference of the syn1588® PTP Management Tool ............................. 131
9.2.1 accuracy Set/Get Clock Accuracy ................................................................... 132
9.2.2 aival Set/Get announce interval ...................................................................... 132
9.2.3 atout Set/Get Announce Receipt Timeout ....................................................... 132
9.2.4 clkman Set/Get syn1588® Clock Registers ..................................................... 133
9.2.5 clock Get clock description ............................................................................. 133
9.2.6 current Get the current dataset ....................................................................... 133
9.2.7 default Get the default dataset ........................................................................ 133
9.2.8 dlymech Set/Get the delay mechanism used .................................................. 134
9.2.9 domain Set/Get the PTP domain .................................................................... 134
9.2.10 init Command to initialize a clock .................................................................... 134
9.2.11 log Get the Fault log ....................................................................................... 135
9.2.12 logres Command to reset the Fault log ........................................................... 135
9.2.13 null Command to send a Null Management Message ..................................... 135
9.2.14 parent Command to get the Parent Dataset .................................................... 135
9.2.15 pival Set/Get the Peer Delay Interval .............................................................. 135
9.2.16 port Get the Port Dataset ................................................................................ 136
9.2.17 portdis Port Disable Command ....................................................................... 136
9.2.18 porten Port Enable Command......................................................................... 136
9.2.19 prio1 Set/Get Priority1 of the Default Dataset ................................................. 136
9.2.20 prio2 Set/Get Priority 2 of the Default Dataset ................................................ 137
9.2.21 reset Resets the Values in non-volatile read-write memory............................. 137
9.2.22 save Save current values in non-volatile read-write memory .......................... 137
9.2.23 sival Set/Get Sync Interval .............................................................................. 137
9.2.24 slave Set/Get Slave Only Bit ........................................................................... 138
9.2.25 time Get/Set Time ........................................................................................... 138
9.2.26 timescale Set/Get Timescale .......................................................................... 139
9.2.27 tprop Get Time Properties............................................................................... 139
9.2.28 traceab Set/Get the Traceabilty Properties ..................................................... 139
9.2.29 user Set/Get the User Description .................................................................. 139
9.2.30 utc Set/Get the UTC Properties ...................................................................... 139
9.2.31 Version Set/Get the PTP Version used on a clock port ................................... 141
10 syn1588® Live CDROM ............................................................................................... 143
11 syn1588® and External Time Sources ......................................................................... 146
11.1 Basics ................................................................................................................... 146
11.2 Reacting to External Events .................................................................................. 147
11.2.1 EVENTINPUT0 and EVENTINPUT1 ............................................................... 147
11.2.2 Timestamping of Ethernet Packets ................................................................. 147
11.3 Generating External Events .................................................................................. 148
11.3.1 One Pulse per Second (1PPS) ....................................................................... 148
11.3.2 Periodical Events PERIODTIME0 and PERIODTIME1 ................................... 148
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11.3.3 One Shot Events TRIGTIME0 and TRIGTIME1 .............................................. 148

11.3.4 Combinations of Periodical Events and One Shot Events ............................... 149
12 syn1588® Optimization and Trade-Offs........................................................................ 151
12.1 Precision ............................................................................................................... 151
12.2 Local Area Ethernet Networks ............................................................................... 151
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0.2 List of Figures

Figure 1: syn1588® PCIe NIC............................................................................................... 12
Figure 2: syn1588® PCI NIC ................................................................................................ 13
Figure 4: syn1588® Switch Evaluation Board ...................................................................... 13
Figure 4: syn1588® Gbit Switch............................................................................................ 14
Figure 5: Block diagrams of available IP cores..................................................................... 15
Figure 6: syn1588® VIP IP Core ........................................................................................... 17
Figure 7: syn1588®VIP Single Chip ...................................................................................... 18
Figure 8: The syn1588®VIP Evaluation Board ...................................................................... 18
Figure 9: Principal SoC block diagram containing syn1588Clock core. ................................ 22
Figure 10: Principal µC/µP board block diagram containing syn1588Clock functionality. ..... 23
Figure 11: a) Principal solution for an integrated network controller chip. b) Principal solution
for a network interface card with controller and PHY separated. ................................... 24
Figure 12: Distributed PLL using syn1588® Technology ....................................................... 25
Figure 13: Principal system setup for an application of clock synchronization in industrial
automation. ................................................................................................................... 26
Figure 14: Example setup for measurement equipment supporting clock synchronization. .. 26
Figure 15: Example setup for a communication network, which uses synchronized clocks. . 27
Figure 16: syn1588® PCI NIC............................................................................................... 29
Figure 17: syn1588® PCI NIC basic block diagram ............................................................. 31
Figure 18 Block diagram of the complete syn1588® NIC design syn1588® PCI NIC ............. 32
Figure 19 IEEE1588 register layout ..................................................................................... 58
Figure 20. MII timestamping units in the syn1588® PCI/PCIe NIC ........................................ 72
Figure 21. Basic timestamper comparator............................................................................ 72
Figure 22: Setup for synchronizing to GPS .......................................................................... 80
Figure 23: syn1588® PCIe NIC............................................................................................. 85
Figure 24: syn1588®VIP: Block diagram .............................................................................. 92
Figure 25 syn1588® VIP Node ............................................................................................. 93
Figure 26: User interface to the kernel driver ..................................................................... 108
Figure 27: Source file structure .......................................................................................... 112
Figure 28: How to enter the NIC attribute context menu..................................................... 114
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0.3 List of Tables

Table 1 syn1588Clock IP core overview – Part I .................................................................. 16
Table 2 syn1588Clock IP core overview – Part II ................................................................. 16
Table 3: syn1588®Clock_M IP core register overview. ......................................................... 36
Table 4 Default functions of the SMA connectors................................................................. 68
Table 5 IOMATRIX register bit description ........................................................................... 69
Table 6 Encoding of sources for IOMATRIX register ............................................................ 70
Table 7 MII Timestamp Control Register – register bits........................................................ 74
Table 8 Address map of the MII Timestamp Control Registers ............................................ 74
Table 9 Addresses map of the MII Timestamp patter and mask memories .......................... 74
Table 10 Addresses of the MII Timestamp FIFOs ................................................................ 75
Table 11 Timestamp FIFO Status Register – register bits .................................................... 75
Table 12 Address map of the MII Timestamp FIFO Status Register..................................... 75
Table 13 Example for controlling the MII timestamper (“main.cpp”)...................................... 79
Table 14 Content of the “miits.zip” file .................................................................................. 79
Table 15 Default functions of the SMA connectors............................................................... 88
Table 16 Linux Clock device driver: C-files ........................................................................ 101
Table 17: Symbolic register names (example for syn1588Clock_M IP core) ...................... 102
Table 18: Synchronization driver: C-files ............................................................................ 105
Table 19 Source files of the FreeBSD driver ...................................................................... 115
Table 20 Options for the syn1588® PTP Stack executable ................................................. 122
Table 21 Available Commands in the syn1588® PTP Management Tool ........................... 131
Table 22 Contents of the syn1588® Live CDROM ............................................................. 143
Table 23 Available syn1588® software on the LiveCD ........................................................ 144
Table 24: Ethernet physical layer uncertainties. ................................................................. 151
Table 25: Cabling uncertainties. ......................................................................................... 152
Table 26: Typical Ethernet link delay uncertainties. ........................................................... 152
Table 27: Uncertainties introduced from oscillator drift. ...................................................... 152
Table 28: Estimated uncertainties through clock implementation. ...................................... 153
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1 syn1588® Product Overview

Oregano Systems offers both a suite of building blocks and complete solutions for designing
systems based on the IEEE1588 standard for Precision Clock Synchronization to be used,
among others, for networked measurement and control systems or telecom applications.
Furthermore, Oregano Systems offers ready-to-use hardware to build IEEE1588 networks as
well as the necessary PTP software stack. The syn1588® hardware is centred around a set
of IP cores that may be licensed separately thus enabling customers to design their own
IEEE1588 systems tailored to the needs of s specific application
Oregano Systems is actively involved in the IEEE1588 Standard revision working group and
supports related research activities on a national and European level. This allows Oregano
Systems to keep its products up to date with the latest developments of the IEEE1588
standard. This chapter gives an overview of Oregano Systems’ syn1588® product range.
1.1 syn1588® Network Interface Cards

Oregano Systems has two Ethernet different network interface cards available, briefly
referred to as syn1588® NICs.
• syn1588® PCI NIC (optionally equipped with OCXO)
• syn1588® PCIe NIC (optionally equipped with OCXO)
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Figure 1: syn1588 PCIe NIC
Both syn1588® NICs support all features of a standard Ethernet network card, one via a 32-
bit PCI, the other via a single lane PCI Express interface. Additionally, the syn1588® NICs
are equipped with dedicated hardware supporting IEEE1588 functions like highly accurate
timestamping and high-precision high resolution clocks. Optionally both cards may be
equipped with an OCXO resulting in an extended frequency stability thus making them suited
for operating as a IEEE1588 Master Clock. For further information see Chapter 3 and
Chapter 4 of this user guide respectively.
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Figure 2: syn1588 PCI NIC
1.2 syn1588® Gbit Switch

The syn1588® Gbit Switch is an 8-port one-step end2end Transparent Clock with respect to
IEEE1588-2008 featuring an on-the-fly time stamping technique patented by Oregano
Systems
It contains eight 10/100/1000 Mbit/s ports in combination with one uplink/management port
implemented as a SFP cage enabling fibre connection. For further details visit our website at
http://www.oregano.at.
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Figure 4: syn1588 Gbit Switch
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1.3 syn1588® Clock IP Cores

Oregano Systems offers a full range of clock IP cores compatible to the IEEE1588 Standard
2002 and 2008. The IP cores differ in footprint, number of I/Os and Ethernet connection and,
and supported interfaces to an external CPU.
Oregano Systems offers four syn1588® IP cores sized in their functionality: small, medium,
extended medium, and large. The product names are syn1588Clock_S, syn1588Clock_M,
syn1588Clock_MX, and syn1588Clock_L respectively. The cores have been successfully
implemented and used in a variety of FPGA, ASIC, and SoC designs.
The following tables compare the features of the four syn1588® Clock IP cores offered by
Oregano Systems.
mii0_txd_to_phy_o<7:0>
mii0_txd_from_mac_i<7:0>
mii0_txer_i
mii0_txdv_i
mii0_txclk_i
mii0_rxd_to_mac_o<7:0>
mii0_rxd_from_phy_i<7:0>
mii0_rxer_i
mii0_rxdv_i
mii0_rxclk_i
SYN1588Clock_MX
mii_txd_to_phy_o<7:0>
mii1_txd_to_phy_o<7:0> Core
mii_txd_from_mac_i<7:0> ahb_s_irq_o
mii1_txd_from_mac_i<7:0> ahb_s_irq_o
ahb_s_sel_i
mii_txer_i ahb_s_sel_i
mii1_txer_i mii_txd<3:0>
ahb_s_addr_i<8:2>
mii_txdv_i ahb_s_addr_i<8:2>
ahb_s_wdata_i<31:0> mii1_txdv_i mii_txdv mosi
ahb_s_wdata_i<31:0>
mii_txclk_i ahb_s_rdata_o<31:0> mii_txclk miso
SYN1588Clock_M mii1_txclk_i ahb_s_rdata_o<31:0> SYN1588Clock_S
ahb_s_trans_i<1:0>
mii_rxd_to_mac_o<7:0> Core mii1_rxd_to_mac_o<7:0>
ahb_s_trans_i<1:0> mii_rxd<3:0> Core sck
ahb_s_write_i
mii_rxd_from_phy_i<7:0> ahb_s_write_i
ahb_s_size_i<2:0> mii1_rxd_from_phy_i<7:0> mii_rxdv ss_n
ahb_s_size_i<2:0>
mii_rxer_i ahb_s_burst_i<2:0> mii_rxclk
mii1_rxer_i ahb_s_burst_i<2:0>
ahb_s_ready_i
mii_rxdv_i ahb_s_ready_i
mii1_rxdv_i
ahb_s_ready_o
ahb_s_ready_o
mii_rxclk_i
onepps_o
trigger_o
period_o
ahb_s_resp_o<1:0> mii1_rxclk_i
event_i
ahb_s_resp_o<1:0>
reset_i
clk_i
clockid_i<63:0>
gmii_modesel_i
gmii1_modesel_i
clockid_i<63:0>
trigger_o<1:0>
period_o<1:0>
trigger_o<1:0>
period_o<1:0>
event_i<1:0>
event_i<1:0>
onepps_o
onepps_o
pwm_o
reset_i
pwm_o
reset_i
clk_i
clk_i
Figure 5: Block diagrams of available IP cores
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syn1588
Basic Parameters Clock_S Clock_M Clock_MX Clock_L
bus interface SPI AHB AHB AHB
external/internal interrupts 0/- 1/12 1/12 1/16..27
trigger outputs 1 2 2 1..4
period timer outputs 1 2 2 1..4
separate one PPS output X X X -
MII event inputs 1 1 2 1..2
event inputs 1 2 2 1..4
core time registers 1 1 1 1..4
negative time values supported / handled -/- -/X -/X -/X
IP core parameter readout - - - X
clock core width 104 104 104 104
timer / event precision 64/64 64/64 64/64 64/96
Timestamping Engine Clock_S Clock_M Clock_MX Clock_L
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on-the-fly timestamping support - - - -
packet FIFOs 2 2 2 1
separated RX & TX / device FIFOs X/- X/- X/- X/X
packet FIFO width [bit] 32 32 32 64
packet FIFO depth [Entries] / [Packets] 256 256/85 256/85 64+/6+
packet FIFO stores ID X X X X
packet FIFO full/empty flag X/X X/X X/X X/X
packet FIFO stores accuracies - - - X
timestamp clear / readout time [clock cycles] 24/24 24/24 24/24 20/30
timestamp storage can be disabled - - - X
Table 1 syn1588Clock IP core overview – Part I
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syn1588
Distributed System Support Clock_S Clock_M Clock_MX Clock_L
apply time (set registers on time) - - - X
amortisation / precision [ns] - - - X/1
stable frequency output support - - - X
programmable interrupt time - X X X
accuracy counters 0 0 0 0..2
event loopback (trigger, period timer), high - - - X
precision readout
free running period timer (no CPU load) X X X X
period timer startable manual / trigger / IRQ time X/1/- X/2/X X/2/X X/2/X
Ethernet bridging support - - - X
function blocking readout (clock overflow pending) - - - X
Hard Real-Time support Clock_S Clock_M Clock_MX Clock_L
Lost IRQ readout - - - X
IRSRC auto. Clear - - - X
Consistent event time readout check - - - X
Table 2 syn1588Clock IP core overview – Part II
Legend:
X ..... supported
+ ..... partly supported
- ....... not yet supported
The Oregano Systems PCI Ethernet NIC is a typical application for the syn1588®Clock IP
cores. It combines the syn1588®Clock_M IP core with a PCI controller and an Ethernet MAC
in a single FPGA device suited for cost sensitive industrial applications. It enables conven-
tional PCs to support highly accurate clock synchronisation following IEEE1588 allowing
accuracies of less than 100 ns to be achieved. Please see the product related website at
http://www.oregano.at/ for further details regarding any of the IP cores mentioned above.
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1.4 syn1588®VIP
1.4.1 A Fully Integrated Single Chip IEEE1588 Solution
The syn1588®VIP fully integrated single chip IEEE1588 solution contains everything that is
needed for a complete IEEE1588 implementation with hardware time stamping. Figure 6
shows a block diagram of the major blocks of the syn1588®VIP IP-Core.
The syn1588®VIP design is based on three major blocks. A 10/100/1000 Mbit Ethernet MAC,
an IEEE1588 based hardware clock unit and a simple offload engine which is an 8 bit
MC8051 CPU.
The task of the Ethernet MAC is to send Ethernet packets generated by the CPU and receive
Ethernet packets and forward them to the CPU. There is also a packet filter implemented into
the Ethernet MAC. This packet filter takes care that the CPU only receives IEEE1588 related
packets and does not need to spend precious CPU cycles on processing non IEEE1588
related packets. Optionally all non IEEE1588 related packets can be forwarded to an optional
more powerful main CPU for processing.
The clock unit is a high accuracy IEEE1588 based hardware clock. The main responsibility of
the clock unit is to keep the high accuracy system time and provide timestamps.
The Ethernet MAC in combination with the clock unit is capable of IEEE1588 hardware time
stamping, which leads to high accuracy time stamps for incoming and outgoing network
packets.
The network packets from the Ethernet MAC and the high accuracy timestamps from the
clock unit are processed by the offload engine which is a 8bit MC8051 CPU. With the
hardware time stamping of the MAC and the high accuracy timestamps of the clock unit
IEEE1588 clock synchronization in the nanosecond range can be achieved.
Figure 6: syn1588® VIP IP Core
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The syn1588® VIP comes in three flavours:

• IP Core
• Single Chip Device
• Evaluation Board
The syn1588®VIP IP Core includes all clock related processing encapsulated within the
intellectual property core and provides a system with a high accuracy synchronized clock
without having it to run any dedicated code. The design is ideally suited for embedded
systems or system-on-chip designs not willing to contaminate the application software with
clock synchronization or protocol code or simply seeking a simple and cost effective solution.
Figure 6 shows a block diagram of the syn1588® VIP IP-Core.
Since the syn1588®VIP IP Core is a standalone system it is also offered as a single chip
solution. Figure 7 shows a symbolic Lattice FPGA which contains the syn1588® VIP design.
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Figure 7: syn1588 VIP Single Chip
To ease test and evaluation of our syn1588®VIP single chip solution we also provide an
evaluation board, which can be seen in Figure 8. The PCB design data of this evaluation
board is available for our syn1588® customers free of charge upon request.
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Figure 8: The syn1588 VIP Evaluation Board
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1.5 syn1588® Software

Oregano Systems offers a protocol stack, which is compatible to the IEEE1588-2008 and
IEEE1588-2002 standard. The stack is fully functional and is tested for compatibility in
environments with stacks of other proveniences at least once every year during the ISPCS
plug fest
A system made up of Oregano Systems' syn1588® 8-Port Ethernet switch, a syn1588® PCI
network interface card, and the Precision Time Protocol (PTP) stack will achieve
synchronization accuracies in the range of 10 ns completely independent from the amount of
network traffic.
For further details about this product view Chapter 7 of this document.
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2 syn1588® Application Scenarios

This section lists and describes possible applications of Oregano Systems’ syn1588® clock
synchronization technology from a system designer’s point of view. It is important to note that
all Oregano syn1588® products are compatible with the IEEE1588 Standard for a Precision
Clock Synchronization Protocol for Networked Measurement and Control Systems.
For a summary of the limiting factors of clock synchronization, achievable precision and
typical values of local area Ethernet networks regard the syn1588® clock synchronization
technology white paper, also available from the Oregano Systems web site.
The Oregano Systems’ set of syn1588Clock IP Cores comprises three cores, which differ in
size, number of interfaces, and extended functionality. All three cores, however, posses the
same basic set of registers and functionality that is vital for support of the IEEE1588
Precision Time Protocol (PTP) to synchronize nodes over the Ethernet network to fractions of
a microsecond.
2.1.1 syn1588® in SoC Designs
SoC designs targeted for various application domains support Ethernet communication by
having one or more Ethernet media access controllers and even the Ethernet physical layer
already on-chip. Adding the Oregano Systems syn1588 Clock cores to such a
communication system is very simple. The standardized media independent interface (MII)
between the Ethernet MAC and the PHY is split and the syn1588 Clock core is inserted. To
allow access to the core’s registers, the syn1588Clock cores implement a 32-bit AHB slave
interface together with one interrupt line. Since both interfaces, the MII and the AHB, are
standardized and well established, seamless integration of both the Oregano Systems
syn1588Clock_L and syn1588Clock_M core is achieved with minimal design effort.
To be able to access trigger and timer outputs as well as the event timestamp inputs of the
core, those I/Os have to be routed to the outside of the SoC (see Figure for a principal
overview).
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2.1.2 syn1588® in µC/µP Board Designs
Many microcontroller or microprocessor centered modules for applications of such varying

types as Voice over IP or embedded control systems use Ethernet for data and/or control
communication. A typical setup is that of an embedded µC/µP already containing the
Ethernet MAC controller yet the Ethernet PHY has to be put on the PCB near the Ethernet
cable connector. In such a setup (see Figure 10) the Oregano Systems syn1588Clock core
offers a simple and cost effective solution to support such products with added clock
synchronization capabilities. By simply adding one component like a low cost, low pin count
programmable logic device to the PCB, the syn1588Clock_S IP core running in that device
delivers full featured clock synchronization capabilities.
UARTs
CPU
DMA
AHB system bus
MII MII
Ethernet SYN1588 Ether
PCI net
MAC Clock PHY
Trigger +
Event I/Os
Figure 9: Principal SoC block diagram containing syn1588Clock core.
The registers of the syn1588Clock are accessible via an SPI interface, thus reducing the
board complexity traces to a minimum. The core is passively connected to the MII interface
and monitors the inbound and outbound traffic for clock synchronization packets. To make
use of the trigger and timer outputs as well as the event timestamp inputs of the core, these
I/Os will have to be made available on board-level according to the needs of the specific
application.
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Memory
Trigger +
µC/µP with internal SPI SYN1588 Event I/Os
Ethernet MAC Clock
Ethernet MII Ether

net
MAC PHY
Figure 10: Principal µC/µP board block diagram containing syn1588Clock functionality.
2.1.3 syn1588® in Ethernet Network Component Designs
When it comes to application domains like computing, database systems, distributed

communication or measurement systems it is very likely that the Ethernet network interface
is represented by a separate PCB, connecting to the system bus (e.g. PCI or PCI-Express).
In this situation the solutions described in Sections 2.1.1 and 2.1.2 respectively are both
viable (see Figure and Figure 10). The syn1588Clock functionality can be added on board
level by adding a component or by integrating the syn1588Clock core in the network
controller chip. A decision for one or the other approach has to take facts like production
volume, design costs, and others into account. Further details may be found within the
Oregano Systems syn1588 PCI and PC/104-Plus network interface card documentation e.g.
syn1588® in Ethernet Switch Designs.
High accuracy clock synchronization, below the microsecond range, does also require the
Ethernet switches to support clock synchronization in hardware. Details about
implementations of “Boundary Clocks” or “Transparent Switches” in conformance with the
IEEE1588 Standard can be found in the respective standards document, available form the
IEEE. Again it depends on whether the switch is built using PHY chips separated from the
switch’s MAC-Processor or as a single integrated SoC. In this situation both solutions
described in Sections 2.1.1 and 2.1.2 respectively are viable solutions. The design, however,
has to be adapted to the number of MII ports present in the product.
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MII
MII MII Ether
Ether Ethernet
SYN1588 Ethernet net
net PHY MAC
PHY Clock MAC
Trigger + AHB Trigger + SYN1588 SPI

Event I/Os Event I/Os Clock PCI
PCI Controller Controller
a b
Figure 11: a) Principal solution for an integrated network controller chip. b) Principal solution
for a network interface card with controller and PHY separated.
2.1.4 syn1588® in Automation Systems
In the recent past industrial automation systems are increasingly using Ethernet networks
also on the field level, thus often replacing proprietary bus systems with high bandwidth,
cheap and standardized network technology. In order to guarantee message delivery
(collisions) and quality of service (network delay) most solutions rely on a Time Division
Multiple Access (TDMA) strategy for exchanging information via the Ethernet network. This,
however, requires all participants to have a common notion of time and it is this same
IEEE1588 compatible clock synchronization mechanism that is being used in related product
development and standardization efforts. All Oregano Systems syn1588 cores perfectly
support this application area, as they provide, for example, a simple means to build a
distributed PLL. The core may be configured via software to output a pulse of given length at
a given frequency. Finally every node has to be configured e.g. using its address with a
unique offset with respect to the local clock of the core (see Figure 12).
Besides making a TDMA based network possible syn1588® clock synchronization has to
offer far more benefits to industrial automation applications. Things like sequence of events
or measurements, scheduled trigger outputs, time-stamped data logs, synchronized
actuation, or transition from mechanical line shafts to distributed motion control are only a
few to mention.
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Figure 12: Distributed PLL using syn1588 Technology
For the entire system to be able to profit from a common notion of time, dedicated support in
the sensor as well as actuator interface hardware as explained in Sections 2.1.1, 2.1.2, 2.1.3,
and 2.1.4 respectively is necessary (see Figure 13). This is especially true for clock
synchronization below the microsecond range.
2.1.5 syn1588® in Measurement Systems
Measurement systems per nature rely on triggers, synchronization of events, or relating data
samples with respect to time to calculate e.g. offsets. In the recent past measurement
equipment has been quickly stepping towards using Ethernet technology to interconnect
instruments such as oscilloscopes, network analyzers, timing analyzers, pattern generators,
frequency generators, or even DMM the like. It is very clear that these systems strongly
benefit from a precisely synchronized common notion of time. All Oregano Systems
syn1588® cores perfectly support this application area (see Figure 14).
2.1.6 syn1588® in Communication Systems
Traditionally communication systems have been using precision oscillators and hierarchical
clock distribution in by means of dedicated hardware, which often was distributed in space.
By the use of synchronized clocks such system can benefit significantly.
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Sensor Actuator Actuator Sensor
Ethernet Switch
Sensor Actuator Actuator Sensor
Figure 13: Principal system setup for an application of clock synchronization in industrial
automation.
By establishing a common notion of time with precisions below the microsecond range a
distributed sample clock can be realized, which allows to sample e.g. voice data with 8 kHz
or 16 KHz completely synchronous in the entire system by means of setting up a distributed
PLL running at, for example, the respective sampling frequency or a multiple of it. Local
codec devices or even analog PLLs may be locked on this frequency.
Ethernet Switch
Logic Analyzer Frequency Generator Pattern Generator Oscilloscope
Figure 14: Example setup for measurement equipment supporting clock synchronization.
This, however, requires all participants to have a common notion of time. The IEEE1588
compatible clock synchronization mechanism that is being used in related product
development and standardization efforts fulfils these requirements. As a consequence all
Oregano Systems syn1588® cores perfectly support this application area (see Figure 15).
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Ethernet Switch
Telephone Loudspeaker Headset Microphone
Figure 15: Example setup for a communication network, which uses synchronized clocks.
For the entire system to be able to profit from the common notion of time, dedicated support
in the measurement equipment’s network interface hardware as explained in Sections 2.1.1,
2.1.2, and 2.1.3 respectively is necessary. This is especially true for clock synchronization
below the microsecond range.
2.1.7 syn1588® in Many Other Systems
The previous sections have arbitrarily highlighted some possible and already existing
application areas of clock synchronization and Oregano Systems syn1588® technology.
Many more systems and possible applications could profit or even be realized for the first
time with this technology. Do not hesitate to contact Oregano Systems for questions or any
further information concerning clock synchronization.
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3 syn1588® PCI NIC

The syn1588® PCI NIC is a 10/100 Mbps fast Ethernet network interface card (32-bit PCI bus
interface card, compliant to PCI version 2.3) with enhancements to provide the network node
with accurate clock synchronization via Ethernet according to the IEEE1588 standard (see
Figure 16). The syn1588® PCI NIC uses Oregano’s syn1588® technology for time stamping
of dedicated packets in the card’s integrated circuit.
®
Figure 16: syn1588 PCI NIC
As the hardware assisted time stamping mechanism has been designed using a generic
architecture, the syn1588® network card supports both version 2002 and version 2008 of the
IEEE1588 standard. Oregano Systems offers the Precision Time Protocol (PTP) Stack
supporting either version 2002 or version 2008 of the IEEE1588 standard.
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3.1 Features
• 10/100 Mbit/s Ethernet network interface card compliant to IEEE802.3-2000
• Fully compliant to IEEE1588-2002 (also referred to as IEEE1588 version 1.0)
• IEEE1588 hardware timestamping supported
• Two-step as well as one-step timestamping supported
• Clock accuracy up to 50 ns
• Linux driver available (binary and source included with the NIC)
• Windows driver available (binary included with the NIC)
• syn1588® PTP Stack available for Linux and Windows (binary included with the NIC)
• Supports all IEEE1588 version 2008 enhancements
o Transparent clocks
o Management messages
o Unicast messages
• 32 bit PCI card (full height)
• supporting both 5 V as well as 3V3 PCI slots compliant to PCI 2.3
• Four programmable I/O signals routed to SMA jacks (3V3 LVCMOS)
• Two independent and programmable timestamping units available for receive and
transmit, enabling parallel timestamping of user specified packets
• Operating temperature range 0 – 50°C
Optional features:
• 80-pin module connector enabling project/user specific extensions
• Connectivity to an external GPS receiver via a 1pps input as well as the serial port of the
host PC
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3.2 Functional Description

Figure 17 shows the block diagram of the syn1588® PCI NIC. The card is based upon a
single pre-configured Flash based FPGA device containing all circuitry except the Ethernet
physical layer device.
Figure 17: syn1588® PCI NIC basic block diagram
The syn1588® PCI NIC module may be equipped with various types of local oscillators
allowing the quality of the synchronization and thus the system performance to be tailored to
the accuracy requirements. Those oscillator options are available upon request.
Figure 18 shows the detailed block diagram of the syn1588® NIC FPGA design. The device
contains a PCI controller core to which both a media access controller (MAC) core and the
syn1588®Clock_M clock synchronization core are attached over an internal 32-bit AHB bus
interface.
The MAC controller is supplied with a 25 MHz clock and is directly wired to the physical layer
IC. It handles both Ethernet data traffic and configuration and control of the physical layer IC
via the serial MDC (media device control) interface.
The syn1588®Clock_M IP core operates as a stand-alone entity and is accessible via a
separate memory map. However, it shares the PCI controller with the MAC.
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SYN1588 PCI NIC
FPGA
Ethernet Core
TX control TX Phy control
signals MAC signals
TX Ethernet
TX Data MAC TX Data
Flow control
PCI Host Signals MAC Control RJ45
Bus Interface Module Jack
(Register, Ethernet
Bus RX control RX Phy control PHY
AHB bus signals
map signals
interface,
PCI - DMS RX Ethernet
Core RX Data MAC RX Data
support)
Management
MII Data
Management
Management
signals
Modul
25 MHz
® SMA
Syn1588 Clock M - Core
25 MHz or 100MHz
high percision OCXO SMA
SMA
SMA
® ®
Figure 18 Block diagram of the complete syn1588 NIC design syn1588 PCI NIC
3.3 Technical Specifications

For technical specification details like supply and I/O voltages or temperature range please
refer to the product datasheet.
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3.4 Installing the syn1588® PCI NIC Hardware

The following instructions are general installing steps. Consult your computer’s user manual
for specific instructions and warnings for installing new PCI components.
1. Be sure to have powered–off your PC prior to installing the
syn1588® PCI NIC
2. Please be sure to thoroughly ground yourself by means of a
grounding strap or by touching a grounded object prior to unpacking the
syn1588® PCI NIC card
3. Insert the syn1588® PCI NIC into the empty PCI slot and verify that the card is
properly inserted and fastened by means of levels or screw of the case
4. Plug in the power cord of the computer and power the computer on
The syn1588® PCI NIC card is now installed. Principle operation of the syn1588® NIC can be
verified by having an entry on the PCI bus overview of the operating system. Use “lspci” on
Linux or the “Device Manager” on Windows.
3.5 Testing the syn1588® PCI NIC with the syn1588® Live CDROM
The syn1588® Live CDROM simplifies using the syn1588® PCI NIC. No software installation
task is required. One just boots the PC using the syn1588® Live CDROM. The syn1588® Live
CDROM boots a pre-configured Linux.
For further details on using the syn1588® Live CDROM please refer to Chapter 10.
3.6 Installing the syn1588® PCI NIC Software

The software consists of two major parts:
• syn1588® NIC driver
• syn1588® PTP Stack
The following sections describe how to install the software on the supported operating
systems Linux and Windows. After the driver is installed, the syn1588® PTP-Stack can be
started.
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3.6.1 Linux OS
The target has to comply with/support the following items:

• Kernel version 2.6.16 to 2.6.30
• Kernel source to compile the driver.
• Module support activated
• Module versioning support activated (config_modversion)
• Daemon for devices (udev daemon)
The drivers are delivered as source and pre-compiled. The pre-compiled version can only be
used for a specific kernel version on Linux OS. To compile the drivers change to the directory
with the driver source files and type “make” followed by “make install”. The driver can be
loaded with the “modprobe” command.
The syn1588® PTP Stack will be delivered as pre-compiled version and with documentation
for all available options.
For further details on using and interfacing the driver and for more API documentation view
Chapter 6.
3.6.2 Windows OS
The following Windows versions are supported:

• Windows XP
• Windows Server 2003 & 2008 32Bit and 64Bit
The drivers are delivered as pre-compiled binaries.
The driver can be installed in the usual way
• System Control
• Add Hardware
• Network Card
• Manually select driver
• have disk (point to directory with the “syn1588.inf” and “syn1588pcie.sys” file)
After the driver has been installed, the syn1588® PTP-Stack can be started (“ptp.exe”). The
syn1588® PTP Stack will be delivered as pre-compiled version and with documentation for all
available options.
For further details on using and interfacing the driver and for more API documentation view
Chapter 6.
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3.7 Register Map

.All registers accessible via software are summarized in the table below. The address is
relative to the based address of the memory windows for the NIC.
Address Name Function Mode
0x000 VERSION syn1588®Clock IP core version number R
0x010 TSFIFO0RX_L Receive timestamp FIFO_0 data[31:0] R
0x018 TSFIFO0TX_L Transmit timestamp FIFO_0 data[31:0] R
0x01C TSFIFO1RX_L Receive timestamp FIFO_1 data[31:0] R
0x020 TSFIFO1TX_L Transmit timestamp FIFO_1 data[31:0] R
0x030 TSFIFO0_STATUS Four 6 bit counter in the TSFIFO and full/empty flags R
0x034 TSFIFO1_STATUS Four 6 bit counter in the TSFIFO and full/empty flags R
0x040 IRSRC Interrupt source R/W
0x044 IREN Enables various interrupts R/W
0x048 TIMECTRL Controls operation of the local clock R/W
0x04C EVENTCTRL Control of events R/W
0x050 SHDWSTEPPU_L Preload of new step size (pure phase), lower 32 bit R/W
0x054 SHDWSTEPPU_H Preload of new step size (pure phase), upper 32 bit R/W
0x060 IRTIME_L Time to send an interrupt, lower 32 bit R/W
0x064 IRTIME_H Time to send an interrupt, upper 32 bit R/W
0x080 SHDWTIME_L Preload of new time of the clock, first 32 bit W
0x084 SHDWTIME_M Preload of new time of the clock, middle 32 bit W
0x088 SHDWTIME_H Preload of new time of the clock, upper 32 bit W
0x08C SHDWTIME_E Preload of new time of the clock, high 32 bit W
0x090 TIME_L Current time, lower 32 bit R
0x094 TIME_M Current time, middle 32 bit R
0x098 TIME_H Current time, upper 32 bit R
0x09C TIME_E Current time, extended 32 bit R
0x0A4 EVENTTIME0_M Time of last event 0, middle 32 bit R
0x0A8 EVENTTIME0_H Time of last event 0, upper 32 bit R
0x0B0 EVENTTIME1_M Time of last event 1, middle 32 bit R
0x0B4 EVENTTIME1_H Time of last event 1, upper 32 bit R
0x0D0 TRIGTIME0_L Time to trigger event 0, first 32 bit R/W
0x0D4 TRIGTIME0_H Time to trigger event 0, upper 32 bit R/W
0x0D8 TRIGTIME1_L Time to trigger event 1, first 32 bit R/W
0x0DC TRIGTIME1_H Time to trigger event 1, upper 32 bit R/W
0x0F0 PERIODTIME0PU_L Period of timer 0, pure phase lower 32 bit R/W
0x0F4 PERIODTIME0PU_H Period of timer 0, pure phase upper 32 bit R/W
0x100 PERIODTIME1PU_L Period of timer 1, pure phase lower 32 bit R/W
0x104 PERIODTIME1PU_H Period of timer 1, pure phase upper 32 bit R/W
0x1E0 OSCPWM_CTR PWM control register for the oscillator adjustment R/W
0x1E4 CLOCKID_L Low word of the 64 bit EUI R
0x1E8 CLOCKID_H High word of the 64 bit EUI R
0x200 IOMATRIX External IO Interconnection definition R/W
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Address Name Function Mode

0x204 CLKFREQ Frequency of the input clock R
0x208 MIITS0_TXCTRL Generic Transmit Time stamper 0 control register R/W
0x20C MIITS1_RXCTRL Generic Receive Time stamper 1 control register R/W
0x210 MIITS1_TXCTRL Generic Transmit Time stamper 1 control register R/W
0x214 MIITS0_RXCTRL Generic Receive Time stamper 0 control register R/W
0x220 TIME2_M Current time, middle 32 bit R
0x224 TIME2_H Current time, upper 32 bit R
0x228 TIME2_E Current time, extended 32 bit R
0x400 MIITS0_RXMEM Generic Receive Time stamper 0 mask/pattern W
memory
0x600 MIITS0_TXMEM Generic Transmit Time stamper 0 mask/pattern W
memory
0x800 MIITS1_RXMEM Generic Receive Time stamper 1 mask/pattern W
memory
0xA00 MIITS1_TXMEM Generic Transmit Time stamper 0 mask/pattern W
memory
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Table 3: syn1588 Clock_M IP core register overview.
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3.7.1 Register Description
A detailed description of the contents of every register is given below. Keep in mind that no
checks of the validity of the data written to any registers of the syn588® NIC is made, thus
false data may corrupt the clock stability, the clock servo and other functions of the syn1588®
NIC.
3.7.1.1 Version Register (SYN1588_VER)
Address Mode Reset Value

0x000h R 4d323130h
SYN1588_VER(31:0) 4 digit ASCII version id, coded in the manner of the following example:
‘M’ .. 4dh,
‘2’ .. 32h .. major version id
nd
‘1’ .. 31h .. minor version id 2 digit
st
‘0’ .. 30h .. minor version id 1 digit
3.7.1.2 Receive Timestamp FIFO Data Register (TSFIFO0_RX)

0x010h R ????h
TSFIFO0_RX(31:0) 32 bit of data is read from the FIFO.
Details see description of TSFIFO0_TX.
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3.7.1.3 Transmit Timestamp FIFO Data Register (TSFIFO0_TX)

0x018h R ????h
TSFIFO0_TX(31:0) 32 bit of data is read from the FIFO..
Every timestamp is made up of four or six entries in the TSFIFO, depending on the version of
the clock synchronization protocol used. The first two entries are the ClockID, followed by the
port number and sequence ID for version 2008, MAC ID and sequence ID for version 2002.
The remaining entries are the timestamp itself; two entries (64 bit) for version 2002 and three
entries (96 bit) for version 2008 (upper 16 bit are zero padded) starting with the most
significant word first.
DWord Version 2002 Version 2008

1 MAC (upper 32 bit) ClockID0
2 MAC (lower 16bit), Sequence ID ClockID1
3 seconds PortNumber, Sequence ID
4 nanoseconds 0x0000, seconds extended
5 N/A seconds
6 N/A nanoseconds
3.7.1.4 Transmit Timestamp FIFO Data Register (TSFIFO1_RX)

0x01Ch R ????h
TSFIFO_TX(31:0) 32 bit of data is read from the FIFO..
3.7.1.5 Transmit Timestamp FIFO Data Register (TSFIFO1_TX)

0x020h R ????h
TSFIFO_TX(31:0) 32 bit of data is read from the FIFO..
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3.7.1.6 Timestamp FIFO Status Register (TSFIFO0_STATUS)

0x030h R ????h
TSFIFOCTRL(0) RX FIFO empty flag

TSFIFOCTRL(1) RX FIFO full flag
TSFIFOCTRL(15:2) RX FIFO word counter
TSFIFOCTRL(16) TX FIFO empty flag
TSFIFOCTRL(17) TX FIFO full flag
TSFIFOCTRL(31:18) TX FIFO word counter
3.7.1.7 Timestamp FIFO Status Register (TSFIFO1_STATUS)

0x034h R ????h
TSFIFOCTRL(0) RX FIFO empty flag

TSFIFOCTRL(1) RX FIFO full flag
TSFIFOCTRL(15:2) RX FIFO word counter
TSFIFOCTRL(16) TX FIFO empty flag
TSFIFOCTRL(17) TX FIFO full flag
TSFIFOCTRL(31:18) TX FIFO word counter
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3.7.1.8 Interrupt Source Register (IRSRC)

0x040h R/W 0000h
IRSRC(0) MIITS0_RX created a Timestamp

IRSRC(1) 1 if TSFIFO0_RX became full
IRSRC(2) MIITS0_TX created a Timestamp
IRSRC(3) 1 if TSFIFO0_TX became full
IRSRC(4) MIITS1_RX created a Timestamp
IRSRC(5) 1 if TSFIFO1_RX became full
IRSRC(6) MIITS1_TX created a Timestamp
IRSRC(7) 1 if TSFIFO1_TX became full
IRSRC(9:8) N/A
IRSRC(10) EVENT0 occurred if 1
IRSRC(11) EVENT1 occurred if 1
IRSRC(12) TRIGGER0 matched if 1
IRSRC(13) TRIGGER1 matched if 1
IRSRC(23:14) N/A
IRSRC(24) 1 if time of PERIODTIME0 has elapsed
IRSRC(25) 1 if time of PERIODTIME1 has elapsed
IRSRC(30:26) N/A
IRSRC(31) 1 if TIME overflowed
Writing a 0 to a bit clears the bit. Writing 1 to a bit does not influence its contents. Whenever
one of the above mentioned sources issues an interrupt the corresponding bit in the IRSRC
register is set and the interrupt line to the CPU is activated, if the appropriate bit in IREN is
set to 1.
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3.7.1.9 Interrupt Enable Register (IREN)

0x044h R/W 0000h
IREN(0) 1 enables MIITS0_RX received packet interrupt.

IREN(1) 1 enables TSFIFO0_RX full interrupt.
IREN(2) 1 enables MIITS0_TX sent packet interrupt.
IREN(3) 1 enables TSFIFO0_TX full interrupt.
IREN(4) 1 enables MIITS1_RX received packet interrupt.
IREN(5) 1 enables TSFIFO1_RX full interrupt.
IREN(6) 1 enables MIITS1_TX sent packet interrupt.
IREN(7) 1 enables TSFIFO1_TX full interrupt.
IREN(9:8) N/A
IREN(10) 1 enables Event 0 interrupt
IREN(11) 1 enables Event 1 interrupt
IREN(12) 1 enables Trigger 0 interrupt
IREN(13) 1 enables Trigger 1 interrupt
IREN(23:14) N/A
IREN(24) 1 enables PERIODTIME0 interrupt
IREN(25) 1 enables PERIODTIME1 interrupt
IREN(30:26) N/A
IREN(31) 1 enables TIME overflow interrupt
3.7.1.10 Time Control Register (TIMECTRL)

0x048h R/W 0000h
TIMECTRL(0) 1 loads all registers simultaneously with the values of their shadow
registers.
TIMECTRL(1) 0 .. two-step mode of transmit time stamping unit
1 .. one-step mode of transmit time stamping unit
TIMECTRL(28:2) N/A
TIMECTRL(29) 1 enables load of the Step Register for the amortisation phase with the
contents of its shadow register SHDWSTEP.
TIMECTRL(30) N/A
TIMECTRL(31) 1 enables load of the Time Register TIME with the contents of its shadow
register SHDWTIME.
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3.7.1.11 Event Control Register (EVENTCTRL)

0x04Ch R/W 0000h
EVENTCTRL(0) 1 enables event 0

EVENTCTRL(1) 1 enables event 1
EVENTCTRL(2) 1 enables trigger 0
EVENTCTRL(3) 1 enables trigger 1
EVENTCTRL(4) 1 enables PERIODTIME0
EVENTCTRL(5) 1 enables PERIODTIME1
EVENTCTRL(6) 1 enables PERIODTIME0 output
EVENTCTRL(7) 1 enables PERIODTIME1 output
EVENTCTRL(14:8) N/A
EVENTCTRL(16:15) “00” starts PERIODTIME0 with writing 1 to EVENTCTRL(4)
“10” RESERVED
“01” starts PERIODTIME0 with trigger 1
EVENTCTRL(18:17) “00” starts PERIODTIME1 with writing 1 to EVENTCTRL(5)
“10” RESERVED
EVENTCTRL(31:19) N/A
Whenever the input event_i(0) or event_i(1) exhibits a transition from 0 to 1 and the related
enable bit (i.e. EVENTCTRL(0) or EVENTCTRL(1)) is set to 1, further the corresponding flag
(i.e. IRSRC(10) or IRSRC(11)) is set to 1 and an interrupt to the CPU is generated, if enabled
in IREN.
Whenever the registers TRIGGERTIME0 or TRIGGERTIME1 are equal or smaller to the
corresponding value of the TIME register, the bits IRSRC(12) and IRSRC(13) respectively
are set. At the same time the outputs trigger_o(0) or trigger_o(1) are set to one. Bits are
cleared with next access to IRSRC register.
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3.7.1.12 Shadow Pure-Step Register (SHDWSTEPPU_L)

0x050h W 0000h
SHDWSTEPPU_L Lower 32 bit for the new value of the step size.
(31:0)
The 32 bits of this register will be added to the bits 23:-8 of the Time Register.
3.7.1.13 Shadow Pure-Step Register (SHDWSTEPPU_H)

0x054h W 0000h
SHDWSTEPPU_H Upper 32 bit for the new value of the step size.
(31:0)
The 32 bits of this register will be added to the bits 55:24 of the Time Register.
3.7.1.14 Shadow Time Register (SHDWTIME_L)

0x080h W 0000h
SHDWTIME_L(31:0) Lower 32 bit of the value that is copied into the TIME register.
3.7.1.15 Shadow Time Register (SHDWTIME_M)

0x084h W 0000h
SHDWTIME_M(31:0) Middle 32 bit of the value that is copied into the TIME register. Note that bit
31:30 are forced to 0.
3.7.1.16 Shadow Time Register (SHDWTIME_H)

0x088h W 0000h
SHDWTIME_H(31:0) Upper 32 bit of the value that is copied into the TIME register.
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3.7.1.17 Time Register (TIME_L)

0x090h R 0000h
TIME_L(31:0) Lowest 32 bit of the current time value. A read access causes a
simultaneous update of all four time registers with the current time of the
high accuracy clock
The unit of this register is sub nsec
3.7.1.18 Time Register (TIME_M)

0x094h R 0000h
TIME_M(31:0) Middle 32 bit of the current time. The value is updated only with the read
access to TIME_L. Note that the absolute value is limited to 10^9 in
conformance to the IEEE1588 standard.
The unit is nsec.
3.7.1.19 Time Register (TIME_H)

0x098h R 0000h
TIME_H(31:0) Upper 32 bit of the current time. The value is updated only with the read
access to TIME_L.
The unit is Seconds
3.7.1.20 Time Register (TIME_E)

0x09Ch R 0000h
TIME_E(31:0) Extended 16 bits of the current time The value is updated with the read access to
TIME_L.
The unit is 2^32 Seconds
Only the lower 16 bits are valid, the high word of this register is undefined.
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3.7.1.21 Event Time 0 Register (EVENTTIME0_L)

0x0A4h R 0000h
EVENTTIME0_L(31:0) Lower 32 bit of the time the last event on input event_i<0> occurred.
These bits correspond to the bits (63:32) of the TIME register.
EVENTTIME0_L and EVENTTIME0_H are both part of a 64Bit

EVENTTIME0 FIFO.
The fifo value gets updated to the next value with each read of the
EVENTTIME0_H register. So the read order of those two registers is
important. Read the EVENTTIME0_L first and the EVENTTIME0_H last.
EVENTTIME0 interrupts are only generated when the EVENTTIME0 FIFO

transitions from the empty state to the nonempty state. So in order to get
an interrupt on the next event, one need to read the EVENTTIME0 FIFO
until it is empty. The EVENTTIME0 FIFO is empty when consecutive
reads from EVENTTIME0_L and EVENTTIME0_H both return 0000h.
The EVENTTIME0 FIFO stores up to 16 event times.
3.7.1.22 Event Time 0 Register (EVENTTIME0_H)

0x0A8h R 0000h
EVENTTIME0_H(31:0) Upper 32 bit of the time the last event on input event_i<0> occurred.
Read the description of EVENTTIME0_L for the correct usage of this
register.
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3.7.1.23 Event Time 1 Register (EVENTTIME1_L)

0x0B0h R 0000h
EVENTTIME1_L(31:0) Lower 32 bit of the time the last event on input event_i<1> occurred.
3.7.1.24 Event Time 1 Register (EVENTTIME1_H)

0x0B4h R 0000h
EVENTTIME1_H(31:0) Upper 32 bit of the time the last event on input event_i<1> occurred.
3.7.1.25 Trigger Time 0 Register (TRIGTIME0_L)

0x0D0h R/W 0000h
TRIGTIME0_L(31:0) TRIGTIME0_L and TRIGTIME0_H are both part of a 64bit TRIGGER

TIME 0 FIFO.
Fill the TRIGGER TIME 0 FIFO by writing to TRIGTIME0_L first and
TRIGTIME0_H last.
If TRIGGER0 is deactivated in the EVENTCTRL register the TRIGGER
TIME 0 FIFO is in a reset state and its contents are flushed.
If the Trigger Time matches the time of the clock the TRIGTIME output is
toggled and the next entry of the TRIGGER TIME 0 FIFO is used as the
next Trigger Time.
The TRIGGER TIME 0 FIFO stores up to 16 entries.
Lower 32 bit of the time the trigger_o<0> output shall be set to 1. These
bits correspond to the bits (63:32) of the TIME register.
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3.7.1.26 Trigger Time 0 Register (TRIGTIME0_H)

0x0D4h R/W 0000h
TRIGTIME0_H(31:0) Upper 32 bit of the time the trigger_o<0> output shall be set to 1. These
To reset this trigger clear the corresponding bit in the IRSRC register.
3.7.1.27 Trigger Time 1 Register (TRIGTIME1_L)

0x0D8h R/W 0000h
TRIGTIME1_L(31:0) Lower 32 bit of the time the trigger_o<1> output shall be set to 1. These
3.7.1.28 Trigger Time 1 Register (TRIGTIME1_H)

0x0DCh R/W 0000h
TRIGTIME1_H(31:0) Upper 32 bit of the time the trigger_o<1> output shall be set to 1. These
To reset this trigger clear the corresponding bit in the IRSRC register.
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3.7.1.29 Period Time Register (PERIODTIME0PU_L)

0x0F0h R/W 0000h
PERIODTIME_L(31:0) Lower 32 bit of the period 0 output/interrupt.

These bits correspond to the bits (67:16) of the TIME register
16 bit nanoseconds, 16 bit sub-nanoseconds (fractional)
3.7.1.30 Period Time Register (PERIODTIME0PU_H)

0x0F4h R/W 0000h
PERIODTIME_H(31:0) Upper 32 bit of the period 0 output/interrupt.

16 bit seconds, 2 bit NA, 14 bit nanoseconds (high word)
The 64 bits of the registers PERIODTIME_L and PERIODTIME_H contain the amount of
time (notably not the number of clock cycles) to elapse after the last interrupt has been
triggered. At the point in time the periodical timer is enabled (by setting bit EVENTCTRL(4)
to 1), the contents of this register will be added to the actual contents of the Time Register at
position 79:16. The result will be stored in a separate register and if the contents of bits 80:16
of the Timer Register are equal or greater than the before registered value, the interrupt is
launched IRSRC(24). If now the periodical timer is still enabled (EVENTCTRL(4) still set to 1)
the next period is started immediately.
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3.7.1.31 Period Time Register (PERIODTIME1PU_L)

0x100h R/W 0000h
PERIODTIME1_L(31:0) Lower 32 bit of the period 1 output/interrupt.

16 bit nanoseconds, 16 bit sub-nanoseconds (fractional).
3.7.1.32 Period Time Register (PERIODTIME1PU_H)

0x104h R/W 0000h
PERIODTIME1_H(31:0) Upper 32 bit of the period 1 output/interrupt.

16 bit seconds, 2 bit NA, 14 bit nanoseconds (high word)
The 64 bits of the registers PERIODTIME1_L and PERIODTIME1_H contain the amount of
time (notably not the number of clock cycles) to elapse after the last interrupt has been
triggered. At the point in time the periodical timer is enabled (by setting bit EVENTCTRL(5) to
1), the contents of this register will be added to the actual contents of the Time Register at
position 79:16. The result will be stored in a separate register and if the contents of bits 80:16
of the Timer Register are equal or greater than the before registered value, the interrupt is
launched IRSRC(25). If now the periodical timer is still enabled (EVENTCTRL(5) still set to
1) the next period is started immediately.
3.7.1.33 PWM Control Register (OSZPWM_CTRL)

0x1E0h R/W 0000h
OSCPWM_CTRL(31) 0 inserts 0
1 inserts 1
OSCPWM_CTRL(16:0) Counter value for inserting 1 or 0 at the PWM output
Periodically inserts 1 or 0 till the counter reaches the value in the register OSZPWM_CTRL
(16:0). After the Value is reached, the PWM output toggles with each clock cycle till the
counter reaches the overflow and starts with value 0. 1 is inserted if the value of highest bit in
the register is set to 1, else there is 0 inserted. Valid values for the counter are 0x000 to
0x100. Value 0x000 the PWM output toggles permanent and with 0x100 the PWM output is
constant 1 or 0, depends on the bit 31 of the OSCZPWM_CTRL register.
The OSZPWM_CTRL register is used to alter the control voltage of an OCXO, if one is
installed on the board. This is used to fine tune the oscillator frequency of the OCXO.
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3.7.1.34 Clock ID register (low word) (CLOCKID_L)

0x1E4h R 0000h
3.7.1.35 Clock ID register (high word) (CLOCKID_H)

0x1E8h R 0000h
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3.7.1.36 Control Register for setting the IO Matrix (IOMATRIX)

0x200h R/W 0x00430059h
IOMATRIX(31-28) reserved
IOMATRIX(27) Level definition for SMA connector 3 input (X5)
0 = high active
1 = low active (inverted internally)
0 = high active
0 = high active
0 = high active
IOMATRIX(23:20) Source definition for event 1 input of syn1588®Clock_M
IOMATRIX(19:16) Source definition for event 0 input of syn1588®Clock_M
IOMATRIX(15:12) Source definition for SMA connector 3 output (X5)
For every of the possible six sinks (SMA connectors 0-3 and the two event inputs of the
syn1588®Clock_M IP core) a 4 bit pattern defines the source for this signal. Additionally
every output may be additionally inverted.
Value Description
0x0 disabled (output tri-state)
0x1 SMA connector 0 (X4)
0x5 period0_o signal of syn1588®Clock_M
0x7 trigger0_o signal of syn1588®Clock_M
0x9 1pps_o signal of syn1588®Clock_M
0xa -0xf disabled (output tri-state)
Encoding of sources for IOMATRIX register
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3.7.1.37 Input Clock Frequency Register (CLKFREQ)

0x204h R 0000h
This register is pre-programmed to the frequency of the external oscillator.
3.7.1.38 Time Register (TIME2_M)

0x220h R 0000h
TIME2_M(31:0) Middle 32 bit of the current time value. A read access causes a
simultaneous update of all three time2 registers with the current time of
the high accuracy clock . Note that the absolute value is limited to 10^9 in
conformance to the IEEE1588 standard.
The unit is nsec.
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3.7.1.39 Time Register (TIME2_H)

0x224h R 0000h
TIME2_H(31:0) Upper 32 bit of the current time. Contents is updated only with the read access
to TIME2_M.
The unit is Seconds
3.7.1.40 Time Register (TIME2_E)

0x228h R 0000h
TIME2_E(31:0) Extended 16 bits of the current time The value is updated with the read access
to TIME2_M.
The unit is 2^32 Seconds
Only the lower 16 bits are valid, the high word of this register is undefined.
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3.7.1.41 Control Register for Time Stamping Unit 0 Transmit (MIITS0_TXCTRL)

0x208h R/W 0000h
CTRL(31:24) OFF2 Offset value for the second data section to extract from the packet if a
match has been found. The values is counted in multiples of bytes
starting with the first byte after the SOF octet
CTRL(23:16) OFF1 Offset value for the first data section to extract from the packet if a
match has been found. The values is counted in multiples of bytes
starting with the first byte after the SOF octet
CTRL(15:12) LEN2 Length in number of bytes to extract from the packet starting at OFF2 to
be stored into the time stamping unit FIFO
Note: (LEN1 + LEN2) mod 4 = 0
CTRL(11:8) LEN1 Length in number of bytes to extract from the packet starting at OFF1 to
be stored into the time stamping unit FIFO
Note: (LEN1 + LEN2) mod 4 = 0
CTRL(7:0) NBYTES Number of byte in the packet to compare against the pattern&mask
memory
If NBYTES is set to 0 the time stamping unit is disabled
If NBYTES is larger than the total packet length no match is found
If the first NBYTES of the packet match against the pattern&mask RAM
the packet is matched.
Caution:
Do not alter this register if the card is operated as an IEEE1588 node (i.e. while the
syn1588® PTP stack is running) !
3.7.1.42 Control Register for Time Stamping Unit 1 Receive (MIITS1_RXCTRL)

0x20Ch R/W 0000h
See description of register bits chapter 3.7.1.41 .
3.7.1.43 Control Register for Time Stamping Unit 1 Transmit (MIITS1_TXCTRL)

0x210h R/W 0000h
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3.7.1.44 Control Register for Time Stamping Unit 0 Receive (MIITS0_RXCTRL)

0x214h R/W 0000h

Caution:
Do not alter this register if the card is operated as an IEEE1588 node (i.e. while the
3.7.1.45 Pattern & Mask Memory for TS Unit 0 Receive (MIITS0_RXMEM)

0x400h - 0x4FFh W undefined
Since the memory content is unknown following a reset the user (application) is responsible
for initializing the whole memory. Each pattern & mask memory is 256 entries deep, allowing
to define a search region within a packet of 512 octets.
MEM(31:24) MASK Allows to select the bits of (PATTERN Byte N+1) to be compared
Byte N+1 against the data in the packet. If a bit in the mask byte is set, the data
of the respective pattern byte is compared against the packet data. If
the bit is set to 0 the bit in the packet is ignored
MEM(23:16) PATTERN
Pattern data for byte N+1
Byte N+1
MEM(15:8) MASK Allows to select the bits of (PATTERN Byte N) to be compared against
Byte N the data in the packet. If a bit in the mask byte is set, the data of the
respective pattern byte is compared against the packet data. If the bit is
set to 0 the bit in the packet is ignored
MEM(7:0) PATTERN
Pattern data for byte N
Byte N
Caution:
Do not alter this memory if the card is operated as an IEEE1588 node (i.e. while the
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3.7.1.46 Pattern & Mask Memory for TS Unit 0 Receive (MIITS0_TXMEM)

MEM(23:16) PATTERN
Byte N+1
MEM(7:0) PATTERN
Byte N
Caution:
Do not alter this memory if the card is operated as an IEEE1588 node (i.e. while the
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3.7.1.47 Pattern & Mask Memory for TS Unit 1 Receive (MIITS1_RXMEM)

MEM(23:16) PATTERN
Byte N+1
MEM(7:0) PATTERN
Byte N
3.7.1.48 Pattern & Mask Memory for TS Unit 1 Receive (MIITS1_TXMEM)

0xA00h - 0xAFFh W undefined
MEM(23:16) PATTERN
Byte N+1
MEM(7:0) PATTERN
Byte N
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3.7.2 IEEE1588 Register Layout
Figure 19 IEEE1588 register layout
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3.8 Diagnostics
For further details on generating and using diagnostics see also chapter 6 and 7.
3.8.1 Verification of Installed Driver
For further details on generating and using diagnostics view Chapter 6 and 7.
3.8.2 Controlling the syn1588® PTP Stack
Unless otherwise noted the command line options are available for both Linux and Windows
version of the syn1588® PTP Stack.
The principle operation of the syn1588® PTP-Stack can be verified by use of the console log
messages as well as a packet dump on the corresponding Ethernet interface, e.g.
Whireshark or TCPdump. Please note that the verbosity level of the console output of the
syn1588® PTP Stack may be controlled by a command line parameter.
Selecting a syn1588® node to act as master or slave is done automatically following the best-
mast-algorithm defined in the IEEE1588 standard. No user interaction is required.
Important driver log messages can be found by using the dmesg command under Linux.
3.8.3 The syn1588app Utility
There is a simple utility “syn1588app” available that allows the user to read and write all
syn1588® registers. This utility eases debugging of your installed syn1588® hard- and
software as well as testing your own application.
Caution!
If you run the syn1588® PTP stack or any other software that accesses the syn1588® NICs
registers in parallel with this utility one may end up with unexpected behaviour of the
software.
Invoking the syn1588app is quite simple. Just run the executable either in a DOS window of
a Windows machine or any shell window of your Linux machine. One receives a short
copyright notice and version information.
C:\>syn1588app
Syn1588 Driver Interface, Version 1.0.0
Oregano Systems - Design & Consulting GesmbH Aug 5 2009
By entering the syn1588® register address one issues a read of this register. Please note that
you have to strip the 0x1000 prefix (base address of the syn1588® registers in the
syn1588®NICs) for the syn1588® register addresses in both the syn1588® PCI/PCIe NIC.
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Reading the version ID of the syn1588®Clock_M is as simple as entering 0x0 for the registers
address. The syn1588app replies with the contents of this register.
C:\>syn1588app
0x0
0x4c313030
The following example show a read of the IOMATRIX register (address 0x200) followed by a
write command to this register finally followed by another read operation to verify that the
write operation had succeeded.
C:\>syn1588app
0x200
0x00430059
0x200 0x00430959
0x200
0x00430959
3.8.3.1 Convenience Commands
The syn1588®app Utility also has some built in Commands for often used functions.
Id – Get the syn1588® Clock ID
With this command you can extract the PTP Clock Id from the syn1588® Clock.
Syntax:
id
Example:

Oregano Systems - Design & Consulting GesmbH Sep 28 2009
id
00:60:35:00:00:01:8e:96
Ver – Get the syn1588® Clock Version
This command extracts the Version of the syn1588® Clock.

Syntax:
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ver
Example:

ver
M 2.1.1
Time – Get/Set the current time of the syn1588® Clock
With the time command you can get and set the current time of the syn1588® Clock.
The optional parameter for this command is the time you want to set in seconds and
nanoseconds.
Syntax:
time [secs,nsecs]
Example:

time
143,853918448
time 1000,000
1000,000
time
1001,056843296
Cfgts – Configure an Ethernet Timestamping Unit
With this command you can configure one of the Ethernet packet timestamping units of the
syn1588® Clock. There are two Ethernet timestamping units inside the syn1588® Clock. The
reception side and the transmission side of each timestamping unit can be configured
separately.
Do not use this command to configure Ethernet timestamping unit 0 while the PTP Stack is
running. This will lead to a loss of sync of the node.
Syntax:
cfgts[timestamping unit 0|1][direction r|t] [offset0] [len0 0-15] [offset1]

[len1 0-15] [pattern] [mask] [pattern] [mask] ...
Example:
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cfgts0r 6 6 12 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x08 0xff
0x00 0xff
getts0r 8
7070,691085839 00 60 35 01 8C 37 08 00
This example shows how to generate timestamps for incoming Ethernet packets using the
cfgts command. In this example the receive side of timestamping unit 0 is configured to
extract the source MAC address and Ethernet type of incoming packets. Further the pattern
is configured to match ARP packets only. Note: the whole command has to be typed on a
single line.
Now we can extract the timestamps from the timestamp fifo using the getts command.
Getts – Get a Timestamp from an Ethernet Timestamping Unit
With this command you can extract timestamps that were created after a timestamper was
configured with the cfgts command and a packet was successfully timestamped.
Syntax:
getts [timestamp length] [pattern] ...
Example:
Have a look at the example for the cfgts command above.
Rate – Set the Rate of the syn1588® Clock
With the rate command you can manually configure the rate of the clock. This command is
only useful for quick testing purposes and should not be used while the syn1588® PTP stack
is running.
Syntax:
rate nsecs
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Example:

rate 1000000
Clrts – Clear the fifo of an Ethernet Timestamping Unit
With this command you can clear the fifo that stores the timestamps of a timestamping unit.
Syntax:
clrts[timestamping unit 0|1][direction r|t]
Example:

clrts0r
clrts0t
clrts1r
clrts1t
Event – Configure an Event Generation Resource
This command is used to configure the event Generation resources TRIGTIME and
PERIODTIME. With this command it is also possible to combine TRIGTIME0 with
PERIODTIME0 or TRIGTIME1 with PERIODTIME1. The command combines the
configuration of TRIGTIME0 with PERIODTIME0 and TRIGTIME1 with PERIODTIME1.
Depending on the parameters of the command it enables PERIODTIME, TRIGTIME or both.
If you set start_sec and start_nsec to zero, only PERIODTIME is enabled. If you set
period_sec and period_nsec to zero, only TRIGTIME is enabled. If you set both,
PERIODTIME is enabled after the timeout of TRIGTIME is reached.
Syntax:
event [port 0-3] [resource number 0 1] start_sec,start_nsec

period_sec,period_nsec
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Example:

event 0 0 2,500000 0,0
event 1 0 0,0 0,500000
event 2 1 5,0 0,250000
Here we have four examples of the usage of the event command. Example 1 shows how to
set a trigger event on SMA port 0 using TRIGTIME0 and waiting for 2 and a half seconds.
Example two shows how to create a periodical signal on SMA port 1 using PERIODTIME0
that toggles every 500000 nanoseconds. Example 3 shows how to combine TRIGTIME and
PERIODTIME. Here we want an event for SMA port 2 using TRIGTIME1 and
PERIODTIME1. We wait until a timeout of 5 seconds is reached by TRIGTIME1 and then the
signal toggles every 250000 nanoseconds using PERIODTIME1.
Pps – Route the syn1588® One Pulse per Second to any SMA Port
The PPS command can be used to route the 1 PPS pulse of the syn1588® Clock to any SMA
output port of the syn1588® PCI/PCIe NIC.
Syntax:
pps [portNr 0-3]
Example:

0x200 0x0
0x200
0x00000000
pps 0
0x200
0x00000009
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Regev – Enable an Event Input and route an SMA Port to it.
With the REGEV command you can enable one of the two Event Input Resources of the
syn1588® Clock and route a SMA input port to it.
Syntax:
regev [port 0-3] [eventinput 0|1]
Example:

regev 0 0
0x200
0x00010000
0x200 0x00090000
wait 0 1 1
3784,598866427
This example needs a little explanation: To show the two functions regev and wait in action,
this command uses the IOMATRIX register to reroute the one PPS pulse internally.
Wait – Wait for an Event on an enabled Event Input
With the wait command you can wait on the interrupt of one of the Event Inputs and extract
the created timestamp if successful.
Syntax:
wait [PortNr 0-3] [EventInput 0|1] [Timeout secs]
Example:
See Regev for an example usage of the wait command.
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3.9 Using the syn1588® PCI NIC

The following sections describe details and some frequently asked questions concerning the
usage of the syn1588® PCI NIC.
3.9.1 Interoperability
The syn1588® PCI NIC has proven compatibility with the corresponding standards by
passing various in-house test scenarios and successful participation in the IEEE1588
compatibility plug-fest organized at the ISPCS conference on a regular basis.
3.9.2 1PPS Output
As soon as the on-board clock of the syn1588® PCI NIC is activated by the software, a one
pulse per second (PPS) output is generated on the SMA connector X4 (next to the RJ45
Ethernet jack). Depending on the accuracy of the clock settings and whether a PTP stack is
running and periodically correcting the local clock, the 1 PPS output shows a rising edge at
the beginning of each second, holding the output to logic 1 for a duration of a few hundred
milliseconds. The syn1588® clock of the chip is derived from an external 25 MHz oscillator
and internally multiplied in a PLL to 62,5 MHz.
Please note that the actual output has a constant delay of three clock cycles plus the clock to
output delay of the chip. On the syn1588® PCI NIC this is
3*(1/62,5 MHz) + 0,36 ns = 48,36 ns.
Here the delay of the board trace from the chip to the SMA connector has been neglected.
Note that if several 1 PPS outputs (e.g. GPS receiver) are to be compared via measurement
equipment, also to cable delay has to be taken into account.
The 1 PPS signal of the clock can be rerouted to any of the four available SMA connectors of
the syn1588® PCI NIC by writing a corresponding value to the IOMATRIX register of the chip.
See the API documentation in Chapter 6 for further details on how to access the hardware
features from application software.
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3.9.3 Frequency Output
To generate a periodic signal, which is derived directly from the synchronized syn1588®
clock, the corresponding values of the PERIODx and related control registers have to be set
accordingly in the chip.
The syn1588® clock of the chip is derived from an external 25 MHz oscillator and internally
multiplied in a PLL to 62,5 MHz. It is thus not possible to generate a frequency larger than
31 MHz out of the periodic timer units of the syn1588® PCI NIC chip. Please note that the
clock resolution is not bounded by the period of the frequency driving the syn1588® clock of
the chip, which is 1/62,5 MHz = 16 ns since the PERIOD registers allow the definition of
16 bit sub-nanoseconds for the clock period (see chapter 3.7.2).
The output of the periodic timer unit can be rerouted to any of the four available SMA
connectors of the syn1588® PCI NIC by writing a corresponding value to the IOMATRIX
register of the chip.
Please note that the actual output has a constant delay of the clock to output delay of the
chip. On the syn1588® PCI NIC this is about 0,36 ns.
3.9.3.1 Example
Assume one would like to generate a PERIOD output signal with a frequency of 500 kHz on
connector X7. Connector X7 is the default connector for the period timer PERIOD0. There
are two PERIOD0 registers PERIODTIME0PU_L (address 0xF0) and PERIODTIME0PU_H
(address 0xF4) which hold combined the half period in nanoseconds of the output signal to
be generated using the notation “48 bit , 16 bit”. Maximum half period is thus 248 while the
resolution is 2-16.
The half period for a 500 kHz signal is 1 µs or 1000 ns. Thus one has to write the value 0x0
to the register PERIODTIME0PU_H and 0x3E80000 to the register PERIODTIME0PU_L.
Note that 0x3E8 is hexadecimal for 1000 while the remaining 0x0000 stand for the 16 bit
fractional part (sub-nanoseconds).
After defining these values one has to activate the PERIOD0 output via the EVENTCTRL
register. Please note, that for simplicity we just write the whole EVENTCTRL (address 0x4C)
register in this example. In real life applications one would have to read the register first and
set/reset the intended bits carefully in order to avoid that bits set by other software are
affected.
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Writing these values can be accomplished simply from command line by using the
“syn1588app” utility. See chapter 3.8.3 for more details on this utility. The following listing
shows how the values are written to the registers and read back.
C:\>syn1588app
0xf0 0x3e80000
0xf4 0x0
0xf0
0x03e80000
0xf4
0x4c 0x0
0x4c
0x00000000
0x4c 0x50
0x4c
0x00000050
For a detailed description of the mentioned registers see chapter 3.7
3.9.4 Changing IO Functions
The syn1588® PCI NIC offers four SMA connectors on the rear side at the PCI bracket.
These SMA connectors are assigned default functions like 1PPS signal output and frequency
output. The following table lists the default functions of the four SMA connectors. See Figure
16 for exact position of the four connectors mentioned in this chapter.
Connector Description
X4 1PPS output
connector next beside RJ45
X7 frequency output
X6 event input
X5 1PPS input
top most connector
Table 4 Default functions of the SMA connectors
The user may change these default assignments via programming the register “IOMATRIX”
that is described in the following sub-chapter.
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3.9.4.1 IOMATRIX Register

0x0200 RW 0x00430059
Bit # Access Description

31-28 RW reserved
RW Level definition for SMA connector input (X5)
27 0 = high active
26 0 = high active
25 0 = high active
24 0 = high active
23-20 RW Source definition for event 1 input of syn1588®Clock_M
19-16 RW Source definition for event 0 input of syn1588®Clock_M
15-12 RW Source definition for SMA connector 3 output (X5)
Table 5 IOMATRIX register bit description
For every of the possible six sinks (SMA connectors 0-3 and the two event inputs of the
syn1588®Clock_M IP core) a 4 bit pattern defines the source for this signal. Additionally
every output may be additionally inverted.
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Value Description
0x0 disabled (output tri-state)

0x1 SMA connector (X4)
0x9 1pps_o signal of syn1588®Clock_M
0xa -0xf disabled (output tri-state)
Table 6 Encoding of sources for IOMATRIX register
The reset value 0x00430059 defines the following behaviour:

• 0x00430059: SMA input signals are not inverted
• 0x00430059: event input 1 of syn1588®clock_M is driven by connector signal X7
• 0x00430059: event input 0 of syn1588®clock_M is driven by connector signal X6
• 0x00430059: SMA output X5 is disabled
• 0x00430059: SMA output X6 is disabled
• 0x00430059: SMA output X7 is driven by the period 0 signal of syn1588®clock_M
• 0x00430059: SMA output X4 is driven by the 1pps signal of syn1588®clock_M
The register is under control of software running in the user space (“the user application”); no
kernel mode software is required.
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3.9.4.2 Example 1
Assume one would like to receive the 1PPS output signal not only on connector X4 but also
on connector X6. Thus the third nibble of the IOMATRIX register that defines the source for
connector X6 has to be changed from 0x0 (disabled) to 0x9 (1pps_o signal of
syn1588®Clock_M).
Writing the value 0x00430959 to the IOMATRIX register results the intended function. This
can be accomplished simply from command line by using the “syn1588app” utility. See
chapter 3.8.3 for more details on this utility.
C:\>syn1588app
0x200
0x00430059
0x200 0x00430959
0x200
0x00430959
3.9.4.3 Example 2
Assume one would like to receive the 1PPS output signal not only on connector X4 but also
as event on the input 0 of the syn1588®Clock_M. Thus the fifth nibble of the IOMATRIX
register that defines the source for event 0 input of the syn1588®Clock_M has to be changed
from 0x3 (X6) to 0x9 (1pps_o signal of syn1588®Clock_M).
Writing the value 0x00490059 to the IOMATRIX register results the intended function. This
can be accomplished simply from command line by using the “syn1588app” utility. See
chapter 3.8.3 for more details on this utility.
C:\>syn1588app
0x200
0x00430059
0x200 0x00490059
0x200
0x00490059
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3.9.5 Timestamping User Defined Packets
The timestamping unit used in Oregano Systems’s syn1588® PCI NIC allows the
independent detection of two different packets for both receive and transmit direction. One
timestamper unit is used for detecting IEEE1588 packets and thus used by the syn1588®
PTP stack. The second timestamping unit may be used by the customer and its software to
detect and timestamp any packet.
3.9.5.1 Introduction
This section briefly outlines the required actions in the user software. A simple example is
presented that may be easily extended to meet your specific requirements.
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Figure 20. MII timestamping units in the syn1588 PCI/PCIe NIC
Please note that the Oregano timestamping units acts as a passive observer on the GMII/MII
interface. It does not alter data transferred on this interface.
The following figure shows the basic timestamper structure; the timestamping comparator.
Two of these comparators made up one timestamping unit. Two timestamping units and thus
four timestamping comparators are available in the syn1588® PCI NIC.
Figure 21. Basic timestamper comparator
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The time stamping unit will compare the first NBYTES octets of the packet against the data in
the pattern&mask memory as expressed in a c-style syntax below (pattern and mask refer to
the respective octets in the pattern&mask memory.
Match = 0;
for (i:= 0; i < NBYTES; i++)
Match += ((packet(i) & mask(i)) ^ pattern(i)) ^ 0xFF;
The timestamping comparator enables checking the first 256 bytes of an Ethernet packet.
The compare process starts with the first byte following the SFD (start-of-frame-delimiter),
i.e. the first byte of the destination MAC address. For every byte of the packet the user may
define an expected value (the pattern) and a mask value. For all bits that are set to one in the
mask the value of the pattern is compared against the value of the actual (G)MII data byte.
For every timestamping comparator there is a control register. One is able to enable the
timestamper comparator as well as to define the length of the check performed. Additionally
one may extract two sections out of the Ethernet packet controlled by this register.
The example given below shows the configuration of the RX and TX time stamping unit 0 to
detect IEEE1588 layer 2 packets.
writeReg(MIITS0_RXMEM + 6*4, 0xFFF7FF88); // Ethernet Type 0x88F7
writeReg(MIITS0_RXMEM + 7*4, 0x0F020C00); // MsgType 0-3, Version 2
if (m_cfg->nwMode == 1)
writeReg(MIITS0_RXMEM + 10*4, 0x00000404); // Unicast Flag
writeReg(MIITS0_TXMEM + 6*4, 0xFFF7FF88); // Ethernet Type 0x88F7
writeReg(MIITS0_TXMEM + 7*4, 0x0F020C00); // MsgType 0-3, Version 2
if (m_cfg->nwMode == 1)
writeReg(MIITS0_TXMEM + 10*4, 0x00000404); // Unicast Flag
// RX extract: SeqId off | SrcMAC off| SeqId len | SrcMac len| cap len
writeReg(MIITS0_RXCRTL, (44 << 24) | (6 << 16) | (6 << 12) | (6 << 8) | 22);
// TX extract: SeqId off | DstMAC off| SeqId len | DstMac len| cap len
writeReg(MIITS0_TXCRTL, (44 << 24) | (0 << 16) | (6 << 12) | (6 << 8) | 22);
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3.9.5.2 MII Timestamp Control Register
There are four MII Timestamp Control registers available; one for each timestamping
comparator. The following table shows the contents of this MII Timestamp Control register.
Bit(s) Description
NBYTES[7:0] number of packet bytes to be compared with pattern & mask memory
A length of 0 disables the unit
LEN1[11:8] number of bytes extracted starting at byte OFF1. The number of
extracted bytes is LEN1 * 2
LEN2[15:12] number of bytes to extracted starting at byte OFF2. The number of
extracted bytes is LEN2 * 2
OFF1[23:16] offset used for extracting LEN1*2 bytes from the packet.
OFF2[31:24] offset used for extracting LEN2*2 bytes from the packet.
Table 7 MII Timestamp Control Register – register bits
The following table lists the address of these control registers. Note that the address listed is
the local address of the syn1588® PCI/PCIe card.
Address Description
0x1214 MII Timestamper #0 Receive – control register
0x1208 MII Timestamper #0 Transmit – control register
0x120c MII Timestamper #1 Receive – control register
0x1210 MII Timestamper #1 Transmit – control register
Table 8 Address map of the MII Timestamp Control Registers
For every timestamping unit there is a pattern and mask memory defining the comparator
condition. Every memory holds 256 entries of two times eight bit thus 512 bytes. The
following table lists the base address of these pattern & mask memories.
Address Description
0x1400 MII Timestamper #0 Receive – pattern & mask memory
0x1600 MII Timestamper #0 Transmit – pattern & mask memory
0x1800 MII Timestamper #1 Receive – pattern & mask memory
0x1a00 MII Timestamper #1 Transmit – pattern & mask memory
Table 9 Addresses map of the MII Timestamp patter and mask memories
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At the even byte of the pattern and mask memory the pattern is stored while at the odd byte
the mask value resides.
For every timestamping comparator there is a timestamping FIFO. Whenever one compa-
rator unit detects a packet matching its comparator condition the packet’s timestamp value
as well as optional data extracted out of the packet are stored in this timestamping FIFO.
Additionally an interrupt is generated informing the user application or the syn1588® PTP
stack that there is new data available.
Address Description
0x1010 MII Timestamper #0 Receive FIFO
0x1018 MII Timestamper #0 Transmit FIFO
0x101C MII Timestamper #1 Receive FIFO
0x1020 MII Timestamper #1 Transmit FIFO
Table 10 Addresses of the MII Timestamp FIFOs
Finally there is a status register for every RX/TX timestamp FIFO pair available.
Bit(s) Description
RX FIFO EMPTY[0] a ‘1’ flags that the RX timestamp FIFO is empty
RX FIFO FULL[1] a ‘1’ flags that the RX timestamp FIFO is full
RX FIFO CNT[9:2] number of words available in the RX timestamp FIFO
RESERVED[15:10] reserved
TX FIFO EMPTY[16] a ‘1’ flags that the TX timestamp FIFO is empty
TX FIFO FULL[17] a ‘1’ flags that the TX timestamp FIFO is full
TX FIFO CNT[25:18] number of words available in the TX timestamp FIFO
RESERVED[31:26] reserved
Table 11 Timestamp FIFO Status Register – register bits
Address Description
0x1030 MII Timestamper #0 FIFO Status
0x1034 MII Timestamper #1 FIFO Status
Table 12 Address map of the MII Timestamp FIFO Status Register
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3.9.5.3 User Timestamping Demo Design
This simple example shows how to setup timestamping unit for comparatoring any Ethernet
packet. The mission: Timestamp every ARP packet sent or received.
For performing this action one comparators the type/length field of the
Ethernet packet for the value 0x0806 denoting that this packet contains an
ARP. The source code is shown in
#include "syn1588_ifc.h"
#include "stdio.h"
#include "unistd.h"
#define MIITS0_RXCTRL 0x214

#define MIITS0_TXCTRL 0x208
#define MIITS1_RXCTRL 0x20C
#define MIITS0_RXMEM 0x400

#define MIITS0_TXMEM 0x600
#define MIITS1_TXMEM 0xA00
#define TSFIFO_STAT0 0x30

#define TSFIFO_RX0 0x10
#define TSFIFO_TX0 0x18
#define TSFIFO_RX1 0x1C
void setupMIITS(Syn1588Ifc *syn, unsigned ctrlReg, int nbytes, int len1, int
off1, int len2, int off2) {
syn->writeReg(ctrlReg, nbytes + (len1 << 8) + (off1 << 16) + (len2 <<

12) + (off2 << 24));
int main() {
Syn1588Ifc syn;
printf("Version: %08x\n", syn.readReg(syn.syn1588_VER));
// Timestamper memory, each entry has the following layout

// mask(n+1) | pattern(n+1) | mask(n) | pattern(n)
// this setting observes the ethernet type field, and matches
// on 0x0806 (ARP)
unsigned long ts_mem[] = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
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0xFF06FF08,
};
for (size_t i = 0; i < sizeof(ts_mem) / sizeof(unsigned long); i++) {
syn.writeReg(MIITS1_RXMEM + i*4, ts_mem[i]);
syn.writeReg(MIITS1_TXMEM + i*4, ts_mem[i]);
}
// Enable the Timestamper1 in both directions

// matching length 14 Bytes,
// grab the first 14+2 Bytes and append it to timestamp in the Fifo
setupMIITS(&syn, MIITS1_RXCTRL, 14, 14, 0, 2, 14);
setupMIITS(&syn, MIITS1_TXCTRL, 14, 14, 0, 2, 14);
int got;
while (1) {
got = 0;
// poll from Receive Fifo and display
while (!(syn.readReg(TSFIFO_STAT1) & 0x1)) {
usleep(10);
printf("RX1: %08x\n", syn.readReg(TSFIFO_RX1));
got = 1;
}
if (got) printf("--------------\n"); // separating line
got = 0;
// poll from Transmit Fifo and display
usleep(10);
printf("\t\tTX1: %08x\n", syn.readReg(TSFIFO_TX1));
got = 1;
}
if (got) printf("\t\t--------------\n");// separating line
usleep(100000);
}
return 0;
}
There is a setup process “setupMIITS” and the “main” process. Every step is well
commented.
#include "syn1588_ifc.h"
#include "stdio.h"
#include "unistd.h"
#define MIITS0_RXCTRL 0x214

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#define MIITS1_RXCTRL 0x20C


#define MIITS0_TXMEM 0x600
#define MIITS1_TXMEM 0xA00

#define TSFIFO_RX0 0x10
#define TSFIFO_RX1 0x1C
void setupMIITS(Syn1588Ifc *syn, unsigned ctrlReg, int nbytes, int len1, int
off1, int len2, int off2) {
syn->writeReg(ctrlReg, nbytes + (len1 << 8) + (off1 << 16) + (len2 <<

12) + (off2 << 24));
int main() {
Syn1588Ifc syn;
printf("Version: %08x\n", syn.readReg(syn.syn1588_VER));
// Timestamper memory, each entry has the following layout

// mask(n+1) | pattern(n+1) | mask(n) | pattern(n)
// this setting observes the ethernet type field, and matches
// on 0x0806 (ARP)
unsigned long ts_mem[] = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
0xFF06FF08,
};
for (size_t i = 0; i < sizeof(ts_mem) / sizeof(unsigned long); i++) {
syn.writeReg(MIITS1_RXMEM + i*4, ts_mem[i]);
syn.writeReg(MIITS1_TXMEM + i*4, ts_mem[i]);
}
// Enable the Timestamper1 in both directions

// matching length 14 Bytes,
// grab the first 14+2 Bytes and append it to timestamp in the Fifo
setupMIITS(&syn, MIITS1_RXCTRL, 14, 14, 0, 2, 14);
setupMIITS(&syn, MIITS1_TXCTRL, 14, 14, 0, 2, 14);
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int got;
while (1) {
got = 0;
// poll from Receive Fifo and display
usleep(10);
printf("RX1: %08x\n", syn.readReg(TSFIFO_RX1));
got = 1;
}
if (got) printf("--------------\n"); // separating line
got = 0;
// poll from Transmit Fifo and display
usleep(10);
printf("\t\tTX1: %08x\n", syn.readReg(TSFIFO_TX1));
got = 1;
}
if (got) printf("\t\t--------------\n");// separating line
usleep(100000);
}
return 0;
}
Table 13 Example for controlling the MII timestamper (“main.cpp”)
The ZIP file “miits.zip” includes this code example as well as all the included files and a
Makefile required to build the software.
basictypes.h
clock_ifc.h
main.cpp
Makefile
syn1588_ifc.cpp
syn1588_ifc.h
Table 14 Content of the “miits.zip” file
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3.9.6 Synchronizing to GPS: ESYNC
Some applications require the notion of time of the IEEE1588 system and network to be tied
to a reference time scale (e.g. GPS time) with the highest possible accuracy. The setup
described in the following offers a cheap and easy way to do exactly this with the help of an
Oregano Systems’ syn1588® NIC and a COTS GPS receiver.
The required components include a GPS receiver with antenna. The GPS receiver has to
have a 1 PPS output signal of sufficient accuracy as required by the application and a NMEA
compatible serial interface. Furthermore a computer or system is needed, able to connect to
the GPS receiver via a RS232 interface or equivalent. Also a syn1588® NIC (either PCI or
PCIe) is needed. The 1 PPS output of the GPS receiver has to be connected to one SMA
input of the syn1588® NIC to allow for precise timestamping.
Note that the used syn1588® NIC does not have to be changed, however, the PTP stack
running on the computer or system must be forced to act as master of the PTP network by
invoking the PTP application e.g. “ptp –C M_EXT”. Having a GPS receiver connected to a
PTP slave and having the two time scales, i.e. PTP time and GPS time synchronized, may
result in instable behaviour of the slave.
The actual synchronization between the PTP time and GPS time is achieved by invoking an
additional executable “esync” while the PTP stack is running. See the following log for some
details.
Figure 22: Setup for synchronizing to GPS
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eSync - External GPS Synchronization engine, Version 1.1.0

usage: esync [-h][-v logLevel][-c comPort][-l latency1PPS][-e][-p smaPort]
-h shows this usage screen

-v logLevel change verbosity level (0..4)[0]
-c comPort set serial communication port [COM1/ttyS1]
-l latency1PPS set latency of the 1PPS input in ps [0]
-e print Event Input timestamp
-p smaPort select SPA Port 1=X5,2=X6,3=X7
Note that this program will synchronize the clock of the PTP master to the GPS time with the
same algorithm that is used for the PTP synchronization in the stack itself. The
communication of the program with the GPS receiver is limited to the widely used NMEA
protocol.
The “esync” application is distributed with Oregano Systems’ syn1588® products and can
thus easily be extended. The source code of the “esync” application is available for all
customers that licensed the syn1588® PTP Stack source code.
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3.9.7 Synchronizing the System Clock: LSYNC
Frequently user require to synchronize the node’s system clock to the highly accurate
synchronised IEEE1588 clock maintained by the syn1588® PTP stack on the syn1588® PCI
NIC instead of accessing the hardware clock directly. This chapter briefly describes typical
questions, common misunderstandings and solutions.
The syn1588® PTP Stack Does Not Sync the System Clock !
A common misunderstanding is the function of the syn1588® PTP stack. This software is
responsible for maintaining the IEEE1588 functions and thus the hardware clock. These
functions are independent from the selected operating system. That’s why the syn1588®
basically runs on “any” operating system (of course there has to be a network driver support
for the syn1588® NICs).
Unfortunately there is no standard way how to access or maintain the system clock in
different operating systems. That’s why the syn1588® cannot synchronize directly the node’s
system clock.
LSYNC
There is a utility called “LSYNC” that enables the user to synchronize several syn1588® NICs
to each other as well as to the system clock. This application is responsible for local
synchronization of at least two clocks. For example LSYNC can be used to synchronize the
system clock to a syn1588® hardware clock found on any Oregano syn1588® NIC.
This utility is available on the syn1588® Live CD for all our syn1588® NIC customers. The file
is named “lsync” for Linux OS and “lsync.exe” for Windows OS. These are the command line
parameters of LSYNC:
PTPv2\bin>lsync -h
usage: lsync [-h][-v logLevel][-U UtcOffset] -O A|L|0|1
-h shows this usage screen

-v logLevel change verbosity level (0..4) [0]
-U utcOffset add utcOffset to local clock [0]
-O forceOrigin force the sync origin
A...automatic sync origin
L...local clock
N...syn1588(R) NIC (requires -i)
-i interface use Interface given by Name(Linux)/IP-Address(Win) [any]
Note, that the parameter “-O” is not an optional but a required parameter.
PTPv2\bin>lsync
Command line parse error: -O is a required parameter
Use -h option for help.
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The parameter “-O” defines the origin for synchronizing the clocks.
“-O N –i <ip_address>” for Windows or “-O N –i <device>” for Linux selects the mentioned
syn1588(R) NIC as the master and syncs all other syn1588(R) NIC clocks as well as the
system clock to the selected syn1588(R) NIC. Please note that the option “-O N” requires the
option “-i <interface>”.
“-O L” selects the local system clock as the master and synchronizes all syn1588(R) NIC
hardware clocks to the system clock.
“-O A” selects the auto mode. One has to distinguish two modes of operation
• A syn1588® PTP Stack is running on the node (in SLAVE mode)
• No syn1588® PTP Stack is running on the node
I.) A syn1588® PTP Stack is running on the node in SLAVE mode
Ia.) The node is equipped with one syn1588®NIC
LSYNC will synchronize the system clock of the node to the syn1588® NIC
IIb.) The node is equipped with two or more syn1588® NICs
LSYNC will synchronize the system clock of your node to the syn1588® NIC where the
syn1588® PTP Stack runs in SLAVE mode. Additionally LSYNC will synchronize all
other syn1588® NICs to the syn1588® NIC where the syn1588® PTP Stack runs in
SLAVE mode.
II.) No syn1588® PTP Stack is running on the node
The system clock will be the clock master for LSYNC
IIa.) The node is equipped with one syn1588® NIC
LSYNC will synchronize the syn1588® NIC to the system clock.
IIb.) The node is equipped with two or more syn1588® NICs
All X4 SMA connectors (that's the one next beside of the RJ45 network connector on
the syn1588® PCI/PCIe NICs) need to be connected to each other. LSYNC will all
syn1588® NICs to the system clock.
The option “-U utcOffset” enables the user to add the leap seconds when synchronizing the
IEEE1588 clock hold in the syn1588(R) NIC. Note that the system clock and the IEEE1588
clocks inherently use a different time notation.
Example of an unsuccessful “lsync” invocation:
PTPv2\bin>lsync -ON -i 192.168.102.64
lSync - Local Synchronization engine, Version 1.1.0 Rev 125 $
Oregano Systems - Design & Consulting GesmbH Feb 18 2011
COMMAND LINE UTC OFFSET VERISON. UTC OFFSET = 0

Device \\.\SYN1588 0 not found
No Syn1588 Clock with given Clock Id found
ClockId 00:00:00:00:00:00:00:00
IIR M2S init
IIR Path init
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At least two clocks are neccessary for local synchronization
Deprecated Simple Solution

One writes a simple user application that regularly (i.e. once every 15 minutes) reads the
TIME or TIME2 registers of the syn1588® NIC and sets the system clock accordingly.
Caution
There is an important drawback of this simple solution. The system time will “jump” since you
update the clock by setting it to a new time. Some applications don’t like discontinuities in the
clock at all. And the time may also jump backwards (!) if the system clock runs too fast
(compared to the accurate synchronized hardware clock).
Common Issues
Using a standard syn1588® PCI or PCIe NIC as master will end up with a somewhat high
jitter performance. This is due to the (simple and cheap) local clock source. We recommend
to use OCXO equipped syn1588® NICs for this purpose. One may also use an external time
reference (e.g. GPS) to overcome this issue.
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4 syn1588® PCIe NIC

The syn1588® PCIe NIC is a 10/100/1000 Mbps Ethernet network interface card (PCI
Express interface card) with enhancements to provide the network node with accurate clock
synchronization via Ethernet according to the IEEE1588 standard (see Figure 23). The
syn1588® PCIe NIC uses Oregano’s syn1588® technology for time stamping of dedicated
packets in the card’s integrated circuit.
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Figure 23: syn1588 PCIe NIC
As the hardware assisted time stamping mechanism has been designed using a generic
architecture, the syn1588® network card supports both version 2002 and version 2008 of the
IEEE1588 standard. Oregano Systems offers the Precision Time Protocol (PTP) Stack
supporting either version 2002 or version 2008 of the IEEE1588 standard.
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4.1 Features
• 10/100/1000 Mbit/s Ethernet network interface card compliant to IEEE802.3-2000
• IEEE1588 hardware timestamping supported
• Two-step as well as one-step timestamping supported
• Clock accuracy up to 50 ns
• Linux driver available (binary and source included with the NIC)
• Windows driver available (binary included with the NIC)
• syn1588® PTP Stack available for Linux and Windows (binary included with the NIC)
• Supports all IEEE1588 version 2008 enhancements
o Transparent clocks
o Management messages
o Unicast messages
• PCI Express card (half height)
• Up to four programmable I/O signals routed to SMA jacks (3V3 LVCMOS)
• Two independent and programmable timestamping units available for receive and
transmit, enabling parallel timestamping of user specified packets
• Operating temperature range 0 – 50°C
Optional features:
• High accuracy local oscillator (OCXO). With the help of the OCXO the frequency stability
increases from 100 PPM to 0.5 PPM. This is very useful if you want to operate the
syn1588® PCIe NIC as a free running Master Clock.
• Connectivity to an external GPS receiver via a 1pps input as well as the serial port of the
host PC. When the syn1588® PCIe NIC is synced to a GPS receiver in this way, you can
effectively sync your whole network to GPS using additional syn1588® Products.

See the description for the syn1588® PCI NIC in Section 3.2. On the syn1588® PCIe NIC the
32-bit PCI bus is translated into a PCI Express bus on board level. The internal chip design
of the central FPGA device is the same as for the syn1588® PCI NIC.

For technical specification details please refer to the product datasheet.
4.4 Installing the syn1588® PCIe NIC Hardware

See the description for the syn1588® PCI NIC in Section 3.4.
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4.5 Testing the syn1588® PCIe NIC with the syn1588® Live CDROM
4.6 Installing the syn1588® PCIe NIC Software

4.7 Register Map

See chapter 3.7 for a description of the syn1588® PCIe NIC registers. Basically the registers
for the syn1588® PCIe NIC and the syn1588® PCI NIC are identical.
4.8 Diagnostics
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4.9 Using the syn1588® PCIe NIC

4.9.1 1PPS Output
See chapter 3.9.2 for more details on generating a 1PPS output signal. Please note that the
internal syn1588® clock frequency for the syn1588® PCIe NIC is 88.88 MHz (instead of
62.5 MHz for the syn1588® PCI NIC).
4.9.2 Frequency Output
See chapter 3.9.3 for more details on generating a frequency output signal. Please note that
the internal syn1588® clock frequency for the syn1588® PCIe NIC is 88.88 MHz (instead of
62,5 MHz for the syn1588® PCI NIC). Thus the maximum frequency of a generated periodical
signal is 42 MHz.
4.9.3 Changing IO Functions
The syn1588® PCIe NIC offers two SMA connectors on the rear side at the PCI bracket.
These SMA connectors are assigned default functions like 1 PPS signal output and
frequency output. Additionally there are two more SMA connectors that may be used
internally. The following table lists the default functions of the four SMA connectors. See
Figure 23 for exact position of the four connectors mentioned in this chapter.
Connector Description
X4 1PPS output
connector next beside RJ45
X7 frequency output
X6 event input
X5 1PPS input
top most connector
Table 15 Default functions of the SMA connectors
The user may change these default assignments via programming the register “IOMATRIX”
that is described in the chapter 3.9.4.1.
4.9.4 Timestamping User Defined Packets
See chapter 3.9.5 for more details on timestamping of user defined packets using the
syn1588® PCIe NIC.
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4.9.5 Synchronizing to GPS
See chapter 3.9.6 for more details on synchronising the IEEE1588 clock maintained in the
syn1588® PCIe NIC to an external GPS reference.
Since the syn1588® PCIe NIC offers just two SMA connectors on the rear side (PCI bracket)
one hast to select the connector X7 for the 1PPS input when invoking the “esync” application
as shown in the following example.
esync –p 3
4.9.6 Synchronizing the System Clock
See chapter 3.9.7 for more details how to synchronize the system clock to the IEEE1588
clock maintained in the syn1588® PCIe NIC.
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5 syn1588® VIP
The syn1588® VIP design is a highly integrated single chip IEEE1588 solution. Only a single
external Ethernet PHY is required to create a fully functional layer2 or layer3 IEEE1588-2008
node.
The syn1588®VIP offers a standard 10/100/1000 Mpbs Ethernet network interface with
hardware enhancements to provide the system with accurate clock synchronization via
Ethernet following the IEEE1588 standard.
The presented solution keeps all clock related processing encapsulated within the Intellectual
Property (IP) Core and provides a system with a highly accurate synchronized clock without
having to run any dedicated code of a host CPU connected to this system. The design is
suited for embedded systems or system-on-chip designs (SoC) not willing to contaminate the
application software with clock synchronization or protocol code or simply seeking a simple
and cost effective solution.
The syn1588®VIP comes in three flavours:
• syn1588®VIP device
• syn1588®VIP IP Core written in VHDL
• syn1588®VIP evaluation Board.
5.1 Features
• Single chip IEEE1588 solution
• 10/100/1000 Mbit/s Ethernet MAC included
• Fully compliant to IEEE802.3-2005
• IEEE1588 hardware timestamping support using syn1588® technology
• IEEE1588 hardware clock using syn1588® technology
• IEEE1588-2008 Layer-2 and Layer-3 compliant
• Clock accuracy better than 50 ns
• syn1588® PTP Stack included (running on integrated 8-bit CPU core)
• 3 programmable I/O signals (1pps output, event input, period output, etc.)
The syn1588®VIP evaluation board allows for fast and easy verification of the syn1588®VIP
features without risks of building an evaluation system. Our customers may receive the board
schematic, the layout data as well as the BOM (bill of material) of the syn1588®VIP
evaluation board free of charge.

An increasing number of industrial distributed systems utilize IEEE 802.3 Ethernet, since it is
a cheap, high bandwidth, and widespread network technology. Furthermore, the recent
IEEE 1588 Standard, Version 2008 for highly accurate clock synchronization defines the
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exchange of PTP messages via IEEE 802.3/Ethernet. This represents a Layer 2 communi-
cation in terms of the OSI reference model. The standard defines the Ethernet type, which
shall be set to 0x88F7, Multicast MAC addresses (01-80-C2-00-00-0E for peer delay
messages, 01-1B-19-00-00-00 for all other messages), and the settings of a few transport
specific field values. Thus the payload of the Ethernet frame does not differ much from the
PTP frames normally used. The length of IEEE1588 Layer 2 messages, however, is
significantly smaller because the entire IP header has become obsolete. A layer 2 PTP sync
message hence has an overall length of 64 bytes, already including two bytes for padding,
compared to the 90 bytes for the normal sync message.
However, the syn1588®VIP is also capable of handling IEEE1588 Layer 3. Choosing
between IEEE1588 Layer 2 Mode and IEEE1588 Layer 3 Mode is simple involving merely
changing the logic level of one input pin.
Based upon out syn1588®PTP Stack, a concept has been developed at Oregano Systems to
perform clock synchronization completely in the background, i.e. Integrated in a chip design
IP-core, the proposed solution provides an easy-to-use, low-gate count, small memory
footprint IEEE 1588 clock synchronization unit for product developments especially for
embedded systems or SoC designs.
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Figure 24: syn1588 VIP: Block diagram
Figure 24 shows the block diagram of Oregano Systems' syn1588®VIP. An Ethernet MAC
with additional interfaces delivers PTP messages to a small 8-bit controller, which runs the
small footprint protocol stack and controls the attached hardware clock.
The main building blocks of the novel solution comprise a dedicated Ethernet Media Access
Controller (MAC), a Clock Unit, and an 8-bit microcontroller core. The MAC is equipped with
a packet filter such that PTP messages can be extracted from and inserted into the
communication traffic.
To overcome various non-deterministic communication delays, hardware-assisted time-
stamping is used. To this end, the Oregano Systems syn1588® concept has been selected to
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be used in the clock unit. It includes an adder-based clock, various triggers and timers, and a
time-stamping logic supporting 10/100/1000 Mbit/s Ethernet. The synchronization algorithm,
all processing of PTP-messages, and low-level accesses to the clock IP-core, however, are
performed by the Offload Engine, basically a small 8-bit 8051 microcontroller.
With its unrivalled small memory footprint of less than 32 kbytes of ROM and less than 24
kbytes of RAM and an ASIC gate count of less than 20k gates, Oregano Systems'
syn1588®VIP Chip is at the leading edge of easy to use, small, and yet fully compatible clock
synchronization solutions.
In combination with a syn1588® PCI/PCIe NIC and a GPS receiver you can propagate GPS
time information through your whole network and effectively sync all your network devices to
GPS using this and other syn1588® Products, having only one real GPS timing receiver in
your network.
5.3 The syn1588®VIP node

In order to build a IEEE1588 node using the syn1588®VIP SoC a few additional components
are required, namely:
• SPI flash
• I2C serial number device
• Ethernet PHY
• Oscillator
• Reset device (optional)
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Figure 25 syn1588 VIP Node
The SPI Flash will store the encrypted bitstream of the FPGA. The syn1588®VIP requires an
8 Mbit SPI flash. The syn1588® VIP evaluation board for example contains the 8 Mbit SPI
flash SST25VF080B-50-4C-S2AF from SST.
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The I2C serial number device assures that each syn1588®VIP node has a unique MAC
address in the network and a unique clock ID for the Precision Time Protocol. The
syn1588® VIP is designed with the 24AA02E48 from Microchip in mind.
The Ethernet PHY connects the digital MII/GMII of the syn1588®VIP to the physical network
medium. The syn1588®VIP supports any commercially available 10/100 Mbit PHY For
1000 Mbit operation the syn1588®VIP supports two PHYs; The 88E1111 from Marvell and
the DP83865 from National Semiconductor. If you need support for an additional Gbit PHY,
please contact Oregano Systems.
The oscillator for the syn1588®VIP shall deliver 25 MHz with Ethernet quality (100 ppm). Our
syn1588®VIP uses the reset and power watch-dog device MAX6854 from Maxim, to enable
the FPGA only when the power supply is stable.

For technical specification details please refer to the product datasheet.
5.5 Serial Logging

The serial interface of the syn1588® VIP allows access to status information about the
syn1588® PTP Stack Version inside the syn1588® VIP. If the syn1588® VIP is in slave mode
and in sync, it shows the current time on the serial interface. The serial interface of the
syn1588® VIP is configured to (57600-8N1):
• baud rate57600
• 8 data bits
• no parity
• 1 stop bit.
Example output syn1588® VIP in PTP Layer 2 mode
Precision Time Protocol (PTP) Engine IEEE1588 V2, V 1.0.10 Rev 159 $
Oregano Systems - Design & Consulting GesmbH Jan 13 2010
ClockId 00:60:35:FF:FF:01:FF:39
Layer 2 operation
State Change Listening -> Uncalibrated
TsM 1263465463.502652983 TsS 6.816810978 Ofs -1.9
Setting time to Origin
TsM 1263465464.506808798 TsS 1263465464.487417628 Ofs -19391170.0
TsM 1263465465.506978961 TsS 1263465465.487563941 Ofs -19415020.0
TsM 1263465466.511136521 TsS 1263465466.510645461 Ofs -491060.0
TsM 1263465467.511354765 TsS 1263465467.512377947 Ofs 1023182.0
TsM 1263465468.515462770 TsS 1263465468.514996870 Ofs -465900.0
State Change Uncalibrated -> Slave
PathDelay -29750 ns
TsM 1263465469.515633384 TsS 1263465469.515511080 Ofs -92554.0
TsM 1263465470.519789918 TsS 1263465470.519793996 Ofs 33828.0
TsM 1263465471.519974272 TsS 1263465471.519941638 Ofs -2884.0
TsM 1263465472.524113449 TsS 1263465472.524077400 Ofs -6299.0
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Example output syn1588® VIP PTP Layer 3 mode

Oregano Systems - Design & Consulting GesmbH Jan 13 2010
ClockId 00:60:35:FF:FF:01:FF:39
Layer 3 operation
DHCP done: 192.168.102.59
TsM 1263465463.502652983 TsS 6.816810978 Ofs -1.9
Setting time to Origin
TsM 1263465464.506808798 TsS 1263465464.487417628 Ofs -19391170.0
TsM 1263465465.506978961 TsS 1263465465.487563941 Ofs -19415020.0
TsM 1263465466.511136521 TsS 1263465466.510645461 Ofs -491060.0
TsM 1263465467.511354765 TsS 1263465467.512377947 Ofs 1023182.0
TsM 1263465468.515462770 TsS 1263465468.514996870 Ofs -465900.0
State Change Uncalibrated -> Slave
PathDelay -29750 ns
TsM 1263465469.515633384 TsS 1263465469.515511080 Ofs -92554.0
TsM 1263465470.519789918 TsS 1263465470.519793996 Ofs 33828.0
TsM 1263465471.519974272 TsS 1263465471.519941638 Ofs -2884.0
5.6 Remote Configuration

The syn1588® VIP is configured using IEEE1588 Management Messages received via the
Ethernet interface. Thus the syn1588®VIP unit can be configured remotely. The syn1588®VIP
management interface is fully compliant to the IEEE1588 standard. One vendor specific
command had been implemented to read/write from/to the hardware registers of the
syn1588®VIP.
The Oregano Systems‘ syn1588® PTP Management Tool described in Chapter 7 is the tool
of choice for configuring syn1588®VIP nodes. This tool can send IEEE1588 standard
management messages as well as the Oregano specific IEEE1588 management messages.
5.6.1 Example 1: Indentifying syn1588®VIP Nodes
The basic usage of the PTPMMM tool in combination with the syn1588®VIP is to read the
value of a syn1588®Clock register. This is accomplished in the following way:
First invoke the PTPMMM utility:
# ./ptpmmm
Oregano Systems - Design & Consulting GesmbH Dec 23 2009
After invocation of PTPMMM you can enter commands that send IEEE1588 management
messages to the syn1588®VIP nodes in the network. Note that PTPMMM has no command
prompt or the like to facilitate batch operation and automated post processing of output data.
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To discover all syn1588®VIP nodes in the network issue the “clock” command. You do this by
typing “clock” followed by a carriage return. This should give a similar output like this:
# ./ptpmmm
clock
clock 0060350000018C37 1 O "IEEE 802.3" 006035018C37 IPv4:00000000 FFFFFF
"Oregano Systems;Model xx;Serial yy" "1.0.1;1.0.1;1.0.2" "name;location"
001B19000100

001B19000100
clock 0060350000018E58 1 O "IEEE 802.3" 006035018E58 IPv4:00000000 FFFFFF

001B19000100
timeout
The timeout message means that after a time of one second the command does not wait for
further responses to the issued clock command.
Now every PTP node in the network responds to the message. In this example only one
node responds. The responding node has a clock id of 0060350000018C37, a port id of 1
and belongs to clock domain 0. Remember the clock id, port id and clock domain, because
you need those values for ”set” commands. For “get” commands it is optional to specify
those values.
5.6.2 Example 2: Reading syn1588®VIP Registers
The syn1588®VIP supports a proprietary extension to the PTP Management Interface. This
extension is made up of only one - very powerful - command. It allows to read and write to
the hardware registers of the syn1588® VIP.
This command is called “clkman”. For example with this command we can read the version
of the syn1588® Clock Core that is embedded in the node. The version of the clock is located
in register 0x0. So to get the version of the clock we issue a “clkman” command to read clock
register 0x0. We do this like this:
# ./ptpmmm
clock
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001B19000100
timeout
clkman 0060350000018C37 1 0 0x000

clkman 0060350000018C37 1 0x4d323130
The result of the “clkman” command is always in hexadecimal notation. Since the clock
version is encoded as four ASCII characters the result of 0x4d323130 has to be converted in
ASCII to get the clock version: 0x4d equals ‘M’, 0x32 equals ‘2’, 0x31 equals ‘1’, and finally
0x30 equals ‘0’. So the clock version is ‘M210’.
5.7 Defining the output frequency

The syn1588®VIP is capable of generating a stable, accurate output frequency with a period
that the user defines. Setting the frequency of the output signal is accomplished using the
clkman command introduced in the previous section.
To get a user specified output frequency three Registers of the Clock need to be configured:
• PERIODTIME0_L which is Register 0x0F0
• PERIODTIME0_H at 0x0F4
• EVENTCTRL at 0x04C
PERIODTIME_H (31:16) are seconds and PERIODTIME_L (15:0) is the upper fraction of the
nanoseconds. PERIODTIME_L (31:0) is the lower fraction of the nanoseconds and
PERIODTIME_L (31:0) are sub nanoseconds. EVENTCTRL contains control bits for enabling
and disabling of some features of the syn1588® Clock Core
If for example we want to generate an output signal that toggles with a frequency of 1 MHz,
we need to set the period to 1000 nanoseconds. Now we convert this value to hex which
results in 0x3e8 nanoseconds. This means we have to set PERIODTIME_H to “0x0” and
PERIODTIME_L to “0x03e80000”. We have to set EVENTCTRL(16:15) to “00” and
EVENTCTRL(4) to “1”.
Therefore we issue the following commands within the ptpmmm tool:
# ./ptpmmm
clock
001B19000100
timeout
clkman 0060350000018C37 1 0 0x0F0 0x03e80000

clkman 0060350000018C37 1
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clkman 0060350000018C37 1 0 0x0F4 0x0000

clkman 0060350000018C37 1
clkman 0060350000018C37 1 0 0x04C 0x0010
clkman 0060350000018C37 1
For further details about the usage of the syn1588® Clock Core refer to Chapter 11 of this
User Guide.
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6 syn1588® NIC Driver

This chapter of the user guide describes the structure, installation, and interface of the
software driver for the Oregano Systems syn1588® PCI NIC and syn1588® PCIe NIC. Both
syn1588® NICs support high accuracy clock synchronisation. Since the driver is distributed
also as source code this sections goes into the necessary details of the driver to enable a
user to compile, change or adapt the driver as needed.
6.1 Features
The syn1588® drivers offer the following system features:
• Basic Ethernet and IP network driver for the operating system (OS)
• Register interface to syn1588® Clock registers for user applications
• Linux kernel version 2.6.16 to 2.6.30 required
• Linux x32 and x64 architectures supported
• Windows XP, Windows Server 2003 and 2008
• Windows x32 and x64 architectures supported
• Windows Vista support available upon request
6.2 Installing the syn1588® NIC Driver
6.2.1 Linux OS
There are two basic software modules running in the Kernel space:
• Clock Device Driver (syn1588nic)
• Synchronization Driver (SyncDriver)
There is one or more user application(s) running in the user mode. One example for this
application is Oregano Systems’ syn1588® PTP stack. The syn1588® NIC driver must be
loaded before the SyncDriver.
6.2.1.1 Clock Device Driver
The clock device drivers operations are divided in three sections

• Basic PCI/PCIe enumeration
• Ethernet access
• syn1588® clock synchronization access (syn1588®Clock IP core)
The clock device driver module performs the basic PCI/PCIe access and device registration
for the syn1588® PCI/PCIe NIC. This module is the only software part that directly accesses
data structures (registers and memories) located in the syn1588® hardware.
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The clock device driver module provides the Ethernet interface as well as the interfacing to
the network subsystem of the OS. Additionally it performs all the hardware access and data
abstractions required for the clock synchronization cell.
Furthermore, the clock device driver module implements the general device interrupt
handling and distribution as well as providing a virtual frequency register, thus allowing
applications to adapt to nodes hardware frequency without recompilation.
C-Code Setup
The clock device driver for Linux is made up of four files.

File name Description
syn1588nic.h Device driver header file (internal data structures)
syn1588nic_reg.h Hardware register address definition
syn1588support.h Macros for logging and time format type definitions
syn1588nic.c Implementation of the device driver
Table 16 Linux Clock device driver: C-files
Building
For building the device driver it is necessary to have the Linux kernel sources and the
necessary binary tools for building the kernel installed. Further, in the first line of the
delivered Makefile the variable KSRC has to be set to the kernel source directory. The driver
module can be built by calling the make target syn1588nic.ko or by building both drivers
using target “all”. Help on available target can be found by “make help”. For installing and
loading the driver root permissions are required!
6.2.1.2 Synchronization Driver
Functional Description
The synchronization driver module provides a character device file for user space
applications. These character device files can be read and written on all valid syn1588®Clock
IP core register addresses using symbolic names.
Register Register Bit Masks

TSFIFO_RX RXFEMPTY
TSFIFO_TX RXFFULL
TSFIFO_CTRL TXFEMPTY
IRSRC TXFFULL
IREN RXFCNT
TIMECTRL TXFCNT
TIMESTAT IRQB_RECV_MAC
SHDWTIME_L IRQB_TSFIFORX_FULL
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Register Register Bit Masks

SHDWTIME_M IRQB_SEND_MAC
SHDWTIME_H IRQB_TSFIFOTX_FULL
SHDWSTEP_L IRQB_EVENT0
SHDWSTEP_H IRQB_EVENT1
TIME0_L IRQB_TRIGGER0
TIME0_M IRQB_TRIGGER1
TIME0_H IRQB_PCLK
EVENTCTRL IRQB_PERIOD0
PERIODTIME0_L IRQB_PERIOD1
PERIODTIME0_H IRQB_TIME_OFLW
IRTIME_L EVCB_EVENT0
IRTIME_H EVCB_EVENT1
EVENTTIME0_L EVCB_TRIGGER0
EVENTTIME0_H EVCB_TRIGGER1
EVENTTIME1_L EVCB_PERIOD0
EVENTTIME1_H EVCB_PERIOD1
TRIGTIME0_L EVCB_PRD0_STIRQ
TRIGTIME0_H EVCB_PRD0_STRG0
TRIGTIME1_L EVCB_PRD0_STRG1
TRIGTIME1_H EVCB_PRD1_STIRQ
PERIODTIME1_L EVCB_PRD1_STRG0
PERIODTIME1_H EVCB_PRD1_STRG1
CSC_VERSION TICB_LSHDWREG
CLK_FREQ TICB_LSTEP
TICB_LTIME
Table 17: Symbolic register names (example for syn1588Clock_M IP core)
These symbolic names for all hardware registers and bit mask names are defined in an
include file specific for a syn1588®Clock IP core. Thus, changing the syn1588®Clock IP core
requires just changing the appropriate include file. Any user space application should include
“SyncDriver.h” in order to get all necessary defined names.
The basic task of the synchronization driver module is to enable multi-application support for
the user. The device virtualization for the important hardware registers (IRSRC, IREN)
supports the following file operations:
• llseek
• read
• write
• poll
• open (blocking/non-blocking)
• release
• fasync
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The commands are described in the following section.
Command llseek
Action: repositions the offset of the file descriptor to the argument (register position)
according to the directive (3rd argument). If the position is not a multiple of REG_SIZE the
position is truncated to the previous multiple.
Example: position file descriptor to interrupt enable register
lseek(fd, IREN, SEEK_SET);
Command read
Action: reads from the current file descriptor position a number of bytes into the given buffer
(gets register value). Reading from IRSRC can be blocking or non-blocking, depending on
the flags given to the open command.
Example: read from the register, the file pointer is currently pointing to
unsigned long data;
read(fd, &data, REG_SIZE);
Command write
Action: writes the given buffer to the current file descriptor position (sets register value)
Example: enable clock overflow and programmable clock interrupt, requires a lseek to IREN
in advance
unsigned long data = IRQB_TIME_OFLW | IRQB_PCLK;
write(fd, &data, REG_SIZE);
Command poll
Describe briefly the commands action.

Example
poll IREN
Command open
Action: opens the device character file with the given flags.
Example: (open character device read and writeable in non-blocking mode)
int fd; // file descriptor
fd = open(“/dev/” SYNC_DEV, O_RDWR | O_NONBLOCK);
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Command release
Action: closes the device character file.

Example
close(fd);
Example
The following C-code shows a simple example how to use the commands available in the
synchronisation driver.
#include "SyncDriver.h"
// open clock device

int fd;
if ((fd = open(“/dev/” SYNC_DEV, O_RDWR)) < 0) {
perror("cannot open clock");
}
// for signal handling: allow the process to receive SIGIO

if (fcntl(fd, F_SETOWN, getpid()) == -1) {
error("unable to allow the process to receive SIGIO");
}
// communicate with the socket asynchronously
if (fcntl(fd, F_SETFL, fcntl(fd, F_GETFL, 0) | O_ASYNC | O_NONBLOCK) < -1)
{
error("unable to declare socket asynchronous");
}
// read from TIME0_L

if (lseek(fd, TIME0_L, SEEK_SET) < 0) {
perror("lseek");
}
unsigned long data;

if (read(fd, &data, sizeof(data)) < 0) {
perror("read");
}
// write to SHDWTIME_M
if (lseek(fd, SHDWTIME0_M, SEEK_SET) < 0) {
perror("lseek");
}
if (write(fd, data, sizeof(data)) < 0) {
error("write");
}
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// close device
close(fd);
C-Code Setup
The synchronization driver for Linux is made up of two files.

file name description
SyncDriver.h Synchronization driver header file (internal data structures)
SyncDriver.c Synchronization driver implementation
Table 18: Synchronization driver: C-files
Building
For building the synchronization driver it is necessary to have the Linux kernel sources and
the necessary binary tools for building the kernel installed. Further, in the first line of the
Makefile the variable KSRC has to be set to the kernel source directory. The driver module
can be built by calling the make target SyncDriver.ko or by building both drivers using target
“all”. Help on available target can be found by “make help”.
A sample script how to load both modules and to generate the device file node is provided as
“syn1588nic.load” and can be started using the target “test”. For installing and loading the
driver root permissions are required!
Installation
The following steps are necessary in order to install the clock device driver under Linux.
1) Plug in syn1588® PCI NIC or syn1588® PCIe NIC to your computer
2) Extract driver sources driver.tgz into the working directory
3) In general two options for installing the driver exist:
A) Installation for use on any Distribution with kernel newer than 2.6.16.x: To compile
the driver just type "make" in the driver working directory. It is necessary to have
the kernel sources installed (usually under /usr/src/linux). Otherwise install them
using Linux distribution-specific package installation routines (e.g. yum install
kernel-devel under CentOS 5.2 distribution). Additionally the kernel has to be
configured for the actual configuration: Copy the kernel configuration file to the
kernel source root directory (cp /boot/config-... /usr/src/linux/.config) and type
"make oldconfig; make" to configure and build the kernel. The kernel build
process may be stopped after a few seconds (when starting actual compiling, CC
output). This is necessary for the module dependencies to be calculated.
B) Using pre-compiled binaries (only for use with CentOS 5.2): Copy the pre-
compiled binaries (SyncDriver.ko and syn1588nic.ko) to the modules directory
(/lib/modules/<kernel-version>/kernel/driver/net.
4) Install driver: Type "make install" with root privileges in the driver working directory.
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5) Activate driver when booting: Add the line "alias eth0 SyncDriver" to the file
/etc/modprobe.conf.local. Replace "eth0" with the actual interface used for the
syn1588(R) PCI/PCIe NIC (use "ifconfig" to figure out the interface name).
6) Automatic network interface configuration: Edit the interface file
(/etc/sysconfig/network/ifcfg-ethx) to set interface options like DHCP, fixed IP address
or the like.
7) Call the "ptp" executeable under root privileges. Starting the "ptp" may be done using
the conventional init.d routines.
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6.2.2 Windows OS
The driver for the syn1588PCI NIC can only be used with Microsoft Windows XP and later
and is optimized for usage with service pack 2. However, service pack 3 is also supported
and fully tested. The NIC appears as Standard Network device in Windows. Therefore, all
applications that are using network devices can be used in context with the syn1588 NIC.
The syn1588 NIC driver supports 100/1000 Mbit/s link speed.
1.1 Supplied files
Files to install the driver:
• syn1588.SYS
• syn1588.INF
• syn1588.CAT
Source files of the driver (./sys/):

• INIT.C
• IOCTL.C
• MII_FUNCTIONS.C
• PUBLIC.H
• RECEIVE.C
• REQUEST.C
• SEND.C
• syn1588_DRIVER.C
• syn1588_DRIVER.H
• syn1588NIC_REG.H
File needed to build the driver:
• SOURCES
• MAKEFILE
Sample application source:
• syn1588_APP.C
The following files are supplied and necessary for compiling, installing and using the driver.
They consist of already compiled and usable files for installation and their corresponding
source code and are grouped as follows.
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Files to install the driver:
• syn1588.SYS
Resides in the .\sys\objxxx_wxp_x86\i368 folder, where xxx is either ‘chk’ or ‘fre’
• syn1588.INF
Resides in the main folder
There is a single software modules running in the Kernel space:

• Network Device Driver
There is one or more user application(s) running in the user mode. One example for this
application is Oregano Systems’ syn1588® PTP stack.
6.2.2.1 Network Driver
To supply an interface, thru which user mode applications can access the syn1588 NIC, the
driver provides the ability to satisfy this need by I/O-Control-Requests (IOCTL). These
requests are initiated by Windows API functions. The functions could be implemented in a
library which contains a set of routines to carry out the communication tasks with the kernel-
mode driver. All interrupts from the PTP Hardware part are also transferred to the user mode.
In Figure 26 a sample application is displayed with an IOCTL library acting in combination
with a WinPCAP library.
Figure 26: User interface to the kernel driver
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syn1588 IOCTL Description
The interface between user-mode applications and the driver is established by a file handle
to the syn1588NIC driver. The windows API offers a set of functions to achieve and process
file handles to device drivers. The sample application supplied with the driver sources is
giving some hints, how to pass requests to the device driver. In general these requests are
passed to the driver by using IOCTL codes. A user mode program has to include the public.h
header file supplied with the driver sources to get the proper code set. Detailed description of
the driver supported IOCTL codes is listed below.
When the first syn1588 NIC is enumerated by the WindowsXP PnP Manager, the driver
creates a device object. There is only one global device object for each installed NIC. To
create a handle to the device object user code must use CreateFile() with “syn1588” as
filename parameter. With DeviceIoControl(), the user program is able to pass requests to the
device object. This function also specifies the number of returned bytes received from the
driver, for this reason the value of the returned bytes is also part of the description.
IOCTL_syn1588_DEVICE_COUNT
Parameter Buffersize Info
Input 0 No input required
Output ULONG Number of installed NICs
Returned bytes sizeof(ULONG) On success
On error
sizeof(IOCTL_STATUS)
Note: This is also 4 Byte long.
Description:
This IOCTL request returns the number of installed syn1588 NIC devices. Only a wrong specified
output buffer length leads to an error and ends in the return of an
IOCTL_STATUS_PARAMETER_ERROR error code.
IOCTL_syn1588_DEVICE_INFO
Input ULONG Number of the desired device
Output syn1588_IOCTL_DEVICE_INFO_DATA Number of installed NICs
Returned bytes Output Buffer size On success
sizeof(ULONG ) Error code
Description:
This request returns the MAC Address as well as the link status of the chosen device. If an error
occurs this request returns the appropriate error code.
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IOCTL_syn1588_DEVICE_SELECT
Input ULONG index of the chosen NIC
Output ULONG Variable to store the result
Returned bytes sizeof(ULONG) On error and success
Description:
With this request the user can choose one of the installed syn1588 NICs. The index starts with one
and ends up to the number returned from IOCTL_syn1588_DEVICE_COUNT. If a wrong index
passed to the driver the request returns IOCTL_STATUS_NO_ADAPTER_AVAILABLE.
Note that if no card has been selected none of the other IO request (except device info) will result
successfully.
IOCTL_syn1588_GET_INT_INFO
Input 0 No Input required
Variable to store the interrupt
Output ULONG
source
Returned bytes sizeof(ULONG) On error and success
Description:
This request returns the last interrupt source in the data field of the IO structure.
IOCTL_syn1588_REGISTER_EVENT
This structure contains a handle to
Input syn1588_IOCTL_INT_REG an event object and the interrupt
mask.
Output syn1588_IOCTL_INT_REG Result of the registration
Returned bytes sizeof(syn1588_IOCTL_INT_REG) On error and success
Description:
To Listen to interrupts generated by the syn1588 Clock IP-Core user mode applications might create
an event object and pass the handle to the object down to the driver. Also the interrupt mask has to
be passed to the driver. If an interrupt occurs, the event will be signaled by the driver.
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IOCTL_syn1588_READ_DATA
Input syn1588_IOCTL_DATA The offset member has to be filled.
Result and data are passed to the
Output syn1588_IOCTL_DATA
user mode application
Returned bytes sizeof(syn1588_IOCTL_DATA) On error and success
Description:
This request initiates a read to the specified offset. Size of the data returned by this request is always
ULONG. If offset is greater than 0x1FFC, an error will be returned within the structure.
IOCTL_syn1588_WRITE_DATA
The offset and the data members
Input syn1588_IOCTL_DATA
have to be filled.
The result is passed to the user
Output syn1588_IOCTL_DATA
mode application
Returned bytes sizeof(syn1588_IOCTL_DATA) On error and success
Description:
This request initiates a write to the specified offset. The write data request always writes one
DWORD to memory. If offset is greater than 0x1FFC, an error will be returned within the structure.
On successful operation all request return a zero value as result.

Following tables describe how the data structures used in the IOCTL request are built.
syn1588_IOCTL_DATA
IOCTL_STATUS status Result of the request
Unsigned long Offset Must be in range of 0x0 to 0x1FFC
On read request the data is stored here. On write
Unsigned long Data request this data will be placed at the specified
offset.
syn1588_IOCTL_INT_REG
IOCTL_STATUS status Result of the request
Unsigned long eventHandle Handle to an event Object
Unsigned long intMask Interrupt Mask
If greater zero an existing handle will be replaced
Unsigned long overwrite
by the one specified above.
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syn1588_IOCTL_DEVICE_INFO_DATA
Unsigned char [ ] MAC_ADDRESS Self-explanatory
0 equals to disconnected and 1 equals to
Unsigned char bLinkStatus
connected
User mode sample application

The sample application is a simple console program it is placed in the usr_mode directory.
Within the program the user can decide to read/write data, to display information about
installed card, to select an installed card or to register an interrupt listener event. The
interrupt listener displays information about the interrupt source every time an interrupt
occurs. Before the user can select these options, one of the installed cards must be selected.
This small program is only for testing purposes, its more or less a hint how to access the
card via IOCTL calls.
C-Code Setup
This section provides information to exemplify the dependencies of the driver source files
and the containing functions. The first figure shown below displays the file dependency within
the driver. The reason for splitting the source code into separate files is to increase the
transparency of the driver project. This structure is adopted from a Microsoft DDK sample
diver project.
Figure 27 depicts the dependencies between the source-code and their corresponding
header files (Included file including file).
Figure 27: Source file structure

Furthermore, global goals of each above displayed source file will be briefly described below.
Header file public.h

The purpose of this header file is providing a set of IOCTL codes. Theses codes are used in
the kernel mode driver as well as in a user mode application, which opens a handle to the
driver and passes these codes down to the driver IO dispatch function. Therefore, this
header file has to be included in user mode application source files too.
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Header file syn1588_driver.h

This header file contains all necessary structures and definitions needed for the separate
source-code files. All prototypes of the functions are within this header file. It also includes
the syn1588 hardware register definition header file.
Header file syn1588nic_reg.h

In this header file all register definitions of the syn1588 NIC hardware are listed. This file is
adopted from the Linux driver project. Except short modifications of base addresses at the
synchronisation register definitions to absolute address offsets, this file is left as it was.
Source file init.c

The functions in this routine cover all the initialization work like allocating memory for buffers
as well as mapping the physical-memory to system useable virtual-memory. All MAC
registers are set to the initial values. All functions in this source file are called by
MPInitialize() which resides in syn1588_driver.c.
Source file ioctl.c

This file includes all functions which process user mode IOCTL requests.
Source file mii_functions.c

The purpose of this source file is, supplying an interface to the PHY transceiver chip. The
functions communicate with the PHY chip via the MII of the MAC IP-Core.
Source file receice.c

As the name suggests, the containing functions of this file handle the reception of Ethernet
frames. Every time the MAC generate interrupts and the frame is acceptable it will be
indicated to NDIS for further processing.
Source file request.c

One of the characteristics of NDIS is, that it posts request to the miniport driver either to get
information like the number of transmitted frames or to set information like a multicast list.
These requests are handled with routines in this file.
Source file send.c

Send requests initiated by NDIS protocol drivers are handled through functions in this file.
Source file syn1588_driver.c

This source file is the entry point of the driver. It contains a set of functions that registers this
driver to the NDIS subsystem. It also includes the Interrupt-Service-Routine and the
corresponding interrupt handler routine. Functions in this file are calling several functions in
the other source files at certain time.
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Building
MS Visual Studio
Installation
The installation is made in a similar way like the installation of each other PnP capable
device, which is inserted into the computer. When the system determines the syn1588NIC
PCI card it asks for the driver. In the installation wizard you specify a path to the driver
provided inf file. Then the wizard passes the information provided within the inf file to the
Windows registry and copies the driver executable sys file to the driver path in the windows
system folder. By default the wizard is looking for the sys file in the same folder the inf file
resides. After these steps are carried out, the system is going to load the driver by calling its
entry routines. If everything is done right, the NIC should appear in the Network Connections
window.
The NIC’s default MAC-Address is no longer static, because it is taken from the cards
internal ROM. However, the user has the ability to replace the default MAC-Address by a
customized address. To enter a custom address, go to the properties menu of the NIC and
select the advanced tab as shown in Figure 28. Amongst other options the Custom MAC-
Address attribute will be found.
Figure 28: How to enter the NIC attribute context menu
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6.2.3 FreeBSD OS
We also have developed a FreeBSD driver for our syn1588® NICs. It is currently tested with
FreeBSD 7.2, but it is compatible with FreeBSD 6.x and FreeBSD 7.x.
C-Code Setup
The device driver for FreeBSD is made up of five files.

File name Description
syn1588nic.h Device driver header file (internal data structures)
syn1588nic_reg.h Hardware register address definition
driver.h Definition of the driver data structures
driver.c The FreeBSD driver itself
Makefile Standard FreeBSD driver Makefile
Table 19 Source files of the FreeBSD driver
Building
Building the FreeBSD driver has one prerequisite; you need to have your FreeBSD kernel
sources installed. If you do not want to install the FreeBSD kernel sources or do not want to
build the driver yourself, you can also try our precompiled FreeBSD driver that comes with
the driver sources; just skip to the Installation section.
After you have installed the kernel sources, building the driver for FreeBSD is a very
streamlined Process:
• Unpack the driver sources to a suitable directory:
> mkdir ~/src
> cd ~/src
> tar –xzvf ../freebsd_driver_*.tgz
• Invoke Make:
> cd freebsd
> make
That’s it! Now you can continue with the Installation.
Installation
• Change to the Driver directory if you have not already done this:
> cd freebsd
• Load the driver into the kernel (must be root user to do this):
# kldload ./if_syn.ko
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• Verify the correct loading of the driver:

> kldstat | grep if_syn
> ifconfig syn0
• If you are satisfied, you can permanently install the module like this:
> make install
• If you want to automatically load the module at boot up:

> echo “if_syn_load=”YES” >> /boot/loader.conf
Functional Description
Please refer to the Section about the Linux driver for a functional description of the FreeBSD
driver, because the userland interface of the FreeBSD driver is the same as for the Linux
driver. In fact our syn1588® PTP Stack for Linux runs unmodified on FreeBSD as well!
6.3 Diagnostics
The principle operation of the syn1588® PCI/PCIe NIC and the syn1588® PTP-Stack can be
verified by use of a packet dump on the corresponding Ethernet interface, e.g. Wireshark or
TCPdump.
6.3.1 Linux
If you run into problems with the Linux driver, try the following two steps to diagnose the
problem:
1.) Verify that the driver was loaded correctly and did not print any errors in the kernel
log.
To verify that the driver was loaded into the kernel use:
$ lsmod
And look for “syn1588nic” and “SyncDriver”.

2.) Verify that the driver was able to initialize the syn1588® PCI/PCIe NIC.
To do this use:
dmesg
And look for error messages regarding “syn1588nic”.
6.3.2 Windows
Correct installation of the driver can be checked on Windows by opening the network
connections menu and checking for the name “syn1588PCIe Ethernet Adapter”.
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Another good place to have a look at in case of problems is the Device Manager. If the
syn1588® PCI/PCIe NIC is marked as faulty in the Device Manager, then open the Error
Event Log and look for Messages regarding “syn1588”.
6.3.3 FreeBSD
If you run into problems with the FreeBSD driver try these steps:
1.) Verify that the syn1588® NIC driver was loaded into the kernel.
Use the commands kldstat and grep to do this:
kldstat | grep if_syn
This should show up a line containing “if_syn”, if the driver was loaded into the kernel.
2.) Verify that the driver correctly detected and initialized the syn1588® PCI/PCIe NIC.
For this task use dmesg to have a look at the kernel log:
dmesg
Look for messages regarding “if_syn”.

3.) Verify that the Ethernet driver of the syn1588® NIC is in the “UP” state.
Use the ifconfig command for this:
ifconfig syn0
Check if the Status Flags of the interface show “UP”.
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7 syn1588® PTP Stack

The syn1588® Precision Time Protocol (PTP) stack is a user space application written in C,
completely supporting the IEEE1588-2008 standard. Hardware enhancements allow for the
synchronization of network nodes in the sub 100 ns range, independently of the network
load. Though the stack is designed for specific syn1588® hardware support, the adaptation to
other hardware is easily possible through the implementation of a well-defined set of
interface functions.
7.2 Features
• Fully IEEE1588-2008 compliant
• IEEE1588 management messages supported
• IEEE1588 hardware timestamping support using syn1588® NICs
• Software timestamping for use with NICs that do not support IEEE1588 timestamping
• IEEE1588 transparent clock supported
• Adjustable synchronization (rate synchronization as well as state synchronization)
• One step and two step clock support
• Master and slave capability
• Layer-2 support (Linux only)
• Support for PDelay, DelayRequest, and pure syntonization mechanism
• Optional support for unicast operation
• C/C++ implementation
• Support for Linux or Windows operating systems
• Optional IEEE1588 security
• Possibility to synchronize time to GPS receiver
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7.3 System Environment

The syn1588® PTP stack uses IP/UDP messages on port 319 for events and on port 320 for
general communication. The synchronization packets sent by the master and management
packets are distributed to the IP multicast address 224.0.1.129 (default) or alternatively to
one out of the range 224.0.1.130-224.0.1.132.
All other event messages are sent as unicast to or from the node. In order to work correctly,
the system has to be able to send and receive these packets. This means that at least a
default route entry for the interface handling the clock synchronization has to exist.
Alternatively the routing entries for multi- and unicast can be set separately, Please make
sure that they point to the same interface to ensure correct timing information.
Caution
Please note that for starting the syn1588® PTP Stack root permissions are required.
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7.4 Calling Convention

The syn1588® PTP Stack is started by executing the application. The usage under Linux and
Windows is: ptp [options]. Following command line options are supported:
Option Brief Description
-h print this help screen
-i interface use the interface associated with the interface name (for Linux OS) or IP-
address (for Windows OS)
-v level change verbosity level (range 0..4) [default 0]
-F disable FollowUp messages
-D dlyMech delay mechanism used:
E .. end-to-end [default]
P .. peer-to-peer
N .. no delay mechanism at all
-p prio sets Priority1 (range 0..255) [default is 128]
-d Domain set Domain (range 0..255) [default is 0]
-s syncInt set synchronization interval (log2 range -8..+8) [default 0]
-S adjInt set clock adjust interval (log2 range 0..8) [default 0]
-a annInt set announce interval (log2 range 0..4) [default 1]
-r dlyReqIval set minimum delay request interval offset added to syncInt
(log2 range 0..5) [default 4]
-R pDlyReqIval set minimum path delay request interval (log2 range 0..5) [default 0]
-A accu set clock accuracy (range 0..255) [default 27]
-V var set clock variance (range 0..0xFFFF) [default 0xFFFF]
-C options set clock class [default 248]
M_EXT....Master on External Reference (6)
M_HOLD...Master on External Reference (in Holdover) (7)
M_NSYNC..Master on External Reference (not synchronized (52)
M_SLAVE..Master on External Reference (may be Slave) (187)
S...Slave Only (255)
-X enable Security (if available)
-l dlyAsym delay asymmetry correction in scaled nanoseconds [default 0]
-c ServoProps Clock Servo Properties: comma-separated list of integers
PI Controller K (rel. to 65536) [(1<<16)/4]
PI Controller T (rel. to 65536) [(1<<16)/16]
IIR Filter Stiffness M2S (rel. to 65536) (1<<16)/2]
IIR Filter Stiffness Path (rel. to 65536) [(1<<16)/2]
IIR Filter Adjustment Period (0..16) [4]
IIR Filter Adjustment Gain (0..24) 16]
-t change size of timestamp plausibility interval (0..31) [default 2]
-L use Layer2 network device (Linux only)
-N mode network mode:
U .. Unicast
M .. Multicast
B .. Both/Mixed [default]
-g pa[,pa..] unicast grantor MAC/IP address(es)
-b boundary set a boundary for OffsetToMaster in scaled nanoseconds [0]
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Option Brief Description

-I VlanID specify VLAN Id and activate VLAN mode [0]
-P another port configuration for boundary clock follows after this parameter
Table 20 Options for the syn1588® PTP Stack executable
7.5 Diagnostics
Designed as a process that rather runs in the background, the syn1588® PTP Stack does not
necessarily produce any output like a log file etc.. While testing or for maintenance purposes,
however, it is frequently convenient to have more outputs or simply to have an idea of how to
check the sanity of the clock synchronization of a node or within a network. Since the main
core of the syn1588® PTP Stack is the same for all products and operating systems, logging
is similar even in the case of the syn1588® VIP fully integrated solution.
7.5.1 Diagnostics without Logging
If running the syn1588® PTP Stack without any logging active the operation of the syn1588®
PTP Stack can be checked by checking the process list the operating system is currently
running. If the syn1588® PTP Stack is listed, this is a first positive indication that the stack is
alive. Under Linux a command for checking this could e.g. look like this:
“ps uax | grep ptp”
Another option is to use software to trace the Ethernet network traffic that is being received
or sent on a machine or system. This can be done with a simple tcpdump or with a more
sophisticated wireshark with graphical user interface. In both cases it will make sense to
limit the dump to PTP messages only by applying corresponding filtering rules. Note that only
a PTP master node will send out PTP sync messages periodically, a PTP slave will only
send out PTP delayrequest messages from time to time.
7.5.2 Diagnostics with Logging
Of course the syn1588® PTP Stack is prepared to produce a sufficient amount of logging for
testing, debugging, or evaluation. To this end the stack has to be started with the according
verbosity level starting with a level of 0 and increasing the amount of logging up to a level of
4, e.g. ptp –v 4. See the following log fragments for comparison or orientation.
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# ptp -C S -v 2
Precision Time Protocol (PTP) Engine IEEE1588 V2, Version 1.1.0 Rev 336 $
Oregano Systems - Design & Consulting GesmbH Apr 7 2011
TsM 7320.748230043 TsS 7320.779999382 Cor 0.0 Ofs 31769339.0 Build Date and
TsM: Timestamp at Master in [ns] Build Version of the
TsM 7321.755767114 TsS 7321.792174078 Cor 0.0 Ofs 36406964.0 syn1558® PTP Stack
TsM 7322.779030907 TsS 7322.777965288 Cor 0.0 Ofs -1065619.0
TsS: Timestamp at Slave in [ns]
TsM 7323.786553058 TsS 7323.787580251 Cor 0.0 Ofs 1027193.0
TsM 7324.809832010 TsS 7324.809786262 Cor 0.0 Ofs -45748.0
TsM 7325.817369352 TsS 7325.817398968 Cor 0.0 Ofs 29616.0
PathDelay 17876 ns
TsM 7326.840640481 TsS 7326.840639175 Cor 0.0 Ofs -19183.5
Cor: Correction field value in [ns]
TsM 7327.848162972 TsS 7327.848199847 Cor 0.0 Ofs 18998.5
TsM 7328.871426119 TsS 7328.871442707 Cor 0.0 Ofs -1289.5
Ofs: Offset from Master in [ns]
TsM 7330.902238049 TsS 7330.902258626 Cor 0.0 Ofs 2700.5
# ptp -C S -v 4
Precision Time Protocol (PTP) Engine IEEE1588 V2, Version 1.1.0 Rev 336 $
Oregano Systems - Design & Consulting GesmbH Apr 7 2011
Syn1588 compatible hardware found
Hardware Clock Version M-Core V 2.0.0 f=87600000 Hz
ClockId 00:60:35:00:00:01:8E:64
rate & step size for clock
Starting PTP Engine adjusting in [ns/s]
Initializing
ClockHAL initialize
Adjusting Rate by 0 ns/s
Step is (00000B6A, 41E58600)
Settings: ClockId 00:60:35:00:00:01:8E:64
Settings: Prio1 128 ClkClass 255 clkAccuracy 39 clkVariance 65535
Settings: Prio2 128 Domain 0
The arrows indicate
Initializing Unicast incoming PTP messages
Event message of size 44 and their type
---> Sync
Sync Msg received
General message of size 44
---> FollowUp
FollowUp Msg received
---> Announce
Announce Msg received
BMC new Foreign Master announced
Event message of size 44
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---> Sync
Sync Msg received
---> FollowUp
---> Announce
Announce Msg received
BMC Foreign Master detected
BMC number of valid Announces: 1
---> Sync
Sync Msg received
---> FollowUp
Timeout: state Listening
Announce Timeout
State Change Event
BMC resetting Foreign Master dataset
---> Sync
Sync Msg received
---> FollowUp
TsM 7421.280727903 TsS 7421.309164679 Cor 0.0 Ofs 28436776.0
Synchronizing M2S-Delay 28436776 ns
Offset (M2S - PathDelay) is 28436776 ns
Adjusting Rate by 0 ns/s
Step is (00000B6A, 41E58600)
---> Announce
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7.5.3 Diagnostics with syn1588® PTP Management Messages
Yet another possibility, and maybe the most convenient one, is to query the status of any
node in a network via the syn1588® management tool, described in more detail in Chapter 7.
If started interactively the log output is visible on the console directly. If started via a boot
script or on the syn1588® Live CDROM the log output can be redirected to a log file, e.g.
/root/ptp.log.
To stop the syn1588® PTP Stack on the syn1588® Live CDROM type: killall -9 ptp .
On other OS this may be different. If started from command line, use CTRL-C to stop the
stack. If properly hooked up to the Linux OS boot setup it can also be started and stopped
via the corresponding scripts, most likely located in the /etc/init.d subdirectory. To start
the syn1588® PTP Stack just change to the directory where the ptp executable is located and
type e.g. ./ptp –v1 –C M. See Section 7.4 for further details.
To find out whether a node or computer is acting as PTP master or as PTP slave, again this
can be checked indirectly using wireshark or tcpdump. If generated, the log files give
indication of the state of the PTP stack starting with verbosity level 2.
To check whether a node or computer is actually synchronizing its local clock accordingly or
to assess the quality or precision of the overall synchronization of a network again there are
several options. First interpreting the log files starting with verbosity level 2 allows getting an
indication of the local clock’s own understanding of its offset from the PTP master. Second a
comparison of the 1 PPS outputs of a number of nodes also gives an indication of the
precision and stability of the synchronization, if possible.
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7.6 Software Interface

The syn1588® PTP Stack has a well defined interface to the outside world. This interface
consists of four distinct parts:
• Operating System Interface
• Logging Interface
• Software / Hardware Clock Interface
• Network Interface
The Operating System Interface is very simple, because it only is used to query the current
system time from the OS. The definition of this interface can be found in ‘os.h’
The Logging Interface is also a simple interface, because you only have to provide four
Functions that get a printf compatible format string and additional variables. What happens
with the format string and the variables is implementation depended. Typically those strings
will be presented to the user or written to a log file. The definition of this interface can be
found in ‘log.h’
The Software / Hardware Clock Interface is a more sophisticated interface. This interface
is used to connect the syn1588® PTP Stack to a precision hardware clock or software based
clock as an automatic fallback. This interface is used to draw timestamps for network packets
and is also used to control the speed of the hardware or software clock so that its offset to
the master is as small as possible. The definition of this interface can be found in
‘clock_hal.h’
The Network Interface is also a very platform dependent one. If the target platform of the
syn1588® PTP Stack supports BSD style sockets not much has to be done for this interface.
For an implementation example on a target platform without BSD style sockets, have a look
on the MC8051 implementation of the syn1588® PTP Stack. The definition of this interface
can be found in ‘network_ifc.h’
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7.7 Directory Structure

The syn1588® PTP Stack repository has the following top level
directories:
• bin Compiled binaries
• doc Documentation of the syn1588® PTP Stack
• proj Project Files for the different compilers
• src The source code of the syn1588® PTP Stack itself
After a successful build of the syn1588® PTP Stack, the bin folder
contains all built binaries.
The doc folder contains Doxygen templates to automatically build a
manual for the internals of the syn1588® PTP Stack.
In the proj folder is a subfolder with a compiler project for each
already supported working target platform of the syn1588® PTP Stack.
As the name implies, the src folder contains the source code of the
syn1588® PTP Stack.
All paths in the repository are relative to the trunk directory.
7.8 Building the syn1588® PTP Stack:

Inside the directory structure of the syn1588® PTP Stack you find the
directory proj with the subfolders gcc, iar, and msvc. Those are
ready made build environments for specific platforms.
7.8.1 Building for Windows
To build the syn1588® PTP Stack for Windows open the ptp.sln file
with Visual Studio. This file is located in the msvc directory. We
recommend Visual Studio 2008 Express Edition to build the syn1588®
PTP Stack for Windows.
7.8.2 Building for Linux
To build the syn1588® PTP Stack on a Linux machine change your current folder to the gcc
directory and execute the build-all.sh script.
7.8.3 Building for the MC8051
To build the syn1588® PTP for our MC8051 based embedded platforms use the IAR compiler
and open the PTP.eww IAR-Workbench file in the iar subdirectory.
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7.9 Installation
To install the syn1588® PTP Stack and its utility applications copy them to wherever you think
is a suitable place for them. We recommend C:\syn1588 for Windows and /syn1588 for
Linux, but this is not enforced by the applications.
The syn1588® PTP Stack and its utility applications are built with static libraries per default.
This means that there are no constraints on the location on the file system for the syn1588®
PTP Stack and its utilities. In fact this also means that the syn1588® PTP Stack is highly
portable between different Linux distributions in its binary form.
7.10 Management Interface

The syn1588® PTP Stack also supports the PTP management interface. To access the
management interface of PTP nodes, Oregano System provides the syn1588® Management
Tool. Refer to chapter 7 for details about the syn1588® Management Tool
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8 syn1588® PTP Stack for Protocol Version 1

We also provide a syn1588® PTP Stack for the IEEE1588-2002 standard which is also called
PTP version 1. Since the current standard is IEEE1588-2008 and is not compatible to
IEEE1588-2002 it is not recommended to use IEEE1588-2002 in new projects. But we still
support IEEE1588-2002 with this application. The binary for the syn1588® PTP Stack for
protocol version 1 is called “ptp1” or “ptp1.exe” respectively.
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9 syn1588® PTP Management Tool

The syn1588® PTP Management Tool is an application that uses the PTP Library in the
same way as the PTP stack application does. Also, the network and logging interfaces are
re-used from the stack application. The syn1588® PTP Management Tool is able to parse
commands from stdin, assemble management messages addressed to specific nodes,
examine their response and display the results on stdout.
This tool not only works with syn1588® Nodes, but with all IEEE1588-2008 compatible PTP
implementations.
9.1 Command Syntax of the syn1588® PTP Management Tool

The binary of the syn1588® PTP Management Tool is called “ptpmmm” or “ptpmmm.exe”
respectively. The command syntax is as follows:
Command [ClockId [PortNumber [Domain [Value [...] ] ] ] ]
Command is a string of characters denoting the actual command. See Table 21 for available
commands.
ClockId is the hexadecimal representation of the clock identifier. If ClockId is not specified, a
default of FFFFFFFFFFFFFFFF is used that addresses all Clocks of a given domain.
PortNumber is the port number of the addressed PTP port. If PortNumber is not specified, a
default value of 0xFFFF is used that addresses all ports of a given clock.
Domain is the domain number of the addressed PTP instance. If Domain is not specified, a
default value of 0 is used, the PTP default domain.
Optional values specify Set-operations instead of the default Get-operations and are
dependent on the specific command.
NOTE: Set Operations are only recognized if ClockID, PortNumber, Domain, and Value are
given.
All Identifiers (ClockId, …) must be represented in hexadecimal form, while all other integer
values may be given decimal or hexadecimal form with a leading “0x”.
All Responses are printed to stdout in the form:
Command ClockId PortNumber [Value [Value [...] ] ]
If the default timeout of 1 second is reached, and no response has been received, “timeout”
is printed to stdout. However, in case of multiple addressed instances (ClockId is equal
FFFFFFFFFFFFFFFF or PortId is 0xFFFF) this string is printed in any case.
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9.2 Command Reference of the syn1588® PTP Management Tool

Table 21 lists all commands available in the syn1588® PTP Management Tool. The table
also shows the Type of command.
• Get means, with this command you can query a value
• Set means, with this command you can set a value
• Command means, this command does not get or set a value, but invokes some
action on the PTP node.
Command Mgmt Id Short Description Action
accuracy 0x2010 Clock Accuracy Set/Get
aival 0x2009 Announce Interval Set/Get
Announce Receipt
atout 0x200A Timeout Set/Get
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clkman 0xC10C Manage syn1588 clock Set/Get
clock 0x0001 Clock Description Get
current 0x2001 Current Dataset Get
default 0x2000 Default Dataset Get
dlymech 0x6000 Delay Mechanism Set/Get
domain 0x2007 Domain Set/Get
init 0x0005 Initalize Command
log 0x0006 Fault Log Get
logres 0x0007 Fault Log Reset Command
null 0x0000 Null Set/Get
parent 0x2002 Parent Dataset Get
pival 0x6001 Pdelay Interval Set/Get
port 0x2004 Port Dataset Get
portdis 0x200E Disable Port Command
porten 0x200D Enable Port Command
prio1 0x2005 Priority1 Set/Get
prio2 0x2006 Priority2 Set/Get
reset 0x0004 Reset Nonvolatile Storage Command
save 0x0003 Save Nonvolatile Storage Command
sival 0x200B Sync Interval Set/Get
slave 0x2008 SlaveOnly Set/Get
time 0x200F Time Set/Get
timescale 0x2013 Timescale Properties Set/Get
tprop 0x2003 Timeproperties Get
traceab 0x2012 Tracability Properties Set/Get
user 0x0002 User Description Set/Get
utc 0x2011 UTC Properties Set/Get
version 0x200C Version Set/Get
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Table 21 Available Commands in the syn1588 PTP Management Tool
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9.2.1 accuracy Set/Get Clock Accuracy
With this command you can set/get the clock accuracy.

Since the clockAccuracy attribute is considered in the operation of the Best Master Clock
algorithm, the setting of the clockAccuracy attribute in any clock by means of this command
can result in a change of grandmaster the next time the Best Master Clock algorithm is
performed.
Invocation Example:
accuracy
accuracy 0060350000018C37 1 39
timeout
Parameter Values:
Default Value: N/A
Allowed Values: 0x20 – 0x31
9.2.2 aival Set/Get announce interval
The announce interval is the interval at which a PTP Master or alternative PTP Master
announces its presence to other PTP nodes in the network.
Invocation Example:
aival
aival 0060350000018C37 1 1
timeout
Parameter Values:
Default Value: 1
Allowed Values: 0 – 4
9.2.3 atout Set/Get Announce Receipt Timeout
The Announce Receipt Timeout specifies the number of Announce Intervals that has to pass
without receipt of an Announce message before the occurrence of the event
ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES
Invocation Example:
atout
atout 0060350000018C37 1 3
timeout
Parameter Values:
Default Value: 3
Allowed Values: 2 – 255 (subject to further restrictions depending on PTP
Profile)
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9.2.4 clkman Set/Get syn1588® Clock Registers
This is a syn1588® specific command. Therefore this command is only usable in combination
with syn1588® Nodes. With this command you can set/get hardware clock registers of
syn1588® nodes.
Refer to chapter 3.7 for further details about the syn1588® registers.
The basic rule for this command is:
clkman <clockid> <portnr> <domain> <addr> <data>
Invocation Example:
clkman 0060350000018C37 1 O 0x0
clkman 0060350000018C37 1 0x00000000
timeout
9.2.5 clock Get clock description
With this command you get the clock description of the specified clocks or of all of them.
Invocation Example:
clock
001B19000100
timeout
9.2.6 current Get the current dataset
With this command you can query the current dataset from a PTP node.
The current dataset shows you the distance of the clock to the grandmaster clock, its offset
from the master and the mean path delay.
Invocation Example:
current
current 0060350000018C37 1 0 0.0 0.0
timeout
9.2.7 default Get the default dataset
This command queries the default dataset of a clock.

Invocation Example:
default
default 0060350000018C37 1 1 128 6 39 65535 128 0060350000018C37 0
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timeout
9.2.8 dlymech Set/Get the delay mechanism used
With this command you can set/query the delay mechanism used by a clock to calculate the
mean path delay
Invocation Example:
dlymech
dlymech 0060350000018C37 1 E2E
timeout
Parameter Values:
Default Value: Implementation/Profile specific
Allowed Values: 0x01 (E2E) Delay Request/Response mechanism used
0x02 (P2P) Peer Delay mechanism used
0xFE No delay mechanism used
9.2.9 domain Set/Get the PTP domain
With this command you can Set/Get the current domain a clock is participating in. Each PTP
node only reacts to messages from other PTP nodes which belong to the same domain.
Invocation Example:
domain
domain 0060350000018C37 1 0
timeout
Parameter Values:
Default Value: 0
Allowed Values: 0x0 – 0xFF
9.2.10 init Command to initialize a clock
With this command you can initialize a PTP Node. This command has a parameter, the
InitializationKey. Depending on the InitializationKey the initialization can yield different
results.
Invocation Example:
init 0060350000018C37 1 0 0x0000
init 0060350000018C37 1
Parameter Values:
InitializationKey Values: 0x0000 Perform default
initialization
0x0001 - 0x7FFF Reserved. No Action
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0x8000 – 0xFFFF Implementation Specific
9.2.11 log Get the Fault log
This command retrieves a list of fault log entries from a clock. This command does not delete
the retrieved records from the fault log.
Invocation Example:
log
log 0060350000018C37 1 NOT_SUPPORTED
timeout
9.2.12 logres Command to reset the Fault log
This command deletes all records in the fault log of a clock.

Invocation Example:
logres
logres 0060350000018C37 1 NOT_SUPPORTED
timeout
9.2.13 null Command to send a Null Management Message
This command sends a null Management Message to a clock.

Invocation Example:
null
null 0060350000018C37 1
timeout
9.2.14 parent Command to get the Parent Dataset
With this command you can query the Parent Dataset from a clock
Invocation Example:
parent
parent 0060350000018C37 1 0060350000018C37 0 0 65535 2147483647 128 6 39
65535 128 0060350000018C37
timeout
9.2.15 pival Set/Get the Peer Delay Interval
With this command you can set/get the Peer Delay Interval. The Peer Delay Interval is the
time between two consecutive measurements of the Peer Delay using the configured Peer
Delay measurement mechanism.
Invocation Example:
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pival
pival 0060350000018C37 1 0
timeout
Parameter Values:
Default Value: 0
Allowed Values: 0 – 5
9.2.16 port Get the Port Dataset
With this command you can query the Port Dataset of a clock port.
Invocation Example:
port
port 0060350000018C37 1 0060350000018C37 1 Master 4 0 1 3 0 E2E 0 2
9.2.17 portdis Port Disable Command
With this command you can disable a port of a clock. This command causes the
DESIGNATED_DISABLED event to occur.
Invocation Example:
portdis 0060350000018C37 1 0
portdis 0060350000018C37 1
9.2.18 porten Port Enable Command
With this command you can enable a port of a clock. This command causes the
DESIGNATED_ENABLED event to occur.
Invocation Example:
porten 0060350000018C37 1 0
porten 0060350000018C37 1
9.2.19 prio1 Set/Get Priority1 of the Default Dataset
With this command you can Set/Get the Value of priority1 of the Default Dataset.
Since the priority1 attribute is considered in the operation of the Best Master Clock algorithm,
the setting of the priority1 attribute in any clock by means of this command can result in a
change of grandmaster the next time the Best Master Clock algorithm is performed.
Invocation Example:
prio1
prio1 0060350000018C37 1 4294967168
timeout
Parameter Values:
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Default Value: 128

Allowed Values: 0 – 255 (subject to further restrictions depending on
PTP Profile)
9.2.20 prio2 Set/Get Priority 2 of the Default Dataset
With this command you can Set/Get the Value of priority2 of the Default Dataset.
Since the priority2 attribute is considered in the operation of the Best Master Clock algorithm,
the setting of the priority2 attribute in any clock by means of this command can result in a
change of grandmaster the next time the Best Master Clock algorithm is performed.
Invocation Example:
prio2
prio2 0060350000018C37 1 4294967168
timeout
Parameter Values:
Default Value: 128
Allowed Values: 0 – 255 (subject to further restrictions depending on
PTP Profile)
9.2.21 reset Resets the Values in non-volatile read-write memory
The receipt of this command causes the values in non-volatile read-write memory to be reset
to their default values.
Invocation Example:
reset
reset 0060350000018C37 1 NOT_SUPPORTED
timeout
9.2.22 save Save current values in non-volatile read-write memory
The receipt of this command causes the current values of the applicable dynamic and
configurable data set members to be copied into non-volatile read−write memory.
Invocation Example:
save
save 0060350000018C37 1 NOT_SUPPORTED
timeout
9.2.23 sival Set/Get Sync Interval
With this command one can Set/Get the current Sync Interval.
Invocation Example:
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sival
sival 0060350000018C37 1 0
timeout
Parameter Values:
Default Value: 0
Allowed Values: -1 – +1
9.2.24 slave Set/Get Slave Only Bit
With this command one can Set/Get the value of the Slave Only Mode bit. If this bit is TRUE
the PTP Node cannot become a Master or Grandmaster Clock.
Invocation Example:
slave
slave 0060350000018C37 1 0
timeout
Parameter Values:
Default Value: 0
Allowed Values: 0 - 1
9.2.25 time Get/Set Time
With this command one can Set/Get the current time of a PTP Node. Setting of the time only
makes sense on a grandmaster clock.
Invocation Example:
time
time 0060350000018C37 1 04b30830f 19570680
ttimeout
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9.2.26 timescale Set/Get Timescale
With this command one can Set/Get the current Timescale of the PTP node.
Invocation Example:
timescale
timescale 0060350000018C37 1 P 160
timeout
9.2.27 tprop Get Time Properties
With this command one can get the Time Properties Dataset of a PTP node.
Invocation Example:
tprop
tprop 0060350000018C37 1 33 P 160
timeout
9.2.28 traceab Set/Get the Traceabilty Properties
With this command one can get the Traceability Properties of a PTP node.
Invocation Example:
traceab
traceab 0060350000018C37 1 0
timeout
9.2.29 user Set/Get the User Description
With this command one can set/get the User Description of a PTP node. This is a text field
with a maximum size of 128 Octets.
Invocation Example:
user
user 0060350000018C37 1 "name;location"
timeout
user 0060350000018C37 1 0 "Grandmaster;Room1"
user 0060350000018C37 1
9.2.30 utc Set/Get the UTC Properties
With this command one can Set/Get the UTC Properties of the PTP node.
Invocation Example:
utc
utc 0060350000018C37 1 33 0
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timeout
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9.2.31 Version Set/Get the PTP Version used on a clock port
With this command one can Set/Get the PTP Version used by a clock port.
Invocation Example:
version
version 0060350000018C37 1 2
timeout
Parameter Values:
Default Value: 2
Allowed Values: 1 Process only PTP version 1 messages on this port
2 Process only PTP version 2 messages on this port
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10 syn1588® Live CDROM

The syn1588® Live CDROM is a minimal Linux System with the drivers for the syn1588 Nic
and the syn1588® PTP Stack installed.
The Live CDROM is very useful as a quick evaluation tool for our syn1588 hardware and
software.
The Live CDROM has also a second function as a “Driver CDROM”. It includes the most
recent version of the syn1588 PCI/PCIe NIC drivers and the latest PTP-Stack and utility
applications like syn1588app and eSync. The Linux and Windows drivers and applications
are included on the CDROM.
Folder Content Description

/doc/ This folder contains the most recent Version of this
document, the syn1588® User Guide.
/isolinux/ This folder contains the minimal Linux System which can
be booted from this disc as a Live System.
/sw/apps/linux/ This folder contains the syn1588® applications for Linux.
This includes ptp the syn1588® PTP Stack, syn1588 the
syn1588® NIC diagnostic/configuration utility, esync the
GPS time sync application.
/sw/apps/win32/ This folder contains the syn1588® applications for
Windows. This includes ptp.exe the syn1588® PTP Stack,
syn1588.exe the syn1588® NIC diagnostic/configuration
utility, esync.exe the GPS time sync application. These
application can also be used on 64bit Windows Systems.
/sw/drv/linux/ This folder contains the source-code for the most recent
version of the Linux driver for the syn1588® PCI/PCIe
NICS.
/sw/drv/win32/ This folder contains the driver for 32 bit versions of
Windows in binary form for the syn1588® PCI/PCIe NICs.
/sw/drv/win64/ This folder contains the driver for 64 bit versions of
Windows in binary form for the syn1588® PCI/PCIe NICs.
Table 22 Contents of the syn1588® Live CDROM
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Our syn1588® software for Windows and Linux is located in the folders mentioned in Table
22 on the Live CD. Here is a list of the syn1588® software and a short description of every
software:
Binary Usage
esync / esync.exe This tool is used for external synchronization to GPS
devices.
lsync / lsync.exe This tool is used for local synchronization of different clocks
on the local system. For example syncing the system clock
to the hardware clock on an Oregano NIC
ptp / ptp.exe This is the PTP-Stack for version 2 of the PTP protocol
ptp1 / ptp1.exe This is the PTP-Stack for version 1 of the PTP protocol
ptp_demo / ptp_demo.exe This is a demo version of the PTP-Stack for version 2 of the
PTP protocol. It runs without syn1588® hardware but stops
syncing after some time.
ptpmmm / ptpmmm.exe This tool is used to query PTP-nodes using the PTP
management interface.
syn1588 / syn1588.exe This tool is used to query the registers of a local syn1588®
hardware clock on an Oregano NIC
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Table 23 Available syn1588 software on the LiveCD
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11 syn1588® and External Time Sources

The syn1588® hardware is not just a sophisticated IEEE1588 compatible clock, but it is also
capable of communicating with the outside world. This is done using the syn1588® Clock
Core that is at the heart of every syn1588® product.
The syn1588® Clock Core has several different inputs and outputs to communicate with the
outside world. This chapter explains the usage of this inputs and outputs.
11.1 Basics
Before one can use the inputs and outputs of the syn1588® Clock Core in an efficient and
easy manner, one has to understand the functionality of three Registers:
• IREN / IRSRC
• EVENTCTRL
• IOMATRIX
The usage of the IREN and IRSRC is straightforward. If you want to get an Interrupt when a
specific hardware event occurs, you set the associated bit in the IREN register.
If the hardware event occurs, the associated bit in the IRSRC register is set and the
hardware interrupt line is activated. To clear the interrupt write a zero to the associated bit in
the IRSRC register.
Refer to 3.7.1.8 and 3.7.1.9 for further details about IREN and IRSRC.
The next important register is EVENTCTRL. With the EVENTCTRL register one can enable
and disable the generation of events. The EVENTCTRL register is very similar to use as the
IREN and IRSRC registers. Every event that can be generated has an associated Bit in the
EVENTCTRL register. Just set the associated Bit to 1 to enable the Feature or 0 to disable it.
Refer to 3.7.1.11 for further details about EVENTCTL.
IOMATRIX
The last but not least of the common registers is the IOMATRIX register. You can think of the
IOMATRIX register as a switch board. With the IOMATRIX register you can connect every
event input port to every event output port, and also invert the signals along the way.
You can sink of every port that generates events as a source and of every port that gets
events routed to as sinks.
Within the IOMATRIX Register every sink has a fixed position in the Register. And every
Source has a fixed value. So if you want to connect a source to a sink you write the value of
the source to the position of the sink.
Refer to 3.7.1.36 for further details about IOMATRIX.
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11.2 Reacting to External Events
11.2.1 EVENTINPUT0 and EVENTINPUT1
There are two sinks to react on external events. They are EVENTINPUT0 and
EVENTINPUT1. Even though the name of them is similar, they are a little different.
EVENTINPUT0 uses a fifo to store occurred events and EVENTINPUT1 does not.
Because of this, EVENTINPUT0 is better suited for situations where a lot of events can occur
in a short amount of time, and EVENTINPUT1 is for events that occur rather seldom.
If there is an event on EVENTINPUT0 the current time of the syn1588® clock is stored and
added to the fifo, which can be read out from the registers EVENTTIME0_L and
EVENTTIME0_H. The read order of these two registers is important! Always read
EVENTTIME0_L first and EVENTTIME0_H last. The fifo stores up to 16 entries.
If you read the contents of the fifo remember to read the fifo until it is empty, which is
indicated by a value of 0 for EVENTTIME0_L and EVENTTIME0_H. This is important,
because EVENTINPUT0 only generates an interrupt if the fifo is empty.
Events on EVENTINPUT1 get recorded in the registers EVENTTIME1_L and
EVENTTIME1_H. Do not wait too long to read the value of EVENTTIME1_L and
EVENTTIME1_H, because it gets overwritten whenever an event on EVENTINPUT1 occurs.
Because of that EVENTINPUT1 generates an Interrupt every time an event occurs.
11.2.2 Timestamping of Ethernet Packets
Another possibility of external events which does not fit in the source/sink analogy is
timestamping of Ethernet packets. Timestamping of Ethernet packets basically works like
this:
You define a pattern that matches the packets you want to timestamp and put it into the
pattern memory of the timestamping unit.
You define some data to extract from the packet, so you can later associate the drawn
timestamp to the timestamped packet. This information goes into the ControlRegister of the
timestamping unit.
When the timestamper detects a packet that matches the pattern and has a correct FCS the
timestamp is copied into a timestamp fifo. This is indicated by the status register of the
timestamp fifo.
Now all you have to do is read out the timestamp from the timestamp fifio.
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11.3 Generating External Events

The syn1588® Clock Core does not just react to external events, but it is also capable of
event generation. There are several types of external events that can be generated using the
syn1588® Clock Core, namely:
• One Pulse per Second (1PPS)
• Periodical Events
• One Shot Events at a well defined time in the future
• Combinations of Periodical and One Shot Events
11.3.1 One Pulse per Second (1PPS)
The One Pulse per Second is the most basic Event to generate and use, because this is
automatically enabled when starting the syn1588® PTP Stack.
11.3.2 Periodical Events PERIODTIME0 and PERIODTIME1
Periodical Events are similar events to the one pulse per second, but as the name implies
the period of the signal can be freely chosen by the user.
Two Resources are available to generate Periodical Events, namely PERIODTIME0 and
PERIODTIME1. These two work exactly the same, so only PERIODTIME0 will be explained.
You define the Period of your Signal with the two registers PERIODTIME0_L and
PERIODTIME0_H and enable the periodical event using the associated bit in the
EVENTCTRL register.
For a diagram of how to enter seconds, nanoseconds and sub nanoseconds into the
PERIODTIME registers, refer to Table 17 for details about the alignment of time into the
registers.
11.3.3 One Shot Events TRIGTIME0 and TRIGTIME1
With the two TRIGTIME resources of the syn1588® Clock Core you can set up events in the
future that will occur exactly at the specified time. TRIGTIME0 is Fifo based and TRIGTIME1
is not. This is similar to EVENTINPUT0 and EVENTINPUT1
The Fifo based TRIGTIME0 is useful for situations where it is necessary to generate a lot of
Events (Signal Edges) in a short Amount of time. You can load the TRIGTIME0 Fifo with up
to 16 Events.
To use TRIGTIME0 you have to enable it using the associated bit in the EVENTCTRL
register first. This is important because if TRIGTIME0 is not enabled the Fifo is in a reset
state and all data is flushed.
After TRIGTIME0 is enabled, fill the Fifo with Values. Be careful to write to TRIGTIME0_L
first and TRIGTIME0_H last, because otherwise the fifo will not contain the values you are
expected.
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What happens next is that every time the syn1588® Clock Core reaches the time of the
current fifo value, the event is generated and the next fifo value is loaded for comparison.
This continues until the fifo is empty or TRIGTIME0 is disabled using the associated
EVENTCTRL bit.
The usage of TRIGTIME1 is straightforward: Enable TRIGTIME1 in the EVENTCTRL register
and write the desired time into the TRIGTIME0_L and TRIGTIME0_H registers. Afterwards
the event will be generated when the syn1588® Core Clock reaches the specified time.
For a diagram of how to enter seconds, nanoseconds and sub nanoseconds into the
TRIGTIME registers, refer to Table 17 for details about the alignment of time into the
registers.
11.3.4 Combinations of Periodical Events and One Shot Events
It is also possible to combine TRIGTIME and PERIODTIME. This is accomplished using the
EVENTCTRL register. Using this you can define exactly when a periodical event should
begin. You can combine PERIODTIME0 and PERIODTIME1 with TRIGTIME0 or
TRIGTIME1.
To accomplish this Task, first setup the desired combination of PERIODTIME and TRIGTIME
resources using the bits reserved for this task in the EVENTCTRL register.
Now setup the PERIODTIME resource as explained in Section 11.3.2. Then setup the
TRIGTIME resource as explained in Section 11.3.3 and that’s it!
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12 syn1588® Optimization and Trade-Offs

The achievable precision (π) of clock synchronization in an Ethernet local area network
depends on a variety of factors. These factors are:
• Physical layer (10/10/1000 Mbit/s) (εPHY)
• Quality of cabling (e.g. CAT5 or CAT6, because of asymmetry) (εCABLE)
• Link (Hub, Switch, direct connection) (εLINK)
• Quality of oscillators (e.g. 100 ppm XO or 0.1 ppm OCXO) (ρ)
• Granularity of local clock (e.g.10 MHz vs. 100 MHz) (G)
• Synchronization intervall (I)
12.1 Precision
Supposing that the mentioned uncertainties are averaged sufficiently long, the achievable
precision can be summarized in the following equation, as
π = Max{ εPHY, εCABLE, εLINK, ρI, G } ,
where
• εPHY is the Ethernet physical layer uncertainty,
• εCABLE is the cable delay asymmetry,
• εLINK is the Ethernet link layer uncertainty,
• ρ is the drift of the local clock oscillator,
• G is the granularity of the local clock,
• I is the synchronization interval.
12.2 Local Area Ethernet Networks

The following tables summarize the typical, estimated uncertainties of the above mentioned
terms contributing to the achievable precision. The distribution of these delay uncertainties is
not regarded.
εPHY
10 Mbit/s 400 ns
100 Mbit/s 2 ns
1 Gbit/s 8 ns
Table 24: Ethernet physical layer uncertainties.
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εCABLE
100 m CAT5 Not defined
100 m CAT5E 45 ns
100 m CAT6 45 ns
Table 25: Cabling uncertainties.
εLINK
Hub 100 Mbit/s (no Collisions) 20 ns
Hub 10 Mbit/s (no Collisions) 40 ns ?
Switch 100 Mbit/s (no Traffic) 100 ns
Switch 10 Mbit/s (no Traffic) 500 ns ?
Transparent Switch 100 Mbit/s (independent of Traffic, 5 ns ?
Timestamping Granularity neglected)
Transparent Switch 10 Mbit/s (independent of Traffic, 400 ns
Timestamping Granularity neglected)
Switch 100 Mbit/s (with Traffic) 20 µs
Switch 10 Mbit/s (with Traffic) 200 µs
Table 26: Typical Ethernet link delay uncertainties.
ρI (1 s) ρI (10 s) ρI (100 s)
XO (100 ppm) worst case 100 µs 1 ms 10 ms
TCXO (10 ppm) worst case 10 µs 100 µs 1 ms
OCXO (0.1 ppm) worst case 100 ns 1 µs 10 µs
XO (100 ppm) typical 10 µs 100 µs 1 ms
Table 27: Uncertainties introduced from oscillator drift.
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G
Adder based clock in FPGA 10 ns
Adder based clock in ASIC 5 ns
Adder based clock in FPGA (with 2,5 ns
HF-Prescaler for Timestamping)
Adder based clock in ASIC(with 1 ns
HF-Prescaler for Timestamping)
Table 28: Estimated uncertainties through clock implementation.
page 153

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syn1588® User Guide

Version 1.7 – May 28th 2011

Oregano Systems – Design & Consulting GesmbH

3.7.1.20 Time Register (TIME_E) ............................................................................. 44

4 syn1588® PCIe NIC ....................................................................................................... 85

7.8 Building the syn1588® PTP Stack:......................................................................... 127

11.3.3 One Shot Events TRIGTIME0 and TRIGTIME1 .............................................. 148

0.2 List of Figures

0.3 List of Tables

1 syn1588® Product Overview

1.1 syn1588® Network Interface Cards

1.2 syn1588® Gbit Switch

1.3 syn1588® Clock IP Cores

Figure 5: Block diagrams of available IP cores

Table 1 syn1588Clock IP core overview – Part I

Table 2 syn1588Clock IP core overview – Part II

1.4.1 A Fully Integrated Single Chip IEEE1588 Solution

Figure 6: syn1588® VIP IP Core

The syn1588® VIP comes in three flavours:

1.5 syn1588® Software

2 syn1588® Application Scenarios

2.1.1 syn1588® in SoC Designs

2.1.2 syn1588® in µC/µP Board Designs

Many microcontroller or microprocessor centered modules for applications of such varying

Figure 9: Principal SoC block diagram containing syn1588Clock core.

Ethernet MII Ether

2.1.3 syn1588® in Ethernet Network Component Designs

When it comes to application domains like computing, database systems, distributed

Trigger + AHB Trigger + SYN1588 SPI

2.1.4 syn1588® in Automation Systems

2.1.5 syn1588® in Measurement Systems

2.1.6 syn1588® in Communication Systems

Sensor Actuator Actuator Sensor

Sensor Actuator Actuator Sensor

Logic Analyzer Frequency Generator Pattern Generator Oscilloscope

Telephone Loudspeaker Headset Microphone

2.1.7 syn1588® in Many Other Systems

3 syn1588® PCI NIC

3.2 Functional Description

Figure 17: syn1588® PCI NIC basic block diagram

SYN1588 PCI NIC

3.3 Technical Specifications

3.4 Installing the syn1588® PCI NIC Hardware

3.6 Installing the syn1588® PCI NIC Software

The target has to comply with/support the following items:

The following Windows versions are supported:

3.7 Register Map

Address Name Function Mode

3.7.1 Register Description

3.7.1.1 Version Register (SYN1588_VER)

Address Mode Reset Value

3.7.1.2 Receive Timestamp FIFO Data Register (TSFIFO0_RX)

Address Mode Reset Value

TSFIFO0_RX(31:0) 32 bit of data is read from the FIFO.

Details see description of TSFIFO0_TX.

3.7.1.3 Transmit Timestamp FIFO Data Register (TSFIFO0_TX)

Address Mode Reset Value

TSFIFO0_TX(31:0) 32 bit of data is read from the FIFO..

DWord Version 2002 Version 2008

3.7.1.4 Transmit Timestamp FIFO Data Register (TSFIFO1_RX)

Address Mode Reset Value

TSFIFO_TX(31:0) 32 bit of data is read from the FIFO..

Details see description of TSFIFO0_TX.