110 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 37, NO.
1, JANUARY 2018
FinSAL: FinFET-Based Secure Adiabatic Logic for
Energy-Efficient and DPA Resistant IoT Devices
S. Dinesh Kumar, Student Member, IEEE, Himanshu Thapliyal, Senior Member, IEEE, and Azhar Mohammad
Abstract—With the emergence of Internet of Things (IoT),
there is an urgent need to design energy-efficient and secure IoT
devices. For example, IoT devices such as radio frequency identi-
fication tags and wireless sensor nodes employ AES cryptographic
module that are susceptible to differential power analysis (DPA)
attacks. With the scaling of technology, leakage power in the
cryptographic device increases, which increases their vulnera-
bility to DPA attack. This paper presents a novel FinFET-based
secure adiabatic logic (FinSAL), that is energy-efficient and DPA-
immune. The proposed adiabatic FinSAL is used to design logic
gates such as buffers, XOR, and NAND. Further, the logic gates
based on adiabatic FinSAL are used to implement a positive
polarity Reed Muller architecture-based S-box circuit. SPICE
simulations at 12.5 MHz show that adiabatic FinSAL (20-nm
FinFET technology) S-box circuit saves up to 81% of energy
per cycle as compared to the conventional S-box circuit imple-
mented using FinFET (20-nm FinFET technology). Further, the
security of adiabatic FinSAL S-box circuit has been evaluated
by performing the DPA attack through SPICE simulations. We
proved that the FinSAL S-box circuit is resistant to a DPA attack
through a developed DPA attack flow applicable to SPICE sim-
ulations. Further, the impact of FinSAL on hardware security at
different technology nodes of FinFETs (7, 10, 14, and 16 nm) are
evaluated. From the simulation results, FinSAL gates at 14-nm
FinFET offer superior security with optimum power consump-
tion, therefore is the best candidate to design low-power secure
IoT devices.
Index Terms—Adiabatic logic, differential power analy-
sis (DPA), FinFETs, hardware security, Internet of Things (IoT)
device, low-power (LP).
I. I NTRODUCTION
HE QUALITY of life of individuals and societies would
T improve with the emergence of Internet of Things
(IoT). IoT has widespread applications in the field of
manufacturing, automotive, medical, communication, finance,
etc. [3]. IoT-based devices such as radio frequency identifi-
cation (RFID) tags and wireless sensor nodes (WSNs) are
used to store and communicate the secret or personal data
over the Internet [4], [5]. However, the secret or personal
information stored and communicated through these IoT-based
Manuscript received September 14, 2016; revised December 29, 2016;
accepted February 26, 2017. Date of publication March 21, 2017; date of
current version December 20, 2017. A preliminary version of this paper has
been published in ISVLSI 2016 [1] and ICRC 2016 [2]. This paper was
recommended by Associate Editor S. Mohanty.
The authors are with the Department of Electrical and Computer
Engineering, University of Kentucky, Lexington, KY 40506 USA (e-mail:
hthapliyal@uky.edu).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCAD.2017.2685588
0278-0070 c 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: INDIAN INST OF INFO TECH AND MANAGEMENT. Downloaded on September 07,2020 at 19:50:42 UTC from IEEE Xplore. Restrictions apply.
devices can be obtained through the side-channel attacks [6].
Among the various side-channel attacks reported in the liter-
ature, differential power analysis (DPA) attack is considered
to be one of the powerful side-channel attacks to reveal the
secret information from the secure devices [7]. Various hard-
ware related DPA countermeasures have been developed over
the years [8]. But none of these countermeasures are suitable
to implement in devices where there is a constraint on power
consumption [8].
Adiabatic logic [10] is one of the circuit design techniques
to design energy-efficient and secure hardware. A survey on
DPA countermeasures has concluded that adiabatic logic is
one of the promising techniques to design low-power (LP)
and secure hardware [8]. Further, the usefulness of adiabatic
logic circuits for LP and DPA resistant IoT devices is also
established in a recent research article on [12].
There are very few contributions that have explored the
utility of adiabatic logic family as a DPA countermeasure
(Table I). However, the existing DPA-resistant adiabatic logic
families have some drawbacks as illustrated in Table I. Among
various logic families listed in Table I, symmetric pass gate
adiabatic logic (SPGAL) consumes LP and is more secure than
the existing DPA-resistant adiabatic logic families. These prop-
erties make it suitable to implement in IoT-based devices [1].
However, at lower technology nodes, SPGAL has relatively
high leakage power as compared to existing DPA-resistant
adiabatic logic families.
Scaling of the device technology leads to the increase
in the leakage current [17]. Increase in the leakage current
reduces the energy-efficiency of the computing circuits [18],
and increases their vulnerability to DPA attack [19]. Hence,
it is important to investigate the crypto circuits in low leak-
age devices such as FinFET to make them ultra-LP and DPA
resistant.
A. Motivation
With the emergence of IoT, there is an urgent need to
design LP and secure IoT devices. Improvement in the secu-
rity of these devices comes at the cost of reduction in battery
life. Battery life is considered as an important parameter in
the design of self-powered IoT devices. Adiabatic logic is
considered to be an alternate way to design LP and DPA-
resistant hardware. One of the main feature of adiabatic logic
is that it can operate efficiently at a frequency less than
1 GHz. Thus, adiabatic logic can be used to design LP and
secure IoT-based devices which operate at low frequencies.
 KUMAR et al.: FINSAL FOR ENERGY-EFFICIENT AND DPA RESISTANT IoT DEVICES
TABLE I
D RAWBACKS OF E XISTING DPA R ESISTANT A DIABATIC L OGIC FAMILIES
For example, RFID operates at 13.56 MHz [21] which is in the
range where adiabatic circuits can operate energy efficiently.
The main motivation of this paper is to design energy-
efficient and secure adiabatic logic using FinFET devices.
This design reduces energy losses which improves the energy-
efficiency and security of the devices. Further, effect of
FinFET parameters on the security of the FinFET-based adia-
batic logic has been considered during the design to avoid the
vulnerability of the circuit to DPA attack. To the best of our
knowledge, this is the first work done on designing energy-
efficient and secure adiabatic logic using FinFET devices. The
proposed designs can be implemented in IoT devices such as
RFIDs and WSNs where energy-efficiency, area and security
are major concern.
B. Contribution of This Paper
In this paper, we are proposing a FinFET-based secure
adiabatic logic (FinSAL). We have designed the basic logic
cells such as buffer/NOT, XOR/XNOR, and AND/NAND using
the FinSAL. The designs are simulated based on predictive
technology model (PTM) for 20-nm FinFETs at 12.5 MHz.
Normalized energy deviation (NED) and normalized standard
deviation (NSD) values are calculated to evaluate the secu-
rity of the proposed logic cells. Further, in this paper we have
discussed the effect of change in load capacitances, number
of fins, and the clock jitter on the security of the FinSAL
logic. Later, the logic cells are implemented at lower tech-
nology FinFET nodes such as 16, 14, 10, and 7 nm. NED
and NSD values of the FinSAL gates when implemented
at different technology nodes of FinFET are also compared.
Leakage power of the FinSAL gates are analyzed. A signifi-
cant reduction of leakage power in FinSAL gates are observed
compared to CMOS-based DPA resistant adiabatic logic fam-
ilies. The security of the FinSAL is ensured by performing a
simulation-based DPA attack on a 8-bit S-box circuit designed
using FinSAL gates. Signal-to-noise ratio (SNR) values of
the FinSAL S-box circuit implemented at different FinFET
technology nodes are also calculated.
C. Organization of This Paper
Section II presents the background of the adiabatic logic,
losses in adiabatic logic, and FinFET devices. Section III
presents the proposed FinSAL design and its operation.
Section IV presents the simulation results of the FinSAL-based
logic gates at 20-nm FinFET technology. NED and NSD
values of FinSAL gates along with existing DPA-resistant adi-
abatic logic gates are also compared. Section V discusses
the effect the change in load capacitances, number of fins,
Authorized licensed use limited to: INDIAN INST OF INFO TECH AND MANAGEMENT. Downloaded on September 07,2020 at 19:50:42 UTC from IEEE Xplore. Restrictions apply.
111
Fig. 1. Adiabatic charging/discharging.
and the clock jitter on the security of the FinSAL logic.
Section VI presents the evaluation of the FinSAL logic gates
at lower FinFET technology nodes. Section VII presents the
leakage power analysis of the FinSAL logic gates. Section VIII
presents the energy efficiency and security evaluation of the
FinSAL-based S-box circuit, DPA attack performed on it
and analyses of the SPICE simulations. Section IX discusses
about the suitable FinFET technology for implementing DPA-
resistant IoT devices which is more resistant to DPA attack
with optimum energy consumption. Section IX also discusses
about the method to minimize the high current pulse in
FinSAL logic and the effect of number of fins in FinSAL
S-box circuit. Section X concludes this paper.
II. BACKGROUND
A. Adiabatic Logic
Adiabatic logic uses power clocks to efficiently recycle the
charge stored in the load capacitor. Because of recycling of
charge, adiabatic logic has reduced dynamic switching energy
loss. Fig. 1 shows the adiabatic charging/discharging of the
load capacitors. The energy dissipated in an adiabatic circuit
when considering the charge is supplied through a constant
current source is shown by
RC
Ediss = CV2dd (1)
T
where T is the charging/discharging time of the capacitor, C is
the load capacitor, and Vdd is the full swing of the power clock.
If T  2RC (time constant), the energy dissipated by the
adiabatic circuit is less than the conventional CMOS circuit.
Further, with T approaching infinity, the energy dissipation in
an adiabatic circuit will tend toward zero. Therefore, adiabatic
circuits are good candidates to design LP circuits operating at
low frequencies.
 112 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 37, NO. 1, JANUARY 2018
(a) (b)
Fig. 2. (a) 3-D structure of SG mode FinFET. (b) Symbols of SG mode
FinFET.
B. FinFET Device
FinFET has a 3-D structure which has a thin silicon
body perpendicular to the plane of the wafer. The chan-
nel of the FinFET is wrapped by the gate in all three
directions. Fig. 2(a) shows the 3-D structure of the FinFET
device. FinFET provide strong gate control over channels.
Strong gate control over channels reduces the short-channel
effects, threshold current, and gate-dielectric leakage current
than MOSFETs [20]. Better gate control in FinFETs over
MOSFETs results in higher on-state current, lower leakage,
and faster switching speed. Multigate structure of FinFET
allows for different working modes of FinFET. The two main
working modes for FinFET are shorted-gate (SG) mode and
independent-gate (IG) mode.
1) Shorted-Gate Mode: In the SG mode, double gate (back
gate and front gate) of the FinFET are tied together. FinFET
acts as a three terminal device in SG mode. Fig. 2(b) shows
the symbols of SG mode FinFET.
2) Independent-Gate Mode: In the IG mode, top part of
the gate is removed to form two IGs. The front gate and back
gate are connected to two different inputs. FinFET acts as a
four terminal device in IG mode. The special case of IG mode
to reduce the threshold leakage is called as LP mode.
III. P ROPOSED F IN FET-BASED S ECURE
A DIABATIC L OGIC
This section explains the logic structure of proposed
FinSAL. In this paper, we have investigated the FinSAL in
SG mode type. SG mode can be consider a replacement to
bulk CMOS without changing the configuration of existing
circuits.
A. Logic Structure
The proposed FinSAL buffer is depicted in Fig. 3(a). Input
and output signals shown in Fig. 3(b) demonstrates the logic
operation.
Let us try to understand the working of the FinSAL buffer
through different phases of the clock (wait, evaluate, hold, and
recovery).
1) T1 (Wait Phase): In this phase, the power clock VCLK
is stable at GND (low level). The evaluation path signal is
established by A or A (M3 or M4) [Fig. 3(a)]. In this case
[Fig. 3(b)], A slowly rises from 0 to Vdd which leads M3 to
Authorized licensed use limited to: INDIAN INST OF INFO TECH AND MANAGEMENT. Downloaded on September 07,2020 at 19:50:42 UTC from IEEE Xplore. Restrictions apply.
turn ON. The DISCHARGE signal is high (Vdd ) in this phase
to discharge the load capacitances through M5 or M6. The
redundant charge stored in load capacitances are discharged to
GND before the logic function is evaluated. Discharging the
load capacitors before the evaluation of logic function prevents
the circuit from depending on previous input data.
2) T2 (Evaluate Phase): In this phase, DISCHARGE signal
is stable at GND (low level) which turns OFF M5 or M6. The
power clock slowly rises from 0 to Vdd which leads to flow
of current through the evaluate transistors (M3 or M4). In
this case [Fig. 3(b)], when VCLK rises from 0 to Vdd , and
the current flow through M3 which leads to the output load
capacitor (OUT) to be charged.
3) T3 (Hold Phase): During the hold phase, the current
active input signal is slowly decrease to low level (GND). The
power clock VCLK is stable at high level (Vdd ). The output
signal remain stable in this phase. In this case [Fig. 3(b)], A
slowly decreases from Vdd to 0. The OUT is stable at high
level (Vdd ).
4) T4 (Recovery Phase): During the recovery phase, the
power clock VCLK slowly decreases from Vdd to 0. The cur-
rent active output discharges to a low level through M1 or M2.
The charge stored in the active output load capacitor is dis-
charged to VCLK through M1 or M2. Consequently, charge
recovery happens in every clock cycle (T1–T4). Recovering
the charge in every clock cycle minimizes the energy lost.
In this case [Fig. 3(b)], charge stored in the output load
capacitor (OUT) is recovered back to VCLK through M1.
Power clocks required for this circuit is generated by a ded-
icated circuit. Examples of such adiabatic clock generation
circuitry are explained in [24].
B. FinSAL-Based Logic Gates
Fig. 4 shows the schematic of the FinSAL XOR/XNOR
gate. In FinSAL XOR/XNOR gate, M1 and M2 transistors
are used to recover the charge stored in the load capacitors to
the power clock VCLK. M9 and M10 are used to discharge
the redundant charge stored in the load capacitors before the
evaluation of next phase inputs. Rest of the transistors are
used for the evaluation of XOR/XNOR logic function. Fig. 5
validates with an example of FinSAL XOR/XNOR gate that
the proposed FinSAL gates have minimum output distortion
which make them less vulnerable to DPA attack.
Fig. 6 shows the schematic of the FinSAL AND/NAND gate.
In FinSAL AND/NAND gate, M1 and M2 transistors are used
to recover the charge to the power clock VCLK. M13 and M14
are used to discharge the redundant charge stored in the load
capacitors before the evaluation of next phase inputs. Rest of
the transistors are used for the evaluation of AND/NAND logic
function.
The intrinsic capacitance of the FinSAL-based logic gates
could play a critically role in the DPA resistance of the crypto-
graphic circuits. This is because as the unequal intrinsic capac-
itances of the dual rail logic functions coupled with unbalanced
load capacitances could produce nonuniform current con-
sumption which can be easily observed through the output
waveform. In this paper, the security of the FinSAL-based
 KUMAR et al.: FINSAL FOR ENERGY-EFFICIENT AND DPA RESISTANT IoT DEVICES
(a)
Fig. 3. (a) Schematic of FinSAL buffer. (b) Timing diagram for FinSAL buffer.
Fig. 4. FinSAL XOR/XNOR gate.
Fig. 5. Input and output waveforms of FinSAL XOR gate.
Fig. 6. FinSAL AND/NAND gate.
circuits are ensured by balancing the current consumption
of the FinSAL-based logic gates through proper gate sizing
and manual layout of the circuit nodes. Current consump-
tion in FinSAL-based logic gates are balanced by balancing
the load capacitances of the logic gates. For instance, the
load capacitance of the FinSAL XOR/XNOR gate is balanced.
Authorized licensed use limited to: INDIAN INST OF INFO TECH AND MANAGEMENT. Downloaded on September 07,2020 at 19:50:42 UTC from IEEE Xplore. Restrictions apply.
113
(b)
Fig. 7. Current consumption of conventional XOR gate implemented in
FinFET technology.
The pull up network of the XOR logic function consist of two
series transistor (M3 and M4) and a parallel transistor (M5).
Similarly, the pull up network of the XNOR logic function
consists of two series transistor (M6 and M7) and a paral-
lel transistor (M8). Thus, the load capacitance of the FinSAL
XOR/XNOR gate is balanced. The pull up network of the
AND logic function can be designed by connecting the M3
and M4 transistors in series. Similarly, the pull up network
of the NAND logic function can be designed by connecting
the M8 and M10 transistors in parallel. But, the overall load
capacitance of the AND logic function is not same as the
overall load capacitance of the NAND logic function. In order
to balance the load capacitance, M5–M7 and M9 transistors
are added. These transistors are connected in such a way (as
shown in Fig. 6) that the overall load capacitances of the AND
and NAND logic functions are balanced while the functionality
of the circuit remains the same.
C. Current Consumption of Adiabatic FinSAL XOR Gate
and FinFET-Based Conventional XOR Gate
Fig. 7 shows the current consumed by the FinFET-based
conventional XOR gate with the load capacitor of 1fF. The cur-
rent consumption of the FinFET-based conventional XOR gate
is not uniform. This can make the circuit vulnerable to DPA
attack. Fig. 8(a) shows the current consumed by the FinSAL
XOR gate with equal size FinFETs. With equal size FinFETs,
for each input transition peak current consumed by the FinSAL
XOR gate is uniform. However, the current consumed dur-
ing the hold phase of the clock is not uniform [Fig. 8(a)].
This nonuniform current consumption during the hold phase
of the clock can make the circuit vulnerable to DPA attack.
 114 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 37, NO. 1, JANUARY 2018
Fig. 8. Current consumption of proposed FinSAL XOR gate for various
input transitions with (a) all FinFETs are equally sized and (b) 2× effective
width of discharge FinFETs.
Fig. 9. Energy consumption comparison of FinSAL and conventional
FinFET-based XOR gate.
To remove the DPA vulnerability during hold phase of
the FinSAL gates, proper sizing of FinFETs are needed.
Therefore, in FinSAL logic gates, discharging transistors are
sized 2× that of the other FinFETs. Doubling the size of the
discharge FinFETs balance the load capacitances. FinFETs
have high intrinsic capacitance than the MOSFET at same
technology node. So, the increase size of the discharge tran-
sistors helps to discharge the redundant charge before the
evaluation of next cycle. Fig. 8(b) shows the uniform cur-
rent consumption of the FinSAL XOR with properly sized
FinFETs. With doubling the size of the discharge FinFETs,
current-data dependency at the hold phase is eliminated.
D. Energy Consumption of FinSAL XOR Gate
Fig. 9 shows the energy consumed during each cycle of the
adiabatic FinSAL- and FinFET-based conventional XOR gate.
It can be seen that the FinFET-based conventional XOR gate
suffers from dynamic switching energy loss whenever there
is a input transition. In the proposed adiabatic FinSAL XOR
gate, there is a small energy loss during the reset of outputs.
But the proposed adiabatic FinSAL XOR gate consumes less
energy as compared to the FinFET-based conventional XOR
gate due to recovery of charge in each phase of clock cycle.
IV. S IMULATION R ESULT OF F IN SAL-BASED
L OGIC G ATES (20- NM F IN FET)
In this section, we are presenting the simulation results of
the proposed FinSAL-based logic gates. The simulations are
Authorized licensed use limited to: INDIAN INST OF INFO TECH AND MANAGEMENT. Downloaded on September 07,2020 at 19:50:42 UTC from IEEE Xplore. Restrictions apply.
TABLE II
20−NM F IN FET D EVICE PARAMETERS
TABLE III
S IMULATED AND C ALCULATED R ESULTS FOR DPA-R ESISTANT
A DIABATIC L OGIC -BASED XOR G ATE
done in Cadence Virtuoso using Spectre simulator. Simulations
are based on PTM for 20-nm FinFETs with the load capaci-
tance of 1 fF. Table II provides the 20-nm FinFET technology
parameters which are used for simulation. In the proposed
designs, the size of the FinFETs are chosen to be minimum.
Effective width in FinFETs is defined as 2 × Hfin + tfin . So, for
20-nm FinSAL gates, effective width of FinFETs of M1–M4 in
Fig. 3(a) is 71 nm and the effective length is 24 nm. However,
the discharging FinFETs [M5 and M6 in Fig. 3(a)] are sized
2× than the other FinFETs. In this case, the effective width
of M5 and M6 are 142 nm. We have increased the size of
the discharge FinFETs to discharge the redundant charge to
ground. Increasing the effective width of FinFETs will allow
more current to flow through the FinFETs. So, increasing the
width of discharge FinFETs will discharge all the redundant
charge to ground. One key difference between the design of
adiabatic CMOS and adiabatic FinFET for security application
is that in adiabatic CMOS circuits all the transistors are sized
equally while in adiabatic FinFET circuits, size of FinFETs
need to be chosen carefully to achieve the uniform current
profile irrespective of input transitions.
The parameter NED, defined as (Emax −Emin )/Emax , is used
to indicate the percentage difference between minimum and
maximum energy consumption for all possible input transi-
tions. NSD [25] indicates the energy consumption variation
based on the inputs and it is calculated as (σE /Ē). Ē denotes
the average energy dissipation for various input transitions. In
general, “n” input gate will have 22n possible input transitions.
For example, two-input gate will have 16-input transitions. σE
denotes the standard deviation of the energy
  consumed dissi-
pated by the circuit and it is shown as ( ni=1 (Ei − Ē)2 /n).
The calculated values of NED and NSD for the proposed
FinSAL XOR gate and FinSAL AND gate show the ability
of the FinSAL logic family to resist DPA attacks at cell level.
Tables III and IV show the simulated and calculated results
of proposed FinSAL XOR and FinSAL AND gate, respec-
tively. The results of FinSAL gates are compared with charge-
sharing symmetric adiabatic logic (CSSAL) [15] and secured
 KUMAR et al.: FINSAL FOR ENERGY-EFFICIENT AND DPA RESISTANT IoT DEVICES
TABLE IV
S IMULATED AND C ALCULATED R ESULTS FOR DPA-R ESISTANT
A DIABATIC L OGIC -BASED AND G ATE
quasi-adiabatic logic (SQAL) [9]. From Tables III and IV, it
can be inferred that FinSAL-based XOR and AND gate have
very negligible energy deviation for various input transitions.
This property of FinSAL gates make it suitable to build DPA
resistant hardware.
V. R ELIABILITY PARAMETERS OF F IN SAL
L OGIC AGAINST DPA ATTACK
This section discusses the reliability parameter of FinSAL
logic against DPA attack. In this section, we discuss the effect
of change in load capacitances, number of fins and the clock
on security of FinSAL logic.
A. Effect of Load Capacitance on Security of FinSAL Logic
The difference in load capacitance will result in difference in
current consumption of the logic gates. Difference in current
consumption due to the load capacitances result the circuit
prone to DPA attack. So, balanced and unbalanced load test
of proposed FinSAL-based gates are performed in this paper.
In the balanced test, we have chosen both load capacitance
values to be 1fF and we calculated the NED and NSD values.
However, in practical circuits, due to manufacturing defects
and routing issues, load capacitances of a gate may not be
balanced. Unbalancing of the load capacitances reduce the reli-
ability of the design in terms of security. In order to address
the unbalanced load capacitance effect, we have tested our
designs with unbalanced load with the tolerance in the capac-
itance value of 50%. In our case, one of the load capacitance
is fixed to be 1 fF and the other is 0.5 fF. In FinSAL AND
and XOR gates for balanced load capacitances, the number of
observations and the energy dissipation chart shows the mini-
mal deviation of energy consumptions. For FinSAL AND gate
with balanced load capacitances, we can see that the minimum
energy consumption of an AND gate is 0.081 fJ and maximum
energy consumption of 0.094 fJ with a energy consumption
difference of 0.013 fJ. The energy consumption range of
energy deviations of a FinSAL AND gate is very small which
improves the security of these gates. In the worst case sce-
nario, with an unbalanced load capacitances, FinSAL AND
gate consumes minimum of 0.062 fJ and maximum energy
consumption of 0.094 fJ. The range of the FinSAL AND gate
with unbalanced load capacitance is 0.031 fJ. FinSAL AND
gates with unbalanced gates has low energy deviations. This
shows that routing problems in FinSAL-based circuits when
implementing complicated circuits will not affect the security
of the circuits.
Authorized licensed use limited to: INDIAN INST OF INFO TECH AND MANAGEMENT. Downloaded on September 07,2020 at 19:50:42 UTC from IEEE Xplore. Restrictions apply.
115
TABLE V
S IMULATED AND C ALCULATED R ESULTS FOR BALANCED
AND U NBALANCED F IN SAL AND G ATE
TABLE VI
S IMULATED AND C ALCULATED R ESULTS FOR BALANCED
AND U NBALANCED F IN SAL XOR G ATE
Further, we have performed the simulations with the unbal-
anced load capacitances. Results of FinSAL AND and FinSAL
XOR gate with unbalanced load capacitances are presented in
Tables V and VI. It can be seen from Tables V and VI that for
unbalanced load capacitances, FinSAL XOR gate, and FinSAL
AND gate have NED and NSD values less than 1%. Energy
consumption, NED and NSD values of proposed FinSAL gates
with balanced and unbalanced load capacitances show that
FinSAL-based logic gates can be used to design LP, secure
and miniaturized IoT devices.
B. Effect of Number of Fins on Security of FinSAL Logic
FinFETs have unique parameters compared to classical
CMOS such as number of fins, thickness and height of fins.
The thickness and the height of the fins are defined by the
technology node, however, the designer has the control over
number of fins to improve the performance and the power
characteristics of the design. Therefore, evaluation of FinSAL
logic with respect to number of fins is performed. The size
of the FinFET is defined by the width and the length of the
FinFET. The width of the FinFET is given by n(2hfin + tfin ),
where hfin is the height of the FinFET, tfin is the thickness of
the FinFET, and n is the number of fins. Width of the FinFETs
are quantized based on the number of fins. Higher value of
width in FinFET is achieved by increasing the number of fins.
Increasing the number of fins will allow more current to pass
through the fins which results in higher on-current.
In this paper, we have evaluated the effect of change in num-
ber of fins on security in FinSAL XOR gate. As an example,
we have consider the effect of change in number of fins on
the NED values. Fig. 10 shows the variations of NED value
with the change in number of fins. With the increase in the
number of fins, it is observed that there is a slight increase
in the NED values. With the increase in number of fins the
current flow through the FinFETs increases which increase the
NED values. Therefore, lower width FinFETs can provide bet-
ter security compared to higher width FinFETs with the cost
of decrease in performance.
 116 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 37, NO. 1, JANUARY 2018

TABLE VIII
C OMPARISON R ESULTS OF F IN SAL AND G ATE AT D IFFERENT F IN FET
T ECHNOLOGY N ODES (BALANCED L OAD C APACITANCES )

Fig. 10. NED values as a function of number of fins in FinSAL XOR gate.

TABLE VII
E FFECT OF C LOCK J ITTER AND C LOCK D ELAY TABLE IX
W ITH THE S ECURITY OF F IN SAL XOR G ATE C OMPARISON R ESULTS OF F IN SAL AND G ATE AT D IFFERENT F IN FET
T ECHNOLOGY N ODES (U NBALANCED L OAD C APACITANCES )

TABLE X
C. Effect of Clock on Security of FinSAL Logic C OMPARISON R ESULTS OF F IN SAL XOR G ATE AT D IFFERENT F IN FET
In FinSAL logic, four phase clocks are used to recover T ECHNOLOGY N ODES (BALANCED L OAD C APACITANCES )
the energy from the load capacitors. However, delay in the
clocks may lead to glitches which can affect the security of
the FinSAL logic. As an example, we have performed the
clock delay-based simulations on a FinSAL XOR gate. Four
FinSAL XOR gates are connected in series and the four phase
clocks are applied with clock jitter and the second clock is
delayed by 40 ns. Table VII shows the NED and NSD values
TABLE XI
of FinSAL XOR gate with jitter and clock delay. As expected, C OMPARISON R ESULTS OF F IN SAL XOR G ATE AT D IFFERENT F IN FET
FinSAL XOR logic with clock jitter consume high power as T ECHNOLOGY N ODES (U NBALANCED L OAD C APACITANCES )
compared to synchronized clock. However, FinSAL logic with
jitter and clock delay has similar energy deviations compared
to FinSAL logic without jitter. This shows that clock delay
and clock jitter has minimum effect on security of FinSAL
logic.

VI. E VALUATION OF F IN SAL L OGIC G ATES
AT L OWER T ECHNOLOGY F IN FET N ODES
It has been already shown in Tables III and IV that
FinSAL-based logic gates are more energy-efficient and secure
against DPA attacks as compared to the existing adiabatic
logic-based DPA countermeasure circuits. The main moti-
vation of this section is to analyze the security offered
by the FinSAL gates at lower FinFET technology nodes.
With the lowering of FinFET technology, Vdd is reduced.
Reduction of power supply reduces the dynamic energy con-
sumption. However, energy deviation of FinSAL gates at
lower technology nodes can be found out by simulation-based
experiments.
Security evaluation of the FinSAL logic gates are investi-
gated at 16-, 14-, 10-, and 7-nm FinFET technology nodes. As
discussed earlier, NED and NSD values are considered as the
security evaluation metrics for the logic gates. In order to con-
sider the effect of routing issues and manufacturing defects,
we have evaluated all the FinSAL logic gates with the bal-
anced and unbalanced load capacitances. The unbalanced load
capacitances are simulated with the tolerance of 50%.
TABLE XII
F IN FET D EVICE PARAMETERS FOR D IFFERENT T ECHNOLOGY N ODES
A. FinSAL Logic Gates at 16-nm Technology FinFET Nodes
Table XII shows the FinFET parameters which are used for
the simulation of the FinSAL logic gates at lower technology
nodes.
Tables VIII and X show the comparison results of the
FinSAL AND and FinSAL XOR gate at different technol-
ogy nodes with the balanced load capacitances, respectively.
From Tables VIII and X, it can be inferred that 16-nm FinSAL
AND and FinSAL XOR gate with balanced load capacitances
(0.8 fF) consume 6% and 7% less energy as compared to the
20-nm FinSAL AND and XOR gate. Tables VIII and X also
show that 16-nm FinSAL AND and XOR gate offer more

Authorized licensed use limited to: INDIAN INST OF INFO TECH AND MANAGEMENT. Downloaded on September 07,2020 at 19:50:42 UTC from IEEE Xplore. Restrictions apply.
 KUMAR et al.: FINSAL FOR ENERGY-EFFICIENT AND DPA RESISTANT IoT DEVICES
resistant to DPA attacks with reduced NED and NSD val-
ues. Tables IX and XI show the comparison results of the
FinSAL AND and XOR gate at different technology nodes
with the unbalanced load capacitances. From the simulation
and calculated results, we have observed that 20-nm FinSAL
AND gate with unbalanced load capacitances offers similar
security as compared to 16-nm FinSAL AND gate. Moreover,
with FinSAL XOR gate, we have observed that 20-nm FinSAL
XOR gate offer more security than 16-nm FinSAL XOR gate.
B. FinSAL Logic Gates at 14-nm Technology FinFET Nodes
From Tables VIII and X, it can be inferred that 14-nm
FinSAL AND and XOR gate with balanced load capacitances
(0.7 fF) consume 1% and 3% less energy as compared to the
16-nm FinSAL gates. Though there is not significant improve-
ment in energy consumption, 14-nm FinSAL AND and XOR
gate offers significant improvement in the security of the secu-
rity gates with NED value less than 0.01%. Very minimum
NED and NSD values of 14-nm FinSAL AND and XOR gate
makes it more secure as compared to the other technology
FinSAL AND gate. However, 14-nm FinSAL AND gate with
unbalanced load capacitance (Table IX) offer similar security
compared to other FinSAL AND gates. But, 14-nm FinSAL
XOR gate offers superior security as compared to other tech-
nology FinSAL XOR gate with unbalanced load capacitances
(Table XI).
C. FinSAL Logic Gates at 10-nm Technology FinFET Nodes
From Tables VIII and X, it can be inferred that 10-nm
FinSAL AND gate and FinSAL XOR gate with balanced load
capacitances (0.6 fF) consume 2% and 1% less energy as com-
pared to the 14-nm FinSAL AND and XOR gates. Though
10-nm FinSAL AND gate has reduced energy consumption
as compared to the 14-nm FinSAL AND gate, it can be seen
from Table VIII that 10-nm FinSAL AND gate have higher
NED values than 14-nm FinSAL AND gate. Higher NED val-
ues results in reduction in security of the 10-nm FinSAL AND
gate than 14-nm FinSAL AND gate. 10-nm FinSAL XOR gate
has almost same energy consumption and offers same security
as 14-nm FinSAL XOR gate. However, with the unbalanced
load capacitances, 14-nm FinSAL XOR gate offers superior
security as compared to 10-nm FinSAL XOR gate (Table XI).
D. FinSAL Logic Gates at 7-nm Technology
FinFET Nodes
With the lower technology nodes, Vdd is reduced which
results in the reduction of the energy consumption. From
Table VIII, it can be seen that 7-nm FinSAL AND gate con-
sumes less energy as compared to all other FinSAL technology
nodes. It is also shown that 7-nm FinSAL AND gate with bal-
anced capacitances (0.6 fF) offer superior security as compared
to 20-, 16-, and 10-nm FinSAL logic gates. From our simula-
tion results, we conclude that 14-nm FinSAL AND gate offer
superior security as compared to all other FinSAL AND gate
with balanced gates. However, 7-nm FinSAL AND gate with
unbalanced load capacitances offer similar security as 14-nm
Authorized licensed use limited to: INDIAN INST OF INFO TECH AND MANAGEMENT. Downloaded on September 07,2020 at 19:50:42 UTC from IEEE Xplore. Restrictions apply.
117
FinSAL AND gate and consumes less energy as compared
other FinSAL AND gate.
From Table XI, it can be inferred that 7-nm FinSAL
XOR gate saves up to 1% of energy as compared to the
FinSAL 10-nm XOR gate. 7-nm FinSAL XOR gate has almost
same energy consumption and offers same security as 14-nm
FinSAL XOR gate. However, with the unbalanced load capac-
itances, 14-nm FinSAL XOR gate offers superior security as
compared to 7-nm FinSAL XOR gate (Table XI).
VII. L EAKAGE P OWER A NALYSIS
OF F IN SAL L OGIC G ATES
With the scaling of technology (sub-100 nm), leakage power
is known to be comparable to the dynamic power and is
expected to become larger [26]. For IoT-based devices, minia-
turization is also an important aspect in the design along with
the security and the battery power. Miniaturization is done by
scaling the device. In a recent article on effectiveness of leak-
age power analysis attacks on DPA-resistant logic styles by
Alioto et al. [19] it has been proved that the existing DPA-
resistant logic styles are unsecured, which means the leakage
power can be used to reveal the secret keys.
FinFET is considered as a low-leakage emerging transistor
which have very low leakage power compared to MOSFET
due to the double gate control over the channel. In this sec-
tion, we are analyzing the reduction of leakage power in the
adiabatic logic-based FinSAL gates implemented at different
FinFET technology nodes. In this paper, leakage power is
calculated during the hold phase of the clock.
A. Leakage Power Analysis of DPA Resistant AND Gate
Table XIII provides the leakage power of various DPA resis-
tant adiabatic logic families for a two-input AND gate. We
have calculated the leakage power of MOSFET device-based
DPA-resistant adiabatic logic families at 45-nm technology.
We have calculated leakage power at 45-nm of MOSFET
device because 45-nm MOSFETs have significant leakage
power as compared to 180-nm MOSFET device [27].
From Table XIII, it is shown that MOSFET device-based
gates have higher leakage power as compared to the FinFET-
based gates. MOSFET devices have higher leakage power at
lower technology nodes due to the formation of the leakage
current in the short channel of the devices. However, leak-
age currents in the FinFETs can be reduced by the control
of double gates. In DPA-resistant adiabatic logic families in
Table XIII, SPGAL has high leakage power. Though SPGAL
have low dynamic power, it suffers from high leakage power
due to the pull down configuration of transistors. It is clearly
shown from the Table XIII that FinSAL AND gates reduces
leakage power dissipation as compared to the MOSFET-based
DPA-resistant adiabatic logic families.
14-nm FinSAL AND gate has very low leakage power as
shown in Table XIII. 14-nm FinSAL AND gate has 80.1% of
reduction of leakage current as compared to CSSAL AND
gate. 14-nm FinSAL AND gate has also reduced leakage
power as compared to other DPA-resistant adiabatic logic fam-
ilies. For example, 14-nm FinSAL AND has 72.45% and
 118 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 37, NO. 1, JANUARY 2018

TABLE XIII
L EAKAGE P OWER OF VARIOUS DPA R ESISTANT A DIABATIC L OGIC FAMILIES AT D IFFERENT
T ECHNOLOGY FOR A LL P OSSIBLE I NPUTS FOR A T WO -I NPUT AND G ATE

TABLE XIV
L EAKAGE P OWER OF VARIOUS DPA R ESISTANT A DIABATIC L OGIC FAMILIES AT D IFFERENT
T ECHNOLOGY FOR A LL P OSSIBLE I NPUTS FOR A T WO -I NPUT XOR G ATE

84.03% reduction of leakage power as compared to SQAL
and SPGAL AND gate. 14-nm FinSAL AND gate has 11.9%,
7.7%, 12.8%, and 13.9% reductions of leakage power as com-
pared to the FinSAL AND gate implemented in 20-, 16-, 10-,
and 7-nm FinFET technologies, respectively.
B. Leakage Power Analysis of DPA Resistant XOR Gate
Table XIV shows the leakage power of the DPA resistant
XOR gate simulated at 12.5 MHz. Similar to the DPA-
resistant AND gate, MOSFET-based DPA-resistant XOR gate
have higher leakage power than the FinFET-based gates. As
expected FinSAL-based XOR gate shows reduced leakage
power consumption as compared to the other DPA-resistant
adiabatic logic families. Similar to FinSAL AND gate, 14-nm
FinSAL XOR gate has lower leakage power consumption.
14-nm FinSAL XOR gate has 85.8%, 83.8%, and 87% of
reduction of leakage current as compared to CSSAL, SQAL,
and SPGAL XOR gate, respectively. 14-nm FinSAL XOR gate
has also reduced leakage power consumption as compared to
FinSAL XOR gate implemented in other FinFET node tech-
nologies. As shown in Table XIV, 14-nm FinSAL XOR gate
has 21.8%, 13.36%, 7.3%, and 11.3% of reduction of leakage
power as compared to the FinSAL XOR gate implemented in
20-, 16-, 10-, and 7-nm FinFET technologies, respectively.
VIII. E NERGY-E FFICIENCY AND S ECURITY E VALUATION
OF THE F IN SAL-BASED S-B OX C IRCUIT
In order to evaluate the security of the proposed FinSAL
logic, we have implemented a positive polarity Reed Muller
architecture-based S-box circuit [28] using FinSAL gates and
performed DPA attack on it.
A. Background on DPA Attack on 8-Bit S-Box Circuit
This section discusses the DPA-attack performed on the
S-box circuit in Cadence Virtuoso. The S-box circuit is
designed and simulated in Cadence Virtuoso. Post process-
ing of the current traces to extract the keys are done using
MATLAB and Python script. The following steps are followed
to perform the DPA attack on the S-box circuit (Fig. 11) [29].
1) A set of plain text I is XORed with a set of hypothet-
ical keys K. The resultant value is passed to the S-box
circuit. A set of expected outputs O (cipher texts) from
the S-box circuit is retrieved.
2) The power consumption of the different runs of the plain
text are recorded. The known current trace values are
written as a vector i = (i1 , i2 , . . . , id ), where in denotes
the current trace value of the nth input plain text. During
each run of the input plain text, current traces are col-
lected and sampled. The sampled current trace values
that corresponds to a particular input plain text is given
as ti = (ti,1 , ti,2 , . . . , ti,T ), where T denotes the length
of the trace.
3) In the next step of the DPA attack, the hypotheti-
cal power consumption model using Hamming distance
model is created. This model is represented by the H
matrix.
4) In the last step of the DPA attack, each column of the H
matrix is compared with each column of the M matrix,
i.e., the hypothetical power consumption values for all

Authorized licensed use limited to: INDIAN INST OF INFO TECH AND MANAGEMENT. Downloaded on September 07,2020 at 19:50:42 UTC from IEEE Xplore. Restrictions apply.
 KUMAR et al.: FINSAL FOR ENERGY-EFFICIENT AND DPA RESISTANT IoT DEVICES
Fig. 11. Simulation-based DPA attack flow.
Fig. 12. Successful DPA attack in a FinFET-based conventional CMOS
circuit.
the keys are compared with recorded traces at different
instances of time. This will result in an another matrix
R which is of size K ×T. Each element of R matrix (ri,j )
contains the comparison result between the columns of
hi and mj
D    energy efficiency becomes the major criteria of evaluation. The
d=1 hd,i − hi . md,j − mj
ri,j =  2 (2)
D  2 D 
d=1 hd,i − hi . d=1 md,j − mj
where hi and mj denotes the average values of the
columns hi and mj . The attacker looks for the maxi-
mal value for the entry in the R matrix. If the DPA
attack is successful, the correct key can be identified by
the maximal value that appears in a row (key) of the R
matrix.
B. Test Case for FinSAL-Based S-Box Circuit
In our test case, the key was chosen to be (181)10 . A DPA
attack was performed on FinSAL-based S-box circuit and
FinFET-based conventional S-box circuit. It was found that the
DPA attack was successful on the FinFET-based conventional
S-box circuit with 512 random plain texts whereas the DPA
attack performed on FinSAL-based S-box circuit was unsuc-
cessful. Fig. 12 shows the correlation co-efficient values of the
hypothetical key guesses for the successful DPA attack in a
conventional S-box circuit. It can be seen that the correlation
co-efficient value is peak for key guess = 181. The correlation
co-efficient value for the correct key is 0.78. Fig. 13 shows the
nonsuccessful DPA attack performed on the 8-bit S-box circuit
implemented using FinSAL gates. The correlation co-efficient
value is maximum for key guess = 231. The correlation
co-efficient of the hidden correct key (key = 181) is 1.6×10−4 .
Authorized licensed use limited to: INDIAN INST OF INFO TECH AND MANAGEMENT. Downloaded on September 07,2020 at 19:50:42 UTC from IEEE Xplore. Restrictions apply.
119
Fig. 13. Nonsuccessful DPA attack in a FinSAL-based S-box circuit.
C. Analysis of FinSAL-Based S-Box Circuit
In this section, analysis of the FinSAL-based S-box circuit
is done. Since the FinSAL-based gates are proposed for build-
ing DPA-resistant hardware in IoT-based devices, security and
proposed FinSAL logic uses four phase trapezoidal clocks to
recover the charge stored in the load capacitors. Since we are
targeting to implement DPA-resistant hardware in IoT-based
devices, we are making sure to use a minimum number of
voltage sources as compared to the existing DPA-resistant
adiabatic logic families. The total number of FinFETs used
to implement the FinSAL and conventional S-box circuit
are 3624 and 2202, respectively. From our simulations, we
found that the FinSAL S-box circuit works up to 800 MHz.
However, from our simulations, we found that FinSAL
S-box circuit is energy-efficient than its CMOS counterpart
up to 400 MHz.
1) Security Analysis of FinSAL S-Box Circuit: The immu-
nity of the FinSAL logic against DPA attack is validated by
calculating the SNR. SNR is defined as the ratio between
the correlation value of the correct key and the second max-
imal value of the wrong key guess [31]. Low SNR values
show the difficulty in distinguishing the correct key and the
wrong key. For the FinSAL-based S-box circuit, the wrong
key guess (key = 231) has the maximum correlation close to
4.35 × 10−4 and was slightly higher than the second maxi-
mal correlation 4.25 × 10−4 leading to SNR value of 1.023,
which is close to unity. For the FinFET implementation of
conventional CMOS-based circuit, for the correct key guess,
the correlation value was 0.8 and was much higher than the
second maximal value 0.42 leading to SNR value of 1.904.
SNR value of FinSAL S-box circuit close to unity shows that
 120 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 37, NO. 1, JANUARY 2018
TABLE XV
C OMPARISON R ESULTS OF S-B OX C IRCUIT I MPLEMENTED W ITH D IFFERENT A DIABATIC L OGIC FAMILY AT 12.5 MH Z
Fig. 14. SNR comparison of FinSAL logic at different FinFET technology
nodes as a function of number of inputs.
Fig. 15. SNR of FinSAL logic at different FinFET technology nodes as a
function of operating frequency.
it is difficult to distinguish the correct key and the wrong key
in a FinSAL S-box circuit.
Fig. 14 shows the SNR values of the FinSAL logic at dif-
ferent FinFET technology nodes as a function of number of
inputs. Fig. 15 shows the SNR values of the FinSAL logic at
different frequencies. SNR values for each technology node
are calculated as a function number of inputs. In this paper,
we have passed up to 20-,000 random input samples to the
test circuit to calculate the SNR values with each technol-
ogy nodes of FinSAL logic. We have observed that, FinSAL
logic implemented with 14-nm FinFET technologies have SNR
value close to unity. SNR value near to unity shows that it is
difficult to distinguish between the correct key and wrong key.
2) Energy-Efficiency Analysis of FinSAL S-Box Circuit:
This section discusses the energy efficiency of the FinSAL
S-box circuit as compared to the other DPA resistant adiabatic
logic-based S-box circuits. Table XV gives the comparison
results of the S-box circuit implemented with different DPA
resistant adiabatic logic family. In this paper, we are com-
paring the energy saving factor (ESF) of the S-box circuit
implemented with different DPA resistant adiabatic logic fam-
ily. ESF is defined as a measure of how much energy is used
Authorized licensed use limited to: INDIAN INST OF INFO TECH AND MANAGEMENT. Downloaded on September 07,2020 at 19:50:42 UTC from IEEE Xplore. Restrictions apply.
in a conventional CMOS gate or system with respect to its
adiabatic counterpart [23]. In this paper, ESF values are calcu-
lated based on conventional CMOS S-box circuit implemented
in 22-nm MOSFET.
As seen from Table XV, FinSAL S-box circuit implemented
with 7-nm FinFETs are more energy efficient with an ESF
value of 64.377. ESF value of 64.377 shows that the FinSAL
S-box circuit implemented with 7-nm FinFET saves up to 98%
of energy as compared to conventional CMOS-based S-box
circuit implemented with 22-nm MOSFET. With the lower-
ing of technology, maximum swing of the power supply is
reduced which reduces the overall energy dissipation. As seen
from the Table XV, FinSAL S-box circuit when implemented
with the lower technology FinFET node saves more energy as
compared to the FinSAL S-box implemented at higher tech-
nology nodes. As far as the other DPA- resistant logic styles,
CSSAL consume more power due to large number of transis-
tors, SQAL consume more energy as compared to SPGAL due
to the nonadiabatic operation of transistors during the evaluate
phase of the clock. SPGAL consume more energy as compared
to the FinSAL logic due to the implementation of SPGAL at
higher technology nodes in MOSFETs. Reduction of technol-
ogy nodes in SPGAL increases the leakage power. Reduced
energy dissipation in FinSAL logic as compared to the exist-
ing DPA-resistant adiabatic logic families makes it suitable
to implement in DPA resistant IoT devices where there is
tight constraint on size of the device, power consumption and
security of the device.
It has been showed that FinSAL S-box circuit has reduced
energy consumption as compared to the CMOS-based S-box
circuit implemented in FinFET. FinSAL S-box circuit imple-
mented at 20-nm FinFET technology saves up to 81% of
energy as compared to the CMOS-based S-box circuit imple-
mented in FinFET (20 nm). Energy consumption improvement
of FinSAL S-box circuit over CMOS-based S-box circuit
implemented in FinFET clearly shows that FinSAL gates are
energy-efficient and can be used to implement in IoT devices.
IX. D ISCUSSION
This section discusses about choosing the FinFET technol-
ogy to design Energy-efficient and DPA-resistant IoT devices.
From Table XV, it is shown that FinSAL logic is more
energy-efficient as compared to the existing DPA-resistant adi-
abatic logic families. However, with the scaling of FinFET
technology, security offered by the logic gates is changed.
 KUMAR et al.: FINSAL FOR ENERGY-EFFICIENT AND DPA RESISTANT IoT DEVICES
Fig. 16. Current consumption of FinSAL XOR with trapezoidal discharge
signal.
For example, 7-nm FinFET technology have short channels
as 14-nm FinFET which increases the leakage current and
makes the circuit more prone to DPA attack. But, 7-nm FinFET
technology is more energy-efficient as compared to the other
technologies due to the reduction in the swing of the volt-
ages. Reduction in the swing of the voltage sources reduces
the dynamic energy consumption.
From Table XV, it is concluded that 7-nm FinSAL logic is
more energy-efficient as compared to the other FinSAL logics.
However, Fig. 14 shows that 7-nm FinSAL logic is not secure
as compared to other FinSAL logic. From the security perspec-
tive, we can see that 14-nm FinFET technology offers superior
security as compared to other FinSAL logic with an SNR value
close to unity. Moreover, 14-nm FinSAL logic has compara-
ble energy consumption with 7-nm FinSAL logic. From our
simulation results, it is concluded that, FinSAL logic when
implemented in 14-nm FinFET technology nodes offer supe-
rior security and can be used to design secure IoT devices for
future.
A. Minimization of Huge Current Pulse in FinSAL Logic
This section discusses about the methods to reduce of cur-
rent pulse in FinSAL logic gates. The current consumption
in FinSAL logic gates can be made uniform by proper sizing
of FinFETs. However, FinSAL gates have huge current pulse
(refer Fig. 8) during the evaluate phase of the clock. This
huge current pulse can be suppressed to make the FinSAL
logic gates more secure against the DPA attack. We propose
to reduce the huge current pulse by reducing the adiabatic
energy loss. As discussed in Section II, energy consumption
in adiabatic circuits can be reduced by increasing the transition
period. So, one design technique which we can use to reduce
the huge current pulse is by replacing the square wave dis-
charge signal with the trapezoidal wave discharge signal. As an
illustration, we have replaced the square wave discharge signal
with the trapezoidal-based discharge signal of FinSAL XOR
gate. Fig. 16 shows the current consumption of the FinSAL
XOR gate with trapezoidal discharge signal. It is observed that
there is a huge minimization of current pulse in the FinSAL
XOR gate as compared to Fig. 8.
B. Impact of Number of Fins on FinSAL S-Box Circuit
The size of the FinFET is defined by the width and the
length of the FinFET. The width of the FinFET is given by
n × (2hfin + tfin), where hfin is the height of the FinFET,
tfin is the thickness of the FinFET, and n is the number of
fins. Width of the FinFETs is quantized based on the num-
Authorized licensed use limited to: INDIAN INST OF INFO TECH AND MANAGEMENT. Downloaded on September 07,2020 at 19:50:42 UTC from IEEE Xplore. Restrictions apply.
121
Fig. 17. Current consumption of FinSAL S-box with number of fins.
(a) n = 1. (b) n = 4. With n = 1, the peak current consumption of FinSAL
S-box is reduced approximately by 1.2 times than the FinSAL S-box circuit
with n = 4.
ber of fins. Higher value of width in FinFET is achieved
by increasing the number of fins. Increasing the number of
fins will allow more current to pass through the fins which
results in higher on-current. Therefore, the performance of
FinSAL-based S-box circuit is evaluated by increasing the
number of fins (n) with a case study of n = 4. Through SPICE
simulation, it is validated that with n = 4 the peak current of
FinSAL-based S-box circuit is 1.2 times higher compared to
the peak current of FinSAL-based S-box circuit with n = 1.
Therefore, the performance of FinSAL-based S-box circuit
can be improved by increasing the number of fins (Fig. 17).
However, as illustrated for FinSAL XOR gate, the increase in
number of fins reduces the security of FinSAL gates, there-
fore tradeoff between performance and security need to be
considered while increasing the number of fins in adiabatic
FinFET-based cryptographic circuits.
X. C ONCLUSION
We have proposed a novel DPA-resistant adiabatic logic
family called FinSAL. We have investigated the security of
the FinSAL logic to implement in secure IoT devices. At
the gate level simulation of FinSAL logic, it is observed that
change in number of fins has a significant effect on the security
of the FinSAL logic gates. With the increase in the number
of fins, security of FinSAL logic gate is reduced. However,
the variations in Vdd and the clock jitter do not have much
impact on the security of the FinSAL logic gates. Further,
the security of FinSAL against DPA attacks is validated by
implementing a S-box circuit and performing DPA attacks
through SPICE simulations. From our simulation results on
FinSAL logic implemented at different technology nodes, it
is concluded that FinSAL logic implemented at 14 nm offers
better security as compared to the other FinFET technology
nodes. As FinSAL is energy-efficient and secure against DPA
attacks, the cryptographic circuits based on it can be employed
in IoT-based portable electronic devices where there is a tight
budget on power consumption and security.
 122 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 37, NO. 1, JANUARY 2018
R EFERENCES
[1] S. D. Kumar, H. Thapliyal, A. Mohammad, V. Singh, and
K. S. Perumalla, “Energy-efficient and secure S-box circuit using sym-
metric pass gate adiabatic logic,” in Proc. IEEE Comput. Soc. Annu.
Symp. VLSI (ISVLSI), Pittsburgh, PA, USA, 2016, pp. 308–313.
[2] S. D. Kumar, H. Thapliyal, and A. Mohammad, “FinSAL: A novel
FinFET based secure adiabatic logic for energy-efficient and DPA
resistant IoT devices,” in Proc. IEEE Int. Conf. Rebooting Comput.,
San Diego, CA, USA, 2016, pp. 1–8.
[3] J. Gubbi, R. Buyya, S. Marusic, and M. Palaniswami, “Internet of Things
(IoT): A vision, architectural elements, and future directions,” Future
Gener. Comput. Syst., vol. 29, no. 7, pp. 1645–1660, 2013.
[4] E. Ilie-Zudor, Z. Kemény, F. van Blommestein, L. Monostori, and
A. van der Meulen, “A survey of applications and requirements of unique
identification systems and RFID techniques,” Comput. Ind., vol. 62,
no. 3, pp. 227–252, 2011.
[5] W. Cheng, S. Wang, and X. Cheng, “Virtual track: Applications and
challenges of the RFID system on roads,” IEEE Netw., vol. 28, no. 1,
pp. 42–47, Jan./Feb. 2014.
[6] D. Bandyopadhyay and J. Sen, “Internet of Things: Applications and
challenges in technology and standardization,” Wireless Pers. Commun.,
vol. 58, no. 1, pp. 49–69, 2011.
[7] P. Kocher, J. Jaffe, B. Jun, and P. Rohatgi, “Introduction to differential
power analysis,” J. Cryptographic Eng., vol. 1, no. 1, pp. 5–27, 2011.
[8] A. Moradi and A. Poschmann, “Lightweight cryptography and DPA
countermeasures: A survey,” in Financial Cryptography and Data
Security. Heidelberg, Germany: Springer, 2010, pp. 68–79.
[9] M. Avital, H. Dagan, I. Levi, O. Keren, and A. Fish, “DPA-secured
quasi-adiabatic logic (SQAL) for low-power passive RFID tags employ-
ing S-boxes,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 1,
pp. 149–156, Jan. 2015.
[10] W. C. Athas, L. J. Svensson, J. G. Koller, N. Tzartzanis, and
E. Y.-C. Chou, “Low-power digital systems based on adiabatic-switching
principles,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 2,
no. 4, pp. 398–407, Dec. 1994.
[11] S. D. Kumar and H. Thapliyal, “QUALPUF: A novel quasi-adiabatic
logic based physical unclonable function,” in Proc. 11th Annu. Cyber
Inf. Security Res. Conf., Oak Ridge, TN, USA, 2016, p. 24.
[12] M. Wolf, “Ultralow power and the new era of not-so-VLSI,” IEEE Des.
Test., vol. 33, no. 4, pp. 109–113, Aug. 2016.
[13] M. Khatir and A. Moradi, “Secure adiabatic logic: A low-energy DPA-
resistant logic style,” IACR Eprint archive, Tech. Rep. 2008/123, 2008.
[Online]. Available: http://eprint.iacr.org/2008/123
[14] B.-D. Choi, K. E. Kim, K.-S. Chung, and D. K. Kim, “Symmetric adia-
batic logic circuits against differential power analysis,” ETRI J., vol. 32,
no. 1, pp. 166–168, 2010.
[15] C. Monteiro, Y. Takahashi, and T. Sekine, “Charge-sharing symmetric
adiabatic logic in countermeasure against power analysis attacks at cell
level,” Microelectron. J., vol. 44, no. 6, pp. 496–503, 2013.
[16] S. Lu, Z. Zhang, and M. Papaefthymiou, “1.32GHz high-throughput
charge-recovery AES core with resistance to DPA attacks,” in
Proc. Symp. VLSI Circuits (VLSI Circuits), Kyoto, Japan, 2015,
pp. C246–C247.
[17] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage
current mechanisms and leakage reduction techniques in deep-
submicrometer CMOS circuits,” Proc. IEEE, vol. 91, no. 2, pp. 305–327,
Feb. 2003.
[18] S. Mukhopadhyay, A. Raychowdhury, and K. Roy, “Accurate estima-
tion of total leakage in nanometer-scale bulk CMOS circuits based
on device geometry and doping profile,” IEEE Trans. Comput.-Aided
Design Integr. Circuits Syst., vol. 24, no. 3, pp. 363–381, Mar. 2005.
[19] M. Alioto, S. Bongiovanni, M. Djukanovic, G. Scotti, and A. Trifiletti,
“Effectiveness of leakage power analysis attacks on DPA-resistant logic
styles under process variations,” IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 61, no. 2, pp. 429–442, Feb. 2014.
[20] D. Hisamoto et al., “FinFET-a self-aligned double-gate MOSFET scal-
able to 20 nm,” IEEE Trans. Electron Devices, vol. 47, no. 12,
pp. 2320–2325, Dec. 2000.
[21] D. Dressen, “Considerations for RFID technology selection,” Atmel
Appl. J., vol. 3, pp. 45–47, 2004.
[22] J. Lim, D.-G. Kim, and S.-I. Chae, “Reversible energy recovery logic
circuits and its 8-phase clocked power generator for ultra-low-power
applications,” IEICE Trans. Electron., vol. 82, no. 4, pp. 646–653, 1999.
[23] P. Teichmann, Adiabatic Logic: Future Trend and System Level
Perspective, vol. 34. Dordrecht, The Netherlands: Springer, 2011.
Authorized licensed use limited to: INDIAN INST OF INFO TECH AND MANAGEMENT. Downloaded on September 07,2020 at 19:50:42 UTC from IEEE Xplore. Restrictions apply.
[24] Y. Ye and K. Roy, “QSERL: Quasi-static energy recovery logic,” IEEE
J. Solid-State Circuits, vol. 36, no. 2, pp. 239–248, Feb. 2001.
[25] M. Bucci, L. Giancane, R. Luzzi, and A. Trifiletti, “Three-phase dual-
rail pre-charge logic,” in Proc. Int. Workshop Cryptographic Hardw.
Embedded Syst., Yokohama, Japan, 2006, pp. 232–241.
[26] (2008). International Technology Roadmap for Semiconductors (ITRS).
[Online]. Available: http://www.itrs2.net/
[27] B. G. Streetman and S. Banerjee, Solid State Electronic Devices, vol. 4.
Upper Saddle River, NJ, USA: Prentice-Hall, 2000.
[28] S. Morioka and A. Satoh, “An optimized S-box circuit architec-
ture for low power AES design,” in Cryptographic Hardware and
Embedded Systems-CHES 2002. Heidelberg, Germany: Springer, 2002,
pp. 172–186.
[29] J. Wu, Y. Shi, and M. Choi, “Measurement and evaluation of power
analysis attacks on asynchronous S-box,” IEEE Trans. Instrum. Meas.,
vol. 61, no. 10, pp. 2765–2775, Oct. 2012.
[30] C. Monteiro, Y. Takahashi, and T. Sekine, “Low-power secure S-box
circuit using charge-sharing symmetric adiabatic logic for advanced
encryption standard hardware design,” IET Circuits Dev. Syst., vol. 9,
no. 5, pp. 362–369, Sep. 2015.
[31] T. S. Messerges, E. A. Dabbish, and R. H. Sloan, “Examining smart-
card security under the threat of power analysis attacks,” IEEE Trans.
Comput., vol. 51, no. 5, pp. 541–552, May 2002.
S. Dinesh Kumar (S’15) received the B.E. degree
in electronics and communication engineering from
Anna University, Chennai, India, in 2013, and the
M.S. degree in electronic systems from the Indian
Institute of Information Technology, Design and
Manufacturing Kancheepuram, Kanchipuram, India,
in 2015. He is currently pursuing the Ph.D. degree
in electrical engineering with the University of
Kentucky, Lexington, KY, USA.
His current research interests include emerging
nanotechnologies and low-power hardware security
for Internet of Things devices.
Mr. Kumar was a recipient of the Upsilon Pi Epsilon Award for academic
achievement in computing discipline by the IEEE Computer Society in 2015.
Himanshu Thapliyal (SM’16) received the Ph.D.
degree in computer science and engineering from
the University of South Florida, Tampa, FL, USA,
in 2011.
From 2012 to 2014, he was a Designer
of Processor Test Solutions with Qualcomm,
San Diego, CA, USA. He is an Assistant Professor
with the Department of Electrical and Computer
Engineering, University of Kentucky, Lexington,
KY, USA. His current research interests include
emerging nanotechnologies, low-power hardware
security of Internet of Things devices, and smart health.
Dr. Thapliyal was a recipient of the Best Ph.D. Dissertation Award at
the 2012 IEEE Computer Society Annual Symposium on VLSI, and the
Qualcomm QualStar Award for contributions to memory built-in self-tests.
Azhar Mohammad received the B.Tech. degree
in electronics and communication engineering
from Jawaharlal Nehru Technological University at
Hyderabad, Hyderabad, India. He is currently pursu-
ing the master’s degree in electrical engineering with
the University of Kentucky, Lexington, KY, USA.
His current research interests include very large-
scale integration design, hardware security, and
cryptography.