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PIC12F509
PIC12F509
Data Sheet
8/14-Pin, 8-Bit Flash Microcontrollers
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
VDD 1 14 VSS
PIC12F508/509
VDD 1 8 VSS
RB5/OSC1/CLKIN 2 13 RB0/ICSPDAT
GP5/OSC1/CLKIN 2 7 GP0/ICSPDAT
RB4/OSC2/CLKOUT 3 12 RB1/ICSPCLK
PIC16F505
GP4/OSC2 3 6 GP1/ICSPCLK
RB3/MCLR/VPP 4 11 RB2
GP3/MCLR/VPP 4 5 GP2/T0CKI
RC5/T0CKI 5 10 RC0
RC4 6 9 RC1
RC3 7 8 RC2
DFN
PIC12F508/509
VDD 1 8 VSS
GP5/OSC1/CLKIN 2 7 GP0/ICSPDAT
GP4/OSC2 3 6 GP1/ICSPCLK
GP3/MCLR/VPP 4 5 GP2/T0CKI
PIC12F508 512 25 6 1
PIC12F509 1024 41 6 1
PIC16F505 1024 72 12 1
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include
literature number) you are using.
Memory
Device
Program Data
PIC12F508 512 x 12 25 x 8
PIC12F509 1024 x 12 41 x 8
PIC16F505 1024 x 12 72 x 8
The PIC12F508/509/16F505 devices can directly or
indirectly address its register files and data memory. All
Special Function Registers (SFR), including the PC,
are mapped in the data memory. The PIC12F508/509/
16F505 devices have a highly orthogonal (symmetri-
cal) instruction set that makes it possible to carry out
any operation, on any register, using any addressing
mode. This symmetrical nature and lack of “special
optimal situations” make programming with the
PIC12F508/509/16F505 devices simple, yet efficient.
In addition, the learning curve is reduced significantly.
12 8 GPIO
Data Bus
Flash Program Counter
512 x 12 or GP0/ISCPDAT
1024 x 12 GP1/ISCPCLK
RAM GP2/T0CKI
Program Stack 1 25 x 8 or
Memory GP3/MCLR/VPP
41 x 8 GP4/OSC2
Stack 2 File
Registers GP5/OSC1/CLKIN
Program 12
Bus RAM Addr 9
Addr MUX
Instruction Reg
Direct Addr 5 Indirect
5-7 Addr
FSR Reg
Status Reg
8
3 MUX
Device Reset
Timer
Instruction
Decode and ALU
Control Power-on
Reset
8
OSC1/CLKIN Timing Watchdog
Generation Timer W Reg
OSC2
Internal RC
OSC Timer0
MCLR
VDD, VSS
12 8 PORTB
Data Bus
Program Counter
Flash RB0/ICSPCLK
1K x 12 RB1/ICSPDAT
Program RAM RB2
Memory Stack 1 72 bytes RB3/MCLR/VPP
Stack 2 File RB4/OSC2/CLKOUT
Registers RB5/OSC1/CLKIN
Program 12
Bus RAM Addr 9 PORTC
Addr MUX
Instruction Reg RC0
Direct Addr 5 Indirect RC1
5-7 Addr RC2
RC3
FSR Reg RC4
RC5/T0CKI
Status Reg
8
3 MUX
Device Reset
Timer
MCLR
VDD, VSS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
phase
Q3 clock
Q4
PC PC PC + 1 PC + 2
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
User Memory
(PC) and PIC12F509 has a 11-bit Program Counter
Space
(PC) capable of addressing a 2K x 12 program memory 512 Word 01FFh
space. 0200h
Only the first 512 x 12 (0000h-01FFh) for the
PIC12F508, and 1K x 12 (0000h-03FFh) for the On-chip Program
PIC12F509 are physically implemented (see Memory
Figure 4-1). Accessing a location above these
boundaries will cause a wraparound within the first 1024 Word 03FFh
512 x 12 space (PIC12F508) or 1K x 12 space 0400h
(PIC12F509). The effective Reset vector is a 0000h
(see Figure 4-1). Location 01FFh (PIC12F508) and
location 03FFh (PIC12F509) contain the internal
clock oscillator calibration value. This value should
never be overwritten. 7FFh
01FFh
0200h
On-chip Program
Memory
7FFh
FSR<6:5> 00 01 10 11
File Address
00h INDF(1) 20h 40h 60h
01h TMR0
02h PCL
03h STATUS Addresses map back to
addresses in Bank 0.
04h FSR
05h OSCCAL
06h PORTB
07h PORTC
08h General
Purpose
0Fh Registers 2Fh 4Fh 6Fh
10h 30h 50h 70h
General General General General
Purpose Purpose Purpose Purpose
Registers Registers Registers Registers
Note 1: Not a physical register. See Section 4.9 “Indirect Data Addressing: INDF and FSR Registers”.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: This bit is used on the PIC12F509. For code compatibility do not use this bit on the PIC12F508.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GPWU: Enable Wake-up on Pin Change bit (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 6 GPPU: Enable Weak Pull-ups bit (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin)
0 = Transition on internal instruction cycle clock, FOSC/4
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on the T0CKI pin
0 = Increment on low-to-high transition on the T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate WDT Rate
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RBWU: Enable Wake-up on Pin Change bit (RB0, RB1, RB3, RB4)
1 = Disabled
0 = Enabled
bit 6 RBPU: Enable Weak Pull-ups bit (RB0, RB1, RB3, RB4)
1 = Disabled
0 = Enabled
bit 5 T0CS: Timer0 clock Source Select bit
1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin)
0 = Transition on internal instruction cycle clock, FOSC/4
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on the T0CKI pin
0 = Increment on low-to-high transition on the T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate WDT Rate
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
For a GOTO instruction, bits 8:0 of the PC are provided The STATUS register page preselect bits are cleared
by the GOTO instruction word. The Program Counter upon a Reset, which means that page 0 is pre-selected.
(PCL) is mapped to PC<7:0>. Bit 5 of the STATUS Therefore, upon a Reset, a GOTO instruction will
register provides page information to bit 9 of the PC automatically cause the program to jump to page 0 until
(Figure 4-6). the value of the page bits is altered.
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are 4.8 Stack
provided by the instruction word. However, PC<8>
The PIC12F508/509/16F505 devices have a 2-deep,
does not come from the instruction word, but is always
12-bit wide hardware PUSH/POP stack.
cleared (Figure 4-6).
A CALL instruction will PUSH the current value of Stack 1
Instructions where the PCL is the destination, or modify
into Stack 2 and then PUSH the current PC value, incre-
PCL instructions, include MOVWF PC, ADDWF PC and
mented by one, into Stack Level 1. If more than two
BSF PC,5.
sequential CALLs are executed, only the most recent two
Note: Because PC<8> is cleared in the CALL return addresses are stored.
instruction or any modify PCL instruction, A RETLW instruction will POP the contents of Stack
all subroutine calls or computed jumps are Level 1 into the PC and then copy Stack Level 2
limited to the first 256 locations of any contents into Stack Level 1. If more than two sequential
program memory page (512 words long). RETLWs are executed, the stack will be filled with the
address previously stored in Stack Level 2. Note that
FIGURE 4-6: LOADING OF PC the W register will be loaded with the literal value
BRANCH INSTRUCTIONS specified in the instruction. This is particularly useful for
the implementation of data look-up tables within the
GOTO Instruction program memory.
11 10 9 8 7 0
PC Note 1: There are no Status bits to indicate stack
PCL
overflows or stack underflow conditions.
2: There are no instruction mnemonics
Instruction Word called PUSH or POP. These are actions
PA0 that occur from the execution of the CALL
7 0 and RETLW instructions.
Status
Instruction Word
Reset to ‘0’
PA0
7 0
Status
1Fh 3Fh
Bank 0 Bank 1(2)
Note 1: For register map detail, see Section 4.3 “Data Memory Organization”.
2: PIC12F509.
Note 1: For register map detail, see Section 4.3 “Data Memory Organization”.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Data Bus
(GP2/RC5)/T0CKI FOSC/4 0
Pin PSOUT 8
1
Sync with
1 Internal TMR0 Reg
Clocks
Programmable 0 PSOUT
Prescaler(2)
T0SE (2 TCY delay) Sync
3
PS2, PS1, PS0(1) PSA(1)
T0CS(1)
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(Program
Counter) PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
Instruction
Executed
Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2
PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(Program
Counter) PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
Instruction
Executed Read TMR0
Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
External Clock Input or Small pulse
Prescaler Output (2) misses sampling
(1)
External Clock/Prescaler (3)
Output After Sampling
Timer0 T0 T0 + 1 T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error
in measuring the interval between two edges on Timer0 input = ±4 TOSC max.
2: External clock if no prescaler selected; prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
T0SE T0CS
PSA
0
8-bit Prescaler
M
U
1 X
Watchdog 8
Timer
8-to-1 MUX PS<2:0>
PSA
0 1
WDT Enable bit
MUX PSA
WDT
Time-out
Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
2: T0CKI is shared with pin RC5 on the PIC16F505 and pin GP2 on the PIC12F508/509.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Refer to the “PIC16F505 Memory Programming Specifications” (DS41226) to determine how to access
the Configuration Word. The Configuration Word is not user addressable during device operation.
FOSC/4 OSC2/CLKOUT
(GP3/RB3)/MCLR/VPP
MCLR Reset
S Q
MCLRE
R Q
WDT Reset
WDT Time-out Start-up Timer CHIP Reset
Pin Change (10 μs or 18 ms)
Sleep Wake-up on pin Change Reset
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
V1
VDD
MCLR
DRT Time-out
Internal Reset
Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
0
M Postscaler
Watchdog 1 U
Time X
WDT Time-out
Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
N/A OPTION(1) GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
N/A OPTION(2) RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer. – = unimplemented, read as ‘0’, u = unchanged.
Note 1: PIC12F508/509 only.
2: PIC16F505 only.
R2 40k(1)
TABLE 7-8: TO/PD/(GPWUF/RBWUF)
STATUS AFTER RESET
GPWUF/
TO PD Reset Caused By
RBWUF Note 1: This brown-out circuit is less expensive,
although less accurate. Transistor Q1 turns
0 0 0 WDT wake-up from Sleep
off when VDD is below a certain level such
0 0 u WDT time-out (not from that:
Sleep) R1
VDD • = 0.7V
0 1 0 MCLR wake-up from Sleep R1 + R2
0 1 1 Power-up 2: Pin must be confirmed as MCLR.
0 u u MCLR not during Sleep
1 1 0 Wake-up from Sleep on pin
FIGURE 7-14: BROWN-OUT
change
PROTECTION CIRCUIT 3
Legend: u = unchanged
VDD
Note 1: The TO, PD and GPWUF/RBWUF bits
maintain their status (u) until a Reset MCP809
Bypass VDD
occurs. A low-pulse on the MCLR input VSS Capacitor
does not change the TO, PD and VDD
GPWUF/RBWUF Status bits. RST
MCLR
VDD
33k PIC16F505
PIC12F508
Q1
MCLR (2) PIC12F509
10k
40k(1)
To Normal
Connections
External
Connector PIC16F505
Signals PIC12F508
PIC12F509
+5V VDD
0V VSS
VPP MCLR/VPP
CLK GP1/RB1
VDD
To Normal
Connections
Description: If bit ‘b’ in register ‘f’ is ‘1’, then the Description: The W register is cleared. Zero bit
next instruction is skipped. (Z) is set.
If bit ‘b’ is ‘1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOP is executed instead,
making this a two-cycle instruction.
5.5
(PIC16F505 only)
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0 4 8 10 20 25
Frequency (MHz)
LP
XT
Oscillator Mode
INTOSC
EXTRC
EC(1)
HS(1)
Frequency (MHz)
Legend:
pin CL CL = 50 pF for all pins except OSC2
15 pF for OSC2 in XT, HS or LP
VSS modes when external clock
is used to drive OSC1
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3
4 4
2
Q4 Q1 Q2 Q3
OSC1
I/O Pin
(input)
17 19 18
20, 21
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
FIGURE 10-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING –
PIC12F508/509/16F505
VDD
MCLR
30
Internal
POR
32 32
32
DRT
Timeout(2)
Internal
Reset
Watchdog
Timer
Reset
31
34 34
I/O pin(1)
Note 1: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.
2: Runs in MCLR or WDT Reset only in XT, LP and HS (PIC16F505) modes.
T0CKI
40 41
42
1,000
4 MHz
800
IDD (μA)
Typical
600 4 MHz
400
200
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
3.00
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
2.50 (-40°C to 125°C)
Max. 5V
2.00
IDD (mA)
Typical 5V
1.50
1.00
Max. 3V
0.50 Typical 3V
0.00
5 10 15 20 25
Fosc (MHz)
FIGURE 11-3: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Typical
(Sleep Mode all Peripherals Disabled)
0.45
Typical: Statistical Mean @25°C
0.40 Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
0.35
0.30
0.25
IPD (μA)
0.20
0.15
0.10
0.05
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
10.0
IPD (μA)
8.0
6.0
4.0
Max. 85°C
2.0
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
5
IPD (μA)
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
25.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
20.0
Max. 125°C
15.0
IPD (μA)
10.0
Max. 85°C
5.0
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 11-7: WDT TIME-OUT or DEVICE RESET TIMER vs. VDD OVER TEMPERATURE (NO
WDT PRESCALER)(1)
50
Typical: Statistical Mean @25°C
45 Max. 125°C Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
40
Max. 85°C
35
30
Time (ms)
Typical. 25°C
25
20
Min. -40°C
15
10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Note 1: Device Reset Timer (DRT) values are for case of Reset of power-up. Table 7-6 shows DRT values for
the case of other types of Reset events.
0.8
0.4
0.2
Min. -40°C
0.1
0.0
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
IOL (mA)
0.45
0.25
VOL (V)
Typ. 25°C
0.20
0.10
0.05
0.00
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
IOL (mA)
3.5
3.0
Max. -40°C
Typ. 25°C
2.5
Min. 125°C
2.0
VOH (V)
1.5
0.5
0.0
0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0
IOH (mA)
5.5
5.0
Max. -40°C
Typ. 25°C
4.5
VOH (V)
Min. 125°C
4.0
3.0
0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0
IOH (mA)
1.7
Max. -40°C
1.3
Typ. 25°C
VIN (V)
1.1
Min. 125°C
0.9
0.7
0.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
4.0
VIH Max. 125°C
Typical: Statistical Mean @25°C
3.5 Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
VIH Min. -40°C
3.0
2.5
VIN (V)
2.0
VIL Max. -40°C
1.0
0.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
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Note: In the event the full Microchip part number cannot be marked on one line, it will
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for customer specific information.
* Standard PIC® device marking consists of Microchip part number, year code, week code, and traceability
code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in QTP price.
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Revision C (03/2007)
Revised Table 3-2 Legend; Revised Table 3-3 RB3 and
Legend; Revised Table 10-4 F10; Replaced Package
Drawings (Rev. AN); Added DFN package; Replaced
Development Support Section; Revised Product ID
System.
Revision D (12/2007)
Revised Title; Operating Current; Table 1-1 added DFN
and revised note; Revised Section 3.0, last paragraph;
Revised Figure 4-4; Revised Table 4-2 (FSR); Revised
Register 7-1 and Register 7-2; Revised Section 7.2.2;
Revised Table 7-3, Note 2; Revised Table 7-4 (FSR)
and Note 2; Deleted Section 7.3.1: External Clock In
and Figure 7-6; Revised new Section 7.3.1; Replaced
TBD with new data in Tables 10-4 and 10-5; Revised
Tables 10-1 (Industrial), 10-2 (Extended), and Tables
10-1 (Industrial, Extended) and 10-2 (Pull-up Resistor
Ranges), 10-3, 10-4 and 10-6; Revised Figure 10-1,
Figure 10-2; Section 11.0, Added Char data; Revised
Package Marking Information; Revised Product ID
System.
B O
Block Diagram Option Register................................................................... 22
On-Chip Reset Circuit ................................................. 48 OSC selection..................................................................... 39
OSCCAL Register............................................................... 24
Timer0......................................................................... 33
TMR0/WDT Prescaler................................................. 37 Oscillator Configurations..................................................... 42
Watchdog Timer.......................................................... 51 Oscillator Types
HS............................................................................... 42
Brown-Out Protection Circuit .............................................. 52
LP ............................................................................... 42
C RC .............................................................................. 42
C Compilers XT ............................................................................... 42
MPLAB C18 ................................................................ 64 P
MPLAB C30 ................................................................ 64
PIC12F508/509/16F505 Device Varieties ............................ 7
Carry ..................................................................................... 9
PICSTART Plus Development Programmer....................... 66
Clocking Scheme ................................................................ 14
POR
Code Protection ............................................................ 39, 53
Device Reset Timer (DRT) ................................... 39, 50
Configuration Bits................................................................ 39
PD............................................................................... 52
Configuration Word ............................................................. 41
Power-on Reset (POR)............................................... 39
Customer Change Notification Service ............................. 101
TO............................................................................... 52
Customer Notification Service........................................... 101
PORTB ............................................................................... 29
Customer Support ............................................................. 101
Power-down Mode.............................................................. 53
D Prescaler ............................................................................ 36
DC and AC Characteristics ................................................. 79 Program Counter ................................................................ 25
Development Support ......................................................... 63 Q
Digit Carry ............................................................................. 9
Q cycles .............................................................................. 14
E
R
Errata .................................................................................... 3
RC Oscillator....................................................................... 43
F Reader Response............................................................. 102
Family of Devices Read-Modify-Write.............................................................. 31
PIC12F508/509/PIC16F505.......................................... 5 Register File Map
FSR ..................................................................................... 26 PIC12F508 ................................................................. 17
PIC12F509 ................................................................. 17
I PIC16F505 ................................................................. 17
I/O Interfacing ..................................................................... 29 Registers
I/O Ports .............................................................................. 29 Special Function ......................................................... 18
I/O Programming Considerations........................................ 31 Reset .................................................................................. 39
ID Locations .................................................................. 39, 53 Reset on Brown-Out ........................................................... 52
INDF.................................................................................... 26
S
Indirect Data Addressing..................................................... 26
Instruction Cycle ................................................................. 14 Sleep ............................................................................ 39, 53
Instruction Flow/Pipelining .................................................. 14 Software Simulator (MPLAB SIM) ...................................... 64
Instruction Set Summary..................................................... 56 Special Features of the CPU .............................................. 39
Internet Address................................................................ 101 Special Function Registers ................................................. 18
Stack................................................................................... 25
L Status Register ............................................................... 9, 20
Loading of PC ..................................................................... 25
T
M Timer0
Memory Organization.......................................................... 15 Timer0 ........................................................................ 33
Data Memory .............................................................. 16 Timer0 (TMR0) Module .............................................. 33
Program Memory (PIC12F508/509)............................ 15 TMR0 with External Clock .......................................... 35
Program Memory (PIC16F505)................................... 16 Timing Diagrams and Specifications .................................. 73
Microchip Internet Web Site .............................................. 101 Timing Parameter Symbology and Load Conditions .......... 73
MPLAB ASM30 Assembler, Linker, Librarian ..................... 64 TRIS Registers ................................................................... 29
MPLAB ICD 2 In-Circuit Debugger ..................................... 65
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator ...................................................... 65
Z
Zero bit .................................................................................. 9
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10/05/07