POSTAL udy Course 2018 Computer Science & IT Objective Practice Sets el pms] Contents SI. Topic Page No. 4. Basies of Digital Logie 2 2. Boolean Algebra and Minimization Techniques 6 3. Logic Gates and Switching Circuits 12 4. Combinational Logie Circuits 8 5. Sequential Logie Crouts 23 6. Registers a 7. Counters 2 MADE ERSY India Bese Instiote for ES GATE & PES oa aan eaeiesiT roy Q4 Let 2,4, ; ...a;4) be the binary representation of an integer b. The integer bis divisible by 3 (@) The difference of alternates sums, ie. (a+ ayt.) ~ (8,+2y+...) is divisible by 3 (©) The number of ones is divisible by 3 (©) The number of ones is divisible by 3, but not by 9 (@) The number of zeros is divisible by 3 Q2 Convert (3121.121), to base 3? (@) 10022100 (b) 22001.100 (©) 22001101 (a) 10022.110 3. (10110011100011110000), in base 32 are (@) 2214716 (®) 1192831 (o) 11976 (@ 11142316 G4 (22), +(101),~ (20), = (x), +(4),., where x > 4 The value of x is (a) 6 (4 © @e Q.5 The hexadecimal representation of (667), is @ (Ay, (0) (078), ©) O70, (0) GA, Q.6 Convert 10010011 (BCD code) into binary. The value of obtained in binary will be equal to, in decimal Q.7_ Inaparticular number system having base 8. (V4i)g = 5,9- The value of ‘" is Q.8 The number of 18 in the binary representation of (@ * 4096 + 15» 256 + 5 + 16 + 3) are @s 9 © 0 12 Q9 The decimal value 0.25 (@) is equivalent to the binary value 0.1 ore Era Basics of Digital Logic (©) is equivalent to the binary value 0.01 (€) is equivalent to the binary value 0.00111 (@) cannot be represented precisely in binar Q.10 The binary equivalent of the decimal numb: 0.4375 is, (@) 00111 (©) 0.1011 (©) a1100 (@) 0.1010 Q.11 Two numbers ~48 and -23 are added using 2's complement. The 2's complement of the result Using 8 bit representation is. (@) 10141001 (b) 01000111 (© o1t01010 = (a) 11100111 Q.12 A number Nis stored in a 4-bit 2% complement tepreseniationas alalals] E-bit register and alter a fow itis copied into a operations, the final bit pattern is [asTas @ 1 [@ [1 ‘The value of this bit pattern in 2's complement representation is given in terms ofthe original number in Nas 2Ne1 (b) 32a,-2N-1 (8) 2N+t Q.13.4 number in 4-bit two's complement representation is X, X,X, X,, This number when stored using 8-bits wil be @) 0000 XXX, X WNT %GX XH ©) KKK (©) yRsoXsXoXoXMo Q.14 What range of decimal integers can be represented by mbit tw representation? ‘8 complementfa MADE EASY (@) -(2")t0 + (21-1) (©) ~(2" + 1)t0+ (2-1) (©) -(2")t0 + (2-1) 8) -2™)10+ 21) Q.15 The greatest negative number which can be stored in computer that has &-bit word length and uses 2's complement arithmetic is (@) 286 (b) -255 (©) -128 (@) -127 Q.16 Result of the subtraction with the following unsigned decimal numbers by taking the 10's complement of the subtrahend. 1753-8640 (@) 3113 (©) 10393, (c) -6887 (@) 3113 Q.17 Number (+46.5),.canbe represented asafoating point binary number with 24 bits. The normalized fraction mantissa has 1 bits and the exponent has 8 bits. The mantissa of the number is. (@) 0101110100000000 (©) 1001410100000000 (©) 0000011000000000 (@) 0000000001011101 sics of Digital Logic 1 @ 2 © 3 @ 4 @ 5. 12, @ 13, ©) 14 @ 15. © 16. 21. @ wwnmadeeasy.in Postal Study Course BIE] [MADE Ensy Digital Logic | .18 Given that (E08),, compliment of Yis (@) 244 (0) 6264 (ABA) = ¥. The radix 8's (o) 1514 (@ 3251 Q.19 4-bit2's complement representation of a decimal number is 1000, The number is .20 Which of the following statement is incorrect for the range of n bits binary numbers? (@) Range of unsigned numbers is Oto 2"— 1 (©) Range of signed numbers is -27-* + 1 to antag (©) Range of signed 1's compliment numbersis -2r4 4 110201 (@) Range of signed 2s compliment numbers is =20 "tot 4 Q21 Let A= 1111 1010 and B= 0000 1010 be two B-bit 2s complement numbers. Their product in 28 complement is (a) 11000100 (b) 1001 1100 © 19100101 (a) 11010101 @ & © 9% (>) 10 @ 11. (©) 17. ©) 18 (@ 20. Objective Practice Sts& coormpene tainennttt EXSEIIELY Basics of Digital Logic 1 aca man ie (@) Consider 10101011 % % % % % % A & Number of 1 in even places = 1 Number of 1 in odd places = 4 The diference (4 1)is dividable by 3 binary number 10101011 = 171 (decimal no. is divisible by 3) (c) 3121 = 3x 4341x424 2x 4h e 1x4? = 217 O12t=tx4t42x 4241 x42 = 0.990 aan a a —|o 2001), 0.9003 = 1.17 0.17x3 = 051 051 x3 = 183 (0.101 (22001.101), $0 (217.990),5 @ To convert to base 8, we group in 3's, because 2-8 To convert to base 16, we group in 4's because 2216 To convert to base 32, we group in 5's because 28 = 32, Grouping in 88, from the right we getthe answer. So 10119 01110 O0111 10000 (a) (22), + (101),~(20), = (04 + (st 4x24 2x4 41x38 +04 1x3-[5x2+ Opa s ext (1x4 yu = 842+941-[W]art4 = 10+10-10=x44 3 ax44 3 x26 fgimabe Ensa famnAce ersu (a) Octal number 657, Binary representation of 657, 00041011114 Hexadecimal representation of (657), = (1AFy (93) fs 10010011 + 101105 9) (6) squaring both side, (ai)? = (5)? A, = Bp (4B+ io = (25ho = B=6 (c) 3°4096 + 18256 + 5°16 +3. As we can see that 4096 = 2'haveone 1 256 = 2haveone1 16 = 2¢have one 1 Hence, they only remain as same in number of ‘Vs and when any other number is multiplied by themselves, the number of 1's is only the count of the number of 1's in other mutiplicant, 3 - on 15 - 1111 5 - 0101 3 - on - Correct option is (c) 10 1's )- (b) (025), 025 x2 x 056 TT 0 (0.25),0=(0.01}, www.madeeasy.in10. (a) (04375), i 2 2 2 Cay 1 i t ° ' 1 0) 080 x2 (0.4375},, ={0.011 1, FD Hence (ais corectooton 1 1 11. (b) (489+ C28)9 ~48 "17010000 -23__()11107001 7i___ 10117001 2s complement of a 2's complement number is. the number itself Here answer -71 is in 2's complement. 2s complement of 10111001 is01000111 12. (a) Given number is [4 [a [a [a] in 2's complement form. We know that in2's complement form. Ifwe copy MSB any number of times the number remains unchanged, $0, 838 a, = 8; 2 8,8, dy = N When we left shift a number by 1 bit then itis muitiped by 2, 50, 2,52, a, a,0 = 2N Now, a, a4 2, 4,041 =a, aga a, 1 =2N41 13. (0) Suppose we have to represent a number +5 and Bin 2's compiement representation using &-bits 00000101 -8= 11111011 (Using 2s complement) From the above example we conclude that when X, XX, Xp number will be stored in 2's complement method using 8-bit will be X, XX, XX XXX wuwmadeeasy.in Postal Study Course RUE] 16, 17, 18. 19. 20. 21. ig mabe easy Digital Logic | (c) 1753 +1360 “BIS + 10% complement -6667 (a) As 485 = (1011101), 0101110100000000 90000110 mantissa exponent (c) (€08),,-(ABF),, = (340), (340), = (001101001100), 1514), 7scompliment = (6263), @’scompliment = (6263), + 1 = (6264), (8) 1000 MSB is 1 s0, -ve number fe 2s complement for magnitude. ont (c) Range of signed 1's compliment number is 20-14 Hott (a) A= 11111010 Sinee MSB is 1 hence no. is negative Le. - (00000110) 00000110) A=46 B = 00001010, there is no. 2's complement representation for positiveno, B = +10 AxB = 10x(-6)=-60 Binary representation of -60 = 00111100 Now take 2's complement = 11000100 Objective Practice Setsa4 a2 as as YA Boolean Algebra and ores Minimization Techniques ‘A Boolean expression (A,B, Cs represented i inits pictorial form as shown below. The function aa Cee fA, B, Chis 1 a an o}t = ® of = : ife 14] 4 (@) BC +80+80 () BD+H84CD (a) (AC+ AC +B) (co) BD+ 80 +CD (d) BD+BD'+CD (©) (BA+oya+ oy] Q.5_ The switching expression corresponding to KA, BCD) = ¥(0,3,4,7.8) and ¥(10,14 12,1 where d : don't care (@) (aBc+ ABC) (@ CD+86 —() Coo The maximum number of Boolean expressions ae a that can be formed for the function Ax, y, 2) @:6 For the following Boolean equation, the value of A, Band C wil be AB+AC=1, AC+B = 0 © [A+e+CyA+ 8+] 2 satistying the relation f(x,y, (9,2) is (@) 441 ©) 1,10 @ 6 (b) 256 © 0.0,1 (@ 0,0,0 © () 72 oe e Q.7 The kmap for the boolean function F of 4 Match column-| with columnIt boolean variables is given below where A, B, Column Column C are don't care conditions. What values of A, (a) (488)8(89Q) 1.(40Q 8, C will result in the minimal expression? (AB AC+ EC BIAFBIOIA+O wz 0001 1 10 (©) (Ao B0(BOO) 3.ABe AC oo] 0] 0 (0) A¥(80Q) 4(A@O) of of 4 5. AC @ AC alate Codes wl o|o AB Cc oD | @4 3 1 2 (@) A=B=C=1 (0) B=C=1;A 3 4 1 2 (©) A=C=1;B=0 d) A=B=1;C=0 2 3 1 2 Q8 The well known fibonacci numbers are 11.23 @4 3 5 2 58 13... Let the boolean variables a, b and o gether represent a 3-bit non-negative binary number (that is, not in 2s compliment representation) Which of the following functions implement the K-map shown below?(a mMaoe EAS Let c be the least significant bit (that is, write the number as abc). Let F be a boolean variable that indicates whether the number represented by a, b, cis a Fibonacci number. (F=1 ifitis fibonacci number and 0 otherwise), Determine the minimized sum of product formula for F. (a) Feac+be (oe) Fedbede () Faab+ be (@) none of these Q.9 The Boolean Expression B@E is a simplified version of expression: ABE + BODE + BCDE + ABDE + BODE + then which of the following choice is correct 1. don't care conditions don't exist 2. don't care conditions exist 3. d (16, 18, 20, 23, 27, 29) is the set of don't ‘care conditions 4. d( 16, 20, 22, 27, 29)is the set of don't care conditions (@) tony (©) 2and 4 only DE (b) Zand only (6) Data insufficient Q.10 Boolean expression A+B 40+ A+B+C + AB +C-+ ABC reducesto @a (bo) 8 oc (d) A+B+C Q.11 The minimized expression for the given K-map (X: don't care) is 4a oo oso eo] o[o]+]1 oto |x] x 1 [x ole x[x[a x[alx ehh (@) Asie (b) B+ AC © C+4B (9) ABC Q.12 The biack box in the below figure consists of a minimum complexity circult that uses only AND, OR and NOT gates. The function fix, y, 2) = 1 whenever x, y are different and 0 otherwise. tn addition the 3 inputs x,y, Znever contain the same value. Which one Of the following equations leads to the correct design for the minimum complexity circuit? ae cceid 2018] (]MADE ERsy Digital Logic | 7 y— Black Box (a) xy 4x7 (xyz +ayz 2.13 Find the correct function forthe following kmap ac 20, oo 1 10 oo or 1 10 wl s}ofo]+] m)z]o]o]7 Moya) xtyz @xytyerz (@) ACE+BCE+ACDE (0) CE+8CE+CDE (©) Ae+E+BCE (@) CE+CDE+8CD Q.14 Minimal POS obtained trom Y= Em(0, 2,3, 6,7) +d (8, 10, 11, 15) (@) AC+8D (©) (AC+ 8B) (b) A(C-+By8+C) (d) None of these Q.16 IY = ABO+ AB+8C then dual and compliment of Yare respectively (@) (ABC +AB)-(8+C) and [Gra+0)+ A+ ay] 2c (&) [(4+8+0+A4-8)]-BC and [asc+ @+B)]-B6 (© [@¥B+O)+AB)]-6+0 ana (ABC + AB)-BC (o) [7B0+4+B] BC ana [\4+8+0)+28]-20 Q.16 The logic function f = (e-7]# CF y) isthe same as (@) fexey (0) f=xoy (© fexty (d) None of these Objective Practice Sets [J| Computer Science & IT aes 2o8] GIMAOE EASY .17 The boolean expression A + BC equals Q.20 Consider a four variable K-map shown below: (@) (A+B)(A+C) (0) (A+ B)(A+ 0) oo no (©) (A+ 8) (A+C) (d) None ot these oo} 1} 4 1 | Q.18 The SOP form af given function 7 a ] y=(A+B++0)-(A+8) is may date wl] | [a ABCD + AB it ‘The total number of all possible Non Essential Prime implicants (NEPIs) is, @ © ABCD + AB (©) y= 7aCB+ AB @6 5 (8) y= ABC + AB 4 @3 Q.19 Which of the following functionsimplements the 21 Consider a 3 variable function 4P, Q, A) having Kamaugh map shown below? min terms representation as, Q AP, Q, Ry = Em (3, 5,6, 7) Se How many minimum NAND gates required to ealefetele implement above expression? i @ 2 (0) 3 nfotafrto wfelt[afo os @6 @ AB+CD (0) DIC+A) (©) AD+AB ——(@) (C+ DG + DK A+B) EXE boi Functions We 2 Oe oe ye CO OC On 8G) 6. oC) 10. (b) 11. @ 12 @ 13 &) 14 () 15. @ 16 () 17. &) 18 @ 19. (b) 20. (0) 21. (@) Logie Functions 1. 272 [Ray ee Representing the graph in K-map 22 8) Yaw 4A 8. C)= B+ AC+AC wR os a ta8.0-(6raesac) eH too, _fetteroeet +s DED §4.8,.0)=[BArGATO] volte [ras |_ foseroor 2. (a) tro femeroort For every combination of, zthe function value remains same for input 5.2 Effectively there are only four rows forthe truth table of the function x,y. 2) -. Total Boolean expressions possible is 2* = 16. (ZF objective Practice sets §g MADE EASY wir madeeasyinG2MADE EASY PRES 2078] 3. (a) (Aone(Be0) = (A@BY\B@C)+(A@B\BOC) = (AB + ABKABC + BC)+(AB+ ABYBC+ BC) = ABC + ABC + ABC + ABC = AC(B+B)+AC(B+B) (AC+AC)=ASC (a) matches with (4) AB® AC + BC= AB@AC This is concensus law in XOR algebra, (®) matches with (3) (A+8)9(A+0) Option (a) matches with (2). A+ (BOC) 4 (c) co BS x fo 00] 0 co of lt t ny = &+co=ced (ce) From AC+B from AB+AC = 1 and B=0 38 AC=1=A=Oand C= Thus(A, BO) (0,0, 1) 10, Qamade Easy Digital Logic | 7. (@) For minimal expression Zoo 1 1 10 wr oof of o [ao al olaiio " ° 10 ° For A= eT Itwall give the minimal expression. (b) Fibonacci numbers are: 1, 1,2,3,5,8. Fibonacci numbers with 3 digits in its binary representation are 1 001 2 010 3 011 5 104 using K-map we can get minimized SOP formula, (c) @\ DE De oe oF A, Bex [1] a4 1 Bo| x x] aft 1 ecl_[x[4 scl [a[4 a{_ | 1[x a|_ [ah] Only (c) option satisties the required condition, (b) AvB+O0+ Av B+ C+A+B4C+ABe = A.B-C+ABC+ABC+ABC = AB(E+C)+AB(C+C) B+ AB = BIA+A)=8 fusing x +2 =] Objective Pace Sts| Computer Science & IT 11. (a) 4a 3X00 or | ot ape why The expression is Y= A+BC 12. (a) xy 2 thy.2) Oa Oogiee 10 0ort 1 So, Fisy.2) = HZ + Rye + 472+ x92 Hy +2) +97 +2) = HtW 13. (b) Bop ot 1 30 ps8 op 0 of en ods al a 0 wd a ace sat) 4 +1) [tee F= CE+CDE+80E 14. (b) 48 o_o 110 co] + [0 a wl 1] 1folal = Aic+5y6+c) 19. (0) Y= ABC+AB+8C Dual of ¥ Ya Gra O- AFB) 6+0) = [FBO AB] 8+0) Objective Praciee Sets 16. 17, 18, 19, 20. (mabe Easy ggmMApE ensy Compliment of ¥ (ABC-+AB) +80 = (ABC + AB). BC = (ABC + AB) -BC ) = EWE &y)-Ey) = G+ y(e+7) = ay tey or (x-7)+(F-y)=@, complement of @is. © ©) A+ BCrepresents the distributive law which can be expanded as A+ BC=(A+B)-(A+C) (a) (AvB+0+0) (A+B) = (A+B+C+D)++B) = ABCD+A (b) Solving the given k-map we have () wo om ©Group-() > NEPI + BB Group) »NEPI> AB Group) + NEPI + ABC: Groupv) +» NEPI-> ACD Group{v) > NEPI> ABD Group-(vi) + NEPI > BCD Group-(vil) + NEPI> ABC wurumadeeasy.in 24 [Mabe Easy G3MBBE SASS MOSM 2075) Digital Logic | (@) Realization of 'Y’ by using only NAND gates is given as below: vee = (PRYPQ+ QR) PR+FO=OR PR+PQ+QR -. Minimum # NAND gates required = 6. Objective Practice Setsa2 If propagation delay of NOT gate is 10 nsec, AND gate is 20 nsec and X-OR gate is 10 nsec. If Ais connected to Vagat t= 0, then waveform for output Vis vt oe bes e, PoE t $b ns ¥ o4 : rT) ” { @ 4 —-—) ee The circuit shown below is to be used to implement the function Z= fA, 8) = A+B.The values of fand J are as as a6 reece Logic Gates and Switching Circuits (@) 1=0andJ=8 (©) 1=BandJ=1 () f= 1andv=8 (@ 1=BandJ=0 fA, 8) =T1M(@, 1,2 term) (@) NORgate (©) NAND gate (©) OR gate (@) a situation where output is independent of input 3) represents (Mis The minimum number of NAND gates required to implement the boolean function ABCDE + ABCD + ABC + AC + Cis (@) 0 4 4 7 ‘The Boolean expression corresponding to the given circuit Le (@) isindependent of A (b) isan inconsistency (@) isa tautology (@) none of these The output fof the given circuit is @o (AMADE ERSY Q.7_ The given mutipiexer diagram can be expressed In canonical SOP form. Ifa function is defined as flw, x, y, 2) then what will be the number of rminterms in canonical SOP form? Do pA 8 Consider a 7 input EXNOR gata shown inthe Foueboow i—\ oe ' : —/, The seven not EXNOR gate ets 2 (@) Oddfunction —(b) Even function (6) Identity function (a) Both (b) and (c) Q.9_ Minimum number of 2-input NOR Gates required {to implement the function. Q.10 Which of the following expressions is not t=As[B+C(8+ AC) equivalent to #7 (a) xNAND x (b) xNOR x (© xNAND1 (d) xNOR 1 Q.11 A positive level logic digital circuits shown below D=p>- The negative level ogic digital crcuttfor the given circuit is @ aaa L>- (6) > ‘ostal Study Course PRE] (gmnoe Easy Digital Logic | (6) All of these Q.12 Consider Y= A@A@ASASASASAGABA then ¥is equivalent to: (@) 10RA () 1NOR A (0) AEXORO (@) AANDA Q.13 Identity the logic function performed by the circuit shown in the given figure ey) y > (©) exclusive NOR (a) NOR (@) exclusive OR (©) NAND Q.14 The following circuit can be represented as: @c ©) 14.8, (@ aeRc @1 BO, 1, 2,8, 4,5,6,7) @.15 Consider the logical functions given below. 1A, B, C) = 22,3, 4) ({4, 8, C)=n(0, 1,3. 6,7) f f. & If Fis logic zero, then maximum number of possible minterms in function f, are __ 1 Q.16 Consider a 3-bit number A and 2 bit number B are given to a multiplier. The output of multiplier ig realized using AND gate and one bit full adders. If minimum number of AND gates required are Xand one bit full adders required are Y, then X+ Y= a Multi c 5 Mater | Objective Practice Sets© | Computer Science & IT Q.17 For the circuit shown in figure the Boolean expression for the output Yin terms of inputs P, Q, Rand Sis Opp! aoe @) PrO+A+S () PORS © P+B)+F+3) (P+Q(R+9 Q.18 Astate diagram of alogic which exhibits a delay in the output is shown in the figure, where Xis the do not care condition, ox, 101 The logic gate represented by the state diagram is (@) XOR (©) AND Q.19 The output Y in the circuit below is always "1" () oR (@) NAND (@) two or more of the inputs, P, Q, Rar (©) two or more of the inputs P, Q, Rare "1" (©) any odd number of the inputs P, Q, Ris (6) any odd number of the inputs P, Q, Ris * Q.20 A digital circuit which compares two numbers Ay Ay A; Ay, B, By 8, 8, is shown in figure. To get output Y= 0, choose one pair of correct input numbers (EY objective Practice Sets Postal Study Course EUHE] G3 MADE Ensy MADE EASY BA BA BA BA Hao : D 0 {@) 10101010 (@) 0101, 0101 (©) 010,010 (d) 1010, 1011 Q.21 The circuit given in figure is to be used to implement the function Z=/(A,6)=A+B What are the values that should be selected for Tand J? q J A @i=0u=8 OT B @i=BJ=1 @T Q.22 Consider the circuit diagram given below ~ Dp. Em, 1,2,3) Em(O.2, 4,6) Ifthe boolean function f,is dual off, then the boolean function ‘fis @ Em, 1,2,3,4,5,6.7) (©) Em(0, 1,2,3,6,7) ©) Em, 1,2,3,7) (@) None of theseMADE EASY Cia Logic Gates and Switching Circuits 1% 2%) 3 @ 4 @ 5 11. @) 12.) 13. ©) 14 @ 17. 22. (a) Postal Study Course PUHE] @ 6 @ 7 ® & @ 10. @ (b) 18. () 19. () 20. @) 21. Oo) PEDEEIIIE oa%c cates and switching circuits 1. (b) 10ns = Minimum number of NOR gate required =9 (d) A 8 10. Letx = 0 then ONOR1= O#¥ Lets = 1 then 1NOR1 = O2¥ Hence, (d) is the reauired option. (a) " ‘The negative level logic citcuitis a dual circuit of positive level logic circuit, Using dual logic gates, it can be shown that the and (c) are all same in circuits in option (a), (t operation. Objective P Sets Postal Study Course BXEE| G3 mane easy 12. (b) Y= ABABA) BIACA OABA BABA) Note: A@A= 0 A@A=1 Y= A@0@0@0@0=Ae0 Hence Y= AEXORO Hence (b) is correct option. 13. (b) {sy fx 9) Ew CFM = rey y y= T= iy Therefore the above circuit performed exclusive NOR gate. 14. (a) From the given diagram we can see that Property: CC= COC=1 18. (6) f(A, B, ©) = 22,3, 4) if, B.C) = w(0, 1,3, 6,7) = 312, 4,8) For function fio be zero: (A, B,C) = [F(ABLC) 9 EA. B, Cj = £0, 1,3, 5,6, 7) Maximum minterms possible are 6 16. (9) Az a a a 8 _ bb AxB= ab ab ab ba ba ba | ba, (@b.+abjab,* bala, aq 6 GG, MADE EASY www.madeeasy.inMADE EASY PRA 2078] Number of AND gates required (X) = 6 24. (b) Number of one bit full adders required (Y) = 3 X+Y = 64+3=9 id i a > 17 % ‘As we can see clearly output must be A+B - which can be abtained only by making J = B andi=1 AB Q a 7 > 0 0 7 So, that J+ A=1 and f =(A+8)1 +8 la Hence (b) is corect option 1 0 1 22, (a) it o f= Fa+F GOR) if any one ofthe input is zer0, outputs ogic 1 _— Otherwise output is logic ‘0’, which represents = fatty + Ole) the NAND gate. Fyt ty tthe +t 19. (b) fy hd Take two or thee input’ then we always get f, = 1m (0.2, 4.6) * i Fg = Em(1,3,5,7) Take two or three input zero then we always get 0’ hence option ‘bis true and output f= Em(1,3,5,7) +Em(4,5,6,7) + Y = PQ*PR+AO 3:0 (0,2, 4) Em (0,1, 2, 3, 4, 5, 6, 7) 20. (d) in EX-NOR gate, if odd number of inputs are 1 tore tort, a9 then outputs zero, wwwimadeeasy.in G@MADE EASY Objective Practice Setsaa a2 as a4 Find the simplified boolean expression fx.y.z.W) forthe below 8 : 1 MUX we i, oy tls —! ol ot? 1) Pn sety (@) syexztaweyw ) x7 + pws 32432 (c) Fy +az+20+ yw (0) sync 2+ yw If-x number of 4 x 1 multiplexers, y number of 2x 1 multiplexers and z number of 16 x 1 multiplexers are needed to impliment a 128 x 1 ‘multiplexer, then which of the following can be value of (x + y + 2)? (Hint: Use exactly two16 x 1 multiplexers ie., 2=2) @) 5 () @ (©) 10 (a) Allof these For ambit carry look ahead adder the gate count (0? +9n) 2 (? +6n) 2 Find the boolean expression Bin the digital circuit given bek (o) () ote [+ 0 (oiterence) subvacter st a (e-0)-0 | + aaron) as as a7 as oa Combinational Logic Circuits (@) ab+bo+a0 (©) ab+bo+ca (©) ab+Bo+ca (@) ab bo+ca AA 1-bitfull adder takes 20 ns to generate carryout bit and 40 ns for the sum bit. What is the maximum rate of addition per second when four ‘-bitfull adders are cascaded? @ 0 (©) 125x107 (©) 625x108 @ 0 ‘The Boolean expression f(a, b, c)in ts canonical form for the decoder circuit shown belowis (a) mM(4,6) (©) Em(4,6) (©) Bm(0, 1,2,3,8.7) (@) TMC, 1,2,3,5) Consider the combinational circuit below has TT fee ol | | oe ee py ! : “ The output of the combinational circuit How many half adders are required to realize the following 4 functions? f=A@Becag ato an a1 f= ABC +(A+B)C 4, = ABC @ 2 4 3 5 Let x,, ¥, and 2, are the sign bits of a number x, y and result z. The overflow condition if C,. be the carty into sign bit (8) BVeCn2 + HIE y-2 (0) BYeCoa + %VeCr-2 () 5 VeCn2+ MY En-2 (@) none of these ‘A combinational circuit outputs a digit in the form of 4 bits. 0 is represented as 0000, 1 by 0001... 9 by 1001, A combinational circuit is to be designed which takes these 4 bits as input and output 1 if the digit > 5 and 0 otherwise, if only AND, OR and NOT gates may be used, what is the minimum number of gates required? (a) 2 () 3 (4 (5 Minimum number of 2 x 1 multiplexers required to realize the following function f= ABC + ABC ‘Assume that inputs are available only in true and boolean constants 1 and 0 are available, fa) 1 (b) 2 3 7 The circuit shown below converts (Here @ is XOR) tp re | % oO, 0, o (2) Binary to gray (0) Binary to excess 3 (0) Excess Sto gray (2) Gray to binary 4 4) h LAS 2018] Digital Logic | 4 Q.13 Consider the following multiplexer: o— {0 wuxl-=r S10 ux | h 7 R The value of output function 'g’ is, (@ PO+PR (0) PO+PR (© PR+PO (@) None ot these Q.14 Minimum number of NAND gates required to implement Sum in hal-adder circuit is @ 2 ) 3 4 @s Q.18 The number of full and hait-adder required to add 16 - bit numbers is (@) Bhall-addors, 8 fulladders {b) 1 halt-adder, 15 full-adders (0) 16half-adders, 0 ful-adders (0) 4halt-adders, 12 fulladders Q.16 A4 x 1 muttiplexer is used to implement 3 inout boolean function as shown in the below figure, The F(A, B, Chis = FAB.) @) 0.4.5.6) (0) 2(3.4,5,6) (c) 10, 4,5, 6) (@) 7(3, 4,5, 6) (@mMAbe Ensy Objective Practice Sets KE)| Computer Science & IT Q.17 The circuit below represents function X(A, 8, C, Dyas: h ° 1 he tik of —s ts as | . ABE @) (3.8.9, 10) (0) E(3,8, 10, 14) (©) (0, 1,2,4,5,6,7, 11, 12, 13, 15) (@) (0, 4,2, 4,5,6, 7, 10, 12, 13, 15) Q.18 Consider the following statements. ‘Ad : 16 decodercan be constructed (with enable input) by: 1, using four 2: 4 decaders (each with an enable input) only using five 2 : 4 decoders (each with an enable input) only using two3 : 8 decoders (each with an enable input) only using two3:8 decoders (each with an enable input) and an inverter. Which of the statements given above is/are correct (@ 2anda (©) only (©) 2and4 (@) None otthese Q.19 A3+10-8 decorder's shown below: pe 7 |, bes bs wow —2 8 output a b—2 abi Enable Signal Allthe output lines of the chip will be high, when all the inputs 1, 2 and 3 w (EY objective Practice sets Postal Study Course FUE] Da MACE EASY (@) arehigh; and G,, Gare tow (6) are high; and G, is low, Gis high (©) are high; and G,, G, are high (@) ate high: and G, is high, G, is iow Q.20 Consider the circuit given below wal yt ans a4 Max [—Y i ~ 1! Doc Which of the following statements is true for ¥. (@ Y= CD+Dc(A+8)+Cos () ¥ =CD+DO(A+B)+CDS (8) ¥=0D+O+C\AFB)+C+ Q.21 The logic function f(A, B, C, D) implemented by the circuit shown below is oy (@) Diae@c) (b) DiAac) (©) DiA@a) (@ DiAeB) Q.22 The function realized by the circut shown infigure is © MADE EASY wwwmadeeasy.inMADE ERSS [RESTS 2078] Digital Logic | *! 2.23 In the folowing circut, S,, S, and S, are select Which ofthe folowing combinations of inputs to lines and X, to X, are input lines. S, and X, are I fy fgand I, of te MUX will realize the sum S? LSBs. The output Yis 1 — —" ocr feet AN & s 5, y (@) indeterminate (6) ASB (© ASB (6) C(ASB)+C(A@B) Q.24 Consider the cirouit given below. .28 Consider a clocked sequential circuit as shown in the figure below. Assuming initial state to be 2, Q=00 For aninput sequence X= 1010, the respective ‘output sequence will be Ifthe decimal input is 92 then ¥, « corresponds i iB eaanascae a DP 0.25 Minimum line to 16 ine decoders required to tsSenex ea ¢ realize @ line 10256 ine decoder are : ay @s 8 ole f ov @ 6 > Q.26 Consider the logic circuit given below. The eal minterms in F(A,B,C,D) are Q.29 A new two input fip flop is designed as shown ao 0 in figure. The table shows the characteristic table ax Lrasco, of the A-Bflipstop, et AS Te 6 ope | o (@) Em(1, 3.5.6.7, 11,14 ‘fo fa (0) Em (6, 7,8, 12, 14, 15) stata (©) Em(G,6,7,8, 11, 12, 14, 18) ——— (@) Em(G,6,7,9, 11, 12, 14, 18) J convinaon- 4 Q.27 Figure shows a 4 0 1 MUX to be used to 8 a Ko implement the sum $of a 1-bit full adder with inputbits Pand Qand the carry input C,, The combination logic is | www.madeeasy.in G3 MADE EASY Objective Practice Sets Fat}| Computer Science & IT © 2.30 A digital circuit which compares two numbers A.A, Ayand 8, B, By is shown in figure YY_Y Y To obtain output ¥ = 1, the valid combination is (@) 010,111 (b) 010, 101 (©) 101,110 (@) 101,011 Q.31 Atwo bit magnitude comparator circuitis shown below. ose [J] : Pia> 8) A Am aa=5, RA< 6) a- The logic circuit for ris Objective Practice Sets Postal Study Course EDIE (@mnAde Easy MADE ERSY t=D5 =D aD a oa) > D>, @ Q.32 Consider the waveforms given below: ouput (2) Ghock—p Lo2 —— om lp tock —$} wunw.madeeasy.inMADE EASY [EEEIEN combinationat Logic circuits 1 @ 2 @ 8 (bo) 4. {o) 5. pes) et et a gee eh 20. (d) 21. (b) 22. (b) 23. (b) 25. 31. (a) 32. (co) Combinational Logic Circuits 1. (@) Funetion table for multiplexer is x y z 7 0 0 0 w | oy] 0 7 7 0 T 0] 0 0 7 1 7 7 0 0 7 i 0 i 7 1 1 a 0 1 1 i 1 Total Four Quads fis yz.) = a taz 2 2. (a) 128 395 4x1 Multiplexers 16% 1 Multiplexers = 1 2x1 Multiplexers wey 47=924142=35 Option (5) and (c) not possible. [Note: Many values can exist for. + y+ 2] “wirwamadeeasy.in Postal Study Course EXHH| (mabe Easy Digital Logic | @ 6 () & © % © 10 &) &) 16 @ 17. @ 18 © 19 (©) 26. () 27. (©) 29. (d) 30. (o) 3. (b) For n-bit carry look ahead adder inst Total #AND gates = MO+D , Total #OR gate: Total #XOR gates Total gate count = “+? nentntn _ (2 +9n) 2 4. (c) Order of subtraction is (ob) - 2 (cele es are | ena Borrow (B) = TBa+cba+Eba+cba be oo or 0 o [aor 1 4 B= Tareb+ba 5. (a) Given, Ty = 20ns T, = 40ns GEGeaTecl 8. cs Computer Science & IT Te, =40ns Tg, =(40+20)ns=60ns | 4 full adders Te, = (60+20)ns = 80 ns {are cascaded Ta, =(80+20) ns = 100 ns Final sum result will take 100 ns Rate of addition 10 toons . (c) The given 3 x 8 decoder is a active low output. Each output represents a maximum term when activated with enable I © = O,then EN=1 The outputs Dy, D,, D, and Dy are active and outputs D,, D,, D, and D, are inactive ‘Output of OR gate is (M, + 1 + M, Cutput of AND gate is (M, M,) = TIM(4, 6) fa,b,0) = TIM4,6) fab) = TIM(, 1,2,3,5,7) fa, b,0) = Xnt4,6) (c) = ABC + ABC =(AB + AB)C (AgBic ABC +(A+B)C = ABC + ABC ABC Single Half Adder —> SSD aesnoe [)—sum=a8 Objective Practice Sets Postal Study Course PXE| Gg maoe Easy OS MADE EAsy To realize the four given equations ABOC=f, aac 10. (b) We need output 1 when input 6, the required boolean expression can be obtained using K- map W820 01 1 10 oo] of ooo TIMP? (ATW wlls Ta [a [ a) y = A+BD+8C = A+B(C+0) oi o = 3 gates are required 14, (b) t= ABc+ABC = AB(C +0) = AB with 2 > 1 multiplexer offense 7 wnwmadeeasy.inG3 MADE EAS! 13. (a) +0P +AP)+0P OUR +OQ\A+P)+OP G\AR + OR = AP +QF)+0P GRP +P (GR +Q)P (+R) (O+0)(Q+ R)=Q+ A) (Q+R)P = PO+PR 14, (c) Expression for sum in half adder is AB+AB=A@Band minimum number of NAND gates requited for EX-OR Gate are “4. Hence correct option is (c). 16. (a) 20. 2 17. (a) ‘The given circuit represents the implementation of four variable function using 8 : 1 MUX here. O as taken as the fourth ifp and A, 8, C act as select lines. ea] oa re] ae Boletstel@leela| i o 11 /Ols[71O/ |] is (weno ]ofoj}o}i}ololo Em(3,8, 9, 10). 18. (©) 4:16 decoder using only 2: 4 decoders: Output Postal Study Course BOIE 4:16 decoder using two 3:8 decoders and an 19. QamAde EASY Digital Logic | inverter: wmf Output (b) Outputs are active low, so all the output lines of the chip willbe high, when chip will be disabled ie, G=Oand G =1 (a) f = DAC+AC) "Objective Practice sets 322. 23. 24, 28. 26. cs | Computer Science & IT Postal Study Course FLEE G3mnAvde Ensy ©) = AGB +805 +0 Fe ABC+ABC+ABC+ABC = AB+B)CD Fs AC(B+B)+AC(8+8) +(a+AoaoB + Ac+ac COA + A\(B +B) F=A@C © = ABCD = ABCD + ABCD Fioating input is accepted by GATE logic gate eee) ica +ABCD + ABCD Hence § MA,B,C,D) = E43, 6,7,.8, 11, 12, 14, 15) co S]5 5 ]¥ bo) 5 1|B/A Tholtfa Sst ‘4 1[ol1|1p 2 7 a[a tht fo Tt] 1 1 Tf fo} 27. (6) Y=A@B For a4: 1 mux (219) 1 Decimal input = 92 A BCD = 10010010 ‘ fol ar Output of Gray code converter ion = 11011011 | | Y, corresponds to J, with (S,,...S,) is 11011011), AB 19 Fe1,AB +1,A8+1,AB +1,A8 (0) epee Numbers of 4 x 16 decoders required Lf 256 Fut 0 ‘or 16 Erle +t=17 s-AdBec where sum of full adder is = A® B@ C (3) Truth table of Full adder a—fo 4 i eae S| S1@ [cameo] sum ‘mst nf? |e es o | o Wo | . 2 1+] 0 Y= AC+BC CEE f= ¥D+CD nf 4 } (AC + BC)D + CD Objective Practice Sets (@mAde EnsyO3 MADE ERsy 28. (0011) Q(t+1) =D, AT Qy(t+ 1) = Q,(NOX (1) Qy(t+ 1) =D, OQy(t+ 1) = QHH@.Q,(0 (2) M9 = Alt) +(Gw9-X) cu WO = Q()+QO+X (3) State table: 5 [eae | NenSae a, Cm Oy a com ons [rate core om aithe sa silanated of+[s[+ olt al oa ool ect Oc [ope fet. 4+ ]4 oppo pepo Fe State diagram: ony ont 31 1" 32, From state diagram output sequence is 0011 for input sequence 1010. 29. (d) a Z[« ° | + [4 ° 1 | 0 1 o | o 1 o Li x e wa 1 ue 1 (3MADE EASY Postal Study Course EXE) Digital Losic | ——) ee ==) (b) gut ‘A3sinput XNOR gate acis as an odd function Y=A,@8, 94,0804, @B, =1 sing definition of XOR the valid combination is A,A, Ay = 010 and B, B, By = 101 (a) Expression of 'F from logical deduction is Ra AoB, +(A: @B2)AB, Rean be implemented by AND-OR logic. () By checking all the options, Option (c) correctly matches.era ia 5 Sequential Logic Circuits CHAPTER Q.1_ Consider the digital circuit shown in below figu The average propagation delay of each NAND gate in the clock generator circuit is 10s. The frequency of the clock signal is MHz, Q.2 Consider the counter shown below J unter is 001, then after how many minimum number af clack pulses the initia If the initial state of the state is reached? Q.3 In the following figure consisting of JHK flip flop assume the flip flop was initially cleared and then clocked for 6 pulses, the sequence at the Q output will be Os 11k Ge (@) 010000 (b) 011001 (6) 010010 (© o10101 Q.4. Consider the following circuit consisting of D flp flops.