Unit 1 Part 2-2 Segmentation

Non-Continuous Memory
allocation
Dr. Neetu Narwal
Assoc. Prof.
BCA[M]
Dr. Neetu Narwal, MSI

Dr. Neetu Narwal, Asso. Prof. BCA [M], MSI
Practice Qt.1 Continuous Memory

allocation

Practice Qt.2 Continuous Memory

allocation

Segmentation
 Segmentation is a memory-management scheme that

supports this programmer view of memory. A logical
address space is a collection of segments.
 Each segment has a name and a length. The addresses
specify both the segment name and the offset within
the segment. The programmer therefore specifies each
address by two quantities: a segment name and an
offset.
 Thus, a logical address consists of a two tuple:
<segment-number, offset>.

Segmentation Hardware
 The mapping of logical address to physical address is

effected by a segment table.
 Each entry in the segment table has a segment base
and a segment limit. The segment base contains the
starting physical address where the segment resides in
memory, and the segment limit specifies the length of
the segment.

Segmentation Hardware


Paging
Segmentation permits the physical address

space of a process to be noncontiguous.
Paging is another memory-management
scheme that offers this advantage. However,
paging avoids external fragmentation and the
need for compaction, whereas segmentation
does not.

Basic Method of Paging
The basic method for implementing paging

involves breaking physical memory into fixed-
sized blocks called frames and breaking logical
memory into blocks of the same size called
pages.
When a process is to be executed, its pages are
loaded into any available memory frames from
their source.

Hardware support for Paging
Every address generated by the CPU is divided

into two parts: a page number (p) and a page
offset (d).
The page number is used as an index into a
page table.
The page table contains the base address of
each page in physical memory. This base
address is combined with the page offset to
define the physical memory address that is sent
to the memory unit.
The following outlines the steps taken by the MMU to

translate a logical address generated by the CPU to a
physical address:
1. Extract the page number p and use it as an index into
the page table.
2. Extract the corresponding frame number f from the
page table.
3. Replace the page number p in the logical address with
the frame number f .
As the offset d does not change, it is not replaced, and the
frame number and offset now comprise the physical
address.



If the size of the logical address space is 2m, and

a page size is 2n bytes, then the high-order m− n
bits of a logical address designate the page
number, and the n low-order bits designate the
page offset. Thus, the logical address is as
follows:
where p is an index into the page table and d is
the displacement within the page.

 Example, consider the

memory. Here, in the logical
address, n= 2 and m = 4.
Using a page size of 4 bytes
and a physical memory of 32
bytes (8 pages), Here, in the
logical address, n= 2 and m
= 4.

Indexing into the page table, we find that

page 0 is in frame 5. Thus, logical address 0
maps to physical address 20 [= (5 × 4) + 0].
 Logical address 3 (page 0, offset 3) maps to
physical address 23 [= (5 × 4) + 3].
Logical address 4 is page 1, offset 0;
according to the page table, page 1 is
mapped to frame 6. Thus, logical address 4
maps to physical address 24 [= (6 × 4) + 0].
Logical address 13 maps to physical address
9.
 When we use a paging scheme, we have no external

fragmentation: any free frame can be allocated to a
process that needs it.
 However, we may have some internal fragmentation.
Notice that frames are allocated as units.
 If the memory requirements of a process do not happen
to coincide with page boundaries, the last frame
allocated may not be completely full.
 For example, if page size is 2,048 bytes, a process of
72,766 bytes will need 35 pages plus 1,086 bytes.
 It will be allocated 36 frames, resulting in internal
fragmentation of 2,048 − 1,086 = 962 bytes.
 In the worst case, a process would need n pages plus 1

byte. It would be allocated n + 1 frames, resulting in
internal fragmentation of almost an entire frame.
 If process size is independent of page size, we expect
internal fragmentation to average one-half page per
process.

Hardware Support
 Each operating system has its own methods for storing page
tables. Some allocate a page table for each process. A
pointer to the page table is stored with the other register
values (like the instruction counter) in the process control
block.
 The standard solution to this problem is to use a special, small,
fast lookup hardware cache called a translation look-aside
buffer (TLB). The TLB is associative, high-speed memory. Each
entry in the TLB consists of two parts: a key (or tag) and a
value.
 When the associative memory is presented with an item, the
item is compared with all keys simultaneously. If the item is
found, the corresponding value field is returned.

Hit Ratio
 The percentage of times that the page number of interest is
found in the TLB is called the hit ratio. An 80-percent hit ratio,
for example, means that we find the desired page number in
the TLB 80 percent of the time. If it takes 100 nanoseconds to
access memory, then a mapped-memory access takes 100
nanoseconds when the page number is in the TLB.
 To find the effective memory-access time, we weight the
case by its probability:
 effective access time = 0.80 × 100 + 0.20 × 200 = 120
nanoseconds
 In this example, we suffer a 20-percent slowdown in average
memory-access time (from 100 to 120 nanoseconds).

Protection
Memory protection in a paged environment is

accomplished by protection bits associated
with each frame. Normally, these bits are kept in
the page table.

Protection

Numerical from Book

Q1. Consider a logical address space of 64 pages of 1,024

words each, mapped onto a physical memory of 32
frames.
 a. How many bits are there in the logical address?
 b. How many bits are there in the physical address?

Q2. Assuming a 1-KB page size, what are the page

numbers and offsets for the following address references
(provided as decimal numbers):
 a. 3085
 b. 42095
 c. 215201
 d. 650000
 e. 2000001

Q3. Consider a computer system with a 32-bit logical

address and 4-KB page size. The system supports up to 512
MB of physical memory.
How many entries are there in each of the following?

Q4. Consider a logical address space of 256 pages with a

4-KB page size, mapped onto a physical memory of 64
frames.
a. How many bits are required in the logical address?
b. How many bits are required in the physical address?

Q5. Given six memory partitions of 100 MB, 170 MB, 40 MB,
205 MB, 300 MB, and 185 MB (in order), how would the first-
fit, best-fit, and worst-fit algorithms place processes of size
200 MB, 15 MB, 185 MB, 75 MB, 175 MB, and 80 MB (in
order)?

Q6. Assuming a 1-KB page size, what are the page

numbers and offsets for the following address references
(provided as decimal numbers)?
a. 21205
b. 164250
c. 121357
d. 16479315
e. 27253187

Q7. Consider a logical address space of 2,048 pages with

a 4-KB page size, mapped onto a physical memory of 512
frames.
a. How many bits are required in the logical address?
b. How many bits are required in the physical address?

Q8. Consider a paging system with the page table stored

in memory.
 a. If a memory reference takes 50 nanoseconds, how
long does a paged memory reference take?
 b. If we add TLBs, and 75 percent of all page-table
references are found in the TLBs, what is the effective
memory reference time? (Assume that finding a page-
table entry in the TLBs takes 2 nanoseconds, if the entry is
present.)

Q9.

END

Unit 1 Part 2-2 Segmentation

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Unit 1 Part 2-2 Segmentation

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Non-Continuous Memory

Dr. Neetu Narwal, MSI

Practice Qt.1 Continuous Memory

Dr. Neetu Narwal, MSI

Practice Qt.2 Continuous Memory

Dr. Neetu Narwal, MSI

 Segmentation is a memory-management scheme that

Dr. Neetu Narwal, MSI

 The mapping of logical address to physical address is

Dr. Neetu Narwal, MSI

Dr. Neetu Narwal, MSI

Dr. Neetu Narwal, MSI

Segmentation permits the physical address

Dr. Neetu Narwal, MSI

Basic Method of Paging

The basic method for implementing paging

Dr. Neetu Narwal, MSI

Hardware support for Paging

Every address generated by the CPU is divided

The following outlines the steps taken by the MMU to

Dr. Neetu Narwal, MSI

Dr. Neetu Narwal, MSI

Dr. Neetu Narwal, MSI

If the size of the logical address space is 2m, and

Dr. Neetu Narwal, MSI

 Example, consider the

Dr. Neetu Narwal, MSI

Indexing into the page table, we find that

 When we use a paging scheme, we have no external

 In the worst case, a process would need n pages plus 1

Dr. Neetu Narwal, MSI

Dr. Neetu Narwal, MSI

Dr. Neetu Narwal, MSI

Memory protection in a paged environment is

Dr. Neetu Narwal, MSI

Dr. Neetu Narwal, MSI

Numerical from Book

Dr. Neetu Narwal, MSI

Q1. Consider a logical address space of 64 pages of 1,024

Dr. Neetu Narwal, MSI

Q2. Assuming a 1-KB page size, what are the page

Dr. Neetu Narwal, MSI

Q3. Consider a computer system with a 32-bit logical

Dr. Neetu Narwal, MSI

Q4. Consider a logical address space of 256 pages with a

Dr. Neetu Narwal, MSI

Dr. Neetu Narwal, MSI

Q6. Assuming a 1-KB page size, what are the page

Dr. Neetu Narwal, MSI

Q7. Consider a logical address space of 2,048 pages with

Dr. Neetu Narwal, MSI

Q8. Consider a paging system with the page table stored

Dr. Neetu Narwal, MSI

Dr. Neetu Narwal, MSI

Dr. Neetu Narwal, MSI

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