Bascule jk

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity basc_jk is

Port ( r,clk ,j,k :IN std_logic;

Q : out std_logic

);

end basc_jk;

architecture Behavioral of basc_jk is

signal Qn : std_logic;

begin

process (clk,r,j,k)

begin

if r<='1' then

Q<='0';

elsif clk'event and clk='1' then

if ( j<='0' and k <='0') then

Qn <= Qn;

elsif (j<='0' and k<='1' )then

Qn <='0';

elsif (j<='1' and k<='0')then

Qn <='1';

elsif (j<='1' and k<='1' )then

Qn <= not Qn;

end if;

end if;

end process ;

q <= qn;

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;
--use UNISIM.VComponents.all;

entity test_jk is

-- Port ( );

end test_jk;

architecture Behavioral of test_jk is

component jk

port ( clk,j,k,s : IN std_logic;

Q : OUT std_logic );

end component ;

signal r,j,k :std_logic ;

signal clk : std_logic ;

begin

u1 :jk port map (

clk => clk ,

j=> j ,

k=> k,

s=> s

);
j<='1' after 5 ns , '0' after 10 ns ;

k<='1' after 10 ns , '0' after 15 ns ;

s<='1' after 7 ns , '0' after 20 ns ;

end Behavioral;

compteur jk

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity test_jk is

-- Port ( );

end test_jk;

architecture Behavioral of test_jk is

component jk

port ( clk,j,k,R : IN std_logic;

Q : OUT std_logic );
end component ;

signal CLK : std_logic :='0';

signal r :std_logic ;

signal j,k ,q : std_logic_vector ( 2 downto 0) ;

begin

u1 : jk port map (

clk => clk ,

r => r ,

j=> j(0) ,

k=> k(0)

);

u2 : jk port map (

clk => q(0) ,

r => r ,

j=> j(1) ,

k=> k(1)

);

u3 : jk port map (

clk => q(1) ,

r => r ,

j=> j(2) ,

k=> k(2)
);

process

begin

clk <= not clk;

wait for 5ns ;

end process;

j(0)<='1' after 5 ns , '0' after 15 ns ;

k(0)<='1' after 7 ns , '0' after 20 ns ;

end Behavioral;

test jk
----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 10.12.2020 15:04:49

-- Design Name:

-- Module Name: test_jk - Behavioral

-- Project Name:
-- Target Devices:

-- Tool Versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity test_jk is

-- Port ( );

end test_jk;
architecture Behavioral of test_jk is

component basc_jk

Port ( r,clk ,j,k :IN std_logic;

Q : out std_logic);

end component ;

signal r,j,k,q :std_logic ;

signal clk : std_logic :='0';

begin

u1 :basc_jk port map (

r => r ,

clk => clk ,

j=> j ,

k=> k,

Q => Q

);
process

begin

clk <= not clk;

wait for 5ns ;

end process;

j<='1' after 5 ns , '0' after 10 ns ;

k<='1' after 10 ns , '0' after 15 ns ;

r<='1' after 7 ns , '0' after 20 ns ;

end Behavioral;