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Analog IC Design Mismatch Calculations
Analog IC Design Mismatch Calculations
Analog IC Design Mismatch Calculations
∆I 2 ∆ VTH AVTH
∆ I ≈ gm × ∆ VTH → ≈ σ ( ∆ VTH ) ≈
I VDSAT WL
A IM: 4.5σ
NOTE:
2K′W AV AV
∆ I ≈ gm × ∆ VTH = I × TH = 2K′I × TH
L WL L
( )
2K′W AVTH
I ×
L WL AVTH K′LOAD LIN
LOAD LOAD
∆ VOS ≈ ∆ VTH IN + → ∆ VOS ≈ ∆ VTH IN + × ×
( )
2K′W LLOADWIN K′IN LLOAD
L
I
IN
1
2 2
VDSATIN
{ VDSATLOAD }
σVos ≈ σIN( ∆ VTH) + σLOAD( ∆ VTH)
2
AVTH
∆ ICURRMIRR ≈ 2K′I ×
L
AVTH K′OTHER LIN
OTHER
∆ VTH OTHER ≈ × ×
LOTHERWIN K′IN LOTHER
∑
∆ VOS ≈
SPEC CHECK4









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