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LG 37lc2r 42lc2r 32lb1r 37lb1r 42lb1r Hurricane3 High Chassis Guide Training (ET)
LG 37lc2r 42lc2r 32lb1r 37lb1r 42lb1r Hurricane3 High Chassis Guide Training (ET)
Table of contents
1. Specification
2. Block Diagram
3. Trouble Shooting
4. Debugging Method
5. Adjustment UI Specification
6. Document
2006.05.03
DDC PA Gr
Design
42PC1R 37LC2R
H&C 2 Tone
• New XD Engine
• 10 Bit
• HDMI
Feature • 3D Surround (Royalty Free)
• 1Tuner(EU), 2Tuner(Non-EU)
• AV Input Navigation
• Stand-by Power consumption 1W
• On Screen Equalizer
• Clear Filter
• Brightness : 1,200 ㏅/㎡ • Brightness : 500 ㏅/㎡
Module • Contrast : 10,000 : 1 • Contrast : 1600 : 1
• ASIC : 4025적용 • View Angle : 178 ˚
Tool line up
H&C ● ●
PB2 PC1/PC3
H&C
LB2 LC2
2 Tone
RF In 1 1 1 1 1 1 1
AV in 4 2 4 2 2 2 2
Monitor out 1 1 1 1 1 1 1
S-Video in 1 1 1 1 2 2 2
J Component 1 2 1 2 2 2 2
A Input(Y,Pb,Pr)
C
Variable 1 1 1 1 1 1 1
K
Audio out
PC Audio In 1 1 1 1 1 1 1
RGB Input 1 1 1 1 1 1 1
RS-232C 1 1 1 1 1 1 1
Remote control 1 1 1 1 1 1 1
RF In 1 1 1 1 1 1 1
AV in 4 2 2 3 4 2 2
Monitor out 1 1 1 1 1 1 1
S-Video in 1 1 1 1 1 1 1
J Component 1 2 2 2 1 2 2
A Input(Y,Pb,Pr)
C
Variable 1 1 1 1 1 1 1
K
Audio out
PC Audio In 1 1 1 1 1 1 1
RGB Input 1 1 1 1 1 1 1
RS-232C 1 1 1 1 1 1 1
Remote control 1 1 1 1 1 1 1
• The FLI8668 chip has a flexible Analog Front End (AFE) with 13 configurable inputs through an analog multiplexer before the Analog to Digital Converters
(ADCs).
• It also contains an embedded Multi-Standard Video Decoder. This decoder contains a digital comb filter for optimum Y/C separation. A 3D comb filter is a
vailable for optimum Y/C separation, that reduces or eliminates any artifacts due to poor Y/C separation seen on standard 2D video decoders on composite
inputs, most commonly found on TV tuners.
• The FLI8668 microprocessor can process a wide range of Vertical Blanking Interval (VBI) data and display this data with the bitmap OSD processor. The
microprocessor can support VBI data processing in the Main or PIP channels as well as in the background when the corresponding video stream is not pre
sent on the output stream. The VBI dataslicer can extract data encoded into the VBI of the input video stream. Decoded data bytes from the VBI dataslicer
are stored in a memory buffer for subsequent processing by the microprocessor. The microprocessor decodes the different formats of the VBI data and pas
ses the information to the OSD controller for output to the display controller. The VBI decoding process can run continuously in the background for inputs th
at contain VBI data.
• The Digital Input Port is a 48-bit data input with flexible configuration to support a wide range of digital sources. It consists of two 24-bit ports (PORT
A and PORTB),two sets of control signals (VS,HS,ODD,etc.), and 4 input clocks. Up to 4 different inputs are supported as long as at least 2 of these in
puts are 8-bit CCIR656. The digital input port can also be configured to support one 30-bit input with a second 16-bit input port. Bit 7 to 0 of PORTA ca
n be configured as a bidirectional interface for media card applications.
• DCDi (Directional Correlation De-Interlacing) is an algorithm from Genesis Microchip’s Faroudja division, that is used to deinterlace video content (co
nvert from interlaced to progressive scan). DCDi is known for its smooth interpolation of video content as it fills in the missing lines. Its purpose is to eli
minate jagged edges (jaggies) along diagonal lines caused by interpolation, resulting in the projection of cinema-like images with exceptional picture q
uality.
• The FLI8668 allows a very flexible PIP display configuration whereby either the graphics or video channel may act as the PIP source to overlay over
the other channel. Any one of the inputs (analog RBG, 24-bit digital, 8-bit digital, YPbPr, composite video, etc) may be multiplexed to either channel. T
he PIP can be from any of the AIP (Analog Input Port) 1 or 2 or DIP (Digital Input Port) 1 or 2. Single PIP allows the PIP display to be placed arbitrarily
in the display window. It can be placed within the Main display, partially overlapped with Main display, or fully detached from Main display. Multiple PIP
s display allows a number of PIP windows to be displayed at the same time depending on display pixel resolution. The Main and one PIP window will
be running in real time. There are up to 16 PIP windows available at the same time, however only one might be active. All of them should be aligned to
the 4x4 grid. Default S/W application uses multiple PIP windows to display different RF channels.
• Two LVDS channels (A and B) are available on the output of the FLI8668 to transmit data and timing information to the display device. FLI8668 direct
ly drives the standard LVDS interface panels, supporting all standard data formats—single and dual bus, 18- or 24-bit data output. The 24-bit data may
be mapped as either standard receiver formats.
• The FLI8668 has a fully programmable, true color bitmapped OSD controller capable of displaying up to 16 “tiles” or bitmap windows on the display.
The individual tiles are programmable for location, size and bits per pixel, and have a precedence determining which tiles appear when overlapping oc
curs on the display. Tile data is stored in the external frame store memory by the OCM in either : 1, 2, 4, or 8-bit per pixel format. On-chip table registe
rs point to the start of tiles in external memory. A programmable on-chip 256x24-bit color lookup table is provided to map the OSD pixels onto a true 2
4-bit color space.
• The FLI8668 on-chip microcontroller (OCM) serves as the system microcontroller. It programs the FLI8668 and manages other devices in the system
such as the keypad and non-volatile RAM (NVRAM) using general-purpose input/output (GPIO) pins. The OCM can address a 22-bit address space to
utilize 4 MB external ROM.
A C
Power Sequence :
1 1. Power Cord connect to set. Power b/d supplies 5VST
CON from wafer P1000 pin 3 and 8. This is also distri
buted as +5VST_CORTEZ, that connect to Regulator
4 IC1001, IC1004, and IC1005, which regulate 1.8, 2.5,
and 3.3V for Cortez (turns ON). Also distributed as +
5VST, that connect to Transistors Q1000,1001,1004,
and 1005.
2. AC_DET signal are sent by Power b/d from pin 1 waf
er P1000 to pin N23 of IC800(Cortez). Then Cortez s
end 3.3V_ON from pin M2 to Power b/d via pin 13 P1
000.
AC_DET 3. IC800 send RL_ON from pin U24, this switches the tr
RL_ON
+5VST ansistor Q1004 ON so +5VST grounded, this makes t
he transistor Q1000 OFF, so other +5VST supplies R
L_ON on pin 2 wafer P1000. So Relay on Power b/d t
urns on to supplies 3.4, 6, 12, and 19V.(section 2)
4. 5VDet is sent by Power b/d to Cortez. Then Cortez s
end command to turn on VaVs from pin U25 that swit
ches ON transistor Q1005, so +5VST grounded, this
makes transistor Q1001 OFF, and this make another
+5VST supplies to pin 5 wafer P1000. The Power b/
d supplies X b/d and Y b/d.
3Và1.8V
5Và3.3V
Power Sequence :
1. The +5VST_Cortez as an input on pin 1 of IC1001(B
A033T), a LOW SATURATION VOLTAGE REGULATO
R, is being step-down to 3.3V. Then this output act
as input and enable for IC1003 pin 2 and pin 1 (SC15
65-1.8TR), a VERY LOW DROP OUT 1.5 Amp REGU
12Và9V LATOR WITH ENABLE, the output 1.8V is in pin
4, that is regulated to +1.8V_ADC_CTZ,+1.8V_CORE
_CTZ, +1.8V_DLL_CTZ, and +1.8V_PLL_CTZ.
2. The P_12 (from section 2), as an input on pin 1 of IC1
002 (KA7809R), a 3-TERMINAL 1A POSITIVE VOL
TAGE REGULATOR, regulated to be 9V output on pin
3, distributed as +9V_CXA2069, +9V_MSP4450, +9
V, and +9V_TK1184.
3. The VAVS_ON from Cortez switches ON transistor Q
1006, and makes +12V_panel grounded and supply pi
n1-4 IC1006(SI925DY), a DUAL P-CHANNEL LOGIC
LEVEL POWER TRENCH MOSFET, minimized ON s
tate resistance, and the output is on pin 5-8 a 12V_L
CD. The VAVS_ON also enable IC1007 pin 7, to s
tep-down an input +12V_PANEL on pin 2 into 5V_LC
D on pin 1 and 3.
5Và3.3V
5Và3.3V
Power Sequence :
Start check
Is inserted a plug NO
Plug in a power cord
in power cord?
YES
YES
YES
Is it connected that NO
PSU and 13pin cable Connect the 13pin cable.
in VSC board?
YES
After remove all cables connected to
PSU(except the CN101), authorizes the AC
voltage marking on manual.
When ST-by 5V doesn’t operate, replace PSU
Start check
YES
Is the each NO After connecting well each
connector normal? Replace the power board
connector the normality it operates?
YES
Is the Y- Board NO Is normal the fuse NO Is normal the output voltage after
(FS2,FS3) on Y-B/D? Replace Y-B/D
normal ? remove P1connector of Y-B/D?
Is the Z- Board NO Is normal the fuse NO Is normal the output voltage after
Replace Z-B/D
normal ? (FS1,FS2) on Z-B/D? remove P1 connector of Z-B/D?
YES
Replace the fuse
YES
Start check
YES
YES Check the PDP/LCD Module
YES
NO NO NO
YES
Check the power
Cable inserts well. Change the Tuner
( L1103)
NO NO
YES
YES
Same as Block A
YES
Same as Block A
YES
Same as Block A
YES
Same as Block A
YES
Same as Block A
10. In the case of becomes unusual display from SCART 1_RGB mode(main)
YES
Same as Block A
YES
Same as Block A
12. In the case of becomes unusual display from SCART 2_YC mode(main)
YES
Same as Block A
NO NO NO
NO NO
YES
YES
Change IC(IC800)
YES
Change IC(IC800)
Is normal R, G, B input
and H,V sync of the JK500? NO Check the input source
(Check R509, R511, R512
R513, R515)
YES
Change IC(IC800)
◈ Symptom
LED is White
Screen is existent, but sound isn’t
◈ Check follow
Is the output
Only AV input is IC400 operate
of IC300(pin52,53) Replace IC300 Replace IC400
no Sound? normally?
NO normal? NO NO
YES YES
Yes
Is normal only video ? Download EDID data each port.
No
Is wave continuous? Check HDMI source. Change another source or cable.
Yes
GProbe 5.2.0.2.exe
Install the GProbe Software from the Desktop using the GProbe 5.2.0.2.exe file.
After installing GProbe 5.2.0.2 install the CGProbe from CGProbe Redistributable 5.2.0.4.exe as
shown in the figure.
GProbe 5
Select the Icon named GProbe 5 Tool for downloading the software in T.V. from the desktop.
Help Menu
Verify the GProbe UI Version: 5.2.02 and CGProbe Version: 5.2.0.4 from the Help menu
under About GProbe.. .
Connection Settings
Select Chip:
Select the “Commands” Option and then select the “Batch” option to locate the Path from
where the “.text file” has to be downloaded which contains the information regarding the
location of final “.hex file”.
browse
Browse the .txt file from its specified location in the directory such as:
C:\clearcase_rohit\rohit_view2\CC_HURRICANE3_H\10_Source\FLI8668\Isp\b
atch\CORTEZ_A.txt
After selecting the Appropriate Batch file Check that the T.V is in GProbe Mode for
downloading the software other wise it generate an Error.
RS232 Host: Gprobe.
Baud Rate: 115200bps(T.V in Power on state)/9600bps (T.V in stand by Power off).
After selecting the Appropriate Batch file Check that the T.V is in GProbe Mode for
downloading the software other wise it generate an Error.
Error: Timeout while waiting for Response.
If the connections between T.V Board and C.P.U are not proper or T.V is not in the GProbe
mode it will give “Error Message” as shown in figure.
Error Message: Timeout while waiting for Response.
So Check the connection properly and GProbe condition & again Start Downloading.
appstest 0 input
PAA,CRW,CRO,RO,WO type è We could not change the register value using the Gprobe5
IC control Example
1) Adjusting PC with S/W for writing EDID Data.(S/W : EDID TESTER Ver.2.5)
2) A Jig for EDID Download
3) Cable : Serial(9Pin or USB) to D-sub 15Pin cable, D-sub 15Pin cable, DVI to HDMI cable.
1) As above Fig. 5, Connect the Set, EDID Download Jig,, PC & Cable
2) Turn on the PC & EDID Download Jig. And Execute the S/W : EDID TESTER Ver.2.5
3) Set up the S/W option .
Repeat Number : 5
Device Address : A0
PageByte : 8
[BLOCK0]
[BLOCK0] [BLOCK1]
5. Sequence of Adjustment
Owner’s
Manual Owner's manual Owner's manual
_ EU _ Non EU
Module
CAS 42X3_PDP 50X3_PDP 32LCD_LPL 37LCD_LPL 42LCD_LPL 37LCD_AUO
Circuit
Diagram Circuit Circuit Diagram Circuit Diagram Circuit Diagram
Diagram_VSC _ Local key _ PreAMP _ Side AV
Adjustment
UI
Specification Adj_UI
Specification
Area Option
Table LCD H3 High PDP H3 High
Option Table Option Table
Gprobe5
GProbe5.2.0.2 CGProbe5.2.0.4