International Islamic University Islamabad

Communication Systems Lab

Experiment No. 9:

Implementation of PCM Decoder

Name of Student: …………………………………..

Roll No.: ……………………………………………
Date of Experiment: ………………………………..
Experiment No. 9
Implementation of PCM Decoder
Objectives:
1. To understand the basic theory Digital to Analog conversion

2. To implement the PCM using CT-3000 trainer modules.

Equipment/Tools:
 CT-3000 Trainer.
 Digital Multimeter (DMM).
 Dual Channel Oscilloscope.
 PCM Encoder (PCME), PCM Decoder (PCMD) Data Generator (DG) and Sample and
Hold (S/H) modules.

Theory:
In PCM receiver (Fig. 9.1), the received signal contaminated by noise, is regenerated to yield
a clean PCM waveform. Using sync and timing information, the serial bits are converted into
parallel words. DAC (digital to analog converter) then generates sample and hold (staircase)
waveform.

This staircase waveform differs from original S/H waveform by the round off error, introduced
in the quantizer. Low pass filter then produces smoothed output signal, which differs from the
original signal to the extent that the quantized samples differ from the exact sample values.
Quantizing process, introduces noise in PCM signal, which depends upon word length “n”. The
signal to noise ratio (SNR), of a PCM signal is given by:
Where K is the ratio of rms to peak signal amplitudes and is always <1. For above it is obvious,
that SNR depends upon K and n. SNR improves by 6 dB whenever PCM word length “n”, is
increased by one bit. K factor is improved through use of companding.

In this experiment, use of 8 bit PCM (word length n=8) has been made. Clock signal of 64
KHz has been made. Each PCM word (encoded signal sample), is followed by a zero to
differentiate it from the succeeding PCM word (next signal sample). PCM waveform is shown
in Fig. 9.2.

Procedure:
 Connect CT-3000 to power and verify that all voltages are available.
 Switch off the trainer. Insert DG module in socket 1, SH in socket 4, PCME in
socket # 5 and PCMD in socket # 2.
 Inter connect the modules as shown in Fig. 9.3 below and switch on the trainer.
 Connect scope CH1 to clock signal of DG module and verify its presence. Next connect
CH2 to J3 of PCME and verify that sampling signal with frequency 1/9th of the clock, is
available. The sampling signal is also frame sync Since in this experiment we have single
channel PCM system.
 Keep Ch2 displaying the sampling sync signal. Using pigtail banana pin, connect AF
signal to J1 of SH. Now connect Ch1 to J2 of SH to display S/H signal. Increase AF
signal and verify that staircase (S/H) waveform is present.
 Next connect Ch1 to J2 of PCME and verify that PCM waveform is available. Vary AF
signal and verify that PCM signal also varies. Verify that in PCM waveform a zero
follows each PCM word.
 Reduce AF signal to zero. Verify that PCM signal becomes of fixed pattern.
 Connect Ch1 to J1 of PCMD. Increase AF signal. S/H waveform of demodulated AF
signal will appear. Vary the amplitude of the AF signal and see that S/H waveform also
varies, accordingly. Change frequency of AF signal and see that frequency of S/H signal
also varies. Now insert LPF module in socket # 3. With AF set to 1 KHz connect S/H
signal to LPF input2 J2 terminal. Smooth AF signal will appear at output2 J4 terminal.

Results:

Plot the Input signal and corresponding Demodulated (decoded ) Signal